WO2022012167A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2022012167A1
WO2022012167A1 PCT/CN2021/095566 CN2021095566W WO2022012167A1 WO 2022012167 A1 WO2022012167 A1 WO 2022012167A1 CN 2021095566 W CN2021095566 W CN 2021095566W WO 2022012167 A1 WO2022012167 A1 WO 2022012167A1
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Prior art keywords
layer
semiconductor device
substrate
hole
material layer
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PCT/CN2021/095566
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English (en)
French (fr)
Inventor
吴秉桓
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/615,059 priority Critical patent/US12426233B2/en
Publication of WO2022012167A1 publication Critical patent/WO2022012167A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/041—Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps

Definitions

  • the present disclosure relates to the field of storage technologies, and in particular, to a semiconductor device and a manufacturing method thereof.
  • the memory is usually composed of a plurality of memory cells, each memory cell includes a capacitive structure, and each capacitive structure can store a logic "1" or "0".
  • each memory cell includes a capacitive structure, and each capacitive structure can store a logic "1" or "0".
  • the memory can only form less capacitance structures within a limited size, or can only form capacitance structures with small capacitance values.
  • a semiconductor device including a plurality of capacitive structures, the semiconductor device further comprising: a substrate and a plurality of electrical conductors.
  • a plurality of conductors are used to form the first electrode of the capacitor structure, and a plurality of rows and columns of the conductors are distributed on one side of the substrate.
  • Each of the electrical conductors includes a cylindrical body and a plurality of annular protrusions.
  • the axial direction of the cylindrical body intersects with the substrate; the annular protrusions are arranged around the circumference of the cylindrical body, and a plurality of the annular protrusions are along the axial direction of the cylindrical body Space distribution; wherein, the annular protrusions adjacent to the conductors in the row and column directions are arranged staggered in the vertical direction to the substrate.
  • the orthographic projections of the annular protrusions adjacent to the electrical conductors on the substrate at least partially overlap.
  • each of the electrical conductors is used to form a first electrode of the capacitive structure.
  • a plurality of the electrical conductors are used to form a first electrode of the capacitive structure.
  • the semiconductor device further includes an electrical connection layer located between the substrate and the conductor for electrically connecting one or more of the capacitor structures. a plurality of the electrical conductors.
  • the semiconductor device further includes: a first dielectric layer and a first conductive layer.
  • the first dielectric layer covers the conductor; the first conductive layer is located on the side of the first dielectric layer away from the substrate, and covers the first dielectric layer, and is used to form the capacitor structure. second electrode.
  • the semiconductor device further includes an electrode connection layer, which is disposed on a side of the first conductive layer away from the substrate and covers the first conductive layer.
  • each of the annular protruding parts has the same or different protruding dimensions along a direction perpendicular to the side surface of the cylindrical main body.
  • the material of the electrical conductor includes one or more of: tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon.
  • a method of fabricating a semiconductor device the semiconductor device including a plurality of capacitive structures, the method comprising:
  • a composite layer is formed on the substrate, and the composite layer includes a first material layer and a second material layer alternately stacked in sequence;
  • a plurality of through holes distributed in rows and columns through the composite layer are formed on the composite layer, the plurality of through holes include a plurality of first through holes and a plurality of second through holes, each of the first through holes Only adjacent to the second through holes in the row and column direction, each of the second through holes only adjacent to the first through hole in the row and column direction;
  • the etching speed of the second etching solution to the second material layer is greater than the etching speed of the second etching solution to the first material layer, Thereby, an annular groove is formed on the side wall of the second through hole located in the second material layer;
  • a conductive material is filled into the through holes to form electrical conductors in each of the through holes, and the electrical conductors are used to form the first electrodes of the capacitive structure.
  • the orthographic projections of the annular grooves in the adjacent through holes in the row and column directions on the substrate at least partially overlap.
  • the material of the first material layer is silicon dioxide
  • the material of the second material layer is silicon nitride
  • the first etching solution is hydrofluoric acid
  • the The second etching solution is phosphoric acid.
  • the conductive material is filled into the through hole, and further includes:
  • a first conductive layer is formed on the side of the first dielectric layer away from the substrate, the first conductive layer covers the first dielectric layer, and the first conductive layer is used to form the capacitor structure the second electrode.
  • the method for fabricating a semiconductor device further includes:
  • connection structures are used for electrically connecting a plurality of the conductors in one or more of the capacitor structures;
  • forming on the composite layer through holes distributed through a plurality of rows and columns of the composite layer further includes:
  • Each layer of the first material layer and each layer of the second material layer are ion-doped with a predetermined concentration, so as to adjust the etching speed of the first material layer or the second material layer.
  • first through holes are formed on the composite layer, and annular grooves are formed on the sidewalls of the first through holes located in the first material layer, and then the first through holes are formed on the sidewall of the first material layer. forming the second through hole through the composite layer on the composite layer;
  • the method further includes:
  • a sacrificial material is injected into the first through hole.
  • the second through hole is filled with the conductive material first, and then the first through hole is filled with the conductive material;
  • the method further includes:
  • the sacrificial material is removed.
  • FIGS. 1-5 are schematic structural diagrams of various stages in the semiconductor device manufacturing process in the related art
  • FIG. 6 is a top view of a semiconductor device in the related art
  • FIG. 7 is a cross-sectional view of a semi-finished semiconductor device along a row/column direction in an exemplary embodiment of the disclosure
  • FIG. 8 is a top view of a semi-finished semiconductor device in an exemplary embodiment of the disclosure.
  • FIG. 9 is a cross-sectional view of a semi-finished semiconductor device along a row/column direction in an exemplary embodiment of the disclosure.
  • FIG. 10 is a cross-sectional view of a semi-finished semiconductor device along a row/column direction in an exemplary embodiment of the disclosure
  • FIG. 11 is a top view of a semi-finished semiconductor device in an exemplary embodiment of the disclosure.
  • 12a is a cross-sectional view of a semi-finished semiconductor device in a row/column direction according to an exemplary embodiment of the disclosure
  • 12b is a cross-sectional view of a semi-finished semiconductor device in a row/column direction in another exemplary embodiment of the present disclosure
  • FIG. 13 is a cross-sectional view of a semi-finished semiconductor device in a row/column direction according to another exemplary embodiment of the present disclosure
  • FIG. 14 is a top view of a semi-finished semiconductor device in another exemplary embodiment of the present disclosure.
  • FIG. 15 is a cross-sectional view of a semi-finished semiconductor device in a row/column direction according to another exemplary embodiment of the disclosure.
  • 16 is a cross-sectional view of a semi-finished semiconductor device in a row/column direction according to another exemplary embodiment of the present disclosure
  • 17 is a cross-sectional view of a semi-finished semiconductor device in a row/column direction according to another exemplary embodiment of the present disclosure.
  • FIG. 18 is a cross-sectional view of a semi-finished semiconductor device in a row/column direction according to another exemplary embodiment of the disclosure.
  • FIG. 19 is a cross-sectional view along a row/column direction in an exemplary embodiment of the disclosed semiconductor device
  • FIG. 20 is a top view of an exemplary embodiment of the disclosed semiconductor device
  • 21 is a cross-sectional view along a row/column direction in an exemplary embodiment of the disclosed semiconductor device
  • FIG. 22 is a cross-sectional view along a row/column direction of an exemplary embodiment of the disclosed semiconductor device.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • a semiconductor device is usually composed of a plurality of memory cells, each memory cell includes a capacitance structure, and each capacitance structure can store a logic "1" or "0".
  • the related art proposes a method for manufacturing a semiconductor device, as shown in FIGS. 1-5 , which are schematic structural diagrams of various stages in the manufacturing process of the semiconductor device in the related art.
  • the method for fabricating a semiconductor device provided by the related art includes: forming multiple layers of a first material layer 2 and a second material layer 3 alternately stacked on a substrate 1 ; . A plurality of respective through holes 4 are formed on the second material layer 3 . As shown in FIG.
  • an etching solution is poured into the through hole 4 , and the etching speed of the etching solution on the second material layer 3 is greater than the etching speed on the first material layer 2 , so that the inner wall of the through hole 4 can be located on the first
  • the position of the two material layers forms an annular groove 5 .
  • the conductive material is filled in the through holes 4 and the grooves 5 to form the conductors 6 .
  • the conductors 6 include a columnar body 61 filled in the through holes 4 and annular protrusions filled in the grooves 5 . 62.
  • the multiple layers of the first material layer 2 and the second material layer 3 are removed.
  • the conductor 6 can be used as the first electrode of the capacitor structure.
  • the manufacturing method may further include forming a dielectric layer 7 on the surface of the conductor 6 , and forming a conductive layer 8 on the side of the dielectric layer 7 away from the substrate 1 , and the conductive layer 8 may form a capacitor structure the second electrode.
  • each conductor 6 can form a capacitance structure with the conductive layer 8 .
  • a plurality of conductors 6 can also be electrically connected to each other, thereby forming a capacitance structure with the conductive layer 8 . As shown in FIG.
  • the present exemplary embodiment provides a method for fabricating a semiconductor device, wherein the semiconductor device includes a plurality of capacitor structures, and the method includes:
  • Step S1 providing a substrate
  • Step S2 forming a composite layer on the substrate, the composite layer comprising a first material layer and a second material layer alternately stacked in sequence;
  • Step S3 forming a plurality of through holes distributed in rows and columns through the composite layer on the composite layer, the plurality of through holes include a plurality of first through holes and a plurality of second through holes, each of the first through holes A through hole is adjacent to the second through hole in the row and column direction, and each of the second through holes is adjacent to the first through hole in the row and column direction;
  • Step S4 injecting a first etching solution into the first through hole, the etching speed of the first etching solution on the first material layer is higher than that of the second material layer by the first etching solution etching speed, so as to form an annular groove on the sidewall of the first through hole located in the first material layer;
  • Step S5 injecting a second etching solution into the second through hole, the etching speed of the second etching solution on the second material layer is higher than that of the first material layer by the second etching solution etching speed, so as to form an annular groove on the sidewall of the second through hole located in the second material layer;
  • Step S6 Filling the through holes with a conductive material to form a conductor in each through hole, and the conductor is used to form the first electrode of the capacitor structure.
  • Step S1 includes: providing a substrate 1 .
  • Step S2 includes: compounding a layer 2 on the substrate 1, and the compounding layer 2 may include a first material layer 21 and a second material layer 22 which are alternately stacked in sequence.
  • the first material layer 21 and the second material layer 22 may be multiple layers respectively, and the number of layers of the first material layer 21 and the second material layer 22 may be the same or different.
  • the bottommost layer of the composite layer 2 facing the substrate may be the first material layer 21 or the second material layer 22 .
  • FIGS. 7 and 8 FIG.
  • Step S3 includes forming a plurality of through-holes distributed in rows and columns on the composite layer 2, and the plurality of through-holes may include a plurality of first through-holes 31 and a plurality of second through-holes 32, each of which is
  • the first through holes 31 are adjacent to the second through holes 32 in the row and column directions, and each of the second through holes 32 is adjacent to the first through holes 31 in the row and column direction.
  • the row direction may be X
  • the column direction may be Y.
  • the first through hole 31 and the second through hole 32 may be cylindrical through holes, and their opening sizes may be the same.
  • the through hole can be formed by dry etching technology, plasma etching technology and wet etching technology.
  • the etching process of the through hole can preferably be dry etching technology or plasma etching technology. etching technique.
  • Step S4 includes injecting a first etching solution into the first through hole 31, and the etching speed of the first etching solution to the first material layer is greater than that of the first etching solution to the second material layer.
  • the etching speed is increased, so that an annular groove 41 is formed on the sidewall of the first through hole located in the first material layer.
  • Step S5 includes injecting a second etching solution into the second through hole 32, and the etching speed of the second etching solution to the second material layer is greater than that of the second etching solution to the first material layer.
  • the etching speed is increased, so that an annular groove 42 is formed on the sidewall of the second through hole located in the second material layer.
  • the material of the first material layer may be silicon dioxide
  • the material of the second material layer may be silicon nitride
  • the first etching solution may be hydrofluoric acid
  • the The second etching solution may be phosphoric acid.
  • the first material layer and the second material layer may also be composed of other materials, and correspondingly, the first etching liquid and the second etching liquid may also be other etching liquids .
  • Step S6 includes filling the through holes with conductive material, and the conductive material may be filled in the entire through holes and the grooves to form electrical conductors 5 in each through hole, and each of the electrical conductors 5 may be used to form all the through holes.
  • the conductor 5 may include a cylindrical body 51 filled in the through hole and an annular protrusion 52 filled in the annular groove.
  • the material of the conductor may include: one or more of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon.
  • FIG. 11 it is a top view of a semi-finished semiconductor device in an exemplary embodiment of the present disclosure. Comparing FIGS. 6 and 11, it can be seen that even in FIG. 11, the distance between the orthographic projections of the substrates between the adjacent annular raised portions 52 along the row and column directions (row direction X, column direction Y) is relatively small, but It can be seen from FIG. 10 that there is a large reserved space between the adjacent annular protrusions 52 in the row and column direction, that is, in this exemplary embodiment, when the annular grooves 41 and 42 are etched, the annular groove 41 A safe distance is reserved between , 42 to prevent engraving. Obviously, it can be seen from FIG.
  • the semiconductor device provided by the present exemplary embodiment disposes the annular protrusions adjacent to the conductors in the row and column directions in a staggered direction with respect to the substrate, so that the Semiconductor devices can integrate more capacitor structures in a limited space.
  • the annular protrusion can increase the surface area of the first electrode, thereby increasing the capacitance value of the capacitance structure.
  • the manufacturing method may further include removing the first material layer 21 and the second material layer 22 . Wherein, the first material layer 21 and the second material layer 22 may be removed by alternate etching with the first etching solution and the second etching solution.
  • the manufacturing method may further include forming a first dielectric layer 61 on the surface of the conductor 5, the first dielectric layer 61 covering the conductor 5; A first conductive layer 71 is formed on one side, the first conductive layer 71 covers the first dielectric layer 61 , and the first conductive layer 71 can be used to form the second electrode of the capacitor structure. Wherein, the first conductive layer 71 may be formed by a coating process, thereby forming a film layer at the level of the upper surface. A plurality of capacitor structures in the semiconductor device may share the first conductive layer 71 as a common electrode.
  • the manufacturing method may include forming a first dielectric layer 61 on the surface of the conductor 5, the first dielectric layer 61 covering the conductor 5; A first conductive layer 71 is formed on the side, and the first conductive layer 71 covers the first dielectric layer 61 .
  • the first conductive layer 71 can be formed by an evaporation process, so as to form a film with the same shape as the outer surface of the first dielectric layer 61 .
  • the semiconductor device may further include an electrode connection layer 10 disposed on a side of the first conductive layer away from the substrate and covering the first conductive layer.
  • FIG. 13 is a cross-sectional view of a semi-finished semiconductor device in another exemplary embodiment of the present disclosure along the row/column direction
  • FIG. 14 is another exemplary embodiment of the present disclosure.
  • step S4 forming the annular groove 41 on the side wall of the first through hole 31
  • step S5 forming the annular groove 42 on the side wall of the second through hole 32, in the row-column direction (the row direction is X
  • the orthographic projections of the annular grooves 41 and 42 in the adjacent through holes 31 and 32 in the column direction Y) on the substrate 1 may at least partially overlap. This arrangement can further increase the number of capacitor structures integrated in a limited space.
  • a plurality of the electrical conductors may be used to form a first electrode of the capacitive structure.
  • FIG. 15 it is a cross-sectional view of a semi-finished semiconductor device in another exemplary embodiment of the present disclosure along the row/column direction.
  • the method for fabricating a semiconductor device may further include: forming a third conductive layer between the substrate 1 and the composite layer 2, and performing a patterning process on the third conductive layer, so that a plurality of third conductive layers are formed on the third conductive layer.
  • An independent connection structure 81, the connection structure 81 is used to electrically connect a plurality of the conductors 5 in one of the capacitor structures. As shown in FIG.
  • connection structure 81 to form a first electrode of a capacitance structure.
  • a connection structure 81 may also be connected with other numbers of The electrical conductors 5 are connected, so that the plurality of electrical conductors form the first electrodes of the capacitive structure.
  • the connection structure 81 may also be connected to only one conductor 5 for connecting the conductor 5 and other hierarchical structures (for example, source and drain layers of transistors).
  • forming on the composite layer through holes distributed through a plurality of rows and columns of the composite layer may further include: forming each layer of the first material layer and each layer of the second material
  • the layer is doped with a preset concentration of ions to adjust the etching speed of the first material layer or the second material layer, and the doping ions can be boron or phosphorus.
  • FIG. 16 it is a cross-sectional view of a semi-finished semiconductor device in another exemplary embodiment of the present disclosure along the row/column direction.
  • first through holes 31 are formed on the composite layer, and at the same time, annular grooves 41 are formed on the sidewalls of the first through holes located in the first material layer.
  • FIG. 17 it is a cross-sectional view of a semi-finished semiconductor device in a row/column direction in another exemplary embodiment of the present disclosure.
  • a sacrificial material 9 can be injected into the first through hole to fill the first through hole 31 and the annular groove 41 , and the sacrificial material can increase the rigidity of the semi-finished semiconductor device.
  • the sacrificial material may be BPSG, silicon oxide, or the like.
  • FIG. 18 which is a cross-sectional view of a semi-finished semiconductor device in a row/column direction in another exemplary embodiment of the present disclosure, the second pass through the composite layer may be formed on the composite layer.
  • the hole 32 is formed, and an annular groove 42 is formed on the sidewall of the second through hole located in the second material layer through an etching process. Then, a conductive material may be poured into the second through hole 32 to fill the second through hole 32 and the annular groove 42, thereby forming an electrical conductor. Then, the sacrificial material is removed, so that the conductive material is poured into the first through hole 31 to fill the first through hole 31 and the annular groove 41 , thereby forming an electrical conductor.
  • FIG. 19 is an exemplary embodiment of the disclosed semiconductor device along the row/column direction.
  • Cross-sectional view FIG. 20 is a top view of an exemplary embodiment of the disclosed semiconductor device.
  • the semiconductor device includes a plurality of capacitor structures, and the semiconductor device further includes: a substrate 1 and a plurality of conductors 5 .
  • a plurality of electrical conductors 5 are used to form the first electrodes of the capacitor structure, and the plurality of electrical conductors 5 are distributed on one side of the substrate 1 in rows and columns.
  • Each of the electrical conductors 5 includes a cylindrical body 51 and a plurality of annular protrusions 52 .
  • the axial direction Z of the cylindrical body 51 may be perpendicular to the substrate 1 ; the annular protrusions 52 may be arranged around the circumference of the cylindrical body 51 , and the protrusions of the annular protrusions 52 The direction may be parallel to the substrate 1, and a plurality of the annular protrusions 52 may be spaced along the axial direction of the cylindrical body 51; wherein, in the row and column direction (row direction is X, column direction is Y)
  • the annular protrusions of the adjacent conductors may be staggered in the vertical direction to the substrate, that is, the annular protrusions of the adjacent conductors in the row and column direction will not be located on the same horizontal plane. parallel to the substrate 1 .
  • the axial direction of the cylindrical body 51 may also intersect the substrate at other angles.
  • the cylindrical body may be cylindrical.
  • the annular protrusions adjacent to the conductors in the row and column directions are staggered in the vertical direction to the substrate, so that the semiconductor device can be integrated in a limited space More capacitive structures.
  • the annular protrusion can increase the surface area of the first electrode, thereby increasing the capacitance value of the capacitance structure.
  • the orthographic projections of the annular protrusions 52 of the adjacent conductors on the substrate may at least partially overlap. This arrangement can further increase the number of capacitor structures integrated in a limited space.
  • each of the electrical conductors may be used to form the first part of the capacitor structure. an electrode.
  • the semiconductor device may further include: a first dielectric layer 61 and a first conductive layer 71 .
  • the first dielectric layer 61 covers the conductor 5 ; the first conductive layer 71 is located on the side of the first dielectric layer 61 away from the substrate 1 and covers the first dielectric layer 61 for A second electrode of the capacitive structure is formed.
  • FIG. 22 which is a cross-sectional view along the row/column direction in an exemplary embodiment of the semiconductor device of the present disclosure
  • a plurality of the electrical conductors 5 may be used to form a
  • the first electrode of the capacitor structure the semiconductor device may further include an electrical connection layer 81, the electrical connection layer 81 is located between the substrate 1 and the conductor 5, and is used to electrically connect one of the capacitor structures. a plurality of the electrical conductors.
  • the semiconductor device may further include: a second dielectric layer 62 and a second conductive layer 72, the second dielectric layer 62 covers the conductor 5 and the electrical connection layer 81; the second conductive layer 72 is located on the The side of the dielectric layer 62 facing away from the substrate and covering the second dielectric layer 62 is used to form the second electrode of the capacitor structure.
  • the electrical connection layer 81 may also be connected to only one conductor 5 for connecting the conductor 5 and other hierarchical structures (eg, source and drain layers of transistors).
  • each of the annular protrusions may have the same or different protrusion sizes along a direction perpendicular to the side surface of the cylindrical body.
  • the material of the electrical conductor may include one or more of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon.
  • the semiconductor device may also include other components integrated between the substrate and the conductor 5 , such as transistors and the like.

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

本公开涉及存储技术领域，提出一种半导体器件及其制作方法，该半导体器件包括：衬底、多个导电体。多个导电体用于形成电容结构的第一电极，且多个导电体行列分布于衬底的一侧。每个导电体包括：柱形主体、多个环形凸起部。所述柱形主体的轴向与所述衬底相交；所述环形凸起部环绕所述柱形主体的周向设置，且所述环形凸起部的凸起方向与所述衬底平行，多个所述环形凸起部沿所述柱形主体的轴向间隔分布；其中，在行列方向上相邻所述导电体的环形凸起部在与所述衬底垂直方向上相错设置。该半导体器件可以在较小的空间内集成较多的电容结构，或在相同尺寸相同电容结构个数情况下集成电容值较大的电容结构。

Description

半导体器件及其制作方法
相关申请的交叉引用
本申请要求于2020年07月17日递交的、名称为《半导体器件及其制作方法》的中国专利申请第202010692526.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及存储技术领域，尤其涉及一种半导体器件及其制作方法。
背景技术
存储器通常由多个存储单元组成，每个存储单元包括有电容结构，每个电容结构能够存储逻辑“1”或“0”。相关技术中，限于光刻工艺等因素的限制，存储器在有限尺寸内仅能形成较少的电容结构，或仅能形成电容值较小的电容结构。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种半导体器件，该半导体器件包括多个电容结构，该半导体器件还包括：衬底、多个导电体。多个导电体用于形成所述电容结构的第一电极，且多个所述导电体行列分布于所述衬底的一侧。每个所述导电体包括：柱形主体、多个环形凸起部。所述柱形主体的轴向与所述衬底相交；所述环形凸起部环绕所述柱形主体的周向设置，且多个所述环形凸起部沿所述柱形主体的轴向间隔分布；其中，在行列方向上相邻所述导电体的环形凸起部在与所述衬底垂直方向上相错设置。
本公开一种示例性实施例中，且相邻所述导电体的环形凸起部在所述衬底的正投影至少部分重合。
本公开一种示例性实施例中，每个所述导电体用于形成一个所述电容结构的第一电极。
本公开一种示例性实施例中，多个所述导电体用于形成一个所述电容结构的第一电极。
本公开一种示例性实施例中，所述半导体器件还包括电连接层，电连接层位于所述衬底和所述导电体之间，用于电连接一个或多个所述电容结构中的多个所述导电体。
本公开一种示例性实施例中，所述半导体器件还包括：第一介电层、第一导电层。第一介电层覆盖所述导电体；第一导电层位于所述第一介电层背离所述衬底的一侧，且覆盖所述第一介电层，用于形成所述电容结构的第二电极。
本公开一种示例性实施例中，所述半导体器件还包括电极连接层，电极连接层设 置于所述第一导电层背离所述衬底的一侧，且覆盖所述第一导电层。
本公开一种示例性实施例中，在所述导电体中，各个所述环形凸起部沿与所述柱形主体侧面垂直的方向凸起尺寸相同或不同。
本公开一种示例性实施例中，所述导电体的材料包括：钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅一种或多种。
根据本公开的一个方面，提供一种半导体器件制作方法，所述半导体器件包括多个电容结构，该方法包括：
提供一衬底；
在所述衬底上复合层，所述复合层包括依次交替层叠设置的第一材料层、第二材料层；
在所述复合层上形成贯穿所述复合层的多个行列分布的通孔，多个所述通孔包括多个第一通孔和多个第二通孔，每个所述第一通孔在行列方向上仅与所述第二通孔相邻，每个所述第二通孔在行列方向上仅与第一通孔相邻；
向第一通孔注入第一刻蚀液，所述第一刻蚀液对所述第一材料层的刻蚀速度大于所述第一刻蚀液对所述第二材料层的刻蚀速度，从而在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽；
向第二通孔注入第二刻蚀液，所述第二刻蚀液对所述第二材料层的刻蚀速度大于所述第二刻蚀液对所述第一材料层的刻蚀速度，从而在所述第二通孔位于所述第二材料层的侧壁形成环形凹槽；
向所述通孔中填充导电材料，以在每个通孔内形成导电体，所述导电体用于形成所述电容结构的第一电极。
本公开一种示例性实施例中，在行列方向上相邻的所述通孔内的所述环形凹槽在所述衬底的正投影至少部分重合。
本公开一种示例性实施例中，所述第一材料层的材料为二氧化硅，所述第二材料层的材料为氮化硅；所述第一刻蚀液为氢氟酸，所述第二刻蚀液为磷酸。
本公开一种示例性实施例中，向所述通孔中填充导电材料，之后还包括：
去除所述第一材料层、第二材料层；
在每个所述导电体表面形成第一介电层；
在所述第一介电层背离所述衬底的一侧形成第一导电层，所述第一导电层覆盖所述第一介电层，所述第一导电层用于形成所述电容结构的第二电极。
本公开一种示例性实施例中，所述半导体器件制作方法还包括：
在所述衬底与所述复合层之间形成第三导电层；
对所述第三导电层进行构图工艺，以使第三导电层形成多个独立的连接结构，所述连接结构用于电连接一个或多个所述电容结构中的多个所述导电体；
本公开一种示例性实施例中，在所述复合层上形成贯穿所述复合层的多个行列分 布的通孔，之前还包括：
对各层所述第一材料层和各层所述第二材料层进行预设浓度的离子掺杂，以调节第一材料层或第二材料层的刻蚀速度。
本公开一种示例性实施例中，先在所述复合层上形成第一通孔，并在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽，然后再在所述复合层上形成贯穿所述复合层的所述第二通孔；
且在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽之后，在所述复合层上形成贯穿所述复合层的所述第二通孔之前，还包括：
向所述第一通孔内注入牺牲材料。
本公开一种示例性实施例中，先向所述第二通孔填充导电材料，然后向所述第一通孔填充导电材料；
向所述第二通孔填充导电材料之后，还包括：
去除所述牺牲材料。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-5为相关技术中半导体器件制造流程中各阶段的结构示意图；
图6为相关技术中半导体器件的俯视图；
图7为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图8为本公开一种示例性实施例中半导体器件半成品的俯视图；
图9为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图10为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图11为本公开一种示例性实施例中半导体器件半成品的俯视图；
图12a为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图12b为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图13为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图14为本公开另一种示例性实施例中半导体器件半成品的俯视图；
图15为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图16为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图17为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图18为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图；
图19为本公开半导体器件一种示例性实施例中沿行/列方向的剖视图；
图20为本公开半导体器件一种示例性实施例中的俯视图；
图21为本公开半导体器件一种示例性实施例中沿行/列方向的剖视图；
图22为本公开半导体器件一种示例性实施例中沿行/列方向的剖视图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，半导体器件通常由多个存储单元组成，每个存储单元包括有电容结构，每个电容结构能够存储逻辑“1”或“0”。相关技术提出一种半导体器件制造方法，如图1-5所示，为相关技术中半导体器件制造流程中各阶段的结构示意图。如图1所示，相关技术提供的半导体器件制作方法包括：在衬底1上形成交替层叠设置的多层第一材料层2、第二材料层3，通过刻蚀工艺在第一材料层2、第二材料层3上形成多个阵列分别的通孔4。如图2所示，向通孔4灌注刻蚀液，该刻蚀液对第二材料层3的刻蚀速度大于对第一材料层2的刻蚀速度，从而可以在通孔4内壁位于第二材料层的位置形成环形凹槽5。如图3所示，在通孔4、凹槽5中填充导电材料从而形成导电体6，导电体6包括填充于通孔4中的柱形主体61和填充于凹槽5的环形凸起部62。如图4所示，去除多层第一材料层2、第二材料层3。其中，导电体6可以作为电容结构的第一电极。此外，如图5所示，该制作方法还可以包括在导电体6的表面形成介电层7，在介电层7背离衬底1的一侧形成导电层8，导电层8可以形成电容结构的第二电极。其中，每个导电体6可以与导电层8形成一个电容结构。应该理解的是，多个导电体6也可以相互电连接，从而与导电层8形成一个电容结构。如图6所示，为相关技术中半导体器件的俯视图，在刻蚀环形凹槽5时，为了避免沿行列方向相邻的环形凹槽5相互连通，需要在沿行列方向相邻的通孔4之间预留较大的距离，从而使得沿行列方向相邻的凹槽5之间具有一定的距离S。相关技术中，由于相邻的凹槽5之间具有一定的距离S，从而该该半导体器件中电容结构的集成度较低，即半导体器件在有限尺寸内仅能形成较少的电容结构。
基于此，本示例性实施例提供一种半导体器件制作方法，所述半导体器件包括多个电容结构，该方法包括：
步骤S1：提供一衬底；
步骤S2：在所述衬底上复合层，所述复合层包括依次交替层叠设置的第一材料层、 第二材料层；
步骤S3：在所述复合层上形成贯穿所述复合层的多个行列分布的通孔，多个所述通孔包括多个第一通孔和多个第二通孔，每个所述第一通孔在行列方向上与所述第二通孔相邻，每个所述第二通孔在行列方向上与第一通孔相邻；
步骤S4：向第一通孔注入第一刻蚀液，所述第一刻蚀液对所述第一材料层的刻蚀速度大于所述第一刻蚀液对所述第二材料层的刻蚀速度，从而在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽；
步骤S5：向第二通孔注入第二刻蚀液，所述第二刻蚀液对所述第二材料层的刻蚀速度大于所述第二刻蚀液对所述第一材料层的刻蚀速度，从而在所述第二通孔位于所述第二材料层的侧壁形成环形凹槽；
步骤S6：向所述通孔中填充导电材料，以在每个通孔内形成导电体，所述导电体用于形成所述电容结构的第一电极。
以下对上述步骤进行详细说明：
如图7所示，为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。步骤S1包括：提供一衬底1。步骤S2包括：在所述衬底1上复合层2，所述复合层2可以包括依次交替层叠设置的第一材料层21、第二材料层22。其中，第一材料层21和第二材料层22可以分别为多层，第一材料层21和第二材料层22的层数可以相同也可以不同。复合层2面向衬底的最底层可以为第一材料层21也可以为第二材料层22。如图7、8所示，图8为本公开一种示例性实施例中半导体器件半成品的俯视图。步骤S3包括在所述复合层2上形成贯穿所述复合层的多个行列分布的通孔，多个所述通孔可以包括多个第一通孔31和多个第二通孔32，每个所述第一通孔31在行列方向上与所述第二通孔32相邻，每个所述第二通孔32在行列方向上与第一通孔31相邻。其中，行方向可以为X，列方向可以为Y。第一通孔31和第二通孔32可以为圆柱形通孔，其开口尺寸可以相同。其中，通孔可以通过干刻技术、等离子体蚀刻技术、湿刻技术形成，为使得通孔在复合层2层叠方向上的开口尺寸相近，通孔的刻蚀工艺可以优选干刻技术或等离子体蚀刻技术。
如图9所示，为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。步骤S4包括向第一通孔31注入第一刻蚀液，所述第一刻蚀液对所述第一材料层的刻蚀速度大于所述第一刻蚀液对所述第二材料层的刻蚀速度，从而在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽41。步骤S5包括向第二通孔32注入第二刻蚀液，所述第二刻蚀液对所述第二材料层的刻蚀速度大于所述第二刻蚀液对所述第一材料层的刻蚀速度，从而在所述第二通孔位于所述第二材料层的侧壁形成环形凹槽42。本示例性实施例中，所述第一材料层的材料可以为二氧化硅，所述第二材料层的材料可以为氮化硅；所述第一刻蚀液可以为氢氟酸，所述第二刻蚀液可以为磷酸。应该理解的是，在其他示例性实施例中，第一材料层、第二材料层还可以由其他材料组成， 相应的，第一刻蚀液、第二刻蚀液还可以为其他刻蚀液。
如图10所示，为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。步骤S6包括向所述通孔中填充导电材料，导电材料可以填充于整个通孔和凹槽内，以在每个通孔内形成导电体5，每个所述导电体5可以用于形成所述电容结构的第一电极。导电体5可以包括填充于通孔中的柱形主体51和填充于环形凹槽中的环形凸起部52。其中，导电体的材料可以包括：钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或多种。
如图11所示，为本公开一种示例性实施例中半导体器件半成品的俯视图。对比图6、图11可以看出，即使在图11中，沿行列方向(行方向X，列方向Y)相邻的环形凸起部52在衬底的正投影之间的距离较小，但是根据图10可以看出，沿行列方向相邻的环形凸起部52之间具有较大的预留空间，即本示例性实施例中，刻蚀环形凹槽41、42时，环形凹槽41、42之间预留有防止刻穿的安全距离。显然，根据图11可以看出，本示例性实施例提供的半导体器件通过将在行列方向上相邻所述导电体的环形凸起部在与所述衬底垂直方向上相错设置，从而使得半导体器件在有限的空间内可以集成更多的电容结构。此外，环形凸起部可以增加第一电极的表面积，从而增加电容结构的电容值。
如图12a所示，为本公开一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。该制作方法还可以包括去除第一材料层21和第二材料层22。其中，可以通过第一刻蚀液、第二刻蚀液交替刻蚀以去除第一材料层21和第二材料层22。该制作方法还可以包括在导电体5表面形成第一介电层61，所述第一介电层61覆盖所述导电体5；在所述第一介电层61背离所述衬底1的一侧形成第一导电层71，所述第一导电层71覆盖所述第一介电层61，所述第一导电层71可以用于形成所述电容结构的第二电极。其中，第一导电层71可以通过涂覆工艺形成，从而形成上表面水平的膜层。该半导体器件中的多个电容结构可以共用第一导电层71为公共电极。
如图12b所示，为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。该制作方法可以包括在导电体5表面形成第一介电层61，所述第一介电层61覆盖所述导电体5；在所述第一介电层61背离所述衬底1的一侧形成第一导电层71，所述第一导电层71覆盖所述第一介电层61。该第一导电层71可以通过蒸镀工艺形成，从而形成与第一介电层61外表面形状相同的膜层。所述半导体器件还可以包括电极连接层10，电极连接层10设置于所述第一导电层背离所述衬底的一侧，且覆盖所述第一导电层。
本公开的一种示例性实施例中，如图13、14所示，图13为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图，图14为本公开另一种示例性实施例中半导体器件半成品的俯视图。在步骤S4：在第一通孔31的侧壁上形成环形凹槽41，以及步骤S5：在第二通孔32的侧壁上形成环形凹槽42时，在行列方向(行方向 为X，列方向为Y)上相邻的所述通孔31、32内的所述环形凹槽41、42在所述衬底1的正投影可以至少部分重合。该设置可以进一步提高有限空间内电容结构的集成数量。
本公开的一种示例性实施例中，多个所述导电体可以用于形成一个所述电容结构的第一电极。相应的，如图15所示，为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。该半导体器件制作方法还可以包括：在所述衬底1与所述复合层2之间形成第三导电层，以及对所述第三导电层进行构图工艺，以使第三导电层形成多个独立的连接结构81，所述连接结构81用于电连接一个所述电容结构中的多个所述导电体5。如图15所示，两个导电体5通过一个连接结构81连接，从而形成一个电容结构的第一电极，应该理解的是，在其他示例性实施例中，一个连接结构81还可以与其他数量的导电体5连接，从而使得多个导电体形成电容结构的第一电极。需要说明的是，连接结构81还可以仅与一个导电体5连接，用于连接导电体5和其他层级结构(例如，晶体管的源漏层)。
本示例性实施例中，在所述复合层上形成贯穿所述复合层的多个行列分布的通孔，之前还可以包括：对各层所述第一材料层和各层所述第二材料层进行预设浓度的离子掺杂，以调节第一材料层或第二材料层的刻蚀速度，掺杂离子可以为硼或磷。
本示例性实施例中，如图7所示，在复合层2上形成通孔后，该半导体器件半成品的刚度降低，在进行以后工艺流程时，容易受到外力损坏。本公开一种示例性实施例中，如图16所示，为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。该半导体器件制作方法可以先在复合层上形成第一通孔31，同时在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽41。如图17所示，为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图。然后，可以向所述第一通孔内注入牺牲材料9，以填充第一通孔31和环形凹槽41，该牺牲材料可以增加半导体器件半成品的刚度。牺牲材料可以为BPSG、氧化硅等。再然后，如图18所示，为本公开另一种示例性实施例中半导体器件半成品沿行/列方向的剖视图，可以在所述复合层上形成贯穿所述复合层的所述第二通孔32，并通过刻蚀工艺在所述第二通孔位于所述第二材料层的侧壁形成环形凹槽42。再然后，可以向第二通孔32灌注导电材料以填充第二通孔32、环形凹槽42，从而形成导电体。再然后，去除牺牲材料，以向第一通孔31灌注导电材料以填充第一通孔31、环形凹槽41，从而形成导电体。
本公开还提供一种半导体器件，该半导体器件可以通过上述的半导体器件制作方法形成，如图19、20所示，图19为本公开半导体器件一种示例性实施例中沿行/列方向的剖视图，图20为本公开半导体器件一种示例性实施例中的俯视图。该半导体器件包括多个电容结构，该半导体器件还包括：衬底1、多个导电体5。多个导电体5用于形成所述电容结构的第一电极，且多个所述导电体5行列分布于所述衬底1的一侧。每个所述导电体5包括：柱形主体51、多个环形凸起部52。所述柱形主体51的轴向 Z可以与所述衬底1垂直；所述环形凸起部52可以环绕所述柱形主体51的周向设置，且所述环形凸起部52的凸起方向可以与所述衬底1平行，多个所述环形凸起部52可以沿所述柱形主体51的轴向间隔分布；其中，在行列方向(行方向为X，列方向为Y)上相邻所述导电体的环形凸起部在与所述衬底垂直方向上可以相错设置，即在行列方向上相邻所述导电体的环形凸起部不会位于同一水平面上，该水平面与衬底1平行。其中，柱形主体51的轴向还可以与所述衬底以其他角度相交。柱形主体可以为圆柱形。
本示例性实施例提供的半导体器件通过将在行列方向上相邻所述导电体的环形凸起部在与所述衬底垂直方向上相错设置，从而使得半导体器件在有限的空间内可以集成更多的电容结构。此外，环形凸起部可以增加第一电极的表面积，从而增加电容结构的电容值。
本示例性实施例中，如图19、20所示，相邻所述导电体的环形凸起部52在所述衬底的正投影可以至少部分重合。该设置可以进一步提高有限空间内电容结构的集成数量。
本示例性实施例中，如图21所示，为本公开半导体器件一种示例性实施例中沿行/列方向的剖视图，每个所述导电体可以用于形成一个所述电容结构的第一电极。所述半导体器件还可以包括：第一介电层61、第一导电层71。第一介电层61覆盖所述导电体5；第一导电层71位于所述第一介电层61背离所述衬底1的一侧，且覆盖所述第一介电层61，用于形成所述电容结构的第二电极。
本公开的一种示例性实施例中，如图22所示，为本公开半导体器件一种示例性实施例中沿行/列方向的剖视图，多个所述导电体5可以用于形成一个所述电容结构的第一电极，所述半导体器件还可以包括电连接层81，电连接层81位于所述衬底1和所述导电体5之间，用于电连接一个所述电容结构中的多个所述导电体。同样的，所述半导体器件还可以包括：第二介电层62、第二导电层72，第二介电层62覆盖所述导电体5和所述电连接层81；第二导电层72位于所述介电层62背离所述衬底的一侧，且覆盖所述第二介电层62，用于形成所述电容结构的第二电极。需要说明的是，电连接层81还可以仅与一个导电体5连接，用于连接导电体5和其他层级结构(例如，晶体管的源漏层)。
本示例性实施例中，在所述导电体中，各个所述环形凸起部沿与所述柱形主体侧面垂直的方向凸起尺寸可以相同或不同。
本示例性实施例中，所述导电体的材料可以包括：钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅一种或多种。
应该理解的是，在其他示例性实施例中，该半导体器件还可以包括集成于衬底与导电体5之间的其他元器件，例如，晶体管等。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用 途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (12)

  1. 一种半导体器件，包括多个电容结构，其中，包括：
    衬底；
    多个导电体，用于形成所述电容结构的第一电极，多个所述导电体行列分布于所述衬底的一侧，且每个所述导电体包括：
    柱形主体，所述柱形主体的轴向与所述衬底相交；
    多个环形凸起部，所述环形凸起部环绕所述柱形主体的周向设置，且多个所述环形凸起部沿所述柱形主体的轴向间隔分布；
    其中，在行列方向上相邻所述导电体的环形凸起部在与所述衬底垂直方向上相错设置。
  2. 根据权利要求1所述的半导体器件，其中，在行列方向上相邻所述导电体的环形凸起部在所述衬底的正投影至少部分重合。
  3. 根据权利要求1或2所述的半导体器件，其中，所述半导体器件还包括：
    第一介电层，覆盖所述导电体；
    第一导电层，覆盖所述第一介电层，用于形成所述电容结构的第二电极。
  4. 根据权利要求1或2所述的半导体器件，其中，所述半导体器件还包括：
    电连接层，位于所述衬底和所述导电体之间，用于电连接一个或多个所述导电体。
  5. 根据权利要求3所述的半导体器件，其中，所述半导体器件还包括：
    电极连接层，设置于所述第一导电层背离所述衬底的一侧，且覆盖所述第一导电层。
  6. 一种半导体器件制作方法，所述半导体器件包括多个电容结构，其中，包括：
    提供衬底；
    在所述衬底上复合层，所述复合层包括依次交替层叠设置的第一材料层、第二材料层；
    在所述复合层上形成贯穿所述复合层的多个行列分布的通孔，多个所述通孔包括多个第一通孔和多个第二通孔，每个所述第一通孔在行列方向上与所述第二通孔相邻，每个所述第二通孔在行列方向上与第一通孔相邻；
    向第一通孔注入第一刻蚀液，所述第一刻蚀液对所述第一材料层的刻蚀速度大于所述第一刻蚀液对所述第二材料层的刻蚀速度，从而在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽；
    向第二通孔注入第二刻蚀液，所述第二刻蚀液对所述第二材料层的刻蚀速度大于所述第二刻蚀液对所述第一材料层的刻蚀速度，从而在所述第二通孔位于所述第二材料层的侧壁形成环形凹槽；
    向所述通孔中填充导电材料，以在每个通孔内形成导电体，所述导电体用于形成所述电容结构的第一电极。
  7. 根据权利要求6所述的半导体器件制作方法，其中，
    所述第一材料层的材料为二氧化硅，所述第二材料层的材料为氮化硅；
    所述第一刻蚀液为氢氟酸，所述第二刻蚀液为磷酸。
  8. 根据权利要求6或7所述的半导体器件制作方法，其中，向所述通孔中填充导电材料，之后还包括：
    去除所述第一材料层、第二材料层；
    在每个所述导电体表面形成第一介电层；
    在所述第一介电层背离所述衬底的一侧形成第一导电层，所述第一导电层覆盖所述第一介电层，所述第一导电层用于形成所述电容结构的第二电极。
  9. 根据权利要求6或7所述的半导体器件制作方法，其中，所述半导体器件制作方法还包括：
    在所述衬底与所述复合层之间形成第三导电层；
    对所述第三导电层进行构图工艺，以使第三导电层形成多个分离的连接结构，所述连接结构用于电连接所述电容结构中的一个或多个所述导电体。
  10. 根据权利要求6或7所述的半导体器件制作方法，其中，在所述复合层上形成贯穿所述复合层的多个行列分布的通孔，之前还包括：
    对各层所述第一材料层和各层所述第二材料层进行预设浓度的离子掺杂，以调节第一材料层或第二材料层的刻蚀速度。
  11. 根据权利要求6或7所述的半导体器件制作方法，其中，先在所述复合层上形成第一通孔，并在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽，然后再在所述复合层上形成贯穿所述复合层的所述第二通孔；
    且在所述第一通孔位于所述第一材料层的侧壁形成环形凹槽之后，在所述复合层上形成贯穿所述复合层的所述第二通孔之前，还包括：
    向所述第一通孔内注入牺牲材料。
  12. 根据权利要求11所述的半导体器件制作方法，其中，先向所述第二通孔填充导电材料，然后向所述第一通孔填充导电材料；
    向所述第二通孔填充导电材料之后，还包括：
    去除所述牺牲材料。
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