WO2022183645A1 - 存储器及其制备方法 - Google Patents

存储器及其制备方法 Download PDF

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Publication number
WO2022183645A1
WO2022183645A1 PCT/CN2021/103739 CN2021103739W WO2022183645A1 WO 2022183645 A1 WO2022183645 A1 WO 2022183645A1 CN 2021103739 W CN2021103739 W CN 2021103739W WO 2022183645 A1 WO2022183645 A1 WO 2022183645A1
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Prior art keywords
word line
active regions
layer
isolation layer
substrate
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PCT/CN2021/103739
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English (en)
French (fr)
Inventor
陈涛
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长鑫存储技术有限公司
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Priority to US17/447,198 priority Critical patent/US20220285352A1/en
Publication of WO2022183645A1 publication Critical patent/WO2022183645A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory and a preparation method thereof.
  • DRAM Dynamic random access memory
  • a shallow trench isolation structure is generally formed to define an active region, and then buried word lines are formed in the active region by etching, and bit line contact columns are formed between the buried word lines. Plug, and then connect each line to contact the plunger through the bit line; and the mainstream dynamic random access memory in the prior art is a 3HPAA multiplied by 2HPWL structure, 3HPAA multiplied by 2HPWL to determine the area of a bit cell (full English name is cell bit), 3HPAA multiplied by 2HPWL refers to 3 times the half pitch of the active region (full name in English is active region, abbreviated in English is AA) multiplied by 2 times the word line (full name in English is word line, abbreviated in English) is the half pitch of WL).
  • the DRAM integration level of this structure is low.
  • embodiments of the present application provide a memory and a preparation method thereof, so as to improve the integration degree of the memory.
  • a first aspect of the embodiments of the present application provides a memory, including a substrate, an isolation layer disposed on the substrate, a plurality of active regions arranged in a row and a column array in the isolation layer, a plurality of active regions and an isolation layer
  • a plurality of word lines are formed in the layer; the plurality of word lines are arranged along the row direction of the plurality of active regions, each word line is S-shaped, and each word line includes a gate electrode arranged in the active region and a gate electrode arranged in the active region.
  • each word line is formed by connecting a plurality of gates and a plurality of word line structures arranged at intervals in turn, and the plurality of gates included in each word line are arranged in corresponding adjacent two columns In the active region, any two adjacent gates in each word line are arranged in the corresponding two adjacent rows of active regions.
  • the isolation layer of the substrate is provided with a plurality of active regions arranged in rows and columns, the isolation layer and the active region are provided with a plurality of word lines, and each word line is S-shaped, Each word line is sequentially connected by a plurality of gates and a plurality of word line structures arranged at intervals, and the plurality of gates in each word line are alternately arranged in the corresponding two adjacent columns of active regions, and each Any two adjacent gates in the word line are arranged in the corresponding adjacent two rows of active regions, so that the number of active regions arranged in the isolation layer on the substrate of unit size is more, and the subsequent arrangement is the same as the active region. After one-to-one correspondence of capacitors, the integration of the memory is higher.
  • the word line structure includes a first word line structure and a second word line structure, and in each word line, one end of any adjacent first word line structure and one end of the second word line structure pass through The corresponding gates are electrically connected, the first word line structure extends along a first direction, the first direction is arranged at an acute angle with the row and column directions of the plurality of active regions, the second word line structure extends along the second direction, and the second word line structure extends along the second direction.
  • the directions are set at acute angles to the row and column directions of the plurality of active regions.
  • the word line includes a metal layer and a dielectric layer
  • the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer
  • the top surface of the first dielectric layer is provided with a metal layer and a second dielectric layer
  • the first dielectric layer is provided with a metal layer and a second dielectric layer.
  • Two dielectric layers are disposed on opposite sides of the metal layer, and a third dielectric layer is disposed on the top surface of the metal layer and the top surface of the second dielectric layer.
  • a plurality of bit lines are further provided on the substrate, each bit line extends along the row direction of the plurality of active regions, and the plurality of bit lines are arranged along the column direction of the plurality of active regions.
  • a plurality of bit line contact plugs are distributed on the bit line at intervals, the plurality of bit line contact plugs are arranged along the row direction of the plurality of active regions, and the plurality of bit line contact plugs are all located in the isolation layer Inside, the bottom end of each bit line contact plunger is electrically connected with the corresponding bit line, and the top end of each bit line contact plunger is electrically connected with the corresponding active region.
  • a plurality of node contact plugs are disposed at the end of each word line away from the substrate, each node contact plug is electrically connected to the corresponding active region, and the node contact plug and the bit line contact plug are one by one. correspond.
  • a second aspect of the embodiments of the present application provides a method for fabricating a memory, which includes the following steps: providing a substrate; forming an isolation layer on the substrate; forming a plurality of active regions arranged in rows and columns in the isolation layer ; A plurality of word lines are formed in the isolation layer and the active region, and the plurality of word lines are arranged along the row direction of the plurality of active regions, each word line is S-shaped, and each word line is arranged in the active region.
  • each word line is formed by connecting a plurality of gates and a plurality of word line structures arranged at intervals in turn, and the plurality of gates included in each word line are located in the corresponding Two adjacent columns of active regions, and any two adjacent gates in each word line are located in corresponding two adjacent rows of active regions.
  • an isolation layer is arranged on a substrate, an active region is arranged in the isolation layer, word lines are arranged in the isolation layer and the active region, and a plurality of word lines are arranged along a plurality of active regions.
  • the row direction of the region is arranged, each word line is S-shaped, the plurality of gates included in each word line are located in the corresponding two adjacent columns of active regions, and any adjacent two in each word line.
  • the gates are located in the corresponding two adjacent rows of active regions, so that in the formed memory, the number of active regions set in the isolation layer on the substrate of unit size is more, and the subsequent settings correspond to the active regions one-to-one After the capacitor, the integration of the memory is higher.
  • forming a plurality of active regions arranged in a row and column array in the isolation layer includes: forming a plurality of concave holes with openings facing away from the substrate in the isolation layer, and filling each concave hole Second polysilicon, etching the second polysilicon in each recessed hole, retaining part of the second polysilicon on the sidewall of each recessed hole to form an active region, the active regions remaining in the plurality of recessed holes Arrays are arranged and isolated from each other.
  • forming a plurality of word lines in the isolation layer and the active region includes: forming a plurality of word line trenches with notches facing away from the substrate in the isolation layer and the active region, each word line trench including a plurality of word line trenches A plurality of first word line grooves and a plurality of second word line grooves arranged at intervals, any two adjacent first word line grooves and second word line grooves have an included angle and pass through a corresponding one of the groove holes Connecting; forming a metal layer and a dielectric layer covering the bottom surface, top surface and two opposite sides of the metal layer in the word line groove to form a word line, the word line includes a plurality of first word line structures, a plurality of first word line structures, and a plurality of first word line structures.
  • each first word line structure is formed in a corresponding first word line groove
  • each second word line structure is formed in a corresponding second word line groove
  • each gate Formed in a corresponding concave hole
  • any two adjacent first word line structures and second word line structures are electrically connected through corresponding gates.
  • forming a metal layer and a dielectric layer covering a bottom surface, a top surface and two opposite sides of the metal layer in the word line groove to form a word line includes: forming a first layer at the bottom of the word line groove a dielectric layer; a second dielectric layer is formed on the first dielectric layer in the word line groove, and the second dielectric layer is formed on the sidewall of the active region; on the first dielectric layer in the word line groove, and the second dielectric layer is formed A metal layer is formed on the side of the dielectric layer away from the active region, and the metal layer fills the word line groove; the top of the metal layer is etched back; and a third dielectric layer is formed on the metal layer of the word line groove.
  • the method before the step of forming the isolation layer on the substrate, the method further includes: forming a plurality of bit lines on the substrate, each bit line extending along a row direction of a plurality of active regions, and the plurality of bit lines extending along a plurality of Column-wise arrangement of active regions.
  • the method before forming the plurality of active regions arranged in rows and columns in the isolation layer, the method further includes: depositing a first polysilicon at the bottom of each recess to form a bit line contact plug, The bit line contact plugs are electrically connected to the corresponding bit lines.
  • the method further includes: forming a protective layer on the second polysilicon; Etching the first polysilicon in each recessed hole includes: etching the protective layer and the second polysilicon to form a node contact groove and a word line groove, the node contact groove is located above the word line groove and communicated with the word line groove , the width of the node contact groove is greater than the width of the word line groove, the node contact groove is formed in the protective layer, the word line groove is formed in the isolation layer and in the active region; the word line is formed in the word line groove, and the node contact groove is formed in the node contact groove.
  • a node contact plug is formed in the , and the formed node contact plug is electrically connected to the corresponding active region.
  • forming an isolation layer on the substrate includes: forming an insulating layer on a bottom surface, a top surface and two opposite sides of the bit line, and etching the insulating layer to form the isolation layer.
  • the memory and the preparation method thereof provided by the embodiments of the present application can solve the problems.
  • Other technical problems, other technical features included in the technical solution, and the beneficial effects brought about by these technical features will be described in further detail in the specific embodiments.
  • FIG. 1 is a flowchart of a method for preparing a memory according to an embodiment of the present application
  • Fig. 2 is the preparation flow chart of the bit line in the embodiment of the present application.
  • 3a is a schematic structural diagram of setting bit line grooves on a substrate according to an embodiment of the present application.
  • Fig. 3b is the sectional view of the AA position in Fig. 3a;
  • Fig. 3c is the sectional view of the BB position in Fig. 3a;
  • FIG. 4a is a schematic structural diagram of disposing a first insulating material in a bit line slot according to an embodiment of the present application
  • Fig. 4b is the sectional view of the AA position in Fig. 4a;
  • Figure 4c is a cross-sectional view of the BB position in Figure 4a;
  • FIG. 5a is a schematic structural diagram of the first insulating material in the bit line slot after removing the first insulating material near the slot according to an embodiment of the present application;
  • Fig. 5b is the sectional view of the AA position in Fig. 5a;
  • Figure 5c is a cross-sectional view of the BB position in Figure 5a;
  • FIG. 6a is a schematic structural diagram of a conductive material being arranged in a bit line slot according to an embodiment of the present application
  • Fig. 6b is the sectional view of the AA position in Fig. 6a;
  • Figure 6c is a cross-sectional view of the BB position in Figure 6a;
  • FIG. 7a is a schematic structural diagram of a bit line formed in a bit line groove according to an embodiment of the present application.
  • Figure 7b is a sectional view of the AA position in Figure 7a;
  • Fig. 7c is a sectional view of the BB position in Fig. 7a;
  • Fig. 8 is the preparation flow chart of the isolation layer in the embodiment of the application.
  • FIG. 9a is a schematic structural diagram after disposing a second insulating material in the bit line slot according to an embodiment of the present application.
  • Figure 9b is a sectional view of the AA position in Figure 9a;
  • Figure 9c is a sectional view of the BB position in Figure 9a;
  • FIG. 10a is a schematic structural diagram after removing the second insulating material on the top surface of the substrate according to an embodiment of the present application.
  • Figure 10b is a sectional view at the AA position in Figure 10a;
  • Figure 10c is a cross-sectional view at the BB position in Figure 10a;
  • FIG. 11a is a schematic structural diagram of an embodiment of the present application after removing a part of the substrate
  • Fig. 11b is a sectional view at the AA position in Fig. 11a;
  • Figure 11c is a cross-sectional view at the BB position in Figure 11a;
  • FIG. 12a is a schematic structural diagram of a substrate after a third insulating material is disposed on the substrate in an embodiment of the present application;
  • Figure 12b is a sectional view at the AA position in Figure 12a;
  • Figure 12c is a cross-sectional view at the BB position in Figure 12a;
  • Fig. 13 is the preparation flow chart of the active region in the embodiment of the application.
  • FIG. 14a is a schematic structural diagram of the embodiment of the present application after the concave holes are arranged in the isolation layer;
  • Figure 14b is a sectional view of the AA position in Figure 14a;
  • Figure 14c is a cross-sectional view at the BB position in Figure 14a;
  • 15a is a schematic structural diagram of forming a bit line contact plug in a recess in an embodiment of the present application
  • Figure 15b is a sectional view of the AA position in Figure 15a;
  • Figure 15c is a cross-sectional view at the BB position in Figure 15a;
  • FIG. 16a is a schematic structural diagram after filling polysilicon in the concave hole according to an embodiment of the present application.
  • Figure 16b is a sectional view at the AA position in Figure 16a;
  • Figure 16c is a sectional view at the BB position in Figure 16a;
  • FIG. 17a is a schematic structural diagram after etching polysilicon and disposing a first dielectric layer in an embodiment of the present application
  • Figure 17b is a cross-sectional view at the AA position in Figure 17a;
  • Figure 17c is a sectional view at the BB position in Figure 17a;
  • FIG. 18a is a schematic structural diagram of a metal layer and a second dielectric layer in the concave hole in an embodiment of the present application
  • Figure 18b is a cross-sectional view at the AA position in Figure 18a;
  • Figure 18c is a cross-sectional view at the BB position in Figure 18a;
  • 19a is a schematic structural diagram of a third dielectric layer disposed in the concave hole and forming a node contact plug according to an embodiment of the present application;
  • Figure 19b is a sectional view at the AA position in Figure 19a;
  • Figure 19c is a cross-sectional view at the BB position in Figure 19a;
  • FIG. 20 is a flow chart of the preparation of word lines in an embodiment of the present application.
  • FIG. 21 is a flow chart of the preparation of the medium in the embodiment of the present application.
  • bit line slot 102: bit line slot; 103: first insulating material;
  • a dynamic random access memory generally includes a substrate, an isolation structure disposed in the substrate, and a plurality of active regions disposed in the isolation structure, each active region is provided with a gate, and an isolation structure is disposed in the isolation structure for A word line structure connecting a plurality of gates located in the same column, the gates and the word line structure together form a word line.
  • the isolation structure is also provided with bit line contact plugs in contact with the active regions, and a plurality of bit line contact plugs in contact with the active regions in the same row are connected through the bit lines.
  • Capacitors are also provided on both ends of each active region, and the capacitors are used to store electric charges.
  • embodiments of the present application provide a memory and a method for preparing the same.
  • an isolation layer is provided in the substrate, and the isolation layer is provided with multiple memory cells arranged in rows and columns.
  • each word line is S-shaped, and each word line is connected in turn by a plurality of gates and a plurality of word line structures arranged at intervals, and A plurality of gates in each word line are alternately arranged in the corresponding two adjacent columns of active regions, and any two adjacent gates in each word line are arranged in the corresponding two adjacent rows of active regions , in this way, on a substrate of unit size, the number of correspondingly arranged active regions is larger, the number of capacitors corresponding to the active regions one-to-one is subsequently arranged, and the integration degree of the memory is higher.
  • a method for preparing a memory includes the following steps:
  • S1 Provide a substrate, and the material of the substrate can be a semiconductor substrate material well known to those skilled in the art, such as silicon and germanium.
  • S2 forming an isolation layer on the substrate, and the material of the isolation layer can be silicon dioxide, for example.
  • the method for fabricating the memory before the step of forming the isolation layer on the substrate, the method for fabricating the memory further comprises:
  • J1 A plurality of bit lines are formed on the substrate, each bit line extends along the row direction of the active regions mentioned later, and the plurality of bit lines are arranged along the column direction of the multiple active regions mentioned later.
  • forming a plurality of bit lines on the substrate includes the following steps:
  • J11 A plurality of bit line grooves are formed on the substrate, and the plurality of bit line grooves are arranged in parallel. The structure formed in this step is shown in FIG. 3a, FIG. 3b and FIG. 3c. A plurality of bit line grooves 102 are provided, and each bit line groove 102 extends along the x direction.
  • J12 Filling the first insulating material 103 in each bit line trench 102, the first insulating material 103 is also disposed on the top surface of the substrate 100, the first insulating material 103 can be, for example, oxide, the structure formed in this step is shown in FIG. 4a 4b and 4c, in the structure formed by this step, the bit line trenches 102 are filled with the first insulating material 103, and the top surface of the substrate 100 is also provided with the first insulating material 103.
  • J13 Remove the first insulating material 103 on the top surface of the substrate 100 and a portion of the first insulating material 103 in each bit line slot 102 near the slot.
  • the structure formed by this step is shown in FIG. 5a, FIG. 5b and FIG. 5c , in the structure formed in this step, the top surface of the first insulating material 103 filled in the bit line trench 102 is lower than the top surface of the substrate 100, for example, the depth of the bit line trench 102 is 240-300 nanometers (nm), and the remaining The thickness of the first insulating material 103 is 20-30 nm.
  • a conductive material 104 is provided on the first insulating material 103 in each bit line trench 102 and on the substrate 100.
  • the conductive material 104 can be, for example, tungsten.
  • the structure formed in this step is shown in FIG. 6a, FIG. 6b and FIG. 6c As shown, in the structure formed in this step, the conductive material 104 is provided on the first insulating material 103 in the bit line trench 102 and on the top surface of the substrate 100 .
  • forming the isolation layer 200 on the substrate 100 includes: forming an insulating layer on the bottom surface, the top surface and two opposite sides of the bit line 101 , etching the insulating layer to form the isolation layer 200 , and covering the isolation layer 200
  • the first insulating material 103 is part of the isolation layer 200 on the bottom surface of the bit line 101
  • the second insulating material described below is part of the isolation layer 200 on the top surface of the bit line 101
  • the following second insulating material is part of the isolation layer 200 on the top surface of the bit line 101
  • the three insulating materials are part of the isolation layer 200 on opposite sides of the bit line 101 .
  • an insulating layer is formed on the top surface of the bit line 101 and two opposite sides, and the insulating layer is etched to form the isolation layer 200 , including the following steps:
  • S21 Disposing a second insulating material 105 on the bit line 101 in the bit line trench 102 and on the top surface of the substrate 100.
  • the second insulating material 105 may be, for example, an oxide.
  • the structure formed in this step is shown in FIG. 9a and FIG. 9b And as shown in FIG. 9 c , in the structure formed by this step, the second insulating material 105 is provided on the bit line 101 in the bit line trench 102 and on the top surface of the substrate 100 .
  • S22 Remove the second insulating material 105 on the top surface of the substrate 100, and the top surface of the remaining second insulating material 105 is flush with the top surface of the substrate 100.
  • the structure formed in this step is shown in FIG. 10a, FIG. 10b and FIG. 10c.
  • the first insulating material 103 , the bit line 101 and the second insulating material 105 are stacked in the bit line trench 102 in order from bottom to top, and the top surface of the second insulating material 105 is flat with the top surface of the substrate 100 together.
  • S23 Remove the substrate 100 above the bottom of the bit line trench 102, and retain the first insulating material 103, the bit line 101, the second insulating material 105 and the substrate 100 under the bottom surface of the bit line trench 102.
  • the structure formed by this step is as follows As shown in FIGS. 11a , 11b and 11c , in the structure formed in this step, the top surface of the remaining substrate 100 is flush with the bottom surface of the first insulating material 103 , and the first insulating material 103 is provided with a bit line 101 .
  • a second insulating material 105 is provided on the wire 101 .
  • the third insulating material 106 Disposing the third insulating material 106 on the remaining second insulating material 105 and the remaining substrate 100, the first insulating material 103, the second insulating material 105 and the third insulating material 106 constitute the above insulating layer, and the first insulating material 103 , the second insulating material 105 and the third insulating material 106 remaining after etching to form the isolation layer 200, the third insulating material 106 can be, for example, oxide, the structure formed by this step is shown in FIG. 12a, FIG. 12b and FIG.
  • a first insulating material 103 and a third insulating material 106 are arranged on the substrate 100 at intervals, a bit line 101 is arranged on the first insulating material 103, and a second insulating material 105 is arranged on the bit line 101, The top surface of the second insulating material 105 is flush with the top surface of the third insulating material 106 .
  • forming a plurality of active regions 201 arranged in a row and column array in the isolation layer 200 includes the following steps:
  • FIGS. 14 a , 14 b and 14 c The structures formed in this step are shown in FIGS. 14 a , 14 b and 14 c .
  • the isolation layer 200 is provided with concave holes 202
  • the holes 202 and the concave holes 202 are arranged in a column and row array, the bottom of the concave holes 202 exposes the bit line 101 , and the concave holes 202 in the same row expose the same bit line 101 .
  • S35 Etch the second polysilicon 203 in each concave hole 202, and retain a portion of the second polysilicon 203 on the sidewall of each concave hole 202 to form an active region 201, and there are a plurality of concave holes 202 remaining in the
  • the source regions 201 are arranged in an array and isolated from each other.
  • the second polysilicon 203 can be ion-doped. Please refer to FIG. 17a and FIG. 17b for the structure formed by this step.
  • one active region 201 is formed in each recessed hole 202, and the active region 201 in each recessed hole 202 is disposed in the recessed hole. 202 on the side wall.
  • each concave hole 202 is filled with first polysilicon, the bottom surface of the first polysilicon is in electrical contact with the bit line 101, and the top of the first polysilicon is in electrical contact with the bit line 101.
  • the surface is lower than the top surface of the isolation layer 200 , the first polysilicon formed in the concave hole 202 constitutes the bit line contact plug 107 , and the second polysilicon in step S33 is disposed on the top surface of the bit line contact plug 107 203 , a second polysilicon 203 is formed on the bit line contact plug 107 and fills the concave hole 202 .
  • each concave hole 202 is filled with the second polysilicon 203 and before the second polysilicon 203 in each concave hole 202 is etched, the following steps are further included:
  • S34 forming a protective layer 204 on the second polysilicon 203, the protective layer 204 is also disposed on the isolation layer 200, the material of the protective layer 204 can be silicon nitride, for example, the structure formed in this step is shown in FIG. 16a, FIG. 16b and As shown in FIG. 16c , in the structure formed by this step, the second polysilicon 203 is filled in each concave hole 202 , and a protective layer 204 is provided on the second polysilicon 203 filled in the concave hole 202 and the isolation layer 200 .
  • the second polysilicon 203 in each recessed hole 202 is etched, further comprising:
  • S35 Etch the protective layer 204 and the second polysilicon layer 203 to form a node contact groove and a word line groove, the node contact groove is located above the word line groove and communicated with the word line groove, and the width of the node contact groove is larger than that of the word line groove 206 width, node contact trenches are formed in the protective layer 204, word line trenches are formed in the isolation layer 200 and in the active region 201, word lines are formed in the word line trenches, and node contact plugs are formed in the node contact trenches, And the formed node contact plugs are electrically connected to the corresponding active regions 201 .
  • the structure formed by this step is shown in FIG. 17a, FIG. 17b and FIG. 17c.
  • the isolation layer 200 and the active region 201 are provided with word line grooves 206, and the protective layer 204 is provided with node contact grooves 205.
  • the node contact grooves 205 and the word line The line grooves 206 are connected, and the groove width of the node contact grooves 205 is larger than the width of the word line grooves 206 .
  • the node contact plugs are formed in the node contact grooves 205, and the third polysilicon can be deposited by chemical vapor deposition and prepared by ion doping.
  • each word line is S-shaped, and each word line includes a The gate 208 in the active region 201 and the word line structure 209 disposed in the isolation layer 200, each word line 207 is formed by sequentially connecting a plurality of gates and a plurality of word line structures arranged at intervals, and each word line A plurality of gates included in are located in corresponding two adjacent columns of active regions 201 , and any two adjacent gates in each word line are located in corresponding two adjacent rows of active regions 201 .
  • each word line 207 is formed by a gate 208 and a word line structure 209 connected at intervals, wherein the gate 208 is arranged in the active region 201 , the word line structure 209 is arranged in the isolation layer 200, and the active regions 201 where the gates 208 on each word line 207 are located are located in two adjacent columns correspondingly, and any two adjacent gates on each word line 207
  • the number of rows of the active regions 201 where the poles 208 are located differs by one row.
  • a plurality of word lines 207 are formed in the isolation layer 200 and the active region 201, including:
  • each word line groove includes a plurality of concave holes 202 and a plurality of first word line grooves and a plurality of first word line grooves arranged at intervals two second word line grooves, any two adjacent first word line grooves and second word line grooves have an included angle and are connected through a corresponding concave hole 202; the structures formed in this step are shown in Figure 17a, Figure 17b and As shown in FIG.
  • the recessed hole 202 is provided in the active region 201, the first word line trench 210 and the second word line trench 211 are provided in the isolation layer 200, and the first word line trench 210 and the second word line are provided in the isolation layer 200.
  • the groove 211 has an included angle, and the first word line groove 210 and the second word line groove 211 are communicated through the concave hole 202 .
  • the word line 207 includes a plurality of first word line structures, A plurality of second word line structures and a plurality of gates, each first word line structure is formed in a corresponding one of the first word line grooves 210 , and each second word line structure is formed in a corresponding one of the second word line grooves 211 , each gate is formed in a corresponding concave hole 202 , and any two adjacent first word line structures and second word line structures are electrically connected through corresponding gates. Please refer to FIGS.
  • the gate 208 is disposed in the active region 201
  • the first word line structure 212 is formed in the isolation layer
  • the second word line structure 213 is formed in the second word line trench 211 of the isolation layer 200
  • the first word line structure 212 and the second word line structure 213 are connected through the gate 208 .
  • a metal layer 214 and a dielectric layer 215 covering the bottom surface, top surface and two opposite sides of the metal layer 214 are formed in the word line groove 206 to form the word line 207, including:
  • the first dielectric layer 216 can be, for example, a silicon oxide layer.
  • the structures formed in this step are shown in FIGS. 17 a , 17 b and 17 c , wherein the first dielectric layer is The material of the layer 216 is disposed in the word line grooves 206 , and the height of the first dielectric layer 216 is less than the groove depth of the word line grooves 206 , that is, the top surface of the first dielectric layer 216 is lower than the top surface of the word line grooves 206 .
  • a second dielectric layer 217 is formed on the first dielectric layer 216 in the word line groove 206, and the second dielectric layer 217 is formed on the sidewall of the active region 201;
  • the material of the second dielectric layer 217 can be, for example, silicon oxide layer
  • the second dielectric layer 217 can be prepared by in-situ water vapor method (English name is in-situ steam generation, English abbreviated as ISSG)
  • the thickness of the second dielectric layer 217 can be about 5nm
  • the structure formed in this step can be referred to as 18a , 18b and 18c
  • the second dielectric layer 217 is disposed in the word line groove 206
  • the second dielectric layer 217 is disposed on the first dielectric layer 216
  • S424 Etch back the top of the metal layer 214 .
  • the structure formed in this step can be referred to as FIGS. 19 a , 19 b and 19 c .
  • the top surface of the metal layer 214 is lower than the top surface of the second dielectric layer 217 .
  • a third dielectric layer 218 is formed on the metal layer 214 of the word line groove 206.
  • the material of the third dielectric layer 218 can be silicon oxide, for example.
  • the structures formed in this step are shown in FIG. 19a, FIG. 19b and FIG.
  • the three dielectric layers 218 are disposed on the metal layer 214 and the second dielectric layer 217 .
  • the isolation layer 200 is disposed on the substrate 100, the active region 201 is disposed in the isolation layer 200, the word line 207 is disposed in the isolation layer 200 and the active region 201, and a plurality of The word lines 207 are arranged along the row direction of the plurality of active regions 201 , each word line 207 is S-shaped, and the plurality of gates 208 included in each word line 207 are located in the corresponding two adjacent columns of the active regions 201 , and any two adjacent gates 208 in each word line 207 are located in the corresponding two adjacent rows of active regions 201, so that in the formed memory, on the substrate 100 of unit size, the corresponding active
  • the number of regions 201 is larger, and the number of capacitors corresponding to the active regions 201 one-to-one is subsequently arranged, and the integration degree of the memory is higher.
  • the memory prepared by the memory preparation method of the embodiment of the present application has a structure of 2HPAA by 2HPWL, 2HPAA by 2HPWL determines a bit cell area, and 2HPAA by 2HPWL refers to twice the half pitch of the active area times the half of the word line.
  • the area of the 4F2 memory cell formed by the 2HPAA multiplied by 2HPWL structure will be reduced to about two-thirds of the 6F2 memory cell formed by the 3HPAA multiplied by 2HPWL structure, which is equivalent to the higher storage density and higher integration of the 4F2 memory structure.
  • the memory provided by this embodiment of the present application includes a substrate 100.
  • the material of the substrate 100 may be silicon, germanium, etc., and an isolation layer is provided on the substrate 100 200, the material of the isolation layer 200 can be silicon dioxide, for example, the isolation layer 200 is provided with a plurality of active regions 201 arranged in a row and a column array, and a plurality of active regions 201 are formed in the isolation layer 200.
  • a word line 207, a plurality of word lines 207 are arranged along the row direction of the plurality of active regions 201, each word line 207 is S-shaped, and each word line 207 extends along the column direction of the plurality of active regions 201, each The word line 207 includes a gate electrode 208 arranged in the active region 201 and a word line structure 209 arranged in the isolation layer 200 , and each word line 207 consists of a plurality of gate electrodes 208 and a plurality of word line structures arranged at intervals 209 are connected in sequence, the plurality of gates 208 included in each word line 207 are arranged in the corresponding two adjacent columns of active regions 201, and any two adjacent gates 208 in each word line 207 are arranged in The corresponding adjacent two rows of active regions 201 .
  • the isolation layer 200 on the substrate 100 is provided with a plurality of active regions 201 arranged in rows and columns, and the isolation layer 200 and the active region 201 are provided with a plurality of word lines 207.
  • the word lines 207 are S-shaped, the plurality of gates 208 and the plurality of word line structures 209 included in each word line 207 are arranged at intervals and connected in sequence, and the plurality of gates 208 in each word line 207 are arranged alternately in sequence.
  • any two adjacent gates 208 in each word line 207 are disposed in corresponding two adjacent rows of active regions 201, so that on the substrate 100 of unit size
  • the number of active regions 201 provided in the isolation layer 200 is larger, and the number of capacitors corresponding to the active regions 201 one-to-one is larger, and the integration degree of the memory is higher.
  • the word line structure 209 includes a first word line structure 212 and a second word line structure 213.
  • any adjacent word line One end of the first word line structure 212 and one end of the second word line structure 213 are electrically connected through corresponding gates 208 , the first word line structure 212 extends along a first direction, and the first direction is connected to the plurality of active regions 201 .
  • the row direction and the column direction are arranged at an acute angle
  • the second word line structure 213 extends along the second direction
  • the second direction is arranged at an acute angle with the row direction and the column direction of the plurality of active regions 201
  • the adjacent first word line structures 213 are arranged at an acute angle.
  • An acute angle is formed between 212 and the second word line structure 213 .
  • the word line structure 209 includes a first word line structure 212 and a second word line structure 213, and a gate is connected between one end of the adjacent first word line structure 212 and one end of the second word line structure 213. 208 is connected, and the first word line structure 212 and the second word line structure 213 are arranged at an acute angle, so that the word line 207 can be S-shaped.
  • the word line 207 includes a metal layer 214 and a dielectric layer 215.
  • the dielectric layer 215 includes a first dielectric layer 216, a second dielectric layer 217 and a third dielectric layer 218.
  • the first dielectric layer The top surface of 216 is provided with a metal layer 214 and a second dielectric layer 217, the second dielectric layer 217 is provided on opposite sides of the metal layer 214, and a third dielectric layer is provided on the top surface of the metal layer 214 and the top surface of the second dielectric layer 217 218 , the material of the first dielectric layer 216 , the second dielectric layer 217 and the third dielectric layer 218 can be, for example, silicon dioxide, and the material of the metal layer 214 can be, for example, metal tungsten.
  • a metal layer 214 and a second dielectric layer 217 are disposed on the top surface of the first dielectric layer 216, the second dielectric layer 217 is disposed on two opposite sides of the metal layer 214, and the top surface of the metal layer 214 and the second dielectric layer
  • the third dielectric layer 218 is disposed on the top surface of the layer 217, so that the first dielectric layer 216, the second dielectric layer 217, and the third dielectric layer 218 separate the metal layer 214 from the active region 201, thereby forming a metal oxide semiconductor Field effect transistor structure.
  • a plurality of bit lines 101 are further disposed on the substrate 100 , each bit line 101 extends along the row direction of the plurality of active regions 201 , and the plurality of bit lines 101 extend along a plurality of The active regions 201 are arranged in a column direction.
  • a plurality of bit lines 101 are formed on the substrate 100 , and each bit line 101 extends along the row direction of the plurality of active regions 201 , and the plurality of bit lines 101 extends along the columns of the plurality of active regions 201 .
  • Directional arrangement in this way, achieves electrical connection with the above-formed MOSFET structure.
  • bit line contact plugs 107 are distributed on the bit line 101 at intervals, and the plurality of bit line contact plugs 107 are arranged along the row direction of the plurality of active regions 201.
  • the bit line contact plugs 107 are all located in the isolation layer 200, the bottom end of each bit line contact plug 107 is electrically connected to the corresponding bit line 101, and the top end of each bit line contact plug 107 is connected to the corresponding active area 201 Electrical connection.
  • the thickness of the bit line contact plug 107 may be, for example, about 50 nm, and thus, the distance between the bit line 101 and the word line 207 is about 50 nm.
  • a plurality of bit line contact plugs 107 are distributed on the bit line 101 at intervals, and the plurality of bit line contact plugs 107 are arranged along the row direction of the plurality of active regions 201, and the plurality of bit line contact plugs
  • the plungers 107 are all located in the isolation layer 200, the bottom end of each bit line contacting the plunger 107 is electrically connected to the corresponding bit line 101, and the top of each bit line contacting the plunger 107 is electrically connected to the corresponding active region 201, In this way, the plurality of MOSFET structures formed in the same row can be electrically connected through the same bit line 101 , thereby simplifying the structure of the memory.
  • a plurality of node contact plugs 219 are disposed at one end of each word line 207 away from the substrate 100, and each node contact plug 219 is electrically connected to the corresponding active region 201, and the node
  • the contact plungers 219 correspond to the bit line contact plungers 107 one-to-one.
  • each word line 207 can be electrically connected to a plurality of node contact plugs 219, thereby making each word line 207 and a capacitor in electrical contact with each node contact plug 219 electrically connected. connect.

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Abstract

本申请提供一种存储器及其制备方法，涉及半导体技术领域，该存储器包括基底，基底上设置有隔离层，隔离层内设置有阵列排布的多个有源区，多个有源区和隔离层内形成有多条字线，每条字线包括设置在有源区内的栅极和设置在隔离层内的字线结构，每条字线由间隔排布的多个栅极和多个字线结构依次连接构成，每条字线中包括的多个栅极设置在对应的相邻两列有源区内，且每条字线中的任意相邻的两个栅极设置在对应的相邻两行有源区。该存储器的制备方法包括如下步骤：提供基底；在基底上形成隔离层；在隔离层内形成阵列排布的多个有源区；在隔离层和有源区内形成多条字线。本申请实施例的存储器以及采用该存储器的制备方法制备的存储器，集成度高。

Description

存储器及其制备方法
本申请要求于2021年03月04日提交中国专利局、申请号为202110241856.8、申请名称为“存储器及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种存储器及其制备方法。
背景技术
动态随机存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
现有的动态随机存储器，一般是先形成浅沟槽隔离结构定义出有源区，然后在有源区中刻蚀形成埋入式字线，在埋入式字线之间形成位线接触柱塞，再通过位线连接各位线接触柱塞；且现有技术中较主流的动态随机存储器是3HPAA乘2HPWL结构，3HPAA乘2HPWL确定一个位单元(英文全称为cell bit)面积，3HPAA乘2HPWL指3倍的有源区(英文全称为active region，英文简称为AA)的半节距(英文全称为half pitch，英文简称为HP)乘以2倍的字线(英文全称为word line，英文简称为WL)的半节距。然而，这种结构的动态随机存储器集成度较低。
发明内容
鉴于上述问题，本申请实施例提供一种存储器及其制备方法，用于提高存储器的集成度。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种存储器，包括基底，基底上设置有隔离层，隔离层内设置有按行且按列阵列排布的多个有源区，多个有源区和隔离层内形成有多条字线；多条字线沿多个有源区的行方向排布，每条字线为 S形，每条字线包括设置在有源区内的栅极和设置在隔离层内的字线结构，每条字线由间隔排布的多个栅极和多个字线结构依次连接构成，每条字线中包括的多个栅极设置在对应的相邻两列有源区内，且每条字线中的任意相邻的两个栅极设置在对应的相邻两行有源区。
本申请实施例的存储器，基底的隔离层内设置有按行且按列排布的多个有源区，隔离层和有源区内设置有多条字线，每条字线成S形，每条字线由间隔设置的多个栅极和多个字线结构依次间隔连接，且每条字线中的多个栅极依次交替设置在对应相邻两列有源区内，且每条字线中的任意相邻两个栅极设置在对应的相邻两行有源区，如此，在单位尺寸的基底上的隔离层内设置的有源区的数量更多，后续设置与有源区一一对应的电容器后，存储器的集成度更高。
在一些实施方式中，字线结构包括第一字线结构和第二字线结构，每条字线中，任意相邻的第一字线结构的一端和第二字线结构的一端之间通过对应的栅极电连接，第一字线结构沿第一方向延伸，第一方向与多个有源区的行方向和列方向呈锐角设置，第二字线结构沿第二方向延伸，第二方向与多个有源区的行方向和列方向呈锐角设置。
在一些实施方式中，字线包括金属层和介质层，介质层包括第一介质层、第二介质层和第三介质层，第一介质层的顶面设置金属层和第二介质层，第二介质层设置在金属层的相对两侧面，金属层的顶面和第二介质层的顶面设置第三介质层。
在一些实施方式中，在基底上还设置有多条位线，每条位线沿多个有源区的行方向延伸，多条位线沿多个有源区的列方向排布。
在一些实施方式中，在位线上间隔分布多个位线接触柱塞，多个位线接触柱塞沿多个有源区的行方向排布，多个位线接触柱塞均位于隔离层内，每个位线接触柱塞的底端与对应的位线电连接，每个位线接触柱塞的顶端与对应的有源区电连接。
在一些实施方式中，在每条字线背离基底的一端设置多个节点接触柱塞，每个节点接触柱塞与对应的有源区电连接，节点接触柱塞与位线接触柱塞一一对应。
本申请实施例的第二方面提供一种存储器的制备方法，其包括如下步骤： 提供基底；在基底上形成隔离层；在隔离层内形成按行且按列阵列排布的多个有源区；在隔离层和有源区内形成多条字线，多条字线沿多个有源区的行方向排布，每条字线为S形，每条字线包括设置在有源区内的栅极和设置在隔离层内的字线结构，每条字线由间隔排布的多个栅极和多个字线结构依次连接构成，每条字线中包括的多个栅极位于对应的相邻两列有源区内，且每条字线中的任意相邻两个栅极位于对应的相邻两行有源区。
本申请实施例的存储器的制备方法，通过在基底上设置隔离层，在隔离层内设置有源区，在隔离层和有源区内设置字线，且使得多条字线沿多个有源区的行方向排布，每条字线为S形，每条字线中包括的多个栅极位于对应的相邻两列有源区内，且每条字线中的任意相邻两个栅极位于对应的相邻两行有源区，如此，使得形成的存储器内，在单位尺寸的基底上的隔离层内设置的有源区的数量更多，后续设置与有源区一一对应的电容器后，存储器的集成度更高。
在一些实施方式中，在隔离层内形成按行且按列阵列排布的多个有源区，包括：在隔离层内形成开口背离基底的多个凹孔，在每个凹孔中填满第二多晶硅，刻蚀每个凹孔中的第二多晶硅，保留每个凹孔侧壁的部分第二多晶硅以形成有源区，多个凹孔中保留的有源区阵列排布且彼此隔离。
在一些实施方式中，在隔离层和有源区内形成多条字线，包括：在隔离层和有源区内形成槽口背离基底的多条字线槽，每条字线槽包括多个凹孔和间隔排布的多个第一字线槽和多个第二字线槽，任意相邻两个第一字线槽和第二字线槽具有一夹角且通过对应的一个凹孔连通；在字线槽内形成金属层和包覆在金属层的底面、顶面以及相对的两个侧面的介质层，以形成字线，字线包括多个第一字线结构、多个第二字线结构以及多个栅极，每个第一字线结构形成在对应一个第一字线槽中，每个第二字线结构形成在对应一个第二字线槽中，每个栅极形成在对应一个凹孔中，任意相邻的两个第一字线结构和第二字线结构通过对应的栅极电连接。
在一些实施方式中，在字线槽内形成金属层和包覆在金属层的底面、顶面以及相对的两个侧面的介质层，以形成字线，包括：在字线槽的底部形成第一介质层；在字线槽内的第一介质层上形成第二介质层，第二介质层形成在有源区的侧壁上；在字线槽内的第一介质层上、且第二介质层远离有源区 的侧部形成金属层，金属层填满字线槽；回刻金属层的顶部；在字线槽的金属层上形成第三介质层。
在一些实施方式中，在基底上形成隔离层的步骤之前，还包括：在基底上形成多条位线，每条位线沿多个有源区的行方向延伸，多条位线沿多个有源区的列方向排布。
在一些实施方式中，在隔离层内形成按行且按列阵列排布的多个有源区之前，还包括：在每个凹孔底部沉积第一多晶硅以形成位线接触柱塞，位线接触柱塞与对应的位线电连接。
在一些实施方式中，在每个凹孔中填满多第二晶硅之后，刻蚀每个凹孔中的第二多晶硅之前，还包括：在第二多晶硅上形成保护层；刻蚀每个凹孔中的第一多晶硅，包括：刻蚀保护层和第二多晶硅以形成节点接触槽和字线槽，节点接触槽位于字线槽上方且与字线槽连通，节点接触槽的宽度大于字线槽的宽度，节点接触槽形成在保护层中，字线槽形成在隔离层中以及有源区中；在字线槽中形成字线，且在节点接触槽中形成节点接触柱塞，并且使得形成的节点接触柱塞与对应的有源区电连接。
在一些实施方式中，在基底上形成隔离层包括：在位线的底面、顶面以及相对两个侧面形成绝缘层，刻蚀绝缘层以形成隔离层。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的存储器及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例的存储器的制备方法的流程图；
图2为本申请实施例中位线的制备流程图；
图3a为本申请实施例中基底上设置位线槽的结构示意图；
图3b为图3a中的AA位置的断面图；
图3c为图3a中的BB位置的断面图；
图4a为本申请实施例中位线槽中设置第一绝缘材料的结构示意图；
图4b为图4a中的AA位置的断面图；
图4c为图4a中的BB位置的断面图；
图5a为本申请实施例中去除位线槽中靠近槽口位置的第一绝缘材料后的结构示意图；
图5b为图5a中的AA位置的断面图；
图5c为图5a中的BB位置的断面图；
图6a为本申请实施例中在位线槽中设置导电材料后的结构示意图；
图6b为图6a中的AA位置的断面图；
图6c为图6a中的BB位置的断面图；
图7a为本申请实施例中在位线槽中形成位线后的结构示意图；
图7b为图7a中的AA位置的断面图；
图7c为图7a中的BB位置的断面图；
图8为本申请实施例中隔离层的制备流程图；
图9a为本申请实施例中在位线槽中设置第二绝缘材料后的结构示意图；
图9b为图9a中的AA位置的断面图；
图9c为图9a中的BB位置的断面图；
图10a为本申请实施例中去除基底顶面的第二绝缘材料后的结构示意图；
图10b为图10a中的AA位置的断面图；
图10c为图10a中的BB位置的断面图；
图11a为本申请实施例中去除部分基底后的结构示意图；
图11b为图11a中的AA位置的断面图；
图11c为图11a中的BB位置的断面图；
图12a为本申请实施例中在基底上设置第三绝缘材料后的结构示意图；
图12b为图12a中的AA位置的断面图；
图12c为图12a中的BB位置的断面图；
图13为本申请实施例中有源区的制备流程图；
图14a为本申请实施例中在隔离层中设置凹孔后的结构示意图；
图14b为图14a中的AA位置的断面图；
图14c为图14a中的BB位置的断面图；
图15a为本申请实施例中在凹孔中形成位线接触柱塞的结构示意图；
图15b为图15a中的AA位置的断面图；
图15c为图15a中的BB位置的断面图；
图16a为本申请实施例中在凹孔中填充多晶硅后的结构示意图；
图16b为图16a中的AA位置的断面图；
图16c为图16a中的BB位置的断面图；
图17a为本申请实施例中刻蚀多晶硅并设置第一介质层后的结构示意图；
图17b为图17a中的AA位置的断面图；
图17c为图17a中的BB位置的断面图；
图18a为本申请实施例中在凹孔中设置金属层和第二介质层后的结构示意图；
图18b为图18a中的AA位置的断面图；
图18c为图18a中的BB位置的断面图；
图19a为本申请实施例中在凹孔中设置第三介质层并形成节点接触柱塞后的结构示意图；
图19b为图19a中的AA位置的断面图；
图19c为图19a中的BB位置的断面图；
图20为本申请实施例中字线的制备流程图；
图21为本申请实施例中介质成的制备流程图。
附图标记：
100：基底；                        101：位线；
102：位线槽；                      103：第一绝缘材料；
104：导电材料；                    105：第二绝缘材料；
106：第三绝缘材料；                107：位线接触柱塞；
200：隔离层；                      201：有源区；
202：凹孔；                        203：第二多晶硅；
204：保护层；                      205：节点接触槽；
206：字线槽；                      207：字线；
208：栅极；                        209：字线结构；
210：第一字线槽；                  211：第二字线槽；
212：第一字线结构；                213：第二字线结构；
214：金属层；                      215：介质层；
216：第一介质层；                  217：第二介质层；
218：第三介质层；                  219：节点接触柱塞。
具体实施方式
在相关技术中，动态随机存储器一般包括基底、设置在基底内的隔离结构、以及设置在隔离结构中的多个有源区，每个有源区内设置有栅极，隔离结构内设置有用于将位于同一列的多个栅极连接的字线结构，栅极和字线结构共同形成字线。隔离结构内还设置有与有源区接触的位线接触柱塞，与同一行的有源区接触的多个位线接触柱塞通过位线连接。每个有源区的两端上还设置有电容器，电容器用于存储电荷。
然而，这种结构的动态随机存储器，单位尺寸的基底上，对应设置的有源区的数量较少，对应设置的电容器的数量较少，存储器的集成度低。为此，本申请实施例提供一种存储器及其制备方法，该存储器以及该存储器的制备方法制备的存储器中，基底内设置有隔离层，隔离层内设置有按行且按列排布的多个有源区，隔离层和有源区内设置有多条字线，每条字线成S形，每条字线由间隔设置的多个栅极和多个字线结构依次间隔连接，且每条字线中的多个栅极依次交替设置在对应相邻两列有源区内，且每条字线中的任意相邻两个栅极设置在对应的相邻两行有源区内，如此，在单位尺寸的基底上，对应设置的有源区的数量更多，后续设置与有源区一一对应的电容器的数量更多，存储器的集成度更高。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
如图1所示，本实施例提供的一种存储器的制备方法，其包括如下步骤：
S1：提供基底，基底的材料可以是硅、锗等本领域技术人员熟知的半导体基底材料。
S2：在基底上形成隔离层，隔离层的材料例如可以是二氧化硅。
在一些实施方式中，在基底上形成隔离层的步骤之前，存储器的制备方法还包括：
J1：在基底上形成多条位线，每条位线沿后续提到的有源区的行方向延伸，多条位线沿后续提到的多个有源区的列方向排布。
请参阅图2，在基底上形成多条位线，包括如下步骤：
J11：在基底上形成多条位线槽，多条位线槽平行设置，该步骤形成的结构如图3a、图3b以及图3c所示，该步骤形成的结构中，基底100上设置有平行设置的多条位线槽102，每条位线槽102沿x方向延伸。
J12：在每条位线槽102中填充第一绝缘材料103，第一绝缘材料103还设置在基底100的顶面，第一绝缘材料103例如可以是氧化物，该步骤形成的结构如图4a、图4b以及图4c所示，该步骤形成的结构中，位线槽102中填充有第一绝缘材料103，基底100的顶面也设置有第一绝缘材料103。
J13：去除基底100顶面上的第一绝缘材料103，以及每条位线槽102内靠近槽口的部分第一绝缘材料103，该步骤形成的结构如图5a、图5b以及图5c所示，该步骤形成的结构中，位线槽102中填充的第一绝缘材料103的顶面低于基底100的顶面，例如，位线槽102的深度为240-300纳米(nm)，保留下的第一绝缘材料103的厚度为20-30nm。
J14：在每条位线槽102内的第一绝缘材料103上、以及基底100上设置导电材料104，导电材料104例如可以是钨，该步骤形成的结构如图6a、图6b以及图6c所示，该步骤形成的结构中，位线槽102内的第一绝缘材料103上、以及基底100的顶面上设置有导电材料104。
J15：去除基底100顶面上的导电材料104，以及每条位线槽102内靠近槽口位置的部分导电材料104，保留在位线槽102中的导电材料104形成位线101，该步骤形成的结构如图7a、图7b以及图7c所示，该步骤形成的结构中，保留的导电材料104设置在第一绝缘材料103上，位线槽102内的导电材料104的顶面低于基底100的顶面，例如，保留的导电材料104的厚度 为20nm，此时，位线槽102内的导电材料104的顶面低于基底100的顶面。
在一些实施方式中，在基底100上形成隔离层200，包括：在位线101的底面、顶面以及相对两个侧面形成绝缘层，刻蚀绝缘层以形成隔离层200，隔离层200包覆在位线101的四周，其中，上述第一绝缘材料103即为位线101底面的部分隔离层200，下述的第二绝缘材料为位线101顶面的部分隔离层200，下述的第三绝缘材料为位线101相对两侧的部分隔离层200。
请参阅图8，在位线101的顶面以及相对两个侧面形成绝缘层，刻蚀绝缘层以形成隔离层200，包括如下步骤：
S21：在位线槽102内的位线101上、以及基底100的顶面上设置第二绝缘材料105，第二绝缘材料105例如可以是氧化物，该步骤形成的结构如图9a、图9b以及图9c所示，该步骤形成的结构中，位线槽102内的位线101上、以及基底100的顶面设置有第二绝缘材料105。
S22：去除基底100顶面上的第二绝缘材料105，剩余的第二绝缘材料105的顶面与基底100顶面平齐，该步骤形成的结构如图10a、图10b以及图10c所示，该步骤形成的结构中，位线槽102中从下往上依次层叠设置有第一绝缘材料103、位线101以及第二绝缘材料105，第二绝缘材料105的顶面与基底100顶面平齐。
S23：去除位线槽102的槽底上方的基底100，保留第一绝缘材料103、位线101、第二绝缘材料105以及位线槽102的槽底面下方的基底100，该步骤形成的结构如图11a、图11b以及图11c所示，该步骤形成的结构中，保留下的基底100的顶面与第一绝缘材料103的底面平齐，第一绝缘材料103上设置有位线101，位线101上设置有第二绝缘材料105。
S24：在保留的第二绝缘材料105以及保留的基底100上设置第三绝缘材料106，第一绝缘材料103、第二绝缘材料105以及第三绝缘材料106构成上述绝缘层，第一绝缘材料103、刻蚀后保留下的第二绝缘材料105以及第三绝缘材料106形成隔离层200，第三绝缘材料106例如可以是氧化物，该步骤形成的结构如图12a、图12b以及图12c所示，该步骤形成的结构中，基底100上设置有间隔设置的第一绝缘材料103和第三绝缘材料106，第一绝缘材料103上设置位线101，位线101上设置第二绝缘材料105，第二绝缘材料105的顶面与第三绝缘材料106的顶面平齐。
S3：在隔离层200内形成按行且按列阵列排布的多个有源区201。
请参阅图13，在隔离层200内形成按行且按列阵列排布的多个有源区201包括如下步骤：
S31：在隔离层200内形成开口背离基底100的多个凹孔202，该步骤形成的结构如图14a、图14b以及图14c所示，该步骤形成的结构中，隔离层200内设置有凹孔202，凹孔202按列且按行阵列排布，凹孔202的底部的暴露出位线101，且位于同一行的凹孔202暴露出同一位线101。
S33：在每个凹孔202中填满第二多晶硅203。
S35：刻蚀每个凹孔202中的第二多晶硅203，保留每个凹孔202侧壁的部分第二多晶硅203以形成有源区201，多个凹孔202中保留的有源区201阵列排布且彼此隔离，该步骤中，可以对第二多晶硅203进行离子掺杂。该步骤形成的结构请参阅图17a和图17b所示，该步骤形成的结构中，每个凹孔202中形成一个有源区201，每个凹孔202中的有源区201设置在凹孔202的侧壁上。
请参阅图13，其中，在隔离层200内形成开口背离基底100的多个凹孔202之后，且每个凹孔202中填满第二多晶硅203之前，还包括如下步骤：
S32：在每个凹孔202底部沉积第一多晶硅以形成位线接触柱塞107，位线接触柱塞107与对应的位线101电连接，每个凹孔202底部沉积第一多晶硅可以采用化学气相沉积法(英文名称为Chemical Vapor Deposition，英文简称为CVD)沉积而成，之后，再进行离子掺杂以形成位线接触柱塞107，该步骤形成的结构如图15a、图15b以及图15c所示，该步骤形成的结构中，每个凹孔202中填充有第一多晶硅，第一多晶硅的底面与位线101电接触，且第一多晶硅的顶面低于隔离层200的顶面，形成在凹孔202的第一多晶硅构成位线接触柱塞107，在位线接触柱塞107的顶面上设置步骤S33中的第二多晶硅203，第二多晶硅203形成在位线接触柱塞107上且填满凹孔202。
请参阅图13，其中，在每个凹孔202中填满第二多晶硅203之后，且在刻蚀每个凹孔202中的第二多晶硅203之前，还包括如下步骤：
S34：在第二多晶硅203上形成保护层204，保护层204还设置在隔离层200上，保护层204的材料例如可以是氮化硅，该步骤形成的结构如图16a、图16b以及图16c所示，该步骤形成的结构中，第二多晶硅203填充在每一 个凹孔202中，且凹孔202内填充的第二多晶硅203和隔离层200上设置有保护层204。
请参阅图13，刻蚀每个凹孔202中的第二多晶硅203，还包括：
S35：刻蚀保护层204和第二多晶硅203层以形成节点接触槽和字线槽，节点接触槽位于字线槽上方且与字线槽连通，节点接触槽的宽度大于字线槽206的宽度，节点接触槽形成在保护层204中，字线槽形成在隔离层200中以及有源区201中，在字线槽中形成字线，且在节点接触槽中形成节点接触柱塞，并且使得形成的节点接触柱塞与对应的有源区201电连接。该步骤形成的结构如图17a、图17b以及图17c所示，隔离层200和有源区201内设置有字线槽206，保护层204内设置有节点接触槽205，节点接触槽205与字线槽206连通，节点接触槽205的槽宽大于字线槽206的宽度。
在节点接触槽205中形成节点接触柱塞，可以通过化学气相沉积法沉积第三多晶硅，并进行离子掺杂制备得到。
S4：在隔离层200和有源区201内形成多条字线，多条字线沿多个有源区201的行方向排布，每条字线为S形，每条字线包括设置在有源区201内的栅极208和设置在隔离层200内的字线结构209，每条字线207由间隔排布的多个栅极和多个字线结构依次连接构成，每条字线中包括的多个栅极位于对应的相邻两列有源区201内，且每条字线中的任意相邻两个栅极位于对应的相邻两行有源区201内。该步骤形成的结构请参阅图18a、图19a、图19b以及图19c，每条字线207由间隔连接的栅极208和字线结构209形成，其中，栅极208设置在有源区201内，字线结构209设置在隔离层200内，且每条字线207上的各栅极208所在的有源区201对应位于相邻两列，每条字线207上的任意相邻两个栅极208所在的有源区201的行数相差一行。
请参阅图20，在隔离层200和有源区201内形成多条字线207，包括：
S41：在隔离层200和有源区201内形成槽口背离基底100的多条字线槽，每条字线槽包括多个凹孔202和间隔排布的多个第一字线槽和多个第二字线槽，任意相邻的两个第一字线槽和第二字线槽具有一夹角且通过对应的一个凹孔202连通；该步骤形成的结构如图17a、图17b以及图17c所示，其中，凹孔202设置在有源区201内，第一字线槽210和第二字线槽211设置在隔离层200内，且第一字线槽210和第二字线槽211具有一夹角，第一字线槽 210和第二字线槽211之间通过凹孔202连通。
S42：在字线槽206内形成金属层和包覆在金属层的底面、顶面以及相对的两个侧面的介质层，以形成字线207，字线207包括多个第一字线结构、多个第二字线结构以及多个栅极，每个第一字线结构形成在对应一个第一字线槽210中，每个第二字线结构形成在对应一个第二字线槽211中，每个栅极形成在对应一个凹孔202中，任意相邻两个第一字线结构和第二字线结构通过对应的栅极电连接。该步骤形成的结构请参阅图18a、图18b、图18c、图19a、图19b以及图19c所示，其中，栅极208设置在有源区201内，第一字线结构212形成在隔离层200的第一字线槽210中，第二字线结构213形成在隔离层200的第二字线槽211中，第一字线结构212和第二字线结构213通过栅极208连接。
请参阅图21，在字线槽206内形成金属层214和包覆在金属层214的底面、顶面以及相对的两个侧面的介质层215，以形成字线207，包括：
S421：在字线槽206的底部形成第一介质层216，第一介质层216例如可以是氧化硅层，该步骤形成的结构如图17a、图17b以及图17c所示，其中，第一介质层216的材料设置在字线槽206内，且第一介质层216的高度小于字线槽206的槽深，也即，第一介质层216的顶面低于字线槽206的顶面。
S422：在字线槽206内的第一介质层216上形成第二介质层217，第二介质层217形成在有源区201的侧壁上；第二介质层217的材料例如可以是氧化硅层，第二介质层217可以通过原位水汽法(英文名称为in-situ steam generation，英文简称为ISSG)制备，第二介质层217的厚度大约可以为5nm，该步骤形成的结构可以参阅如图18a、图18b以及图18c，其中，第二介质层217设置在字线槽206内，第二介质层217设置在第一介质层216上，且设置在有源区201的侧壁上。
S423：在字线槽206内的第一介质层216上、且第二介质层217远离有源区201的侧部形成金属层214，金属层214填满字线槽206，金属层214的材料例如可以金属钨，该步骤形成的结构如图18a、图18b以及图18c，其中，金属层214设置在字线槽206内，第二介质层217设置在金属层214的相对的两侧面。
S424：回刻金属层214的顶部，该步骤形成的结构可以参阅如图19a、 图19b以及图19c，金属层214的顶面低于第二介质层217的顶面。
S425：在字线槽206的金属层214上形成第三介质层218，第三介质层218的材料例如可以是氧化硅，该步骤形成的结构如图19a、图19b以及图19c，其中，第三介质层218设置在金属层214和第二介质层217上。
本申请实施例的存储器的制备方法，通过在基底100上设置隔离层200，在隔离层200内设置有源区201，在隔离层200和有源区201内设置字线207，且使得多条字线207沿多个有源区201的行方向排布，每条字线207为S形，每条字线207中包括的多个栅极208位于对应的相邻两列有源区201内，且每条字线207中的任意相邻两个栅极208位于对应的相邻两行有源区201，如此，使得形成的存储器内，在单位尺寸的基底100上，对应设置的有源区201的数量更多，后续设置与有源区201一一对应的电容器的数量更多，存储器的集成度更高。
本申请实施例的存储器的制备方法制备的存储器是2HPAA乘2HPWL结构，2HPAA乘2HPWL确定一个位单元面积，2HPAA乘2HPWL指2倍的有源区的半节距乘以2倍的字线的半节距，2HPAA乘2HPWL结构形成的4F2存储单元的面积会缩小至3HPAA乘2HPWL结构形成的6F2存储单元的三分之二左右，相当于4F2存储结构的存储密度更大，集成度更高。
请参阅图18a、图18b、图18c、图19a、图19b以及图19c，本申请实施例提供的存储器，包括基底100，基底100的材料可以为硅、锗等，基底100上设置有隔离层200，隔离层200的材料例如可以是二氧化硅，隔离层200内设置有按行且按列阵列排布的多个有源区201，多个有源区201和隔离层200内形成有多条字线207，多条字线207沿多个有源区201的行方向排布，每条字线207为S形，每条字线207沿多个有源区201的列方向延伸，每条字线207包括设置在有源区201内的栅极208和设置在隔离层200内的字线结构209，每条字线207由间隔排布的多个栅极208和多个字线结构209依次连接构成，每条字线207中包括的多个栅极208设置在对应的相邻两列有源区201内，且每条字线207中的任意相邻两个栅极208设置在对应的相邻两行有源区201。
本申请实施例的存储器，基底100上的隔离层200内设置有按行且按列排布的多个有源区201，隔离层200和有源区201内设置有多条字线207，每 条字线207成S形，每条字线207包括的多个栅极208和多个字线结构209依次间隔设置并连接，且每条字线207中的多个栅极208依次交替设置在对应相邻两列有源区201内，且每条字线207中的任意相邻两个栅极208设置在对应的相邻两行有源区201内，如此，在单位尺寸的基底100上的隔离层200内设置的有源区201的数量更多，后续设置与有源区201一一对应的电容器的数量更多，存储器的集成度更高。
请参阅图18a、图18b、图18c、图19a、图19b以及图19c，字线结构209包括第一字线结构212和第二字线结构213，每条字线207中，任意相邻的第一字线结构212的一端和第二字线结构213的一端之间通过对应的栅极208电连接，第一字线结构212沿第一方向延伸，第一方向与多个有源区201的行方向和列方向呈锐角设置，第二字线结构213沿第二方向延伸，第二方向与多个有源区201的行方向和列方向呈锐角设置，相邻的第一字线结构212和第二字线结构213之间呈锐角设置。
本实施例的存储器，字线结构209包括第一字线结构212和第二字线结构213，相邻的第一字线结构212的一端和第二字线结构213的一端之间通过栅极208连接，且第一字线结构212和第二字线结构213之间呈锐角设置，可以实现字线207为S形。
请继续参阅图19a、图19b以及图19c，字线207包括金属层214和介质层215，介质层215包括第一介质层216、第二介质层217和第三介质层218，第一介质层216的顶面设置金属层214和第二介质层217，第二介质层217设置在金属层214的相对两侧面，金属层214的顶面和第二介质层217的顶面设置第三介质层218，第一介质层216、第二介质层217以及第三介质层218的材质例如可以为二氧化硅，金属层214的材质例如可以是金属钨。
本实施例的存储器，第一介质层216的顶面设置金属层214和第二介质层217，第二介质层217设置在金属层214的相对两侧面，金属层214的顶面和第二介质层217的顶面设置第三介质层218，可以使得第一介质层216、第二介质层217、以及第三介质层218将金属层214与有源区201隔开，进而形成金属氧化物半导体场效应晶体管结构。
请继续参阅图19a、图19b以及图19c，在基底100上还设置有多条位线101，每条位线101沿多个有源区201的行方向延伸，多条位线101沿多个有 源区201的列方向排布。
本实施例的存储器，在基底100上形成多条位线101，且使得每条位线101沿多个有源区201的行方向延伸，多条位线101沿多个有源区201的列方向排布，如此，实现与上述形成的金属氧化物半导体场效应晶体管结构电连接。
请继续参阅图19a、图19b以及图19c，在位线101上间隔分布多个位线接触柱塞107，多个位线接触柱塞107沿多个有源区201的行方向排布，多个位线接触柱塞107均位于隔离层200内，每个位线接触柱塞107的底端与对应的位线101电连接，每个位线接触柱塞107的顶端与对应的有源区201电连接。位线接触柱塞107的厚度例如可以是50nm左右，如此，位线101和字线207之间的距离大约为50nm。
本实施例的存储器，在位线101上间隔分布多个位线接触柱塞107，且使得多个位线接触柱塞107沿多个有源区201的行方向排布，多个位线接触柱塞107均位于隔离层200内，每个位线接触柱塞107的底端与对应的位线101电连接，每个位线接触柱塞107的顶端与对应的有源区201电连接，如此，可以使得上述形成的同一行的多个金属氧化物半导体场效应晶体管结构通过同一个位线101电连接，简化存储器的结构。
请继续参阅图19a、图19b以及图19c，在每条字线207背离基底100的一端设置多个节点接触柱塞219，每个节点接触柱塞219与对应的有源区201电连接，节点接触柱塞219与位线接触柱塞107一一对应。
本实施例的存储器，在每条字线207背离基底100的一端设置多个节点接触柱塞219，且使得每个节点接触柱塞219与对应的有源区201电连接，节点接触柱塞219与位线接触柱塞107一一对应，可以使得每条字线207与多个节点接触柱塞219电连接，进而使得每条字线207和与每个节点接触柱塞219电接触的电容器电连接。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施 方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (18)

  1. 一种存储器，其中，包括基底，所述基底上设置有隔离层，所述隔离层内设置有按行且按列阵列排布的多个有源区，多个所述有源区和所述隔离层内形成有多条字线；
    多条所述字线沿多个所述有源区的行方向排布，每条所述字线为S形，每条所述字线包括设置在所述有源区内的栅极和设置在所述隔离层内的字线结构，每条所述字线由间隔排布的多个所述栅极和多个所述字线结构依次连接构成，每条所述字线中包括的多个所述栅极设置在对应的相邻两列所述有源区内，且每条所述字线中的任意相邻的两个所述栅极设置在对应的相邻两行所述有源区。
  2. 根据权利要求1所述的存储器，其中，所述字线结构包括第一字线结构和第二字线结构，每条所述字线中，任意相邻的所述第一字线结构的一端和所述第二字线结构的一端之间通过对应的所述栅极电连接，所述第一字线结构沿第一方向延伸，所述第一方向与多个所述有源区的行方向和列方向呈锐角设置，所述第二字线结构沿第二方向延伸，所述第二方向与多个所述有源区的行方向和列方向呈锐角设置。
  3. 根据权利要求1所述的存储器，其中，所述字线包括金属层和介质层，所述介质层包括第一介质层、第二介质层和第三介质层，所述第一介质层的顶面设置所述金属层和所述第二介质层，所述第二介质层设置在所述金属层的相对两侧面，所述金属层的顶面和所述第二介质层的顶面设置所述第三介质层。
  4. 根据权利要求1所述的存储器，其中，在所述基底上还设置有多条位线，每条所述位线沿多个所述有源区的行方向延伸，多条所述位线沿多个所述有源区的列方向排布。
  5. 根据权利要求4所述的存储器，其中，在所述位线上间隔分布多个位线接触柱塞，多个所述位线接触柱塞沿多个所述有源区的行方向排布，多个所述位线接触柱塞均位于所述隔离层内，每个所述位线接触柱塞的底端与对应的所述位线电连接，每个所述位线接触柱塞的顶端与对应的所述有源区电连接。
  6. 根据权利要求5所述的存储器，其中，在每条所述字线背离所述基底 的一端设置多个节点接触柱塞，每个所述节点接触柱塞与对应的所述有源区电连接，所述节点接触柱塞与所述位线接触柱塞一一对应。
  7. 根据权利要求2所述的存储器，其中，在所述基底上还设置有多条位线，每条所述位线沿多个所述有源区的行方向延伸，多条所述位线沿多个所述有源区的列方向排布。
  8. 根据权利要求3所述的存储器，其中，在所述基底上还设置有多条位线，每条所述位线沿多个所述有源区的行方向延伸，多条所述位线沿多个所述有源区的列方向排布。
  9. 一种存储器的制备方法，其中，包括如下步骤：
    提供基底；
    在所述基底上形成隔离层；
    在所述隔离层内形成按行且按列阵列排布的多个有源区；
    在所述隔离层和所述有源区内形成多条字线，多条所述字线沿多个所述有源区的行方向排布，每条所述字线为S形，每条所述字线包括设置在所述有源区内的栅极和设置在所述隔离层内的字线结构，每条所述字线由间隔排布的多个所述栅极和多个所述字线结构依次连接构成，每条所述字线中包括的多个所述栅极位于对应的相邻两列所述有源区内，且每条所述字线中的任意相邻两个所述栅极位于对应的相邻两行所述有源区。
  10. 根据权利要求9所述的存储器的制备方法，其中，在所述隔离层内形成按行且按列阵列排布的多个有源区，包括：
    在所述隔离层内形成开口背离所述基底的多个凹孔，在每个所述凹孔中填满第二多晶硅，刻蚀每个所述凹孔中的所述第二多晶硅，保留每个所述凹孔侧壁的部分所述第二多晶硅以形成所述有源区，多个所述凹孔中保留的所述有源区阵列排布且彼此隔离。
  11. 根据权利要求10所述的存储器的制备方法，其中，在所述隔离层和所述有源区内形成多条字线，包括：
    在所述隔离层和所述有源区内形成槽口背离所述基底的多条字线槽，每条所述字线槽包括多个所述凹孔和间隔排布的多个第一字线槽和多个第二字线槽，任意相邻两个所述第一字线槽和所述第二字线槽具有一夹角且通过对应的一个所述凹孔连通；
    在所述字线槽内形成金属层和包覆在所述金属层的底面、顶面以及相对的两个侧面的介质层，以形成所述字线，所述字线包括多个第一字线结构、多个第二字线结构以及多个栅极，每个所述第一字线结构形成在对应一个所述第一字线槽中，每个所述第二字线结构形成在对应一个所述第二字线槽中，每个所述栅极形成在对应一个所述凹孔中，任意相邻的两个所述第一字线结构和所述第二字线结构通过对应的所述栅极电连接。
  12. 根据权利要求11所述的存储器的制备方法，其中，在所述字线槽内形成金属层和包覆在所述金属层的底面、顶面以及相对的两个侧面的介质层，以形成所述字线，包括：
    在所述字线槽的底部形成第一介质层；
    在所述字线槽内的所述第一介质层上形成第二介质层，所述第二介质层形成在所述有源区的侧壁上；
    在所述字线槽内的所述第一介质层上、且所述第二介质层远离所述有源区的侧部形成所述金属层，所述金属层填满所述字线槽；
    回刻所述金属层的顶部；
    在所述字线槽的所述金属层上形成第三介质层。
  13. 根据权利要求10所述的存储器的制备方法，其中，在所述基底上形成隔离层的步骤之前，还包括：
    在所述基底上形成多条位线，每条所述位线沿多个所述有源区的行方向延伸，多条所述位线沿多个所述有源区的列方向排布。
  14. 根据权利要求13所述的存储器的制备方法，其中，在所述隔离层内形成按行且按列阵列排布的多个有源区之前，还包括：
    在每个所述凹孔底部沉积第一多晶硅以形成位线接触柱塞，所述位线接触柱塞与对应的所述位线电连接。
  15. 根据权利要求13所述的存储器的制备方法，其中，在每个所述凹孔中填满第二多晶硅之后，刻蚀每个所述凹孔中的所述第二多晶硅之前，还包括：
    在所述第二多晶硅上形成保护层；
    刻蚀每个所述凹孔中的所述第二多晶硅，包括：
    刻蚀所述保护层和所述第二多晶硅以形成节点接触槽和字线槽，所述节 点接触槽位于所述字线槽上方且与所述字线槽连通，所述节点接触槽的宽度大于所述字线槽的宽度，所述节点接触槽形成在所述保护层中，所述字线槽形成在所述隔离层中以及所述有源区中；在所述字线槽中形成字线，且在所述节点接触槽中形成节点接触柱塞，并且使得形成的所述节点接触柱塞与对应的所述有源区电连接。
  16. 根据权利要求13所述的存储器的制备方法，其中，在所述基底上形成所述隔离层包括：
    在所述位线的底面、顶面以及相对两个侧面形成绝缘层，刻蚀所述绝缘层以形成所述隔离层。
  17. 根据权利要求11所述的存储器的制备方法，其中，在所述基底上形成隔离层的步骤之前，还包括：
    在所述基底上形成多条位线，每条所述位线沿多个所述有源区的行方向延伸，多条所述位线沿多个所述有源区的列方向排布。
  18. 根据权利要求12所述的存储器的制备方法，其中，在所述基底上形成隔离层的步骤之前，还包括：
    在所述基底上形成多条位线，每条所述位线沿多个所述有源区的行方向延伸，多条所述位线沿多个所述有源区的列方向排布。
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