WO2022183629A1 - 存储器及其制备方法 - Google Patents

存储器及其制备方法 Download PDF

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Publication number
WO2022183629A1
WO2022183629A1 PCT/CN2021/101283 CN2021101283W WO2022183629A1 WO 2022183629 A1 WO2022183629 A1 WO 2022183629A1 CN 2021101283 W CN2021101283 W CN 2021101283W WO 2022183629 A1 WO2022183629 A1 WO 2022183629A1
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WO
WIPO (PCT)
Prior art keywords
layer
bit line
polysilicon
isolation
isolation layer
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PCT/CN2021/101283
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English (en)
French (fr)
Inventor
乔梦竹
陈涛
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长鑫存储技术有限公司
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Priority to US17/460,988 priority Critical patent/US11877441B2/en
Publication of WO2022183629A1 publication Critical patent/WO2022183629A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory and a preparation method thereof.
  • DRAM Dynamic random access memory
  • a shallow trench isolation structure is generally formed to define an active region, and then buried word lines are formed in the active region by etching, and bit line contact columns are formed between the buried word lines. Plug, and then connect each line to contact the plunger through the bit line; and the mainstream dynamic random access memory in the prior art is a 3HPAA multiplied by 2HPWL structure, 3HPAA multiplied by 2HPWL to determine the area of a bit cell (full English name is cell bit), 3HPAA multiplied by 2HPWL refers to 3 times the half pitch of the active region (full name in English is active region, abbreviated in English is AA) multiplied by 2 times the word line (full name in English is word line, abbreviated in English) is the half pitch of WL).
  • the DRAM integration level of this structure is low.
  • embodiments of the present application provide a memory and a preparation method thereof, so as to improve the integration degree of the memory.
  • a first aspect of the embodiments of the present application provides a memory, which includes a substrate, an isolation layer is disposed on the substrate, a plurality of bit lines are arranged at intervals in the isolation layer, the plurality of bit lines are arranged along a first direction, and each The bit lines are S-shaped.
  • a plurality of bit lines arranged at intervals are arranged in the isolation layer of the substrate, and each bit line is S-shaped and arranged along the first direction.
  • the number of bit line contact plungers set subsequently that are in contact with the bit line will increase, and the number of subsequently set active regions corresponding to the bit line contact plungers one-to-one will increase.
  • the number of capacitors corresponding to the active regions one-to-one will also increase, so that the integration of the memory is higher.
  • each bit line includes a plurality of first bit line structures and a plurality of second bit line structures arranged at intervals and connected in sequence, the first bit line structures extend along a second direction, and the second direction is opposite to the first bit line structure.
  • One direction is inclined
  • the second bit line structure extends along a third direction
  • the third direction is inclined relative to the first direction
  • the third direction is opposite to the inclination direction of the second direction relative to the first direction.
  • each bit line is provided with a plurality of bit line contact plungers arranged at intervals, the bit line contact plungers are arranged in the isolation layer, and each bit line contact plunger is arranged in a corresponding first The connection position of the bit line structure and the second bit line structure.
  • an active region is provided on each bit line contact plug, and the active region is provided within the isolation layer.
  • a plurality of word lines are further provided in the isolation layer, the plurality of word lines are arranged along a fourth direction, each word line extends along a first direction, and the fourth direction is perpendicular to the first direction.
  • each word line includes a plurality of gates and a plurality of word line structures, each of the gates is correspondingly disposed in one active region, and the plurality of gates included in each word line is correspondingly disposed in the same column In the active area, the same column of active areas is arranged along the first direction, a plurality of gates and a plurality of word line structures are arranged one by one at intervals, each word line structure is arranged in the isolation layer, and each word line structure is used for Connect two adjacent gates.
  • the word line includes a metal layer and a dielectric layer
  • the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer
  • the top surface of the first dielectric layer is provided with a metal layer and a second dielectric layer
  • the first dielectric layer is provided with a metal layer and a second dielectric layer.
  • Two dielectric layers are disposed on opposite sides of the metal layer, and a third dielectric layer is disposed on the top surface of the metal layer and the top surface of the second dielectric layer.
  • each word line is provided with a plurality of node contact plugs at intervals, each node contact plug is electrically connected to the top of the active region, and the node contact plug and the bit line contact plug are perpendicular to the substrate.
  • each word line is provided with a plurality of node contact plugs at intervals, each node contact plug is electrically connected to the top of the active region, and the node contact plug and the bit line contact plug are perpendicular to the substrate.
  • a second aspect of the embodiments of the present application provides a method for fabricating a memory, which includes the steps of: providing a substrate; forming a plurality of bit line trenches on the substrate, the plurality of bit line trenches are arranged along a first direction, and each The bit line trenches are S-shaped; a first isolation layer is formed in each bit line trench, and the thickness of the first isolation layer is less than the depth of the bit line trench; bit lines are formed on the first isolation layer, and the first isolation layer is The total thickness of the layer and the bit line is less than the depth of the bit line trench, a plurality of bit lines are arranged along the first direction, and each bit line is S-shaped; a second isolation layer is formed on the bit line, and the second isolation layer is The top surface is flush with the top surface of the substrate; the substrate between adjacent isolation walls is removed, and the substrate below the bottom surface of the first isolation layer is retained, wherein the isolation wall includes a first isolation layer, a bit line and a second isolation layer; A third isolation
  • an S-shaped bit line trench is arranged on the substrate, and then an S-shaped bit line is formed in the S-shaped bit line trench, so that in the prepared memory,
  • the length of each bit line set in the isolation layer increases, and the number of bit line contact plungers that are subsequently set in contact with the bit line will increase, and the subsequently set bit line contact plungers correspond one-to-one.
  • the number of active regions will increase, and the number of capacitors corresponding to the active regions will also increase, and the integration of the memory will be higher.
  • each formed bit line includes a plurality of first bit line structures and a plurality of second bit line structures that are arranged at intervals and connected in sequence, the first The bit line structure extends along a second direction, the second direction is inclined relative to the first direction, the second bit line structure extends along a third direction, the third direction is inclined relative to the first direction, and the third direction is opposite to the second direction The inclination direction of the first direction is opposite.
  • the method further includes: removing a part of the isolation layer on the connecting position of the first bit line structure and the second bit line structure to form a plurality of concave holes, each concave hole exposing a bit lines; deposit a first layer of polysilicon in each recess to form bit line contact plugs.
  • the step of depositing a first layer of polysilicon in each recessed hole to form the bit line contact plug includes: depositing a first layer of polysilicon in each recessed hole, the first layer of polysilicon filling the recessed hole and Covering the remaining isolation layer; removing part of the first layer of polysilicon, the remaining first layer of polysilicon is located in the concave hole, and the top surface of the remaining first layer of polysilicon is lower than the top surface of the isolation layer, remaining in the concave hole.
  • the first layer of polysilicon in the hole forms the bit line contact plug.
  • the method further includes: forming a second layer of polysilicon on the bit line contact plug, the top surface of the second layer of polysilicon being flat with the top surface of the isolation layer aligning; forming a protective layer on the remaining isolation layer and the second polysilicon layer; removing part of the protective layer, part of the second polysilicon layer and part of the isolation layer to form word line trenches, and the word line trenches are arranged along the fourth direction , and extends along the first direction, the fourth direction is perpendicular to the first direction, the remaining second layer of polysilicon forms the active region on both sides of the word line trench, and the remaining protective layer is formed with the word line trench
  • the width of the node plug grooves is greater than the width of the word line grooves.
  • the remaining second layer of polysilicon is ion-implanted to form an active region.
  • the method further includes: forming a first dielectric layer at the bottom of the word line trench; forming a second dielectric layer on the first dielectric layer, the second dielectric layer covering the side of the active region wall; a metal layer is formed on the first dielectric layer in the word line trench and on the side of the second dielectric layer away from the active region, the metal layer fills the word line trench and the node plug groove, and covers the reserved On the isolation layer and the remaining protective layer; the metal layer is etched back so that the metal layer is lower than the active area; a third dielectric layer is formed on the metal layer, and the top surface of the third dielectric layer is flush with the bottom surface of the protective layer.
  • the method further includes: forming a third layer of polysilicon on the third dielectric layer, the third layer of polysilicon filling the node plug grooves and covering the protective layer; removing part of the third layer of polysilicon, The remaining third layer of polysilicon forms a plurality of node contact plugs, each node contact plug is electrically connected to the top of the corresponding active region, and the node contact plug and the bit line contact plug are in a direction perpendicular to the substrate one by one correspond.
  • the memory and the preparation method thereof provided by the embodiments of the present application can solve the problems.
  • Other technical problems, other technical features included in the technical solution, and the beneficial effects brought about by these technical features will be described in further detail in the specific embodiments.
  • FIG. 1 is a flowchart of a method for preparing a memory according to an embodiment of the present application
  • FIG. 2a is a schematic view of the structure after bit line trenches are arranged on the substrate according to an embodiment of the present application;
  • Fig. 2b is the sectional view of the AA position in Fig. 2a;
  • Figure 2c is a cross-sectional view of the BB position in Figure 2a;
  • 3a is a schematic structural diagram of a first layer of silicon dioxide being arranged in the bit line trench in an embodiment of the present application;
  • Fig. 3b is the sectional view of the AA position in Fig. 3a;
  • Fig. 3c is the sectional view of the BB position in Fig. 3a;
  • FIG. 4a is a schematic structural diagram of a first isolation layer formed in a bit line trench according to an embodiment of the present application
  • Fig. 4b is the sectional view of the AA position in Fig. 4a;
  • Figure 4c is a cross-sectional view of the BB position in Figure 4a;
  • FIG. 5a is a schematic structural diagram of a tungsten metal layer after a metal tungsten layer is disposed in the bit line trench according to an embodiment of the present application;
  • Fig. 5b is the sectional view of the AA position in Fig. 5a;
  • Figure 5c is a cross-sectional view of the BB position in Figure 5a;
  • 6a is a schematic structural diagram of a bit line formed in a bit line trench according to an embodiment of the present application.
  • Fig. 6b is the sectional view of the AA position in Fig. 6a;
  • Figure 6c is a cross-sectional view of the BB position in Figure 6a;
  • FIG. 7a is a schematic structural diagram of a second layer of silicon dioxide disposed in the bit line trenches according to an embodiment of the present application.
  • Figure 7b is a sectional view of the AA position in Figure 7a;
  • Fig. 7c is a sectional view of the BB position in Fig. 7a;
  • FIG. 8a is a schematic structural diagram after removing part of the second layer of silicon dioxide in an embodiment of the present application.
  • Figure 8b is a cross-sectional view of the AA position in Figure 8a;
  • Figure 8c is a cross-sectional view of the BB position in Figure 8a;
  • FIG. 9a is a schematic structural diagram after removing a part of the substrate between adjacent partition walls in an embodiment of the present application.
  • Figure 9b is a sectional view of the AA position in Figure 9a;
  • Figure 9c is a sectional view of the BB position in Figure 9a;
  • FIG. 10a is a schematic structural diagram of a third isolation layer provided in the gap between the isolation walls in the embodiment of the present application.
  • Figure 10b is a sectional view at the AA position in Figure 10a;
  • Figure 10c is a cross-sectional view at the BB position in Figure 10a;
  • FIG. 11a is a schematic structural diagram of the isolation layer provided with concave holes in an embodiment of the present application.
  • Fig. 11b is a sectional view at the AA position in Fig. 11a;
  • Figure 11c is a cross-sectional view at the BB position in Figure 11a;
  • Fig. 12a is a schematic structural diagram of a first layer of polysilicon in the concave hole and on the remaining isolation layer in the embodiment of the present application;
  • Figure 12b is a sectional view at the AA position in Figure 12a;
  • Figure 12c is a cross-sectional view at the BB position in Figure 12a;
  • FIG. 13a is a schematic structural diagram after removing part of the first layer of polysilicon according to an embodiment of the present application.
  • Figure 13b is a sectional view at the AA position in Figure 13a;
  • Figure 13c is a sectional view at the BB position in Figure 13a;
  • 14a is a schematic structural diagram of forming a bit line contact plug in a recess in an embodiment of the present application
  • Figure 14b is a sectional view of the AA position in Figure 14a;
  • Figure 14c is a cross-sectional view at the BB position in Figure 14a;
  • 14d is a flowchart of forming a bit line contact plug in an embodiment of the present application.
  • 15a is a schematic structural diagram of filling a second layer of polysilicon in the concave hole and disposing a protective layer on the second layer of polysilicon and the remaining isolation layer in an embodiment of the present application;
  • Figure 15b is a sectional view of the AA position in Figure 15a;
  • Figure 15c is a cross-sectional view at the BB position in Figure 15a;
  • FIG. 16a is a schematic structural diagram after forming word line trenches and node plug trenches and after forming a first dielectric layer in the word line trenches according to an embodiment of the present application;
  • Figure 16b is a sectional view at the AA position in Figure 16a;
  • Figure 16c is a sectional view at the BB position in Figure 16a;
  • FIG. 17a is a schematic structural diagram after disposing a second dielectric layer in the word line trenches according to an embodiment of the present application.
  • Figure 17b is a cross-sectional view at the AA position in Figure 17a;
  • Figure 17c is a sectional view at the BB position in Figure 17a;
  • FIG. 18a is a schematic structural diagram after a metal layer is disposed in the word line trench in an embodiment of the present application.
  • Figure 18b is a cross-sectional view at the AA position in Figure 18a;
  • Figure 18c is a cross-sectional view at the BB position in Figure 18a;
  • 19a is a schematic structural diagram after removing the metal layer above the top surface of the protective layer in an embodiment of the present application
  • Figure 19b is a sectional view at the AA position in Figure 19a;
  • Figure 19c is a cross-sectional view at the BB position in Figure 19a;
  • 20a is a schematic structural diagram of removing a part of the metal layer in the word line trench and disposing a third dielectric layer on the metal layer in an embodiment of the present application;
  • Figure 20b is a sectional view at the AA position in Figure 20a;
  • Figure 20c is a cross-sectional view at the BB position in Figure 20a;
  • 21a is a schematic structural diagram of a third layer of polysilicon disposed in the node plug groove according to an embodiment of the present application.
  • Figure 21b is a sectional view at the AA position in Figure 21a;
  • Figure 21c is a cross-sectional view at the BB position in Figure 21a.
  • 200 the first isolation layer
  • 201 the first layer of silicon dioxide
  • 700 isolation layer
  • 701 concave hole
  • 800 The bit line contacts the plunger; 801: The first layer of polysilicon;
  • A01 Node plunger groove
  • B00 The first dielectric layer
  • C00 Second dielectric layer
  • D00 Metal layer
  • E00 The third dielectric layer
  • F00 The third layer of polysilicon.
  • a shallow trench isolation structure is generally formed to define an active region, and then buried word lines are formed in the active region by etching, and bit line contacts are formed between the buried word lines.
  • the plunger is connected to the plunger through the bit line; and the mainstream dynamic random access memory in the prior art is a 3HPAA multiplied by 2HPWL structure, 3HPAA multiplied by 2HPWL to determine a bit cell area, 3HPAA multiplied by 2HPWL refers to 3 times the active area
  • the half pitch is multiplied by 2 times the half pitch of the word line.
  • the length of each bit line is short, the number of bit line contact plungers corresponding to each bit line is small, and the number of active regions corresponding to the subsequent settings is small. , the number of capacitors set subsequently is relatively small, and the integration degree of the memory is low.
  • the embodiments of the present application provide a memory and a method for preparing the same.
  • the length of each bit line increases on a substrate of unit size, and the subsequently arranged bit lines are in contact with the bit lines.
  • the number of bit line contact plungers will increase, the number of subsequently set active regions corresponding to the bit line contact plungers will increase, and the number of subsequently set capacitors corresponding to the active regions will also increase. Increase, thus, improve the integration degree of memory.
  • an embodiment of the present application provides a method for preparing a memory, which includes the following steps:
  • S01 Provide a substrate, and the material of the substrate can be a semiconductor substrate material well known to those skilled in the art, such as silicon and germanium.
  • each bit line trench is S-shaped, wherein the first The direction is the X direction as shown in FIG. 2a, and the structure formed in this step is shown in FIG. 2a, FIG. 2b and FIG. 2c.
  • a plurality of bit line trenches 101 are arranged at intervals and along the first direction. Arranged, each bit line trench 101 is S-shaped.
  • a first isolation layer is formed in each bit line trench 101.
  • the thickness of the first isolation layer is less than the depth of the bit line trench 101.
  • the material of the first isolation layer can be silicon dioxide, for example, and the first isolation layer can be It is formed in the bit line trench 101 by a deposition method.
  • a first layer of silicon dioxide is formed on the substrate 100 provided with the bit line trench 101, and the first layer of silicon dioxide is filled with silicon dioxide.
  • the bit line trench 101 is filled and covered on the remaining substrate 100, and part of the first layer of silicon dioxide higher than the top surface of the substrate 100 is removed. The structure formed by this step is shown in FIG. 3a, FIG. 3b and FIG. 3c.
  • the first layer of silicon dioxide 201 is located in the bit line trench 101, and the first layer of silicon dioxide 201 is flush with the top surface of the substrate 100; secondly, continue to remove part of the first layer of silicon dioxide 201, only part of the first layer of silicon dioxide 201 in the bit line trench 101 is retained, and the thickness of the first layer of silicon dioxide 201 retained in the bit line trench 101 is less than the depth of the bit line trench 101 to form
  • the first isolation layer the structure formed by this step is shown in FIG. 4a, FIG. 4b and FIG. 4c.
  • the first isolation layer 200 is located in the bit line trench 101, and the thickness of the first isolation layer 200 is Less than the depth of the bit line trench 101 , the top surface of the first isolation layer 200 is lower than the notch of the bit line trench 101 .
  • bit line on the first isolation layer 200, the total thickness of the first isolation layer 200 and the bit line is less than the groove depth of the bit line trench 101, a plurality of bit lines are arranged along the first direction, and each bit line It is S-shaped, and the material of the bit line may be metal tungsten, for example, and the bit line may be formed on the first isolation layer 200 in the bit line trench 101 by a deposition method.
  • a metal tungsten layer is formed on the substrate 100 provided with the bit line trench 101 and the first isolation layer 200. The metal tungsten layer fills the bit line trench 101 and covers the remaining portion.
  • FIG. 5a The dotted line in FIG. 5a is used to show the position of the bit line trench 101.
  • the metal tungsten layer 301 is located in the bit line trench. inside the trench 101, and the metal tungsten layer 301 also covers the top surface of the remaining substrate 100; secondly, part of the metal tungsten layer 301 is removed, and only the metal tungsten layer 301 in the bit line trench 101 remains, and remains in place
  • the thickness of the metal tungsten layer 301 in the line trench 101 is smaller than the depth of the bit line trench 101 to form the bit line.
  • the structure formed in this step is shown in FIG. 6a, FIG. 6b and FIG. 6c.
  • the bit line 300 is located on the first isolation layer 200 in the bit line trench 101, the top surface of the bit line 300 is lower than the notch of the bit line trench 101, and the thickness of the bit line 300 plus the thickness of the first isolation layer 200 is less than that of the bit line 300.
  • the groove depth of the wire groove 101 is less than that of the bit line 300.
  • each bit line 300 formed includes a plurality of first bit line structures 302 and a plurality of second bit lines arranged at intervals and connected in sequence Structure 303, the first bit line structure 302 extends in a second direction, the second direction is inclined relative to the first direction, the second bit line structure 303 extends in a third direction, the third direction is inclined relative to the first direction, and the third The direction is opposite to the inclination direction of the second direction relative to the first direction, wherein the second direction is the Y direction as shown in Fig. 6a, and the third direction is the Z direction as shown in Fig. 6a.
  • a second isolation layer is formed on the bit line 300.
  • the top surface of the second isolation layer is flush with the top surface of the substrate 100.
  • the material of the second isolation layer and the material of the first isolation layer 200 may be the same material.
  • the material of the second isolation layer is silicon dioxide, for example, and the second isolation layer can be formed on the bit line 300 in the bit line trench 101 by a deposition method.
  • a second layer of silicon dioxide is formed on the substrate 100 provided with the bit lines 300 , the second layer of silicon dioxide fills the bit line trenches 101 and covers the remaining substrate 100 7a, 7b and 7c, the dotted line in FIG.
  • FIG. 7a is used to show the position of the bit line trench 101, in the structure formed by this step, the second layer of silicon dioxide 401 is located in the bit line In the trench 101, the second layer of silicon dioxide 401 also covers the top surface of the remaining substrate 100; secondly, part of the second layer of silicon dioxide 401 is removed, and only the second layer of the second layer in the bit line trench 101 is retained Silicon oxide 401, and the top surface of the second layer of silicon dioxide 401 remaining in the bit line trench 101 is flush with the top surface of the substrate 100 to form a second isolation layer.
  • the structure formed in this step is shown in FIG. 8a and FIG.
  • the second isolation layer 400 is located on the bit line 300 in the bit line trench 101, the thickness of the second isolation layer 400 plus the thickness of the bit line 300, plus the The thickness of an isolation layer 200 is equal to the trench depth of the bit line trenches 101 .
  • S06 Remove the substrate 100 between adjacent isolation walls, and retain the substrate 100 below the bottom surface of the first isolation layer 200, wherein the isolation wall includes the first isolation layer 200, the bit line 300 and the second isolation layer 400, and remove the phase
  • the substrate 100 between adjacent isolation walls can be etched.
  • the structure formed in this step is shown in FIG. 9a, FIG. 9b and FIG. 9c.
  • each isolation wall 500 includes a first isolation layer 200 disposed on the substrate 100 , a bit line 300 disposed on the first isolation layer 200 , and a second isolation layer disposed on the bit line 300 400, wherein each partition wall 500 is S-shaped, and a plurality of partition walls 500 are arranged along the first direction.
  • a third isolation layer is formed in the gap between adjacent isolation walls 500.
  • the third isolation layer, the second isolation layer 400 and the first isolation layer 200 together form an isolation layer.
  • the material of the third isolation layer is the same as that of the first isolation layer.
  • the material of the isolation layer 200 and the material of the second isolation layer 400 can be the same material, the material of the third isolation layer is silicon dioxide, for example, and the third isolation layer can be formed between the two adjacent isolation walls 500 by a deposition method. in the gap between.
  • the structure formed in this step is shown in FIG. 10 a , FIG. 10 b and FIG. 10 c .
  • the isolation wall 500 and the third isolation layer 600 are arranged on the substrate 100 at intervals.
  • the top is the second isolation layer 400 , the two sides of the bit line 300 are the third isolation layer 600 , and the bit line 300 is formed in the isolation layer 700 formed by the first isolation layer 200 , the second isolation layer 400 and the third isolation layer 600 ,
  • the isolation layer 700 can achieve insulation between adjacent bit lines 300.
  • the dotted line in FIG. 10a is used to show the position of the bit line trench 101
  • the dotted line in FIG. 10b and FIG. 10c is used to show the first isolation layer 200 and the second isolation layer. 400 and the third isolation layer 600 are formed in different process steps.
  • an S-shaped bit line trench 101 is provided on the substrate 100, and an S-shaped bit line 300 is formed in the S-shaped bit line trench 101.
  • the preparation In the memory, on the substrate 100 of a unit size, the length of the bit line 300 arranged in the isolation layer 700 increases, the number of the bit line contact plungers that are subsequently arranged in contact with the bit line 300 will increase, and the subsequently arranged bit line 300 contacts with the bit line.
  • the number of active regions corresponding to the contact plungers one-to-one will increase, the number of capacitors corresponding to the active regions one-to-one will be increased, and the integration degree of the memory will be higher.
  • the memory prepared by the memory preparation method of the embodiment of the present application has a structure of 2HPAA by 2HPWL, 2HPAA by 2HPWL determines a bit cell area, and 2HPAA by 2HPWL refers to twice the half pitch of the active area times the half of the word line.
  • the area of the 4F2 memory cell formed by the 2HPAA multiplied by 2HPWL structure will be reduced to about two-thirds of the 6F2 memory cell formed by the 3HPAA multiplied by 2HPWL structure, which is equivalent to the higher storage density and higher integration of the 4F2 memory structure.
  • the third isolation layer 600 further includes:
  • each concave hole exposes the bit line 300, and the shape of the concave hole can be a circular hole, Removing part of the isolation layer 700 at the connection position between the first bit line structure 302 and the second bit line structure 303 can be etched to form a concave hole.
  • the structure formed by this step is shown in FIG. 11a, FIG. 11b and FIG.
  • each concave hole 701 is located at the connection position of the first bit line structure 302 and the second bit line structure 303, and each concave hole 701 exposes its corresponding bit line 300, wherein the dotted line in FIG. In the position showing the bit line trench 101, the dotted lines in FIGS. 11b and 11c are used to show that the first isolation layer 200 and the third isolation layer 600 are formed in different process steps.
  • S09 deposit a first layer of polysilicon in each recessed hole 701 to form a bit line contact plug, and deposit the first layer of polysilicon in each recessed hole 701 by chemical vapor deposition (Chemical Vapor Deposition, English abbreviation). CVD), or atomic layer deposition (Atomic Layer Deposition in English, ALD for short in English), and while depositing the first layer of polysilicon, doping with ions that change the electrical properties of the first layer of polysilicon, such as doping Phosphorus or boron ions.
  • the structure formed by this step is shown in FIG. 14a, FIG. 14b and FIG. 14c.
  • the bit line contact plug 800 is located in the recessed hole 701, and the top surface of the bit line contact plug 800 is lower than the third isolation
  • the thickness of the bit line contact plug 800 may be, for example, 50 nanometers (nm), wherein the dotted line in FIG.
  • the dotted lines in 14b and 14c are used to show that the first isolation layer 200 and the third isolation layer 600 are formed in different process steps.
  • the step of depositing a first layer of polysilicon in each recess 701 to form the bit line contact plug 800 includes:
  • FIGS. 12 a , 12 b and 12 c depositing a first layer of polysilicon in each concave hole 701 , the first layer of polysilicon fills the concave hole 701 and covers the remaining isolation layer 700 , the structure formed by this step is shown in FIGS. 12 a , 12 b and 12 c As shown, in the structure formed by this step, the first layer of polysilicon 801 fills the concave hole 701, and the first layer of polysilicon 801 covers the remaining isolation layer 700, wherein the dotted line in FIG. 12a is used to show the bit line trench 101 and the positions of the concave holes 701, the dotted lines in FIG. 12b and FIG. 12c are used to show that the first isolation layer 200 and the third isolation layer 600 are formed in different process steps.
  • S92 remove part of the first layer of polysilicon 801 , the remaining first layer of polysilicon 801 is located in the concave hole 701 , and the top surface of the remaining first layer of polysilicon 801 is lower than the top surface of the isolation layer 700 and remains in the concave hole 701
  • the first layer of polysilicon 801 in this step forms the bit line contact plug 800.
  • the structure formed in this step is shown in FIG. 14a, FIG. 14b and FIG. 14c. In the structure formed in this step, the first layer of polysilicon 801 is filled in the concave hole 701.
  • the top surface of the first layer of polysilicon 801 is lower than the top surface of the third isolation layer 600 and the top surface of the second isolation layer 400 , and the first layer of polysilicon 801 remaining in the recess 701 forms the bit line contact plug 800 .
  • a structure is formed as shown in FIG. 13a, FIG. 13b and FIG. 13c.
  • the first layer of polysilicon 801 is filled in the In the recessed hole 701, the top surface of the first layer of polysilicon 801 is flush with the top surface of the third isolation layer 600 and the top surface of the second isolation layer 400.
  • FIG. 13a is used to show the position of the bit line trench 101.
  • FIG. The dotted lines in 13b and 13c are used to show that the first isolation layer 200 and the third isolation layer 600 are formed in different process steps. Continue to remove part of the first layer of polysilicon 801 in the recessed hole 701, and the formed structure is shown in FIG. 14a and FIG. 14b and Figure 14c.
  • the method further includes:
  • a second layer of polysilicon is formed on the bit line contact plug 800, the top surface of the second layer of polysilicon is flush with the top surface of the isolation layer 700, and the second layer of polysilicon can be formed on the bit line contact plug 800 by a deposition method 15a, 15b and 15c, in the structure formed in this step, the bottom surface of the second layer of polysilicon 900 is in contact with the bit line contact plug 800, and the top of the second layer of polysilicon 900 is in contact with the bit line contact plug 800.
  • the surface is flush with the top surface of the isolation layer 700, wherein the dotted line in FIG. 15a is used to show the position of the bit line trench 101 and the position of the concave hole 701, and the dotted line in FIG. 15b and FIG. 15c is used to show the first isolation layer 200 and the
  • the third isolation layer 600 is formed in different process steps.
  • a protective layer is formed on the remaining isolation layer 700 and the second layer of polysilicon 900.
  • the material of the protective layer can be, for example, silicon nitride, and the protective layer can also be formed on the remaining isolation layer 700 and the second layer by deposition.
  • the structure formed in this step is shown in FIG. 15a, FIG. 15b and FIG. 15c.
  • the protective layer A00 is disposed on the second layer of polysilicon 900 and the remaining isolation layer 700.
  • the remaining isolation layer 700 includes the third isolation layer 600 , the first isolation layer 200 and a part of the second isolation layer 400 .
  • SOC remove part of the protective layer A00, part of the second layer of polysilicon 900 and part of the isolation layer 700 to form word line trenches, the word line trenches are arranged along the fourth direction and extend along the first direction, the fourth direction and the first direction One direction is vertical, the fourth direction is the U direction as shown in FIG. 16a, the remaining second layer of polysilicon 900 forms active regions on both sides of the word line trench, and the remaining protective layer A00 is formed with the word line trench For the node plug grooves connected to the grooves, the width of the node plug grooves is greater than the width of the word line grooves.
  • the word line trenches 901 extend along the first direction, and a plurality of word line trenches 901 are arranged along the fourth direction.
  • the width of the word line trenches 901 is smaller than the width of the second layer of polysilicon 900, and the remaining The second layer of polysilicon 900 is located on both sides of each word line trench 901, the remaining second layer of polysilicon 900 constitutes the active region 902, the width of the word line trench 901 is smaller than the width of the node plug groove A01, the node column
  • the plug groove A01 exposes the top surface of the active region 902 .
  • step SOC the remaining second layer of polysilicon 900 needs to be ion implanted to form an active region 902.
  • the ions implanted can be boron ions or phosphorus ions.
  • Implanting ions on the second layer of polysilicon 900 can form an active region 902.
  • the active region 902 is provided with source/drain.
  • the word line trench 901 further includes:
  • a first dielectric layer is formed at the bottom of the word line trench 901 .
  • the material of the first dielectric layer may be silicon dioxide, and the first dielectric layer may also be formed at the bottom of the word line trench 901 by a deposition method.
  • the structure formed in this step is shown in FIG. 16a, FIG. 16b and FIG. 16c.
  • the first dielectric layer B00 is disposed in the word line trench 901, and the thickness of the first dielectric layer B00 is smaller than that of the word line trench.
  • the depth of the trench 901, the top surface of the first dielectric layer B00 is lower than the notch of the word line trench 901, wherein the dotted line in FIG. 16a is used to show the position of the bit line trench 101, and the dotted line in FIG. It is shown that the first isolation layer 200, the third isolation layer 600 and the first dielectric layer B00 are formed in different process steps.
  • a second dielectric layer is formed on the first dielectric layer B00.
  • the second dielectric layer covers the sidewall of the active region 902.
  • the material of the second dielectric layer can be silicon dioxide, for example, and the second dielectric layer can be processed by an in-situ water vapor method.
  • the thickness of the second dielectric layer can be about 5nm
  • the structure formed by this step is shown in Figure 17a, Figure 17b and Figure 17c
  • the structure formed by this step Among them, the second dielectric layer C00 is disposed on the first dielectric layer B00, and the second dielectric layer C00 covers the sidewall of the active region 902, and the thickness of the second dielectric layer C00 is less than half of the groove width of the word line trench 901,
  • the dotted line in FIG. 17a is used to show the position of the bit line trench 101
  • the dotted line in FIG. 16b and FIG. 16c is used to show the first isolation layer 200, the third isolation layer 600, the first dielectric layer B00 and the second dielectric layer C00 are formed in different process steps.
  • a metal layer is formed on the first dielectric layer B00 in the word line trench 901 and on the side of the second dielectric layer C00 away from the active region 902, and the metal layer fills the word line trench 901 and the node plug trench A01 , and cover the remaining isolation layer 700 and the remaining protective layer A00;
  • the material of the metal layer can be metal tungsten, for example, and the metal layer can be deposited on the first dielectric layer in the word line trench 901, for example. in the space formed by B00 and the second dielectric layer C00.
  • the structure formed by this step is shown in FIG. 18a, FIG. 18b and FIG. 18c.
  • the metal layer D00 fills the word line trench 901 and the node plug groove A01, and the metal layer D00 covers the remaining On the isolation layer 700 and the remaining protective layer A00, wherein the dotted line in FIG. 18a is used to show the position of the bit line trench 101 and the position of the concave hole 701, and the dotted line in FIG. 18b and FIG. 18c is used to show the first isolation layer 200 , the third isolation layer 600 , the first dielectric layer B00 and the second dielectric layer C00 are formed in different process steps.
  • the metal layer D00 is etched back so that the top surface of the metal layer D00 is lower than the top surface of the active region 902.
  • the metal layer D00 can be etched back.
  • FIG. 20a and FIG. 20b for the structure formed by this step.
  • the metal layer D00 is arranged in the trench enclosed by the first dielectric layer B00 and the second dielectric layer C00 in the word line trench 901, and the top surface of the metal layer D00 is low on the top surface of the active region 902 .
  • the metal layer D00 is etched back, when the top surface of the metal layer D00 is flush with the top surface of the protective layer A00, a structure is formed as shown in FIG.
  • FIG. 19a FIG. 19b and FIG. 19c.
  • the layer D00 fills the word line trench 901 and the node plug trench A01, and the top surface of the metal layer D00 is flush with the top surface of the protective layer A00, wherein the dotted line in FIG. 19a is used to show the position of the bit line trench 101,
  • the dotted lines in FIGS. 19b and 19c are used to show that the first isolation layer 200 , the third isolation layer 600 , the first dielectric layer B00 and the second dielectric layer C00 are formed in different process steps.
  • a third dielectric layer is formed on the metal layer D00, the top surface of the third dielectric layer is flush with the bottom surface of the protective layer A00, the material of the third dielectric layer can be silicon dioxide, for example, the third dielectric layer can be deposited 20a, 20b and 20c.
  • the bottom surface of the third dielectric layer E00 is in contact with the top surface of the metal layer D00, and the first The top surface of the three dielectric layers E00 is flush with the active region 902, and the metal layer D00 forms a word line.
  • the dotted line in FIG. 20a is used to show the position of the bit line trench 101, and the dotted line in FIG. 20b and FIG.
  • An isolation layer 200, a third isolation layer 600, a first dielectric layer B00, a second dielectric layer C00 and a third dielectric layer E00 are formed in different process steps.
  • the third dielectric layer E00 further includes:
  • a third layer of polysilicon is formed on the third dielectric layer E00, the third layer of polysilicon fills the node plug groove A01 and covers the protective layer A00, and the third layer of polysilicon can use a chemical vapor deposition method (the English name is Chemical Vapor Deposition, English abbreviated as CVD) fills the node plug groove A01 and covers the protective layer A00, and at the same time of depositing the third layer of polysilicon, doping with ions that change the electrical properties of the third layer of polysilicon, such as doping phosphorus ions or boron ion.
  • CVD Chemical Vapor Deposition
  • the bottom surface of the third layer of polysilicon F00 is in contact with the top surface of the third dielectric layer E00 and the top surface of the active region 902, the third layer of polysilicon F00 is filled with the node plug groove A01, and the third layer of polysilicon The top surface of F00 covers the top surface of the protective layer A00.
  • the bottom surface of the third layer of polysilicon F00 is in contact with the top surface of the third dielectric layer E00 and the top surface of the active region 902 , the third layer of polysilicon F00 is filled with the node plug groove A01 , and the top surface of the third layer of polysilicon F00 is in contact with the protective layer A00 21a is used to show the position of the bit line trench 101, and the dashed lines in FIGS. 21b and 21c are used to show the first isolation layer 200, the third isolation layer 600, the first dielectric layer B00 , the second dielectric layer C00 and the third dielectric layer E00 are formed in different process steps.
  • a plurality of node contact plugs are formed in each node plug groove A01, and each node contact plug corresponds to the corresponding The tops of the active regions 902 are electrically connected, and the node contact plugs correspond to the bit line contact plugs 800 in a direction perpendicular to the substrate 100 .
  • the memory provided by the embodiment of the present application includes a substrate 100, an isolation layer 700 is disposed on the substrate 100, a plurality of bit lines 300 are arranged at intervals in the isolation layer 700, and the plurality of bit lines 300 are arranged along a first direction, and each The strip bit lines 300 are S-shaped, and the first direction is the X direction as shown in FIG. 2a.
  • the isolation layer 700 of the substrate 100 is provided with a plurality of bit lines 300 arranged at intervals, and each bit line 300 is S-shaped and arranged along the first direction.
  • the number of the bit line contact plungers 800 that are subsequently set in contact with the bit line 300 will increase, and the subsequently set active regions corresponding to the bit line contact plungers 800 one-to-one
  • the number of 902 will increase, and the number of capacitors corresponding to the active regions 902 one-to-one will also increase, so that the integration degree of the memory is higher.
  • each bit line 300 includes a plurality of first bit line structures 302 and a plurality of second bit line structures 303 arranged at intervals and connected in sequence.
  • the first bit line structures 302 extend along the second direction, and the second The direction is inclined relative to the first direction, the second bit line structure 303 extends along a third direction, the third direction is inclined relative to the first direction, and the third direction is opposite to the inclination direction of the second direction relative to the first direction.
  • each bit line 300 includes three first bit line structures 302 and three second bit line structures 303, three first bit line structures 302 and three second bit lines The structures 303 are arranged at intervals and connected in sequence.
  • the first bit line structures 302 extend along the second direction, the second direction is the Y direction as shown in FIG. 6a, and the second bit line structures 303 extend along the third direction, which is shown in the third direction
  • the Z-direction, Y-direction and Z-direction shown in 6a are opposite to the inclination directions of the X-direction shown in FIG. 2a.
  • each bit line 300 is provided with a plurality of bit line contact plugs 800 arranged at intervals, and the bit line contact plugs 800 are disposed in the isolation layer 700 , and each bit line contact plunger 800 is disposed at the connection position of the corresponding first bit line structure 302 and the second bit line structure 303 .
  • five bit line contact plugs 800 are disposed above each bit line 300, and each bit line contact plug 800 is disposed on the connected first bit line structure 302 and the first The connection of the two-bit line structure 303 .
  • each bit line contact plug 800 is provided with an active region 902 , and the active region 902 is provided in the isolation layer 700 .
  • the active region 902 is disposed in the isolation layer 700, the active region 902 is connected to the bit line 300 through the bit line contact plug 800, and the bottom surface of the active region 902 is connected to the bit line
  • the top surface of the contact plug 800 is in contact, and the bottom surface of the bit line contact plug 800 is in contact with the top surface of the bit line 300 .
  • the isolation layer 700 is also provided with a plurality of word lines, the plurality of word lines are arranged along the fourth direction, each word line extends along the first direction, the fourth direction is perpendicular to the first direction, and the fourth direction is shown in FIG. 16a out of the U direction.
  • Each word line includes a plurality of gates and a plurality of word line structures, each gate is correspondingly disposed in one active region 902 , and the plurality of gates included in each word line is correspondingly disposed in the same column of active regions 902 , the active regions 902 in the same column are arranged along the first direction, a plurality of gates and a plurality of word line structures are arranged one by one at intervals, each word line structure is arranged in the isolation layer 700, and each word line structure is used to connect the phase adjacent to the two gates.
  • each word line includes five gates and five word line structures, and the gates are at least composed of the metal layer D00 disposed in the active region 902,
  • the word line structure is composed of at least a metal layer D00 disposed in the isolation layer 700, and five gates and five word line structures are spaced apart.
  • the word line includes a metal layer D00 and a dielectric layer
  • the dielectric layer includes a first dielectric layer B00, a second dielectric layer C00 and a third dielectric layer E00
  • the first dielectric layer B00 is set in place
  • a metal layer D00 and a second dielectric layer C00 are arranged on the top surface of the first dielectric layer B00, and the top surface of the metal layer D00 is flush with the top surface of the second dielectric layer C00.
  • the dielectric layer C00 is disposed on two opposite sides of the metal layer D00
  • the third dielectric layer E00 is disposed on the top surface of the metal layer D00 and the top surface of the second dielectric layer C00.
  • a plurality of node contact plugs are arranged at intervals on each word line, each node contact plug is electrically connected to the top of the active region 902 , and the node contact plug and the bit line contact plug 800 are in a direction perpendicular to the substrate 100 .

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Abstract

本申请提供一种存储器及其制备方法，涉及半导体技术领域，该存储器包括基底，基底上设置有隔离层，隔离层内间隔排布有多条位线，多条位线沿第一方向排布，且每条位线呈S形。该存储器的制备方法包括如下步骤：提供基底；在基底上形成多条位线沟槽；在每条位线沟槽内形成第一隔离层；在第一隔离层上形成位线；在位线上形成第二隔离层；去除相邻的隔离墙之间的基底，隔离墙包括第一隔离层、位线以及第二隔离层；在相邻的隔离墙之间的间隙内形成第三隔离层，第三隔离层、第二隔离层和第一隔离层共同形成隔离层。本申请实施例的存储器以及采用该存储器的制备方法制备的存储器，集成度高。

Description

存储器及其制备方法
本申请要求于2021年03月04日提交中国专利局、申请号为202110240857.0、申请名称为“存储器及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种存储器及其制备方法。
背景技术
动态随机存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
现有的动态随机存储器，一般是先形成浅沟槽隔离结构定义出有源区，然后在有源区中刻蚀形成埋入式字线，在埋入式字线之间形成位线接触柱塞，再通过位线连接各位线接触柱塞；且现有技术中较主流的动态随机存储器是3HPAA乘2HPWL结构，3HPAA乘2HPWL确定一个位单元(英文全称为cell bit)面积，3HPAA乘2HPWL指3倍的有源区(英文全称为active region，英文简称为AA)的半节距(英文全称为half pitch，英文简称为HP)乘以2倍的字线(英文全称为word line，英文简称为WL)的半节距。然而，这种结构的动态随机存储器集成度较低。
发明内容
鉴于上述问题，本申请实施例提供一种存储器及其制备方法，以提升存储器的集成度。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种存储器，其包括基底，基底上设置有隔离层，隔离层内间隔排布有多条位线，多条位线沿第一方向排布，且每条位线呈S形。
本申请实施例的存储器，基底的隔离层内设置有间隔排布的多条位线，每条位线呈S形且沿第一方向排布，在单位尺寸的基底上，隔离层内设置的每条位线长度增长，后续设置的与位线接触的位线接触柱塞的数量就会增加，后续设置的与位线接触柱塞一一对应的有源区的数量就会增多，后续设置的与有源区一一对应的电容器的数量也会增多，如此，存储器的集成度更高。
在一些实施方式中，每条位线包括间隔排布且依次连接的多个第一位线结构和多个第二位线结构，第一位线结构沿第二方向延伸，第二方向相对第一方向倾斜设置，第二位线结构沿第三方向延伸，第三方向相对第一方向倾斜设置，且第三方向与第二方向相对第一方向的倾斜方向相反。
在一些实施方式中，每条位线上设置有间隔排布的多个位线接触柱塞，位线接触柱塞设置在隔离层内，且每个位线接触柱塞设置在对应的第一位线结构和第二位线结构的连接位置。
在一些实施方式中，每个位线接触柱塞上设置有源区，有源区设置在隔离层内。
在一些实施方式中，隔离层内还设置有多条字线，多条字线沿第四方向排布，每条字线沿第一方向延伸，第四方向与第一方向垂直设置。
在一些实施方式中，每条字线包括多个栅极和多个字线结构，每个栅极对应设置在一个有源区内，每条字线包括的多个栅极对应设置在同一列有源区内，同一列有源区沿第一方向排布，多个栅极和多个字线结构一一间隔设置，每个字线结构设置在隔离层内，每个字线结构用于连接相邻两个栅极。
在一些实施方式中，字线包括金属层和介质层，介质层包括第一介质层、第二介质层和第三介质层，第一介质层的顶面设置金属层和第二介质层，第二介质层设置在金属层的相对两侧面，金属层的顶面和第二介质层的顶面设置第三介质层。
在一些实施方式中，每条字线上间隔设置有多个节点接触柱塞，每个节点接触柱塞与有源区的顶端电连接，节点接触柱塞与位线接触柱塞在垂直于基底方向上一一对应。
本申请实施例的第二方面提供一种存储器的制备方法，其包括如下步骤：提供基底；在基底上形成多条位线沟槽，多条位线沟槽沿第一方向排布，且每条位线沟槽呈S形；在每条位线沟槽内形成第一隔离层，第一隔离层的厚 度小于位线沟槽的深度；在第一隔离层上形成位线，第一隔离层和位线的总厚度小于位线沟槽的深度，多条位线沿第一方向排布，且每条位线呈S形；在位线上形成第二隔离层，第二隔离层的顶面与基底的顶面平齐；去除相邻的隔离墙之间的基底，且保留第一隔离层底面以下的基底，其中，隔离墙包括第一隔离层、位线以及第二隔离层；在相邻的隔离墙之间的间隙内形成第三隔离层，第三隔离层、第二隔离层和第一隔离层共同形成隔离层。
本申请实施例的存储器的制备方法，通过在基底上设置呈S形的位线沟槽，进而在S形的位线沟槽内形成呈S形的位线，如此，使得制备的存储器内，在单位尺寸的基底上，隔离层内设置的每条位线长度增长，后续设置的与位线接触的位线接触柱塞的数量就会增加，后续设置的与位线接触柱塞一一对应的有源区的数量就会增多，后续设置的与有源区一一对应的电容器的数量也会增多，存储器的集成度更高。
在一些实施方式中，在第一隔离层上形成位线的步骤中：形成的每条位线包括间隔排布且依次连接的多个第一位线结构和多个第二位线结构，第一位线结构沿第二方向延伸，第二方向相对第一方向倾斜设置，第二位线结构沿第三方向延伸，第三方向相对第一方向倾斜设置，且第三方向与第二方向相对第一方向的倾斜方向相反。
在一些实施方式中，在形成第三隔离层之后，还包括：去除第一位线结构和第二位线结构连接位置上的部分隔离层以形成多个凹孔，每个凹孔暴露出位线；在每个凹孔中沉积第一层多晶硅以形成位线接触柱塞。
在一些实施方式中，在每个凹孔中沉积第一层多晶硅以形成位线接触柱塞的步骤，包括：在每个凹孔中沉积第一层多晶硅，第一层多晶硅填充满凹孔且覆盖在保留下的隔离层上；去除部分第一层多晶硅，保留下的第一层多晶硅位于凹孔中，并且保留下的第一层多晶硅的顶面低于隔离层的顶面，保留在凹孔中的第一层多晶硅形成位线接触柱塞。
在一些实施方式中，在每个凹孔中形成位线接触柱塞之后，还包括：在位线接触柱塞上形成第二层多晶硅，第二层多晶硅的顶面与隔离层的顶面平齐；在保留下的隔离层和第二层多晶硅上形成保护层；去除部分保护层、部分第二层多晶硅以及部分隔离层，以形成字线沟槽，字线沟槽沿第四方向排布，且沿第一方向延伸，第四方向与第一方向垂直设置，保留下的第二层多 晶硅形成位于字线沟槽两侧的有源区，保留下的保护层内形成与字线沟槽连通的节点柱塞槽，节点柱塞槽的宽度大于字线沟槽的宽度。
在一些实施方式中，保留下的第二层多晶硅经离子注入后形成有源区。
在一些实施方式中，形成字线沟槽后，还包括：在字线沟槽的底部形成第一介质层；在第一介质层上形成第二介质层，第二介质层覆盖有源区侧壁；在字线沟槽内的第一介质层上、且第二介质层远离有源区的侧部形成金属层，金属层填充满字线沟槽和节点柱塞槽，并覆盖在保留下的隔离层和保留下的保护层上；回刻金属层，使金属层低于有源区；在金属层上形成第三介质层，第三介质层的顶面与保护层的底面平齐。
在一些实施方式中，形成第三介质层之后，还包括：在第三介质层上形成第三层多晶硅，第三层多晶硅填充满节点柱塞槽且覆盖保护层；去除部分第三层多晶硅，保留下的第三层多晶硅形成多个节点接触柱塞，每个节点接触柱塞与对应的有源区的顶端电连接，节点接触柱塞与位线接触柱塞在垂直于基底方向上一一对应。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的存储器及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例的存储器的制备方法的流程图；
图2a为本申请实施例中基底上设置位线沟槽后的结构示意图；
图2b为图2a中的AA位置的断面图；
图2c为图2a中的BB位置的断面图；
图3a为本申请实施例中在位线沟槽中设置第一层二氧化硅后的结构示意 图；
图3b为图3a中的AA位置的断面图；
图3c为图3a中的BB位置的断面图；
图4a为本申请实施例中在位线沟槽中形成第一隔离层后的结构示意图；
图4b为图4a中的AA位置的断面图；
图4c为图4a中的BB位置的断面图；
图5a为本申请实施例中在位线沟槽中设置金属钨层后的结构示意图；
图5b为图5a中的AA位置的断面图；
图5c为图5a中的BB位置的断面图；
图6a为本申请实施例中在位线沟槽中形成位线后的结构示意图；
图6b为图6a中的AA位置的断面图；
图6c为图6a中的BB位置的断面图；
图7a为本申请实施例中在位线沟槽中设置第二层二氧化硅后的结构示意图；
图7b为图7a中的AA位置的断面图；
图7c为图7a中的BB位置的断面图；
图8a为本申请实施例中去除部分第二层二氧化硅后的结构示意图；
图8b为图8a中的AA位置的断面图；
图8c为图8a中的BB位置的断面图；
图9a为本申请实施例中去除相邻隔离墙之间的部分基底后的结构示意图；
图9b为图9a中的AA位置的断面图；
图9c为图9a中的BB位置的断面图；
图10a为本申请实施例中在隔离墙之间的间隙设置第三隔离层后的结构示意图；
图10b为图10a中的AA位置的断面图；
图10c为图10a中的BB位置的断面图；
图11a为本申请实施例中在隔离层上设置凹孔后的结构示意图；
图11b为图11a中的AA位置的断面图；
图11c为图11a中的BB位置的断面图；
图12a为本申请实施例中在凹孔中以及保留下的隔离层上设置第一层多 晶硅后的结构示意图；
图12b为图12a中的AA位置的断面图；
图12c为图12a中的BB位置的断面图；
图13a为本申请实施例中去除部分第一层多晶硅后的结构示意图；
图13b为图13a中的AA位置的断面图；
图13c为图13a中的BB位置的断面图；
图14a为本申请实施例中在凹孔中形成位线接触柱塞后的结构示意图；
图14b为图14a中的AA位置的断面图；
图14c为图14a中的BB位置的断面图；
图14d为本申请实施例中形成位线接触柱塞的流程图；
图15a为本申请实施例中在凹孔中填充第二层多晶硅并在第二层多晶硅和保留下的隔离层上设置保护层后的结构示意图；
图15b为图15a中的AA位置的断面图；
图15c为图15a中的BB位置的断面图；
图16a为本申请实施例中形成字线沟槽和节点柱塞槽后并在字线沟槽中形成第一介质层后的结构示意图；
图16b为图16a中的AA位置的断面图；
图16c为图16a中的BB位置的断面图；
图17a为本申请实施例中在字线沟槽中设置第二介质层后的结构示意图；
图17b为图17a中的AA位置的断面图；
图17c为图17a中的BB位置的断面图；
图18a为本申请实施例中在字线沟槽中设置金属层后的结构示意图；
图18b为图18a中的AA位置的断面图；
图18c为图18a中的BB位置的断面图；
图19a为本申请实施例中去除保护层顶面以上的金属层后的结构示意图；
图19b为图19a中的AA位置的断面图；
图19c为图19a中的BB位置的断面图；
图20a为本申请实施例中去除字线沟槽中的部分金属层并在金属层上设置第三介质层后的结构示意图；
图20b为图20a中的AA位置的断面图；
图20c为图20a中的BB位置的断面图；
图21a为本申请实施例中在节点柱塞槽中设置第三层多晶硅后的结构示意图；
图21b为图21a中的AA位置的断面图；
图21c为图21a中的BB位置的断面图。
附图标记：
100：基底；                      101：位线沟槽；
200：第一隔离层；                201：第一层二氧化硅；
300：位线；                      301：金属钨层；
302：第一位线结构；              303：第二位线结构；
400：第二隔离层；                401：第二层二氧化硅；
500：隔离墙；                    600：第三隔离层；
700：隔离层；                    701：凹孔；
800：位线接触柱塞；              801：第一层多晶硅；
900：第二层多晶硅；              901：字线沟槽；
902：有源区；                    A00：保护层；
A01：节点柱塞槽；                B00：第一介质层；
C00：第二介质层；                D00：金属层；
E00：第三介质层；                F00：第三层多晶硅。
具体实施方式
在相关技术中，动态随机存储器一般是先形成浅沟槽隔离结构定义出有源区，然后在有源区中刻蚀形成埋入式字线，在埋入式字线之间形成位线接触柱塞，再通过位线连接各位线接触柱塞；且现有技术中较主流的动态随机存储器是3HPAA乘2HPWL结构，3HPAA乘2HPWL确定一个位单元面积，3HPAA乘2HPWL指3倍的有源区的半节距乘以2倍的字线的半节距。然而，这种结构的动态随机存储器，单位尺寸的基底上，每条位线的长度短，每条位线对应设置的位线接触柱塞数量少，后续对应设置的有源区的数量较少，后续对应设置的电容器的数量较少，存储器的集成度低。
为此，本申请实施例提供一种存储器及其制备方法，通过在基底上形成 呈S形的位线，使得单位尺寸的基底上，每条位线的长度增长，后续设置的与位线接触的位线接触柱塞的数量就会增多，后续设置的与位线接触柱塞一一对应的有源区的数量就会增多，后续设置的与有源区一一对应的电容器的数量也会增多，如此，提高存储器的集成度。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
如图1所示，本申请实施例提供一种存储器的制备方法，其包括如下步骤：
S01：提供基底，基底的材料可以是硅、锗等本领域技术人员熟知的半导体基底材料。
S02：在基底上形成多条位线沟槽，多条位线沟槽间隔设置，多条位线沟槽沿第一方向排布，且每条位线沟槽呈S形，其中，第一方向如图2a示出的X方向，该步骤形成的结构如图2a、图2b以及图2c所示，该步骤形成的结构中，多条位线沟槽101间隔排布，并且沿第一方向排布，每条位线沟槽101呈S形。
S03：在每条位线沟槽101内形成第一隔离层，第一隔离层的厚度小于位线沟槽101的深度，第一隔离层的材料例如可以为二氧化硅，第一隔离层可以通过沉积的方法形成在位线沟槽101内，第一隔离层形成过程中，首先，在设置有位线沟槽101的基底100上形成第一层二氧化硅，第一层二氧化硅填充满位线沟槽101，且覆盖在保留下的基底100上，去除高于基底100顶面的部分第一层二氧化硅，该步骤形成的结构如图3a、图3b以及图3c所示，该步骤形成的结构中，第一层二氧化硅201位于位线沟槽101内，且第一层二氧化硅201与基底100的顶面平齐；其次，继续去除部分第一层二氧化硅201，仅保留位线沟槽101内的部分第一层二氧化硅201，且保留在位线沟槽101内的第一层二氧化硅201的厚度小于位线沟槽101的深度，以形成第一隔离层，该步骤形成的结构如图4a、图4b以及图4c所示，该步骤形成的结构中，第一隔离层200位于位线沟槽101内，且第一隔离层200的厚度小于 位线沟槽101的深度，第一隔离层200的顶面低于位线沟槽101的槽口。
S04：在第一隔离层200上形成位线，第一隔离层200和位线的总厚度小于位线沟槽101的槽深，多条位线沿第一方向排布，且每条位线呈S形，位线的材料例如可以是金属钨，位线可以采用沉积的方法形成在位线沟槽101内的第一隔离层200上。位线形成过程中，首先，在设置有位线沟槽101以及第一隔离层200的基底100上形成一层金属钨层，金属钨层填充满位线沟槽101，且覆盖在保留下的基底100上，该步骤形成的结构如图5a、图5b以及图5c所示，图5a虚线用于显示位线沟槽101的位置，该步骤形成的结构中，金属钨层301位于位线沟槽101内，且该层金属钨层301还覆盖在保留下的基底100的顶面；其次，去除部分金属钨层301，仅保留位线沟槽101内的金属钨层301，且保留在位线沟槽101内的金属钨层301的厚度小于位线沟槽101的深度，以形成位线，该步骤形成的结构如图6a、图6b以及图6c所示，该步骤形成的结构中，位线300位于位线沟槽101内的第一隔离层200上，位线300的顶面低于位线沟槽101的槽口，位线300的厚度加第一隔离层200的厚度小于位线沟槽101的槽深。
请参阅图6a，在第一隔离层200上形成位线300的步骤中：形成的每条位线300包括间隔排布且依次连接的多个第一位线结构302和多个第二位线结构303，第一位线结构302沿第二方向延伸，第二方向相对第一方向倾斜设置，第二位线结构303沿第三方向延伸，第三方向相对第一方向倾斜设置，且第三方向与第二方向相对第一方向的倾斜方向相反，其中，第二方向如图6a示出的Y方向，第三方向如图6a示出的Z方向。
S05：在位线300上形成第二隔离层，第二隔离层的顶面与基底100的顶面平齐，第二隔离层的材料和第一隔离层200的材料可为同一种材料，第二隔离层的材料例如为二氧化硅，第二隔离层可以采用沉积的方法形成在位线沟槽101内的位线300上。第二隔离层形成过程中，首先，在设置有位线300的基底100上形成第二层二氧化硅，第二层二氧化硅填充满位线沟槽101，且覆盖在保留下的基底100上，该步骤形成的结构如图7a、图7b以及图7c所示，图7a虚线用于显示位线沟槽101的位置，该步骤形成的结构中，第二层二氧化硅401位于位线沟槽101内，且第二层二氧化硅401还覆盖在保留下的基底100的顶面；其次，去除部分第二层二氧化硅401，仅保留位线沟 槽101内的第二层二氧化硅401，且保留在位线沟槽101内的第二层二氧化硅401的顶面与基底100的顶面平齐，以形成第二隔离层，该步骤形成的结构如图8a、图8b以及图8c所示，该步骤形成的结构中，第二隔离层400位于位线沟槽101内的位线300上，第二隔离层400的厚度加上位线300的厚度，再加上第一隔离层200的厚度等于位线沟槽101的槽深。
S06：去除相邻的隔离墙之间的基底100，且保留第一隔离层200底面以下的基底100，其中，隔离墙包括第一隔离层200、位线300以及第二隔离层400，去除相邻的隔离墙之间的基底100可以采用刻蚀的方法，该步骤形成的结构如图9a、图9b以及图9c所示，该步骤形成的结构中，基底100的顶面设置有多个间隔排布的隔离墙500，每个隔离墙500包括设置在基底100上的第一隔离层200、设置在第一隔离层200上的位线300，以及设置在位线300上的第二隔离层400，其中，每个隔离墙500呈S形，多个隔离墙500沿第一方向排布。
S07：在相邻的隔离墙500之间的间隙内形成第三隔离层，第三隔离层、第二隔离层400和第一隔离层200共同形成隔离层，第三隔离层的材料与第一隔离层200的材料、第二隔离层400的材料可为同一种材料，第三隔离层的材料例如为二氧化硅，第三隔离层可以采用沉积的方法形成在相邻两个隔离墙500之间的间隙内。该步骤形成的结构如图10a、图10b以及图10c所示，该步骤形成的结构中，基底100上间隔设置有隔离墙500和第三隔离层600，隔离墙500包括设置在基底100上的第一隔离层200、设置在第一隔离层200上的位线300，以及设置在位线300上的第二隔离层400；位线300正下方为第一隔离层200，位线300的正上方为第二隔离层400，位线300的两侧为第三隔离层600，位线300形成在第一隔离层200、第二隔离层400以及第三隔离层600形成的隔离层700内，隔离层700能够实现相邻位线300之间的绝缘，图10a中虚线用于显示位线沟槽101的位置，图10b和图10c中虚线用于显示第一隔离层200、第二隔离层400与第三隔离层600在不同的工艺步骤中形成。
本申请实施例的存储器的制备方法，通过在基底100上设置呈S形的位线沟槽101，进而在S形的位线沟槽101内形成呈S形的位线300，如此，使得制备的存储器内，在单位尺寸的基底100上，隔离层700内设置的位线300 长度增长，后续设置的与位线300接触的位线接触柱塞的数量就会增加，后续设置的与位线接触柱塞一一对应的有源区的数量就会增多，后续设置的与有源区一一对应的电容器的数量也会增多，存储器的集成度更高。
本申请实施例的存储器的制备方法制备的存储器是2HPAA乘2HPWL结构，2HPAA乘2HPWL确定一个位单元面积，2HPAA乘2HPWL指2倍的有源区的半节距乘以2倍的字线的半节距，2HPAA乘2HPWL结构形成的4F2存储单元的面积会缩小至3HPAA乘2HPWL结构形成的6F2存储单元的三分之二左右，相当于4F2存储结构的存储密度更大，集成度更高。
请继续参照图1，在形成第三隔离层600之后，还包括：
S08：去除第一位线结构302和第二位线结构303连接位置上的部分隔离层700以形成多个凹孔，每个凹孔暴露出位线300，凹孔的形状可以为圆孔，去除第一位线结构302和第二位线结构303连接位置上的部分隔离层700可以采用刻蚀的方式形成凹孔，该步骤形成的结构如图11a、图11b以及图11c所示，该步骤形成的结构中，每个凹孔701位于第一位线结构302和第二位线结构303的连接位置，每个凹孔701暴露出与其对应的位线300，其中，图11a中虚线用于显示位线沟槽101的位置，图11b和图11c中虚线用于显示第一隔离层200与第三隔离层600在不同的工艺步骤中形成。
S09：在每个凹孔701中沉积第一层多晶硅以形成位线接触柱塞，在每个凹孔701中沉积第一层多晶硅可以采用化学气相沉积法(英文名称为Chemical Vapor Deposition，英文简称为CVD)，也可以采用原子层沉积法(英文名称为Atomic Layer Deposition，英文简称为ALD)，且在沉积第一层多晶硅的同时，掺杂改变第一层多晶硅电学特性的离子，例如掺杂磷离子或者硼离子。该步骤形成的结构如图14a、图14b以及图14c所示，该步骤形成的结构中，位线接触柱塞800位于凹孔701内，位线接触柱塞800的顶面低于第三隔离层600的顶面以及第二隔离层400的顶面，位线接触柱塞800的厚度例如可以为50纳米(nm)，其中，图14a中虚线用于显示位线沟槽101的位置，图14b和图14c中虚线用于显示第一隔离层200与第三隔离层600在不同的工艺步骤中形成。
请参阅图14d，在每个凹孔701中沉积第一层多晶硅以形成位线接触柱塞800的步骤，包括：
S91：在每个凹孔701中沉积第一层多晶硅，第一层多晶硅填充满凹孔701且覆盖在保留下的隔离层700上，该步骤形成的结构如图12a、图12b以及图12c所示，该步骤形成的结构中，第一层多晶硅801填充满凹孔701，且第一层多晶硅801覆盖在保留下的隔离层700上，其中，图12a中虚线用于显示位线沟槽101的位置以及凹孔701的位置，图12b和图12c中虚线用于显示第一隔离层200与第三隔离层600在不同的工艺步骤中形成。
S92：去除部分第一层多晶硅801，保留下的第一层多晶硅801位于凹孔701中，并且保留下的第一层多晶硅801的顶面低于隔离层700的顶面，保留在凹孔701中的第一层多晶硅801形成位线接触柱塞800，该步骤形成的结构如图14a、图14b以及图14c所示，该步骤形成的结构中，第一层多晶硅801填充在凹孔701内，第一层多晶硅801的顶面低于第三隔离层600的顶面以及第二隔离层400的顶面，保留在凹孔701中的第一层多晶硅801形成位线接触柱塞800。其中，当去除第三隔离层600以及第二隔离层400顶面的第一层多晶硅801，形成的结构如图13a、图13b以及图13c所示，该结构中，第一层多晶硅801填充在凹孔701内，第一层多晶硅801的顶面与第三隔离层600的顶面以及第二隔离层400的顶面平齐，图13a中虚线用于显示位线沟槽101的位置，图13b和图13c中虚线用于显示第一隔离层200与第三隔离层600在不同的工艺步骤中形成，继续去除凹孔701中的部分第一层多晶硅801，形成的结构如图14a、图14b以及图14c所示。
请继续参照图1，在每个凹孔701中形成位线接触柱塞800之后，还包括：
S0A：在位线接触柱塞800上形成第二层多晶硅，第二层多晶硅的顶面与隔离层700的顶面平齐，第二层多晶硅可以采用沉积的方法形成在位线接触柱塞800上，该步骤形成的结构请参阅图15a、图15b以及图15c所示，该步骤形成的结构中，第二层多晶硅900的底面与位线接触柱塞800接触，第二层多晶硅900的顶面与隔离层700的顶面平齐，其中，图15a中虚线用于显示位线沟槽101的位置以及凹孔701的位置，图15b和图15c中虚线用于显示第一隔离层200与第三隔离层600在不同的工艺步骤中形成。
S0B：在保留下的隔离层700和第二层多晶硅900上形成保护层，保护层的材料例如可以是氮化硅，保护层也可以采用沉积的方式形成在保留下的 隔离层700和第二层多晶硅900上，该步骤形成的结构如图15a、图15b以及图15c所示，该步骤形成的结构中，保护层A00设置在第二层多晶硅900和保留下的隔离层700上，该步骤中，保留下的隔离层700包括第三隔离层600、第一隔离层200以及部分第二隔离层400。
S0C：去除部分保护层A00、部分第二层多晶硅900以及部分隔离层700，以形成字线沟槽，字线沟槽沿第四方向排布，且沿第一方向延伸，第四方向与第一方向垂直设置，第四方向如图16a所示的U方向，保留下的第二层多晶硅900形成位于字线沟槽两侧的有源区，保留下的保护层A00内形成与字线沟槽连通的节点柱塞槽，节点柱塞槽的宽度大于字线沟槽的宽度。该步骤形成的结构中，字线沟槽901沿第一方向延伸，多个字线沟槽901沿第四方向排布，字线沟槽901的宽度小于第二层多晶硅900的宽度，保留下的第二层多晶硅900位于每个字线沟槽901的两侧，保留下的第二层多晶硅900构成有源区902，字线沟槽901的宽度小于节点柱塞槽A01的宽度，节点柱塞槽A01暴露出有源区902的顶面。
在步骤S0C中，保留下的第二层多晶硅900，需经离子注入后形成有源区902，离子注入的离子可以是硼离子或磷离子，在第二层多晶硅900上注入离子，可以使得形成的有源区902设置有源/漏极。
请继续参照图1，形成字线沟槽901后，还包括：
S0D：在字线沟槽901的底部形成第一介质层，第一介质层的材料可以为二氧化硅，第一介质层也可以采用沉积的方法形成在字线沟槽901的底部。该步骤形成的结构如图16a、图16b以及图16c所示，该步骤形成的结构中，第一介质层B00设置在字线沟槽901内，且第一介质层B00的厚度小于字线沟槽901的深度，第一介质层B00的顶面低于字线沟槽901的槽口，其中，图16a中虚线用于显示位线沟槽101的位置，图16b和图16c中虚线用于显示第一隔离层200、第三隔离层600以及第一介质层B00在不同的工艺步骤中形成。
S0E：在第一介质层B00上形成第二介质层，第二介质层覆盖有源区902侧壁，第二介质层的材料例如可以是二氧化硅，第二介质层可以通过原位水汽法(英文名称为in-situ steam generation，英文简称为ISSG)制备，第二介质层的厚度大约可以为5nm，该步骤形成的结构如图17a、图17b以及图17c 所示，该步骤形成的结构中，第二介质层C00设置在第一介质层B00上，且第二介质层C00覆盖在有源区902的侧壁，第二介质层C00的厚度小于字线沟槽901槽宽的一半，其中，图17a中虚线用于显示位线沟槽101的位置，图16b和图16c中虚线用于显示第一隔离层200、第三隔离层600、第一介质层B00和第二介质层C00在不同的工艺步骤中形成。
S0F：在字线沟槽901内的第一介质层B00上、且第二介质层C00远离有源区902的侧部形成金属层，金属层填充满字线沟槽901和节点柱塞槽A01，并覆盖在保留下的隔离层700和保留下的保护层A00上；金属层的材料例如可以是金属钨，金属层例如可以采用沉积的方法设置在字线沟槽901内的第一介质层B00和第二介质层C00形成的空间内。该步骤形成的结构如图18a、图18b以及图18c所示，该步骤形成的结构中，金属层D00填充满字线沟槽901和节点柱塞槽A01，且金属层D00覆盖在保留下的隔离层700和保留下的保护层A00上，其中，图18a中虚线用于显示位线沟槽101的位置以及凹孔701的位置，图18b和图18c中虚线用于显示第一隔离层200、第三隔离层600、第一介质层B00和第二介质层C00在不同的工艺步骤中形成。
S0G：回刻金属层D00，使金属层D00的顶面低于有源区902的顶面，回刻金属层D00可以采用刻蚀的方式进行，该步骤形成的结构请参阅图20a、图20b以及图20c所示，该步骤形成的结构中，金属层D00设置在字线沟槽901内的第一介质层B00和第二介质层C00围合出的槽内，金属层D00的顶面低于有源区902的顶面。其中，回刻金属层D00时，当回刻的金属层D00的顶面与保护层A00的顶面平齐时，形成的结构如图19a、图19b以及图19c所示，该结构中，金属层D00填充满字线沟槽901和节点柱塞槽A01，且金属层D00的顶面与保护层A00的顶面平齐，其中，图19a中虚线用于显示位线沟槽101的位置，图19b和图19c中虚线用于显示第一隔离层200、第三隔离层600、第一介质层B00和第二介质层C00在不同的工艺步骤中形成。
S0H：在金属层D00上形成第三介质层，第三介质层的顶面与保护层A00的底面平齐，第三介质层的材料例如可以是二氧化硅，第三介质层例如可以采用沉积的方法形成在金属层D00上，该步骤形成的结构如图20a、图20b以及图20c所示，该步骤形成的结构中，第三介质层E00的底面与金属层D00的顶面接触，第三介质层E00的顶面与有源区902平齐，金属层D00形成字 线，其中，图20a中虚线用于显示位线沟槽101的位置，图20b和图20c中虚线用于显示第一隔离层200、第三隔离层600、第一介质层B00、第二介质层C00和第三介质层E00在不同的工艺步骤中形成。
请继续参照图1，形成第三介质层E00之后，还包括：
S0I：在第三介质层E00上形成第三层多晶硅，第三层多晶硅填充满节点柱塞槽A01且覆盖保护层A00，第三层多晶硅可以采用化学气相沉积方法(英文名称为Chemical Vapor Deposition，英文简称为CVD)填充满节点柱塞槽A01，并覆盖在保护层A00上，且在沉积第三层多晶硅的同时，掺杂改变第三层多晶硅电学特性的离子，例如掺杂磷离子或者硼离子。该步骤形成的结构中，第三层多晶硅F00的底面与第三介质层E00的顶面和有源区902的顶面接触，第三层多晶硅F00填充满节点柱塞槽A01，第三层多晶硅F00顶面覆盖在保护层A00的顶面上。
S0J：去除部分第三层多晶硅F00，保留下的第三层多晶硅F00形成多个节点接触柱塞，每个节点接触柱塞与对应的有源区902的顶端电连接，节点接触柱塞与位线接触柱塞800在垂直于基底100方向上一一对应。去除部分第三层多晶硅F00时，首先，去除保护层A00的顶面以上的第三层多晶硅F00，此步骤形成的结构如图21a、图21b以及图21c所示，该步骤形成的结构中，第三层多晶硅F00的底面与第三介质层E00的顶面和有源区902的顶面接触，第三层多晶硅F00填充满节点柱塞槽A01，第三层多晶硅F00顶面与保护层A00的顶面平齐，其中，图21a中虚线用于显示位线沟槽101的位置，图21b和图21c中虚线用于显示第一隔离层200、第三隔离层600、第一介质层B00、第二介质层C00和第三介质层E00在不同的工艺步骤中形成。其次，去除节点柱塞槽A01中的部分第三层多晶硅F00，该步骤形成的结构中，每个节点柱塞槽A01中形成多个节点接触柱塞，且每个节点接触柱塞与对应的有源区902的顶端电连接，节点接触柱塞与位线接触柱塞800在垂直于基底100方向上一一对应。
本申请实施例提供的存储器，其包括基底100，基底100上设置有隔离层700，隔离层700内间隔排布有多条位线300，多条位线300沿第一方向排布，且每条位线300呈S形，第一方向如图2a示出的X方向。
本申请实施例的存储器，基底100的隔离层700内设置有间隔排布的多 条位线300，每条位线300呈S形且沿第一方向排布，在单位尺寸的基底100上，隔离层700内设置的位线300长度增长，后续设置的与位线300接触的位线接触柱塞800的数量就会增加，后续设置的与位线接触柱塞800一一对应的有源区902的数量就会增多，后续设置的与有源区902一一对应的电容器的数量也会增多，如此，存储器的集成度更高。
请参阅图6a，每条位线300包括间隔排布且依次连接的多个第一位线结构302和多个第二位线结构303，第一位线结构302沿第二方向延伸，第二方向相对第一方向倾斜设置，第二位线结构303沿第三方向延伸，第三方向相对第一方向倾斜设置，且第三方向与第二方向相对第一方向的倾斜方向相反。在如图6a示出的实施方式中，每条位线300包括三个第一位线结构302和三个第二位线结构303，三个第一位线结构302和三个第二位线结构303间隔排布且依次连接，第一位线结构302沿第二方向延伸，第二方向如图6a示出的Y方向，第二位线结构303沿第三方向延伸，第三方向如图6a示出的Z方向，Y方向和Z方向相对图2a示出的X方向的倾斜方向相反。
请参阅图6a、图8b、图14a、图14b以及图14c，每条位线300上设置有间隔排布的多个位线接触柱塞800，位线接触柱塞800设置在隔离层700内，且每个位线接触柱塞800设置在对应的第一位线结构302和第二位线结构303的连接位置。在如图6a和14a示出的实施方式中，每条位线300上方设置有五个位线接触柱塞800，每个位线接触柱塞800设置在相连的第一位线结构302和第二位线结构303的连接处。
请参阅图8b、图16a、图16b以及图16c，每个位线接触柱塞800上设置有源区902，有源区902设置在隔离层700内。在如图8b和16b示出的实施方式中，有源区902设置在隔离层700内，有源区902与位线300通过位线接触柱塞800连接，有源区902的底面与位线接触柱塞800的顶面接触，位线接触柱塞800的底面与位线300的顶面接触。
隔离层700内还设置有多条字线，多条字线沿第四方向排布，每条字线沿第一方向延伸，第四方向与第一方向垂直设置，第四方向如图16a示出的U方向。
每条字线包括多个栅极和多个字线结构，每个栅极对应设置在一个有源区902内，每条字线包括的多个栅极对应设置在同一列有源区902内，同一 列有源区902沿第一方向排布，多个栅极和多个字线结构一一间隔设置，每个字线结构设置在隔离层700内，每个字线结构用于连接相邻两个栅极。在如图20a、图20b以及图20c示出的实施方式中，每条字线包括五个栅极和五个字线结构，栅极至少由设置在有源区902内的金属层D00构成，字线结构至少由设置在隔离层700内的金属层D00构成，五个栅极和五个字线结构间隔设置。
请参阅图20a、图20b以及图20c，字线包括金属层D00和介质层，介质层包括第一介质层B00、第二介质层C00和第三介质层E00，第一介质层B00设置在位线接触柱塞800和隔离层700上，第一介质层B00的顶面设置金属层D00和第二介质层C00，金属层D00的顶面和第二介质层C00的顶面平齐，第二介质层C00设置在金属层D00的相对两侧面，金属层D00的顶面和第二介质层C00的顶面设置第三介质层E00。
每条字线上间隔设置有多个节点接触柱塞，每个节点接触柱塞与有源区902的顶端电连接，节点接触柱塞与位线接触柱塞800在垂直于基底100方向上一一对应。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

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  1. 一种存储器，其中，包括基底，所述基底上设置有隔离层，所述隔离层内间隔排布有多条位线，多条所述位线沿第一方向排布，且每条所述位线呈S形。
  2. 根据权利要求1所述的存储器，其中，每条所述位线包括间隔排布且依次连接的多个第一位线结构和多个第二位线结构，所述第一位线结构沿第二方向延伸，所述第二方向相对所述第一方向倾斜设置，所述第二位线结构沿第三方向延伸，所述第三方向相对所述第一方向倾斜设置，且所述第三方向与所述第二方向相对所述第一方向的倾斜方向相反。
  3. 根据权利要求2所述的存储器，其中，每条所述位线上设置有间隔排布的多个位线接触柱塞，所述位线接触柱塞设置在所述隔离层内，且每个所述位线接触柱塞设置在对应的所述第一位线结构和所述第二位线结构的连接位置。
  4. 根据权利要求3所述的存储器，其中，每个所述位线接触柱塞上设置有源区，所述有源区设置在所述隔离层内。
  5. 根据权利要求4所述的存储器，其中，所述隔离层内还设置有多条字线，多条所述字线沿第四方向排布，每条所述字线沿所述第一方向延伸，所述第四方向与所述第一方向垂直设置。
  6. 根据权利要求5所述的存储器，其中，每条所述字线包括多个栅极和多个字线结构，每个所述栅极对应设置在一个所述有源区内，每条所述字线包括的多个所述栅极对应设置在同一列所述有源区内，同一列所述有源区沿所述第一方向排布，多个所述栅极和多个所述字线结构一一间隔设置，每个所述字线结构设置在所述隔离层内，每个所述字线结构用于连接相邻两个所述栅极。
  7. 根据权利要求5所述的存储器，其中，所述字线包括金属层和介质层，所述介质层包括第一介质层、第二介质层和第三介质层，所述第一介质层的顶面设置所述金属层和所述第二介质层，所述第二介质层设置在所述金属层的相对两侧面，所述金属层的顶面和所述第二介质层的顶面设置所述第三介质层。
  8. 根据权利要求6所述的存储器，其中，所述字线包括金属层和介质层， 所述介质层包括第一介质层、第二介质层和第三介质层，所述第一介质层的顶面设置所述金属层和所述第二介质层，所述第二介质层设置在所述金属层的相对两侧面，所述金属层的顶面和所述第二介质层的顶面设置所述第三介质层。
  9. 根据权利要求5所述的存储器，其中，每条所述字线上间隔设置有多个节点接触柱塞，每个所述节点接触柱塞与所述有源区的顶端电连接，所述节点接触柱塞与所述位线接触柱塞在垂直于所述基底方向上一一对应。
  10. 根据权利要求6所述的存储器，其中，每条所述字线上间隔设置有多个节点接触柱塞，每个所述节点接触柱塞与所述有源区的顶端电连接，所述节点接触柱塞与所述位线接触柱塞在垂直于所述基底方向上一一对应。
  11. 一种存储器的制备方法，其中，包括如下步骤：
    提供基底；
    在所述基底上形成多条位线沟槽，多条所述位线沟槽沿第一方向排布，且每条所述位线沟槽呈S形；
    在每条所述位线沟槽内形成第一隔离层，所述第一隔离层的厚度小于所述位线沟槽的深度；
    在所述第一隔离层上形成位线，所述第一隔离层和所述位线的总厚度小于所述位线沟槽的深度，多条所述位线沿第一方向排布，且每条所述位线呈S形；
    在所述位线上形成第二隔离层，所述第二隔离层的顶面与所述基底的顶面平齐；
    去除相邻的隔离墙之间的所述基底，且保留所述第一隔离层底面以下的所述基底，其中，所述隔离墙包括所述第一隔离层、所述位线以及所述第二隔离层；
    在相邻的所述隔离墙之间的间隙内形成第三隔离层，所述第三隔离层、所述第二隔离层和所述第一隔离层共同形成隔离层。
  12. 根据权利要求11所述的存储器的制备方法，其中，在所述第一隔离层上形成位线的步骤中：
    形成的每条所述位线包括间隔排布且依次连接的多个第一位线结构和多个第二位线结构，所述第一位线结构沿第二方向延伸，所述第二方向相对所 述第一方向倾斜设置，所述第二位线结构沿第三方向延伸，所述第三方向相对所述第一方向倾斜设置，且所述第三方向与所述第二方向相对所述第一方向的倾斜方向相反。
  13. 根据权利要求12所述的存储器的制备方法，其中，在形成所述第三隔离层之后，还包括：
    去除所述第一位线结构和所述第二位线结构连接位置上的部分所述隔离层以形成多个凹孔，每个所述凹孔暴露出所述位线；
    在每个所述凹孔中沉积第一层多晶硅以形成位线接触柱塞。
  14. 根据权利要求13所述的存储器的制备方法，其中，在每个所述凹孔中沉积第一层多晶硅以形成位线接触柱塞的步骤，包括：
    在每个所述凹孔中沉积所述第一层多晶硅，所述第一层多晶硅填充满所述凹孔且覆盖在保留下的所述隔离层上；
    去除部分所述第一层多晶硅，保留下的所述第一层多晶硅位于所述凹孔中，并且保留下的所述第一层多晶硅的顶面低于所述隔离层的顶面，保留在所述凹孔中的所述第一层多晶硅形成所述位线接触柱塞。
  15. 根据权利要求13所述的存储器的制备方法，其中，在每个所述凹孔中形成所述位线接触柱塞之后，还包括：
    在所述位线接触柱塞上形成第二层多晶硅，所述第二层多晶硅的顶面与所述隔离层的顶面平齐；
    在保留下的所述隔离层和所述第二层多晶硅上形成保护层；
    去除部分所述保护层、部分所述第二层多晶硅以及部分所述隔离层，以形成字线沟槽，所述字线沟槽沿第四方向排布，且沿所述第一方向延伸，所述第四方向与所述第一方向垂直设置，保留下的所述第二层多晶硅形成位于所述字线沟槽两侧的有源区，保留下的所述保护层内形成与所述字线沟槽连通的节点柱塞槽，所述节点柱塞槽的宽度大于所述字线沟槽的宽度。
  16. 根据权利要求15所述的存储器的制备方法，其中，保留下的所述第二层多晶硅经离子注入后形成所述有源区。
  17. 根据权利要求15所述的存储器的制备方法，其中，形成所述字线沟槽后，还包括：
    在所述字线沟槽的底部形成第一介质层；
    在所述第一介质层上形成第二介质层，所述第二介质层覆盖所述有源区侧壁；
    在所述字线沟槽内的所述第一介质层上、且所述第二介质层远离所述有源区的侧部形成金属层，所述金属层填充满所述字线沟槽和所述节点柱塞槽，并覆盖在保留下的所述隔离层和保留下的所述保护层上；
    回刻所述金属层，使所述金属层低于所述有源区；
    在所述金属层上形成第三介质层，所述第三介质层的顶面与所述保护层的底面平齐。
  18. 根据权利要求17所述的存储器的制备方法，其中，形成所述第三介质层之后，还包括：
    在所述第三介质层上形成第三层多晶硅，所述第三层多晶硅填充满所述节点柱塞槽且覆盖所述保护层；
    去除部分所述第三层多晶硅，保留下的所述第三层多晶硅形成多个节点接触柱塞，每个所述节点接触柱塞与对应的所述有源区的顶端电连接，所述节点接触柱塞与所述位线接触柱塞在垂直于所述基底方向上一一对应。
  19. 根据权利要求14所述的存储器的制备方法，其中，在每个所述凹孔中形成所述位线接触柱塞之后，还包括：
    在所述位线接触柱塞上形成第二层多晶硅，所述第二层多晶硅的顶面与所述隔离层的顶面平齐；
    在保留下的所述隔离层和所述第二层多晶硅上形成保护层；
    去除部分所述保护层、部分所述第二层多晶硅以及部分所述隔离层，以形成字线沟槽，所述字线沟槽沿第四方向排布，且沿所述第一方向延伸，所述第四方向与所述第一方向垂直设置，保留下的所述第二层多晶硅形成位于所述字线沟槽两侧的有源区，保留下的所述保护层内形成与所述字线沟槽连通的节点柱塞槽，所述节点柱塞槽的宽度大于所述字线沟槽的宽度。
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