WO2022095454A1 - 存储器及其制备方法 - Google Patents

存储器及其制备方法 Download PDF

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Publication number
WO2022095454A1
WO2022095454A1 PCT/CN2021/100737 CN2021100737W WO2022095454A1 WO 2022095454 A1 WO2022095454 A1 WO 2022095454A1 CN 2021100737 W CN2021100737 W CN 2021100737W WO 2022095454 A1 WO2022095454 A1 WO 2022095454A1
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Prior art keywords
regions
region
active
source
active regions
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PCT/CN2021/100737
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English (en)
French (fr)
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阮吕军昇
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长鑫存储技术有限公司
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Priority to US17/442,280 priority Critical patent/US20230056921A1/en
Publication of WO2022095454A1 publication Critical patent/WO2022095454A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a memory and a preparation method thereof.
  • DRAM Dynamic random access memory
  • a dynamic random access memory generally includes a plurality of memory cells, and the plurality of memory cells are arranged in rows and columns to form a memory matrix, wherein the memory cells in each column are connected by a word line, and the memory cells in each row are connected by a bit line.
  • the entire column of memory cells connected by a word line is selected by column, and then the entire row of memory cells connected by a bit line is selected by row.
  • the target memory cell can be selected, and then the read data or write data of the target memory cell can be realized.
  • the read or write cycle of the dynamic random access memory is long and the speed is slow, which is not conducive to improving the performance of the dynamic random access memory.
  • embodiments of the present application provide a memory and a method for preparing the memory, which are used to improve the speed of the memory, thereby improving the performance of the memory.
  • a first aspect of the embodiments of the present application provides a memory, which includes a substrate, a control area is disposed on the substrate, and storage areas are respectively disposed on both sides of the control area; each storage area includes a plurality of first active areas, and a plurality of first active areas.
  • An active area is arranged in several rows along the first direction, each first active area is provided with a first contact area, and each first contact area in the first active area of each row is connected to a bit line; the control area Including several second active regions arranged along the first direction and corresponding to several rows of first active regions one-to-one; each second active region is provided with a first gate and two sides of the first gate In the first source-drain region and the second source-drain region, the first gates in the control region are connected to each other to form a control line; in the same second active region, the first source-drain region and the second source-drain region are respectively It is connected with a corresponding bit line, and the bit line connected with the first source-drain region and the bit line connected with the second source-drain region are located on both sides of the control line.
  • a first conductive portion is disposed on the first source-drain region, and the first source-drain region is connected to a corresponding bit line through the first conductive portion.
  • a second conductive portion is disposed on the second source-drain region, and the second source-drain region is connected to a corresponding bit line through the second conductive portion.
  • the first conductive portion and the second conductive portion are located on the same layer.
  • a third conductive portion is disposed on the first contact region; in each row of the first active region of each storage region, the third conductive portion on each of the first contact regions is connected to a bit line.
  • the first conductive part, the second conductive part and the third conductive part are located in the same layer.
  • a plurality of first active regions are arranged in several columns along the second direction, and among the first active regions in any two adjacent rows, all the first active regions in one row are The column where the source region is located and the column where all the first active regions of the other row are located are arranged alternately at intervals, and each first active region in the same column intersects with two word lines, and in the first active region of any adjacent column, The ends of the first active regions in one column and the first active regions in the other column that are close to each other intersect with the same word line, wherein the second direction is perpendicular to the first direction; each first active region in the same column is arranged There are two second gates, and the two second gates are respectively connected to the two word lines alternately arranged in the first active region.
  • the first contact region on each of the first active regions is located between the two second gate electrodes.
  • the first gate and the second gate are located on the same layer.
  • each first active region further includes a second contact region disposed on a side of each second gate facing away from the first contact region, and each second contact region is connected to a corresponding charge storage element .
  • a plurality of control areas and a plurality of storage areas are provided on the substrate, and each control area and each storage area are alternately arranged at intervals.
  • a second aspect of the embodiments of the present application provides a method for preparing a memory, which includes the following steps:
  • a control area is formed on the substrate and storage areas are formed on both sides of the control area; each storage area includes a plurality of first active areas, and the plurality of first active areas are arranged in several rows along the first direction, and the control area including several second active regions arranged along the first direction and corresponding to several rows of first active regions one-to-one;
  • a first contact region is formed in each first active region, a first gate and a first source-drain region and a second source-drain region on both sides of the first gate are arranged in each second active region, and the control region
  • the first gates within are connected to each other to form a control line;
  • a bit line connected to each of the first contact regions is formed above the first active region in each row, and in the same second active region, the first source-drain region and the second source-drain region are respectively associated with a corresponding bit line connected, and the bit lines connected with the first source and drain regions and the bit lines connected with the second source and drain regions are located on both sides of the control lines.
  • a first conductive portion is formed on the first source-drain region, and the first source-drain region is connected to a corresponding bit line through the first conductive portion.
  • a second conductive portion is formed on the second source-drain region, and the second source-drain region is connected to a corresponding bit line through the second conductive portion.
  • the first conductive portion and the second conductive portion are formed in the same process step.
  • a third conductive portion is formed on the first contact region; in each row of the first active region of each storage region, the third conductive portion on each first contact region is connected to a bit line .
  • the first conductive portion, the second conductive portion, and the third conductive portion are formed in the same process step.
  • a plurality of first active regions are arranged in several columns along the second direction, and among the first active regions in any two adjacent rows, all the first active regions in one row are arranged in several columns along the second direction.
  • the column where the active area is located and the column where all the active areas in another row are located are arranged alternately at intervals, and each first active area in the same column is arranged alternately with two word lines, and in the first active area of any adjacent column, One of the first active regions in one column and the ends of the first active regions in the other column close to each other are connected to a word line; two second gates are formed in each first active region in the same column, and the two The second gate electrodes are respectively connected to the two word lines alternately arranged in the first active region.
  • the first contact region on each of the first active regions is located between the two second gates.
  • the first gate and the second gate are provided in the same process step.
  • a second contact region is further formed in each first active region on a side of each second gate away from the first contact region, and each second contact region is connected with the corresponding charge storage element connect.
  • a plurality of control regions and a plurality of storage regions are formed on the substrate, and the control regions and the storage regions are alternately arranged at intervals.
  • the memory provided by the embodiment of the present application, by setting a control area on the substrate, setting storage areas on both sides of the control area, and connecting the first contact areas of the first active areas in each row of the storage areas with a bit line , the first source-drain region and the second source-drain region of the second active region of the control region are connected to the corresponding bit lines on both sides of the second active region, and then the voltage of the control line is controlled to control the communication with the first source Whether the bit line connected to the drain region and the bit line connected to the second source-drain region is turned on, and further, to control the effective length of the bit line in each read operation and write operation, that is, controllable in each read operation In and write operations, the number of memory cells connected to valid bit lines is controlled, and the time of each read operation and write operation is controlled, so that the average storage speed of the memory is accelerated and the performance of the memory is improved.
  • the prepared memory has fast storage speed, good performance, simple preparation process and low technological difficulty.
  • the memory and the preparation method thereof provided by the embodiments of the present application can solve the problems.
  • Other technical problems, other technical features included in the technical solution, and the beneficial effects brought about by these technical features will be described in further detail in the specific embodiments.
  • Fig. 1 is the principle schematic diagram of the memory in the related art
  • FIG. 2a is a schematic structural diagram of arranging a first active region and a second active region on the substrate of this embodiment
  • Figure 2b is a cross-sectional view of Figure 2a at the line AA;
  • FIG. 3 a is a schematic structural diagram of a memory forming word line and a control line provided in this embodiment
  • Fig. 3b is a sectional view of Fig. 3a at the position of line BB;
  • FIG. 4a is a schematic structural diagram 1 of a memory formation bit line provided in this embodiment.
  • Figure 4b is a sectional view of Figure 4a at the CC line position
  • FIG. 4c is a second structural schematic diagram of a memory formation bit line provided in this embodiment.
  • Fig. 4d is the sectional view of Fig. 4d at the DD line position
  • FIG. 5a is a schematic structural diagram of a memory provided with a capacitor formed in this embodiment
  • Figure 5b is a cross-sectional view of Figure 5a at the line EE;
  • Fig. 5c is the sectional view of Fig. 5a at the FF line position
  • FIG. 6 is a schematic diagram of the principle of the memory provided in this embodiment.
  • FIG. 7 is a flowchart of a method for preparing a memory according to this embodiment.
  • 100 memory cell; 101: buffer area; 200: substrate; 201: control area; 202: storage area; 203: first active area; 204: first contact area; 205: bit line; 206: word line; 207 : trench insulating portion; 208: second gate electrode; 209: gate oxide layer; 210: gate barrier layer; 211: gate conductive layer; 212: second contact region; 213: fourth conductive portion; 214: capacitor; 215: second active region; 216: first gate; 217: first source-drain region; 218: second source-drain region; 219: control line; 220: gate insulating layer; 221: first conductive layer part; 222: second conductive part; 223: third conductive part.
  • a memory generally includes a plurality of storage units 100.
  • the memory includes fifteen storage units 100, and the fifteen storage units 100 form a storage matrix with five rows and three columns, wherein, Each row of memory cells 100 is connected by a word line 206 (English name is Word line, abbreviated as WL), and each column of memory cells 100 is connected by a bit line 205 (English name is Bit line, abbreviated as BL).
  • the read operation principle of this memory is as follows:
  • the memory cells 100 in the first row and the first column Taking the read operation of the memory cells 100 in the first row and the first column as an example, first, through the word lines 206 connected to the memory cells 100 in the first row, all the memory cells 100 in the first row are selected and temporarily stored in the cache area. 101. Then, all the memory cells 100 in the first column are selected through the bit lines 205 connected to the memory cells 100 in the first column. In this way, the memory cells 100 in the first row and the first column can be selected to perform a read operation.
  • the inventor of the present application found that, for example, when the memory cells 100 in the first row and the first column need to be selected, the memory cells 100 in the second row and the first column and the memory cells 100 in the third row and the first column are also selected at the same time. , the memory cell 100 in the fourth row and the first column, and the memory cell 100 in the fifth row and the first column, cause the memory cell 100 in the second row and the first column, the memory cell 100 in the third row and the first column, and the memory cell 100 in the third row and the first column.
  • the loading of the memory cells 100 in one column and the memory cells 100 in the fifth row and the first column is redundant, which will lengthen the entire loading time, slow down the storage speed of the memory, and degrade the performance of the memory.
  • the present application proposes a memory and a preparation method, wherein a control area and storage areas located on both sides of the control area are arranged on a substrate, and multiple rows of first active areas are arranged in each storage area, and each row has a first active area.
  • the source region is connected to the bit line, a plurality of second active regions are arranged in the control region, and each second active region forms a first gate, a first source-drain region located in the first gate, and a second source-drain region , the first source-drain region and the second source-drain region are respectively connected to the bit lines on both sides of the second active region, so that the corresponding voltage in the adjacent two storage regions can be controlled by controlling the voltage of the first gate Whether all the first active regions of a row are turned on through the bit lines connected to the first source and drain regions and the bit lines connected to the second source and drain regions, thereby controlling the effective length of the bit lines during each read operation and write operation , that is, controllable in each read operation and write operation, control the number of memory cells connected to the effective bit line, thereby reducing the time of each read operation and write operation, so that the average storage speed of the memory is accelerated, and the memory performance improvement.
  • a memory provided in this embodiment includes a substrate 200, the substrate 200 is provided with a control area 201, and storage areas 202 are respectively provided on both sides of the control area 201.
  • each storage area 202 includes a plurality of first active areas 203, and the plurality of first active areas 203 are arranged in several rows along the first direction.
  • a plurality of first active areas 203 The active regions 203 are arranged in seven rows along the first direction, and each row includes four first active regions 203, wherein the first direction may be the X direction as shown in FIG. 2a.
  • each first active region 203 is provided with a first contact region 204.
  • the first contact region 204 is approximately located in the middle of the first active region 203, and the first contact region 204 in each row
  • a bit line 205 is connected to each of the first contact regions 204 in an active region 203 .
  • the plurality of first active areas 203 are also arranged in several columns along the second direction, the second direction is perpendicular to the first direction, and the second direction may be as follows The Y direction shown in Figure 3a.
  • all the first active regions 203 in one row are arranged in a staggered position with all the first active regions 203 in the other row, and each first active region in the same column 203 intersects with two word lines 206.
  • the ends of the first active regions 203 in one column and the first active regions 203 in the other column close to each other are the same word line 206. intersect.
  • first active region 203 is a strip-shaped structure, and the first active region 203 extends along a third direction, the third direction and the second direction are arranged at a predetermined angle, and the included angle ranges from 15° to 30° , the third direction is the Z direction as shown in Figure 3a.
  • a trench insulating portion 207 is provided between adjacent first active regions 203 , and the trench insulating portion 207 is located between adjacent first active regions 203
  • the trenches are filled with insulating material and are used to electrically separate the adjacent first active regions 203 .
  • each of the first active regions 203 in the same column is provided with two second gates 208 , and the two second gates 208 are arranged alternately with the first active regions 203 respectively.
  • the two word lines 206 are connected.
  • the second gate 208 includes, for example, a gate oxide layer 209 , a gate barrier layer 210 and a gate conductive layer 211 .
  • a first gate trench is provided on the first active region 203 , and the inner portion of the first gate trench is A gate oxide layer 209 is deposited on the surface, a gate barrier layer 210 is deposited on the inner surface of the gate oxide layer 209 , and the gate conductive layer 211 is filled in the grooves in the gate barrier layer 210 .
  • the gate anodic oxide layer is made of high dielectric constant material or oxide
  • the gate barrier layer 210 can be, for example, a metal electrode material, which is used to block the mixture between the gate oxide layer 209 and the gate conductive layer 211, and the gate
  • the conductive layer 211 is made of, for example, a metal electrode material.
  • the trench insulating portion 207 disposed between the adjacent first active regions 203 is further provided with word line grooves, and the gate conductive layers are deposited in the word line grooves.
  • the conductive material 211 is electrically connected, the conductive material in the word line groove is electrically connected with the gate conductive layer 211 , and the word line 206 is formed.
  • each first active region 203 further includes a second contact region 212 disposed on a side of each second gate 208 away from the first contact region 204, each The second contact region 212 is connected to the corresponding charge storage element.
  • the charge storage element is, for example, the capacitor 214 shown in Figure 5a.
  • the capacitor 214 is connected to the second contact area 212, eg by the fourth conductive portion 213 shown in FIG. 5b.
  • the first contact region 204 on each of the first active regions 203 is located between the two second gate electrodes 208, and at this time, each of the first active regions 203 is connected to a bit line 205 , and is connected to the two word lines 206 .
  • the two second gates 208 on each first active region 203, the first contact region 204 and the two second contact regions 212 together form two MOS transistors (the English name is Metal Oxide Semiconductor, the Chinese name is Metal-oxide-semiconductor field effect transistor), wherein a second gate 208, a second contact region 212 on one side of the second gate 208 and a first contact region 204 on the other side of the second gate 208 are jointly formed A MOS tube.
  • This arrangement can make the structure of the memory more compact and the integration level higher.
  • each control region 201 includes a plurality of second active regions 215 arranged along the first direction and corresponding to the first active regions 203 in a one-to-one relationship with a plurality of rows.
  • the second active region 215 is also a strip-shaped structure, and the second active region 215 also extends along the third direction, the third direction and the second direction are arranged at a predetermined angle, and the included angle ranges from 15° to 30° .
  • trench insulating portions 207 are also provided between the second active regions 215 and between the second active regions 215 and the first active regions 203 , and the trench insulating portions 207 are also used to separate adjacent two The second active regions 215 and the adjacent first active regions 203 and the second active regions 215 are electrically separated from each other.
  • each second active region 215 is provided with a first gate 216 and a first source-drain region 217 and a second source-drain region 218 on both sides of the first gate 216, each Each of the control regions 201 includes a control line 219 that penetrates through each of the second active regions 215 , that is, is formed by connecting each of the first gates 216 .
  • the first gate 216 includes a gate oxide layer 209 , a gate barrier layer 210 and a gate conductive layer 211 .
  • a second gate trench is formed inside the second active region 215 , a gate oxide layer 209 is deposited on the inner surface of the second gate groove, a gate barrier layer 210 is deposited on the inner surface of the gate oxide layer 209 , and a gate conductive layer 211 is filled in the groove formed by the gate barrier layer 210 .
  • the gate oxide layer 209 is made of a high dielectric constant material or oxide, and the gate barrier layer 210 can be, for example, a metal electrode material, which is used to block the mixture between the gate oxide layer 209 and the gate conductive layer 211.
  • the conductive layer 211 is made of, for example, a metal electrode material, and the selection and combination of the materials of each layer of the first gate electrode 216 can be defined according to the actual required work function.
  • a control wire groove is provided in the trench insulating portion 207 of the control region 201 , the control wire groove in the trench insulating portion 207 of the control region 201 and the wire groove in the second active region 215 are provided.
  • the second gate groove is connected, and the control wire groove in the trench insulating portion 207 of the control region 201 is filled with conductive material.
  • the conductive material in the control wire groove in the trench insulating portion 207 in the control region 201 and the first gate The gate conductive layer 211 in the electrode 216 is electrically connected and forms the control line 219 together.
  • the gate conductive layer 211 , the gate barrier layer 210 and the top surface of the gate oxide layer 209 are lower than the second gate
  • the notch of the groove, in the second gate groove provided on the second active region 215, is also provided with a gate insulating layer 220 located above the gate conductive layer 211, the gate barrier layer 210 and the gate oxide layer 209 , for insulating the gate conductive layer 211 .
  • the top surface of the conductive material filled in the control wire groove is also lower than the notch of the control wire groove, and the above-mentioned gate insulating layer 220 is also disposed above the conductive material in the control wire slot for insulating the conductive material in the control wire slot.
  • the first source-drain region 217 and the second source-drain region 218 are each connected to a corresponding bit line 205, and the bit line 205 connected to the first source-drain region 217 and the second source-drain region
  • the bit line 205 connected by 218 is located on both sides of the control line 219 .
  • first source-drain region 217 and the second source-drain region 218 can be prepared by ion implantation.
  • boron is doped into the second active region 215 to form a P-type semiconductor, and then, in Phosphorus or arsenic is doped into the first source-drain region 217 and the second source-drain region 218 to form an N-type semiconductor. In this way, the first source-drain region 217 and the second source-drain region 218 are formed.
  • first gate electrode 216 the first source and drain regions 217 and the second source and drain regions 218 provided in the second active region form a MOS transistor.
  • the memory includes three columns and four rows of storage cells 100 , and the storage cells 100 are the aforementioned capacitors 214 .
  • a total of three second active areas 215 are arranged between the rows.
  • all the storage units 100 in the first row, all the storage units 100 in the second row, and all the storage units 100 in the third row constitute a storage area 202, and the fourth row stores
  • the cell 100 constitutes a memory area 202
  • the three second active areas 215 located in a row constitute a control area 201 .
  • the memory also includes three columns of bit line groups, four rows of word lines 206 and one row of control lines 219.
  • the four rows of word lines 206 connect the memory cells 100 where each row of word lines 206 is located, and each column of bit line groups includes a first row, the second row of the column and the bit line 205 of the third row of the column, and the bit line 205 connected to the fourth row of the column, the two bit lines 205 of the bit line 205 group of each column are respectively connected with the corresponding second active region
  • the first source-drain region 217 of 215 is connected to the second source-drain region 218 .
  • the gate voltage of the second active region 215 in the first column can be controlled so that the two bit lines 205 in the first column are not connected.
  • the loading time is shortened.
  • the gate voltage of the source region 215 makes the two bit lines 205 in the first column conduct.
  • the memory cells 100 in the fourth row and the first column can be loaded through all the memory cells 100 in the first column.
  • the storage area 202 can be divided reasonably by controlling the position of the second active area 215, so that the frequently used storage unit 100 is located in one storage area 202, which can further speed up the average storage speed of the memory and improve the performance of the memory.
  • the first contact of each row of the first active area 203 of each storage area 202 is The region 204 is connected to a bit line 205, and the first source-drain region 217 and the second source-drain region 218 of the second active region 215 of the control region 201 are connected to the corresponding bit lines 205 on both sides of the second active region 215, Further, by controlling the voltage of the control line 219, the bit line 205 connected to the first source-drain region 217 and the bit line 205 connected to the second source-drain region 218 are controlled to be turned on, thereby controlling each read operation and write operation.
  • the effective length of the bit line 205 that is, controllable in each read operation and write operation, control the number of memory cells 100 connected to the effective bit line 205, and then control the time of each read operation and write operation,
  • the average storage speed of the memory is accelerated, and the performance of the memory is improved.
  • the first source and drain regions 217 are provided with a first conductive portion 221 .
  • the line 205 is connected, and the first conductive portion 221 can ensure reliable connection between the first source and drain regions 217 and the bit line 205, thereby reducing the contact resistance.
  • a second conductive portion 222 is disposed on the second source and drain regions 218 , and the second source and drain regions 218 pass through the second conductive portion 222 and the corresponding one
  • the bit line 205 is connected, and the second conductive portion 222 can ensure reliable connection between the second source and drain regions 218 and the bit line 205, thereby reducing the contact resistance.
  • the first conductive part 221 and the second conductive part 222 are located on the same layer. In this way, the structure of the memory can be more compact, the integration degree is high, and the preparation is more convenient.
  • a third conductive portion 223 is disposed on the first contact region 204 , and in each row of the first active region 203 of each storage region 202 , the third conductive portion on each of the first contact regions 204 223 connects a bit line 205.
  • the third conductive portion 223 can make reliable contact between the first contact region 204 and the bit line 205 and reduce the contact resistance.
  • the first conductive part 221, the second conductive part 222 and the third conductive part 223 are located in the same layer, so that the structure of the memory can be more compact, the integration degree is higher, and the preparation is more convenient.
  • the first gate 216 and the second gate 208 are located in the same layer, so that the structure of the memory can be more compact, the integration level is higher, and the fabrication is more convenient.
  • a plurality of control areas 201 and a plurality of storage areas 202 are disposed on the substrate 200 , and the control areas 201 and the storage areas 202 are alternately arranged at intervals.
  • two control areas 201 and three storage areas 202 are disposed on the substrate 200 , the three storage areas 202 are arranged along the second direction, and one storage area 202 is disposed between every two adjacent storage areas 202 .
  • the control area 201 is set alternately between the control area 201 and the storage area 202. Setting multiple control areas 201 and storage areas 202 on the substrate 200 can make the storage speed of the memory faster and the storage performance improved.
  • a second aspect of this embodiment further provides a method for preparing a memory, as shown in FIG. 7 , which includes the following steps:
  • Step S1 providing a substrate 200
  • the material of the substrate 200 can be, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon on insulator, and other materials known to those skilled in the art.
  • Step S2 forming a control region 201 on the substrate 200 and forming storage regions 202 on both sides of the control region 201;
  • each storage region 202 includes a plurality of first active regions 203, and the plurality of first active regions 203 are Arranged into several rows in one direction,
  • each control region 201 includes several second active regions 215 arranged along the first direction and corresponding to several rows of first active regions 203 one-to-one;
  • control area 201 and the storage area 202 include the following steps:
  • Step S21 forming a trench on the substrate 200; specifically, for example, first, a patterned mask layer is formed on the top surface of the substrate 200 by a photolithography process, and secondly, an etching process is performed on the substrate 200 by using the mask layer to obtain a trench groove.
  • Step S22 filling the trench with insulating material to form a trench insulating portion 207, wherein the insulating material can be silicon oxide or silicon nitride, for example, and filling the insulating material in the trench can flatten the substrate 200 on which the trench is provided. process, and the first active region 203 and the second active region 215 are effectively electrically isolated.
  • the method of filling the insulating material in the trench specifically, for example, first, a deposition process is used to deposit an insulating layer on the substrate 200 provided with the trench, and then, the insulating layer on the top surface of the substrate 200 is removed, leaving only the trench The insulating material inside forms the trench insulating portion 207 .
  • high temperature annealing treatment can also be performed after the insulating material is filled in the trench to reduce the pressure on the substrate.
  • a first contact region 204 is formed in each first active region 203 , a first gate 216 and first source and drain regions 217 located on both sides of the first gate 216 are provided in each second active region 215 and the second source and drain regions 218, the first gates 216 in the control region 201 are connected to each other to form a control line 219;
  • step S3 please refer to Fig. 3a and Fig. 3b, which specifically includes the following steps:
  • Step S31 performing ion implantation twice on the first active region 203 and the second active region 215 to form an upper first ion-doped layer on the first active region 203 and the second active region 215 and a second ion-doped layer located below, wherein the first ion-doped layer and the second ion-doped layer are respectively formed as different types of semiconductors, for example, the first ion-doped layer is an n-type semiconductor, and the second ion-doped layer is an n-type semiconductor.
  • the doped layer is a p-type semiconductor.
  • Step S32 forming a second gate trench in each of the second active regions 215 , and forming a first source-drain region 217 and a second source-drain region 218 with the first ion doping layer on both sides of the second gate trench, respectively, On the trench insulating portion 207 between the adjacent two second active regions 215 in each control region 201, a control wire trench is formed that communicates with the gate trench; the specific preparation process of this step is, for example, first, after forming the second active region 215.
  • a patterned mask layer is formed by a photolithography process, and secondly, the first ion-doped layer and the second ion-doped layer are formed by using the mask layer pair.
  • the substrate 200 of the layer is subjected to an etching process to obtain a first gate groove and a control line groove.
  • Step S33 forming a first gate 216 in the first gate trench of the second active region 215 .
  • the first gate 216 includes, for example, a gate oxide layer 209 , a gate barrier layer 210 and a gate conductive layer 211 .
  • Deposition of conductive material in the control wire groove includes steps: first, a layer of gate oxide layer 209 is deposited on the substrate 200 provided with the first gate groove and the control wire groove by a deposition process, and a layer of gate oxide layer 209 is deposited on the top surface of the substrate 200.
  • the gate oxide layer 209 and the gate oxide layer 209 in the control wire groove are removed, and only the gate oxide layer 209 in the first gate groove is retained; secondly, a layer of gate barrier layer 210 is deposited by the deposition process, and the The gate barrier layer 210 on the top surface of the substrate 200 and the gate barrier layer 210 in the control wire groove are removed, and only the gate barrier layer 210 in the first gate groove is retained; layer 211, and the gate conductive layer 211 on the top surface of the substrate 200 is removed, and only the gate conductive layer 211 in the gate groove and the control wire groove is retained.
  • Step S34 disposing the gate insulating layer 220 in the first gate trench, for example, including steps: first, an etch-back process is used to make the top surface of the gate oxide layer 209 , the top surface of the gate barrier layer 210 and the gate electrode The top surface of the conductive layer 211 is lower than the notch of the first gate trench, wherein, due to different etching selectivity ratios, the top surface of the gate oxide layer 209 , the top surface of the gate barrier layer 210 and the top surface of the gate conductive layer 211 are located at different heights; secondly, a layer of gate insulating layer 220 is deposited by a deposition process, and the gate insulating layer 220 on the top surface of the substrate 200 is removed, and only the gate insulating layer 220 in the gate groove and the control line groove is retained.
  • the gate insulating layer 220 is used to effectively insulate the gate conductive layer 211 .
  • step S3 is only exemplary steps, and in the actual preparation process, steps can be optimized. If the optimization of this step is only by changing the pattern of the mask layer, Further, forming the control wire groove in different steps and depositing the gate conductive layer 211 and the gate insulating layer 220 in the control wire groove are all within the protection scope of this embodiment.
  • step S32 including forming a first gate trench in each of the second active regions 215, excluding the trench insulating portion 207 between two adjacent second active regions 215 in each control region 201, forming a A control wire groove connected to the first gate groove;
  • step S33 includes forming the first gate 216 in the first gate groove, but does not include depositing a conductive material in the control wire groove, and the specific steps of the above step S3 also include steps S35, forming a control wire groove communicating with the first gate groove on the trench insulating portion 207 between two adjacent second active regions 215 in each control region 201; and step S36, forming a control wire groove in the control wire groove Deposit conductive material.
  • Step S4 forming bit lines 205 connected to the first contact regions 204 on each row of the first active regions 203, and in the same second active region 215, the first source and drain regions 217 and the second source and drain regions 218 is connected to a corresponding bit line 205 , and the bit line 205 connected to the first source-drain region 217 and the bit line 205 connected to the second source-drain region 218 are located on both sides of the control line 219 .
  • step S4 please refer to Fig. 4a, Fig. 4b, Fig. 4c and Fig. 4d, which specifically includes the following steps:
  • Step S41 forming the bit lines 205 on the substrate 200 provided with the control lines 219 by means of a photolithography process, an etching process and a deposition process. All the first contact regions 204 corresponding to one row are connected, and all the first contact regions 204 corresponding to one row include all the first contact regions 204 corresponding to one row of all storage regions 202 , and each bit line 205 is also connected to the corresponding second active region 215 The first source-drain region 217 or the second source-drain region 218 is connected.
  • step S42 the bit lines 205 are cut off on the substrate 200 provided with the bit lines 205 by means of a photolithography process and an etching process.
  • the bit line 205 is cut off at the bit line 205 just above the control line 219 .
  • a third ion doping may be performed in the second active region 215, thereby improving the conductivity of the semiconductor and reducing the contact resistance.
  • a first conductive portion 221 is formed on the first source-drain region 217, and the first source-drain region 217 passes through the first conductive portion 221 and the corresponding one Bit line 205 is connected.
  • step S41 of the above step S4 it further includes:
  • a patterned mask layer is arranged on the substrate 200 provided with the control lines 219, and the openings arranged on the mask layer leak out the first source and drain regions 217;
  • the upper half of the first source and drain regions 217 is etched away, and then the mask layer is removed;
  • a conductive layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, and only the conductive layer in the first source and drain regions 217 is retained to form a first conductive portion 221;
  • step S41 of the above-mentioned step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
  • a second conductive portion 222 is formed on the second source-drain region 218, and the second source-drain region 218 passes through the second conductive portion 222 and the corresponding one Bit line 205 is connected.
  • step S41 of the above step S4 it further includes:
  • a patterned mask layer is arranged on the substrate 200 provided with the control lines 219, and the openings arranged on the mask layer leak out the second source and drain regions 218;
  • the upper half of the second source and drain regions 218 is etched away, and then the mask layer is removed;
  • a conductive layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, and only the conductive layer in the second source and drain regions 218 is retained to form a second conductive portion 222;
  • step S41 of the above-mentioned step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
  • a third conductive portion 223 is formed on the first contact region 204, and in each row of the first active region 203 of each storage region 202, the third conductive portion on each first contact region 204 is electrically conductive Section 223 is connected to one bit line 205 .
  • the third conductive portion 223 can reduce the contact resistance between the first contact region 204 and the bit line 205 .
  • the specific preparation process is for example:
  • a patterned mask layer is arranged on the substrate 200 provided with the control lines 219, and the openings arranged on the mask layer leak out the first contact region 204;
  • the upper half of the first contact region 204 is etched away, and then the mask layer is removed;
  • a wire layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, and only the conductive layer in the first contact area 204 is retained to form the third conductive portion 223;
  • step S41 of the above-mentioned step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
  • the first conductive portion, the second conductive portion 222 and the third conductive portion 223 may be formed in the same process step. That is, in this embodiment, the preparation process is, for example:
  • a patterned mask layer is provided on the substrate 200 provided with the control lines 219 , and the openings provided on the mask layer can simultaneously leak out the first source and drain regions 217 , the second source and drain regions 218 and the first contact region 204 ;
  • a conductive layer is deposited by a deposition process, and the conductive layer on the surface of the substrate 200 is removed, and only the conductive layer in the first source and drain regions 217 , the conductive layer in the second source and drain regions 218 and the conductive layer in the first contact region 204 remain.
  • a conductive layer forming a first conductive part 221, a second conductive part 222 and a third conductive part 223;
  • step S41 of the above-mentioned step S4 is performed, that is, the bit line 205 is formed on the substrate 200 provided with the control line 219 by means of a photolithography process, an etching process and a deposition process.
  • a plurality of first active areas 203 are arranged in several columns along the second direction, and any adjacent two In the first active regions 203 in the row, the columns where all the first active regions 203 of one row are located are alternately arranged with the columns where all the first active regions 203 of the other row are located, and the first active regions 203 in the same column are arranged alternately at intervals.
  • the region 203 intersects with two word lines 206. In any adjacent column of the first active regions 203, the end of the first active region 203 in one column and the first active region 203 in the other column close to each other is the same word line 206.
  • each first active region 203 is located between the two second gates on the first active region 203 , that is, the first contact on each first active region 203
  • the region 204 is located between two word lines 206 staggered with the first active region 203 .
  • step S32 further includes: forming two first gate trenches in each of the first active regions 203, between the two first gate trenches The process of forming the first contact region 204 with the first ion-doped layer of the Corresponding improvements are made to the pattern of the mask.
  • Step S33 further includes, forming a second gate electrode 208 in the first gate electrode groove of the first active region 203 , the preparation process of the second gate electrode 208 and the first gate electrode
  • the preparation process of 216 is exactly the same, except that the pattern of the mask is changed accordingly during the preparation process.
  • two first gate trenches are provided on the first active region 203 , and the first ion implantation layer on the side of the two first gate trenches away from each other is the second contact region 212 .
  • a second gate 208 on the side of each second gate 208 away from the first contact region 204 is further formed in each first active region 203 .
  • the contact regions 212 connect each of the second contact regions 212 with the corresponding charge storage element.
  • the charge storage source element is, for example, capacitor 214 .
  • the specific example of preparing the capacitor 214 is as follows:
  • a fourth conductive portion 213 is provided above the second contact region 212 through a photolithography process, an etching process and a deposition process;
  • a capacitor 214 is formed over the fourth conductive portion 213 through a photolithography process, an etching process and a deposition process.
  • a plurality of control areas 201 and a plurality of storage areas 202 are formed on the substrate 200 , and the control areas 201 and the storage areas 202 are alternately arranged at intervals. Setting multiple control areas 201 and storage areas 202 on the substrate 200 can make the storage speed of the memory faster and the storage performance improved. It should be noted that, multiple control areas 201 and multiple storage areas 202 are formed on the substrate 200, for example, one control area 201, two storage areas 202, or two control areas 201 and three storage areas 202 are used. With the same preparation steps, this enables the fabricated memory to be faster and have improved performance without adding additional fabrication steps.
  • the first active region 203 and the second active region 215 can be formed in the same process step, and the first contact region 204, the second contact region 212, the first contact region 212, the first contact region 204, the first contact region 212, and the The source and drain regions 217 and the second source and drain regions 218, the first gate 216 and the second gate 208 are formed in the same process step, the word line 206 and the control line 219 are formed in the same process step, and the same process step is formed
  • the bit line 205 which makes the whole memory preparation process without adding new process steps, and, compared with the first active region 203, the second active region 215 only needs to be made corresponding to the structure near the second gate 208 Therefore, it is only necessary to make corresponding changes to the opening position of the mask in the manufacturing process, and the layout pattern of this mask does not change much compared with related technologies. Therefore, this paper
  • the preparation method of the memory of the embodiment is simple in process and easy to operate.

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Abstract

本申请提供一种存储器及其制备方法，涉及半导体技术领域，该存储器包括基底，基底设置有控制区，控制区的两侧分别设置有存储区；每个存储区包括若干行第一有源区，每行第一有源区内的各第一接触区连接一条位线；控制区包括若干个第二有源区，每个第二有源区设置有第一栅极以及位于第一栅极两侧的第一源漏区和第二源漏区，控制区内的各第一栅极相互连接构成控制线；在同一个第二有源区内，第一源漏区和第二源漏区各自与对应的一条位线连接。本申请的存储器，通过控制线控制与第一源漏区连接的位线以及与第二源漏区连接的位线是否导通，进而控制每次读操作和写操作时间，使得存储器的存储速度加快，存储器性能提升。

Description

存储器及其制备方法
本申请要求于2020年11月5日提交中国专利局、申请号为202011221712.8、申请名称为“存储器及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种存储器及其制备方法。
背景技术
动态随机存储器(dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。
动态随机存储器一般包括多个存储单元，多个存储单元按行按列排布形成存储矩阵，其中，每一列的存储单元通过一根字线连接，每一行的存储单元通过一根位线连接，在读取或写入的过程中，通常先按列选中一根字线连接的整列的存储单元，之后再按行选中一根位线连接的整行的存储单元，如此，当目标存储单元的位线和字线同时选中时，即可实现选中目标存储单元，进而实现对该目标存储单元的读取数据或写入数据。
然而，在选中目标存储单元时，动态随机存储器的读取或写入周期较长，速度较慢，不利于提升动态随机存储器的性能。
发明内容
鉴于上述问题，本申请实施例提供一种存储器以及存储器的制备方法，用于提升存储器的速度，进而提升存储器的性能。
为了实现上述目的，本申请实施例提供如下技术方案：
本申请实施例的第一方面提供一种存储器，其包括基底，基底设置有控制区，控制区的两侧分别设置有存储区；每个存储区包括多个第一有源区，多个第一有源区沿第一方向排布成若干行，每个第一有源区设置有第一接触区，且每行第一有源区内的各第一接触区连接一条位线；控制区包括沿第一方向排布且与若干行第一有源区一一对应的若干个第二有源区；每个第二有源区设置有第一栅极以及位于第一栅极两侧的第一源漏区和第二源漏区，控制区内的各第一栅极相互连接以构成控制线；在同一个第二有源区内，第一源漏区和第二源漏区各自与对应的一条位线连接，且与第一源漏区连接的位线和与第二源漏区连接的位线位于控制线的两侧。
在一些实施方式中，在每个第二有源区内，第一源漏区上设置有第一导电部，第一源漏区通过第一导电部与对应的一条位线连接。
在一些实施方式中，在每个第二有源区内，第二源漏区上设置有第二导电部，第二源漏区通过第二导电部与对应的一条位线连接。
在一些实施方式中，第一导电部和第二导电部位于同一层。
在一些实施方式中，第一接触区上设置有第三导电部；在每个存储区的每行第一有源区内，各第一接触区上的第三导电部连接一条位线。
在一些实施方式中，第一导电部、第二导电部以及第三导电部位于同一层。
在一些实施方式中，每个存储区内，多个第一有源区沿第二方向排布成若干列，任意相邻两行中的第一有源区中，其中一行的所有第一有源区所在列与另一行的所有第一有源区所在列交替间隔设置，且同一列中的各第一有源区与两条字线相交，任意相邻列的第一有源区中，其中一列第一有源区与另一列第一有源区彼此靠近的端部与同一字线相交，其中，第二方向与第一方向垂直设置；同一列中的每个第一有源区设置有两个第二栅极，两个第二栅极分别与该第一有源区交错设置的两条字线连接。
在一些实施方式中，每个第一有源区上的第一接触区位于与两个第二栅极之间。
在一些实施方式中，第一栅极和第二栅极位于同一层。
在一些实施方式中，每个第一有源区还包括设置在每个第二栅极的背离第一接触区一侧的第二接触区，每个第二接触区与对应的电荷存储元件连接。
在一些实施方式中，基底上设置有多个控制区以及多个存储区，各控制区与各存储区交替间隔设置。
本申请实施例的第二方向提供一种存储器的制备方法，其包括如下步骤：
提供基底；
在基底上形成控制区以及在控制区的两侧分别形成存储区；每个存储区包括多个第一有源区，多个第一有源区沿第一方向排布成若干行，控制区包括沿第一方向排布且与若干行第一有源区一一对应的若干个第二有源区；
在每个第一有源区形成第一接触区，在每个第二有源区设置第一栅极以及位于第一栅极两侧的第一源漏区和第二源漏区，控制区内的第一栅极相互连接以构成一条控制线；
在每行第一有源区上方形成与各第一接触区连接的位线，在同一个第二有源区内，第一源漏区和第二源漏区与各自与对应的一条位线连接，且与第一源漏区连接的位线和与第二源漏区连接的位线位于控制线的两侧。
在一些实施方式中，在每个第二有源区内，在第一源漏区上形成第一导电部，将第一源漏区通过第一导电部与对应的一条位线连接。
在一些实施方式中，在每个第二有源区内，在第二源漏区上形成第二导电部，将第二源漏区通过第二导电部与对应的一条位线连接。
在一些实施方式中，在同一工艺步骤中形成第一导电部和第二导电部。
在一些实施方式中，在第一接触区上形成第三导电部；在每个存储区的每行第一有源区内，将各第一接触区上的第三导电部与一条位线连接。
在一些实施方式中，在同一工艺步骤中形成第一导电、第二导电部以及第三导电部。
在一些实施方式中，在每个存储区内，多个第一有源区沿第二方向排布成若干列，任意相邻两行中的第一有源区中，其中一行的所有第一有源区所在列与另一行的所有有源区所在列交替间隔设置，且同一列中的各第一有源区与两条字线交错设置，任意相邻 列的第一有源区中，其中一列第一有源区与另一列第一有源区彼此靠近的端部与一根字线连接；在同一列中的每个第一有源区形成两个第二栅极，将两个第二栅极分别与该第一有源区交错设置的两条字线连接。
在一些实施方式中，每个第一有源区上的第一接触区位于两个第二栅极之间。
在一些实施方式中，在同一工艺步骤中设置第一栅极和第二栅极。
在一些实施方式中，在每个第一有源区还形成位于每个第二栅极的背离第一接触区一侧的第二接触区，将每个第二接触区与对应的电荷存储元件连接。
在一些实施方式中，在基底上形成多个控制区以及多个存储区，且将各控制区与各存储区交替间隔排布。
本申请实施例所提供的存储器中，通过在基底上设置控制区，在控制区的两侧分别设置存储区，将各存储区的各行第一有源区的第一接触区与一条位线连接，将控制区的第二有源区的第一源漏区和第二源漏区与第二有源区两侧的对应位线连接，进而通过控制该控制线的电压，控制与第一源漏区连接的位线以及与第二源漏区连接的位线是否导通，进而，控制每次读操作和写操作时，位线的有效长度，也即，可控的在每次读操作和写操作中，控制有效位线连接的存储单元的数量，进而控制每次读操作和写操作的时间，使得存储器的平均存储速度加快，存储器的性能提升。
本申请实施例的存储器的制备方法，制备的存储器的存储速度快，性能好，且制备过程简单，工艺难度低。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的存储器及其制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中的存储器的原理示意图；
图2a为本实施例基底上设置第一有源区和第二有源区的结构示意图；
图2b为图2a在AA线位置的剖视图；
图3a为本实施例提供的存储器形成字线和控制线的结构示意图；
图3b为图3a在BB线位置处的剖视图；
图4a为本实施例提供的存储器形成位线的结构示意图一；
图4b为图4a在CC线位置的剖视图；
图4c为本实施例提供的存储器形成位线的结构示意图二；
图4d为图4d在DD线位置的剖视图；
图5a为本实施例提供的存储器形成有电容器的结构示意图；
图5b为图5a在EE线位置的剖视图；
图5c为图5a在FF线位置的剖视图；
图6为本实施例提供的存储器的原理示意图；
图7为本实施例提供的存储器的制备方法的流程图。
附图标记：
100：存储单元；101：缓存区；200：基底；201：控制区；202：存储区；203：第一有源区；204：第一接触区；205：位线；206：字线；207：沟槽绝缘部；208：第二栅极；209：栅极氧化层；210：栅极阻挡层；211：栅极导电层；212：第二接触区；213：第四导电部；214：电容器；215：第二有源区；216：第一栅极；217：第一源漏区；218：第二源漏区；219：控制线；220：栅极绝缘层；221：第一导电部；222：第二导电部；223：第三导电部。
具体实施方式
在相关技术中，存储器一般包括多个存储单元100，示例性的，如图1所示，该存储器包括十五个存储单元100，十五个存储单元100形成五行三列的存储矩阵，其中，每行存储单元100通过一根字线206(英文名称为Word line，简称为WL)连接，每列存储单元100通过一根位线205(英文名称为Bit line，简称为BL)连接。该存储器的读操作原理如下：
以对第一行第一列的存储单元100进行读操作为例，首先，通过第一行存储单元100连接的字线206，选中第一行所有的存储单元100，并将其暂存在缓存区101，然后，通过第一列存储单元100连接的位线205，选中第一列所有的存储单元100，如此，即可将第一行第一列的存储单元100选中，进而进行读操作。
然而，本申请的发明人发现，例如当需要选中第一行第一列的存储单元100时，同时也会选中第二行第一列的存储单元100、第三行第一列的存储单元100、第四行第一列的存储单元100以及第五行第一列的存储单元100，造成对第二行第一列的存储单元100、第三行第一列的存储单元100、第四行第一列的存储单元100、以及第五行第一列的存储单元100的加载是多余，这会使得整个加载时间变长，存储器的存储速度变慢，存储器的性能变差。
为此，本申请提出一种存储器以及制备方法，其在基底上设置控制区、以及位于控制区的两侧的存储区，在各存储区设置多行第一有源区，每行第一有源区与一位线连接，在控制区设置多个第二有源区，每个第二有源区形成第一栅极、位于第一栅极的第一源漏区和第二源漏区，第一源漏区和第二源漏区分别与所在第二有源区两侧的位线连接，如此，即可通过控制第一栅极的电压，控制相邻两个存储区中的对应一行的所有第一有源区，是否通过与第一源漏区连接的位线以及与第二源漏区连接的位线导通，进而控制每次读操作和写操作时位线的有效长度，也即，可控的在每次读操作和写操作中，控制有效位线连接的存储单元的数量，进而减小每次读操作和写操作的时间，使得存储器的平均存储速度加快，存储器的性能提升。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申 请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
如图2a所示，本实施例提供的一种存储器，其包括基底200，基底200设置有控制区201，控制区201的两侧分别设置有存储区202。
请参阅图2a，每个存储区202包括多个第一有源区203，多个第一有源区203沿第一方向排布成若干行，例如，在本实施例中，多个第一有源区203沿第一方向排布成七行，每行包括四个第一有源区203，其中，第一方向可以为如图2a所示的X方向。请参阅图4b所示，每个第一有源区203设置有第一接触区204，在本实施例中，第一接触区204大概位于第一有源区203的中间位置，且每行第一有源区203内的各第一接触区204连接有一条位线205。
请参阅图2a和图3a，每个存储区202内，多个第一有源区203还沿第二方向排布成若干列，第二方向与第一方向垂直设置，第二方向可以为如图3a所示的Y方向。任意相邻两行中的第一有源区203中，其中一行的所有第一有源区203与另一行的所有第一有源区203错位设置，且同一列中的各第一有源区203与两条字线206相交，任意相邻两列的第一有源区203中，其中一列第一有源区203与另一列第一有源区203彼此靠近的端部与同一字线206相交。进一步，第一有源区203为带状结构，且第一有源区203沿第三方向延伸，第三方向与第二方向呈预定夹角设置，夹角范围在15°至30°之间，第三方向如图3a所示的Z向。
需要说明的是，如图2a和图2b所示，相邻的第一有源区203之间设置有沟槽绝缘部207，沟槽绝缘部207由位于相邻第一有源区203之间的沟槽中填充绝缘材料形成，用于将相邻第一有源区203电性隔开。
请参阅图3a和图3b所示，同一列中的每个第一有源区203设置有两个第二栅极208，两个第二栅极208分别与该第一有源区203交错设置的两条字线206连接。第二栅极208例如包括栅极氧化层209、栅极阻挡层210以及栅极导电层211，具体的，第一有源区203上设置有第一栅极槽，第一栅极槽的内表面沉积有一层栅极氧化层209、栅极氧化层209的内表面沉积一层栅极阻挡层210，栅极阻挡层210内的槽中填充栅极导电层211。其中，栅极阳氧化层采用高介电常数材料或者氧化物，栅极阻挡层210例如可以是金属电极材料，用于阻挡栅极氧化层209和栅极导电层211之间的混合，栅极导电层211例如采用金属电极材料。并且，同一列的第一有源区203中，相邻的第一有源区203之间设置的沟槽绝缘部207上还设置有字线槽，字线槽中沉积有与栅极导电层211电连接的导电材料，字线槽中的导电材料和栅极导电层211电连接，并形成字线206。
请参阅图3b所示，在一些实施方式中，每个第一有源区203还包括设置在每个第二栅极208的背离第一接触区204一侧的第二接触区212，每个第二接触区212与对应的电荷存储元件连接。电荷存储元件例如为图5a示出的电容器214。电容器214例如通过图5b示出第四导电部213与第二接触区212连接。请参阅图3b所示，每个第一有源区203上的第一接触区204位于两个第二栅极208之间，此时，每个第一有源区203与一条位线205连接，而与两条字线206连接。如此，每个第一有源区203上的两个第二栅极208， 第一接触区204以及两个第二接触区212共同形成两个MOS管(英文名称为Metal Oxide Semiconductor，中文名称为金属氧化物半导体场效应晶体管)，其中，一个第二栅极208、该第二栅极208一侧的第二接触区212以及该第二栅极208另一侧的第一接触区204共同形成一个MOS管。这种设置方式，可以使得存储器的结构更加紧凑，集成度更高。
请参阅图4a所示，本实施例的存储器，每个控制区201包括沿第一方向排布且与若干行第一有源区203一一对应的若干个第二有源区215。第二有源区215也为带状结构，且第二有源区215也沿第三方向延伸，第三方向与第二方向呈预定夹角设置，夹角范围在15°至30°之间。需要说明的是，第二有源区215之间、第二有源区215和第一有源区203之间也设置有沟槽绝缘部207，沟槽绝缘部207还用于将相邻两个第二有源区215、相邻的第一有源区203和第二有源区215电性隔开。
请参阅图4a和图4b所示，每个第二有源区215设置有第一栅极216以及位于第一栅极216两侧的第一源漏区217和第二源漏区218，每个控制区201内包含一条贯穿各第二有源区215的一条控制线219，即由各第一栅极216连接形成。
请继续参阅图4b所示，第一栅极216包括栅极氧化层209和栅极阻挡层210和栅极导电层211，具体的，第二有源区215的内部形成有第二栅极槽，第二栅极槽的内表面沉积有栅极氧化层209，栅极氧化层209的内表面沉积有栅极阻挡层210，栅极阻挡层210形成的凹槽中填充栅极导电层211。其中，栅极氧化层209采用高介电常数材料或者氧化物，栅极阻挡层210例如可以是金属电极材料，用于阻挡栅极氧化层209和栅极导电层211之间的混合，栅极导电层211例如采用金属电极材料，第一栅极216的各层材料的选取和组合可以根据实际需要的功函数来定义。
示例性的，在一些实施方式中，在控制区201的沟槽绝缘部207内设置有控制线槽，控制区201的沟槽绝缘部207内的控制线槽和第二有源区215内的第二栅极槽连通，控制区201的沟槽绝缘部207内的控制线槽中填充有导电材料，如此，控制区201内沟槽绝缘部207内控制线槽中的导电材料和第一栅极216内的栅极导电层211电性连接，并共同形成控制线219。
请继续参阅图4b所示，第二有源区215上设置的第二栅极槽中，栅极导电层211和栅极阻挡层210以及栅极氧化层209的顶面低于第二栅极槽的槽口，在第二有源区215上设置的第二栅极槽中，还设置有位于栅极导电层211和栅极阻挡层210以及栅极氧化层209上方的栅极绝缘层220，用于对栅极导电层211进行绝缘。示例性的，在控制区201的沟槽绝缘部207内设置的控制线槽中，该控制线槽中填充的导电材料的顶面也低于该控制线槽的槽口，上述栅极绝缘层220也设置在该控制线槽内导电材料的上方，用于对该控制线槽内的导电材料进行绝缘。
请参阅图4c所示，第一源漏区217和第二源漏区218各自与对应的一条位线205连接，且与第一源漏区217连接的位线205和与第二源漏区218连接的位线205位于控制线219的两侧。
需要说明的是，第一源漏区217和第二源漏区218可以通过离子注入的方式制备得到，例如，首先在第二有源区215内掺入硼，形成P型半导体，其次，在第一源漏区217和第二源漏区218内掺入磷或者砷，形成N型半导体，如此，形成第一源漏区217和第二源漏区218。
值得说明的是，在第二有源内设置的第一栅极216、第一源漏区217和第二源漏区218即形成一个MOS管。
为了说明本实施例的存储器的工作原理，请参阅图6所示，在该实施方式中，存储器包括三列四行存储单元100，存储单元100为前述的电容器214，在第三行和第四行之间设置一行共计三个第二有源区215，显然，第一行所有存储单元100、第二行所有存储单元100以及第三行所有存储单元100构成一个存储区202，第四行存储单元100构成一个存储区202，位于一行的三个第二有源区215构成控制区201。该存储器还包括三列位线组、四行字线206以及一行控制线219，四行字线206将每行字线206所在的存储单元100连接，每列位线组包括连接该列第一行、该列第二行以及该列第三行的位线205，以及连接该列第四行的位线205，每列位线205组的两条位线205分别与对应第二有源区215的第一源漏区217和第二源漏区218相连。示例性的，当对第一行第一列的存储单元100进行读操作的时候，可以控制第一列的第二有源区215的栅极电压，使得第一列的两个位线205不导通，此时，无需加载第四行第一列的存储单元100，加载时间缩短，当对第四行第一列的存储单元100进行读操作的时候，可以控制第一列的第二有源区215的栅极电压，使得第一列的两个位线205导通，此时，可以通过第一列所有存储单元100，实现加载第四行第一列的存储单元100，如此，当读操作的数量增加时，这使得存储器的平均存储速度加快，存储器的性能得到提成。此外，可以通过控制第二有源区215的位置，合理的划分存储区202，这样经常使用的存储单元100位于一个存储区202，可以进一步加快存储器的平均存储速度，提上存储器的性能。
本申请实施例所提供的存储器中，通过在基底200上设置控制区201，在控制区201的两侧分别设置存储区202，将各存储区202的各行第一有源区203的第一接触区204与一条位线205连接，将控制区201的第二有源区215的第一源漏区217和第二源漏区218与第二有源区215两侧的对应位线205连接，进而通过控制该控制线219的电压，控制与第一源漏区217连接的位线205以及与第二源漏区218连接的位线205是否导通，进而，控制每次读操作和写操作时，位线205的有效长度，也即，可控的在每次读操作和写操作中，控制有效位线205连接的存储单元100的数量，进而控制每次读操作和写操作的时间，使得存储器的平均存储速度加快，存储器的性能提升。
请参阅图4d所示，在每个第二有源区215内，第一源漏区217上设置有第一导电部221，第一源漏区217通过第一导电部221与对应的一条位线205连接，第一导电部221可以使得第一源漏区217和位线205之间可靠连接，减小接触电阻。
请继续参阅图4d所示，在每个第二有源区215内，第二源漏区218上设置有第二导电部222，第二源漏区218通过第二导电部222与对应的一条位线205连接，第二导电部222可以使得第二源漏区218和位线205之间可靠连接，减小接触电阻。
在一些实施方式中，第一导电部221和第二导电部222位于同一层。这样可以使得存储器的结构更加紧凑，集成度高，制备更加方便。
请参阅图4d所示，第一接触区204上设置有第三导电部223，在每个存储区202的每行第一有源区203内，各第一接触区204上的第三导电部223连接一条位线205。第三导电部223可以使得第一接触区204和位线205之间可靠接触，减小接触电阻。
在一些实施方式中，第一导电部221、第二导电部222以及第三导电部223位于同一 层，如此，可以使得存储器的结构更加紧凑，集成度更高，制备更加方便。
在一些实施方式中，第一栅极216和第二栅极208位于同一层，如此，可以使得存储器的结构更加紧凑，集成度更高，制备更加方便。
在一些实施方式中，基底200上设置有多个控制区201以及多个存储区202，各控制区201与各存储区202交替间隔设置。例如，在一些实施方式中，基底200上设置有两个控制区201以及三个存储区202，三个存储区202沿第二方向排布，每相邻两个存储区202之间设置有一个控制区201，以实现控制区201和存储区202交替间隔设置。在基底200上设置多个控制区201和存储区202，可以使得存储器的存储速度更快，存储性能得到提升。
本实施例第二方面还提供一种存储器的制备方法，如图7所示，其包括如下步骤：
步骤S1，提供基底200；
在上述步骤S1中，基底200的材质例如可以为单晶硅，多晶硅、无定型硅、硅锗化合物、绝缘体上硅、以及本领域技术人员已知的其他材料。
步骤S2，在基底200上形成控制区201以及在控制区201的两侧分别形成存储区202；每个存储区202包括多个第一有源区203，多个第一有源区203沿第一方向排布成若干行，每个控制区201包括沿第一方向排布且与若干行第一有源区203一一对应的若干个第二有源区215；
在上述步骤S2中，请参阅图2a和图2b所示，控制区201和存储区202例如包括如下步骤：
步骤S21，在基底200上设置沟槽；具体例如，首先，在基底200的顶面通过光刻工艺形成图形化掩膜层，其次，利用掩膜层在基底200上进行刻蚀工艺，得到沟槽。
步骤S22，在沟槽中填充绝缘材料，形成沟槽绝缘部207，其中，绝缘材料例如可以为氧化硅或氮化硅，在沟槽中填充绝缘材料，可以对设置沟槽的基底200进行平坦化处理，且将第一有源区203和第二有源区215有效电性隔离。在沟槽中填充绝缘材料的方式，具体例如，首先，在设置有沟槽的基底200上采用沉积工艺沉积一层绝缘层，之后，在将基底200顶面的绝缘层去除，仅保留沟槽内的绝缘材料，形成沟槽绝缘部207。
当然，也可以在沟槽中填充绝缘材料后，进行高温退火处理，以降低衬底受到的压力。
步骤S3，在每个第一有源区203形成第一接触区204，在每个第二有源区215设置第一栅极216以及位于第一栅极216两侧的第一源漏区217和第二源漏区218，控制区201内的各第一栅极216相互连接以构成一条控制线219；
在上述步骤S3中，请参阅图3a和图3b所示，具体包括如下步骤：
步骤S31：在第一有源区203和第二有源区215进行两次离子植入，以于第一有源区203和第二有源区215上形成位于上方的第一离子掺杂层以及位于下方的第二离子掺杂层，其中，第一离子掺杂层和第二离子掺杂层分别形成为不同类型的半导体，例如，第一离子掺杂层为n型半导体，第二离子掺杂层为p型半导体。
步骤S32：在各第二有源区215中形成第二栅极槽，第二栅极槽两侧的第一离子掺杂层分别形成第一源漏区217和第二源漏区218，在每个控制区201内相邻两个第二有源区215之间的沟槽绝缘部207上，形成与栅极槽连通的控制线槽；该步的具体制备过程例如， 首先，在形成第一离子掺杂层和第二离子掺杂层的基底200的顶面，通过光刻工艺形成图形化掩膜层，其次，利用掩膜层对形成第一离子掺杂层和第二离子掺杂层的基底200进行刻蚀工艺处理，得到第一栅极槽和控制线槽。
步骤S33：在第二有源区215的第一栅极槽中形成第一栅极216，第一栅极216例如包括栅极氧化层209、栅极阻挡层210和栅极导电层211，在控制线槽中沉积导电材料，具体例如包括步骤：首先，在设置有第一栅极槽和控制线槽的基底200上采用沉积工艺沉积一层栅极氧化层209，并将基底200顶面的栅极氧化层209以及控制线槽中的栅极氧化层209去除，仅保留第一栅极槽内的栅极氧化层209；其次，继续采用沉积工艺沉积一层栅极阻挡层210，并将基底200顶面的栅极阻挡层210以及控制线槽中的栅极阻挡层210去除，仅保留第一栅极槽内的栅极阻挡层210；然后，继续采用沉积工艺沉积一层栅极导电层211，并将基底200顶面的栅极导电层211去除，仅保留栅极槽和控制线槽内的栅极导电层211。
步骤S34：在第一栅极槽中设置栅极绝缘层220，具体例如包括步骤：首先，采用回刻工艺，使得栅极氧化层209的顶面、栅极阻挡层210的顶面和栅极导电层211顶面低于第一栅极槽的槽口，其中，由于刻蚀选择比不同，栅极氧化层209的顶面、栅极阻挡层210的顶面和栅极导电层211顶面位于不同的高度；其次，采用沉积工艺沉积一层栅极绝缘层220，并将基底200顶面的栅极绝缘层220去除，仅保留栅极槽和控制线槽内的栅极绝缘层220。栅极绝缘层220用于对栅极导电层211进行有效绝缘。
需要解释的是，在上述步骤S3的具体步骤仅是示例性的步骤，在实际的制备过程中，可以进行步骤的优化，这种步骤的优化若仅是通过对掩膜层的图形进行更改，进而在不同的步骤中形成控制线槽和在控制线槽中沉积栅极导电层211和栅极绝缘层220等，均为本实施例的保护范围，例如，上述步骤S3的具体步骤中，步骤S32，包括在各第二有源区215中形成第一栅极槽，不包括在每个控制区201内相邻两个第二有源区215之间的沟槽绝缘部207上，形成与第一栅极槽连通的控制线槽；步骤S33，包括在第一栅极槽中形成第一栅极216，不包括在控制线槽中沉积导电材料，并且上述步骤S3的具体步骤还包括步骤S35，在每个控制区201内相邻两个第二有源区215之间的沟槽绝缘部207上形成与第一栅极槽连通的控制线槽；以及步骤S36，在控制线槽中沉积导电材料。
步骤S4，在每行第一有源区203上形成与各第一接触区204连接的位线205，在同一个第二有源区215内，第一源漏区217和第二源漏区218与各自与对应的一条位线205连接，且与第一源漏区217连接的位线205和与第二源漏区218连接的位线205位于控制线219的两侧。
在上述步骤S4中，请参阅图4a、图4b、图4c和图4d所示，具体包括如下步骤：
步骤S41：在设置有控制线219的基底200上通过光刻工艺、刻蚀工艺以及沉积工艺的方式形成位线205，此时，形成的若干行位线205中，每根位线205与位于对应一行的所有第一接触区204连接，对应一行的所有第一接触区204包括所有存储区202对应一行的第一接触区204，且每根位线205还与对应的第二有源区215的第一源漏区217或者第二源漏区218相连。
步骤S42，在设置有位线205的基底200上通过光刻工艺、刻蚀工艺的方式，将位线205截断，截断位置为每根位线205与控制线219交错的位置，也即，在控制线219正上 方的位线205处截断位线205。
在一些实施方式中，可以在第二有源区215，进行第三次离子掺杂，进而改善半导体的导电率，降低接触电阻。
请参阅图4b所示，在每个第二有源区215内，在第一源漏区217上形成第一导电部221，将第一源漏区217通过第一导电部221与对应的一条位线205连接。
具体例如，在上述步骤S4的步骤S41之前还包括：
首先，在设置有控制线219的基底200上设置图形化的掩膜层，该掩膜层上设置的开口漏出第一源漏区217；
其次，利用该掩膜层，刻蚀掉第一源漏区217的上半部分，之后去除该掩膜层；
然后，采用沉积工艺沉积导电层，并将基底200表面的导电层去除，仅保留第一源漏区217中的导电层，形成第一导电部221；
之后，执行上述步骤S4的步骤S41，也即，在设置有控制线219的基底200上通过光刻工艺、刻蚀工艺以及沉积工艺的方式形成位线205。
请参阅图4b所示，在每个第二有源区215内，在第二源漏区218上形成第二导电部222，将第二源漏区218通过第二导电部222与对应的一条位线205连接。
具体例如，在上述步骤S4的步骤S41之前还包括：
首先，在设置有控制线219的基底200上设置图形化的掩膜层，该掩膜层上设置的开口漏出第二源漏区218；
其次，利用该掩膜层，刻蚀掉第二源漏区218的上半部分，之后去除该掩膜层；
然后，采用沉积工艺沉积导电层，并将基底200表面的导电层去除，仅保留第二源漏区218中的导电层，形成第二导电部222；
最后，执行上述步骤S4的步骤S41，也即，在设置有控制线219的基底200上通过光刻工艺、刻蚀工艺以及沉积工艺的方式形成位线205。
请参阅图4b所示，在第一接触区204上形成第三导电部223，在每个存储区202的每行第一有源区203内，将各第一接触区204上的第三导电部223与一条位线205连接。第三导电部223能够降低第一接触区204和位线205的接触电阻。
具体制备过程例如：
首先，在设置有控制线219的基底200上设置图形化的掩膜层，该掩膜层上设置的开口漏出第一接触区204；
其次，利用该掩膜层，刻蚀掉第一接触区204的上半部分，之后去除该掩膜层；
然后，采用沉积工艺沉积导线层，并将基底200表面的导电层去除，仅保留第一接触区204内的导电层，形成第三导电部223；
最后，执行上述步骤S4的步骤S41，也即，在设置有控制线219的基底200上通过光刻工艺、刻蚀工艺以及沉积工艺的方式形成位线205。
请参阅图4b所示，在一些实施方式中，可以在同一工艺步骤中形成第一导电、第二导电部222以及第三导电部223。也即，该实施方式中，制备过程例如为：
首先，在设置有控制线219的基底200上设置图形化的掩膜层，该掩膜层上设置的开口能够同时漏出第一源漏区217、第二源漏区218以及第一接触区204；
其次，利用该掩膜层，刻蚀掉第一源漏区217的上半部分、第二源漏区218的上半 部分以及第一接触区204的上半部分，之后去除该掩膜层；
然后，采用沉积工艺沉积导电层，并将基底200表面的导电层去除，仅保留第一源漏区217中的导电层、第二源漏区218中的导电层以及第一接触区204中的导电层，形成第一导电部221、第二导电部222和第三导电部223；
最后，执行上述步骤S4的步骤S41，也即，在设置有控制线219的基底200上通过光刻工艺、刻蚀工艺以及沉积工艺的方式形成位线205。
请参阅图3a所示，采用本实施例的存储器的制备方法制备的存储器，在每个存储区202内，多个第一有源区203沿第二方向排布成若干列，任意相邻两行中的第一有源区203中，其中一行的所有第一有源区203所在列与另一行的所有第一有源区203所在列交替间隔设置，且同一列中的各第一有源区203与两条字线206相交，任意相邻列的第一有源区203中，其中一列第一有源区203与另一列第一有源区203彼此靠近的端部与同一字线206相交；在同一列中的每个第一有源区203形成两个第二栅极208，将两个第二栅极208分别与该第一有源区203交错设置的两条字线206连接。每个第一有源区203上的第一接触区204位于该第一有源区203上的两个第二栅极之间，也即，每个第一有源区203上的第一接触区204位于与该第一有源区203交错设置的两条字线206之间。
需要说明的是，可以在同一工艺步骤中设置第一栅极216和第二栅极208，以简化制备过程。请参阅图3a和3b所示，具体例如，在前述步骤S3中，步骤S32还包括：在各第一有源区203中形成两个第一栅极槽，两个第一栅极槽之间的第一离子掺杂层形成第一接触区204，在第一有源区203上形成第一栅极槽和在第二有源区215上形成第二栅极槽的过程可以一样，仅是对掩膜版的图形做相应的改进，步骤S33还包括，在第一有源区203的第一栅极槽中形成第二栅极208，第二栅极208的制备过程和第一栅极216的制备过程完全一样，仅是在制备过程中，对掩膜版的图形做出相应的改变。
在上述实施方式中，在第一有源区203上设置两个第一栅极槽，两个第一栅极槽相背离的一侧第一离子注入层即为第二接触区212。
在一些实施方式中，采用本实施例的存储器的制备方法制备的存储器，在每个第一有源区203还形成位于每个第二栅极208的背离第一接触区204一侧的第二接触区212，将每个第二接触区212与对应的电荷存储元件连接。电荷存储源元件例如为电容器214。
请参阅图5a、图5b、图5c所示，制备电容器214具体例如为：
首先，通过光刻工艺、刻蚀工艺以及沉积工艺在第二接触区212的上方设置第四导电部213；
其次，再通过光刻工艺、刻蚀工艺以及沉积工艺在第四导电部213的上方形成电容器214。
请参阅图5b和图5c所示，本实施例的存储器及其制备方法制备的存储器，仅在存储区202内第一有源区203的第二接触区212上方形成了电容器214，在控制区201的第二有源区215上方不设置电容器214，而是，在控制区201仅相应沉积有绝缘层。
在一些实施方式中，在基底200上形成多个控制区201以及多个存储区202，且将各控制区201与各存储区202交替间隔排布。在基底200上设置多个控制区201和存储区202，可以使得存储器的存储速度更快，存储性能得到提升。需要说明的是，在基底200上形成多个控制区201以及多个存储区202，例如设置一个控制区201，两个存储区202， 或者两个控制区201，三个存储区202，均使用相同的制备步骤，这使得制备的存储器的速度更快，性能得到提升，同时不增加制备步骤。
本实施例的存储器的制备方法，可以在同一工艺步骤中形成第一有源区203和第二有源区215，在同一工艺步骤中形成第一接触区204、第二接触区212、第一源漏区217以及第二源漏区218，在同一工艺步骤中形成第一栅极216和第二栅极208，在同一工艺步骤中形成字线206和控制线219，在同一工艺步骤中形成位线205，这使得整个存储器的制备过程没有增加新的工艺步骤，而且，第二有源区215和第一有源区203相比，仅需要对第二栅极208的附近结构做出相应的修改即可，因而，仅需要对制程中的掩膜版的开口位置做出相应的修改即可，而且这种掩膜版的版图图形与相关技术相比，变化并不大，因此，本实施例的存储器的制备方法，工艺过程简单，易操作。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (22)

  1. 一种存储器，其中，包括基底，所述基底设置有控制区，所述控制区的两侧分别设置有存储区；
    每个所述存储区包括多个第一有源区，多个所述第一有源区沿第一方向排布成若干行，每个所述第一有源区设置有第一接触区，且每行所述第一有源区内的各所述第一接触区连接一条位线；
    所述控制区包括沿第一方向排布且与若干行第一有源区一一对应的若干个第二有源区；
    每个所述第二有源区设置有第一栅极以及位于所述第一栅极两侧的第一源漏区和第二源漏区，所述控制区内的各所述第一栅极相互连接以构成控制线；
    在同一个所述第二有源区内，所述第一源漏区和所述第二源漏区各自与对应的一条所述位线连接，且与所述第一源漏区连接的所述位线和与所述第二源漏区连接的所述位线位于所述控制线的两侧。
  2. 根据权利要求1所述的存储器，其中，在每个所述第二有源区内，所述第一源漏区上设置有第一导电部，所述第一源漏区通过所述第一导电部与对应的一条所述位线连接。
  3. 根据权利要求2所述的存储器，其中，在每个所述第二有源区内，所述第二源漏区上设置有第二导电部，所述第二源漏区通过所述第二导电部与对应的一条所述位线连接。
  4. 根据权利要求3所述的存储器，其中，所述第一导电部和所述第二导电部位于同一层。
  5. 根据权利要求3所述的存储器，其中，所述第一接触区上设置有第三导电部；
    在每个所述存储区的每行所述第一有源区内，各所述第一接触区上的所述第三导电部连接一条所述位线。
  6. 根据权利要求5所述的存储器，其中，所述第一导电部、所述第二导电部以及第三导电部位于同一层。
  7. 根据权利要求1-6任一项所述的存储器，其中，每个所述存储区内，多个所述第一有源区沿第二方向排布成若干列，任意相邻两行中的所述第一有源区中，其中一行的所有第一有源区所在列与另一行的所有第一有源区所在列交替间隔设置，且同一列中的各所述第一有源区与相同两条字线相交，任意相邻列的所述第一有源区中，其中一列第一有源区与另一列第一有源区彼此靠近的端部与同一所述字线相交，其中，所述第二方向与所述第一方向垂直设置；
    同一列中的每个所述第一有源区设置有两个第二栅极，两个所述第二栅极分别与该第一有源区交错设置的两条所述字线连接。
  8. 根据权利要求7所述的存储器，其中，每个所述第一有源区上的所述第 一接触区位于两个所述第二栅极之间。
  9. 根据权利要求7所述的存储器，其中，所述第一栅极和所述第二栅极位于同一层。
  10. 根据权利要求7所述的存储器，其中，每个所述第一有源区还包括设置在每个所述第二栅极的背离所述第一接触区一侧的第二接触区，每个所述第二接触区与对应的电荷存储元件连接。
  11. 根据权利要求1-6任一项所述的存储器，其中，所述基底上设置有多个所述控制区以及多个所述存储区，各所述控制区与各所述存储区交替间隔设置。
  12. 一种存储器的制备方法，其中，包括如下步骤：
    提供基底；
    在所述基底上形成控制区以及在所述控制区的两侧分别形成存储区；每个所述存储区包括多个第一有源区，多个所述第一有源区沿第一方向排布成若干行，所述控制区包括沿第一方向排布且与若干行第一有源区一一对应的若干个第二有源区；
    在每个所述第一有源区形成第一接触区，在每个所述第二有源区设置第一栅极以及位于所述第一栅极两侧的第一源漏区和第二源漏区，所述控制区内的各所述第一栅极相互连接以构成一条控制线；
    在每行所述第一有源区上方形成与各所述第一接触区连接的位线，在同一个所述第二有源区内，所述第一源漏区和所述第二源漏区与各自与对应的一条所述位线连接，且与所述第一源漏区连接的所述位线和与所述第二源漏区连接的所述位线位于所述控制线的两侧。
  13. 根据权利要求12所述的存储器的制备方法，其中，在每个所述第二有源区内，在所述第一源漏区上形成第一导电部，将所述第一源漏区通过所述第一导电部与对应的一条所述位线连接。
  14. 根据权利要求13所述的存储器的制备方法，其中，在每个所述第二有源区内，在所述第二源漏区上形成第二导电部，将所述第二源漏区通过所述第二导电部与对应的一条所述位线连接。
  15. 根据权利要求14所述的存储器的制备方法，其中，在同一工艺步骤中形成所述第一导电部和所述第二导电部。
  16. 根据权利要求14所述的存储器的制备方法，其中，在所述第一接触区上形成第三导电部；
    在每个所述存储区的每行所述第一有源区内，将各所述第一接触区上的所述第三导电部与一条所述位线连接。
  17. 根据权利要求16所述的存储器的制备方法，其中，在同一工艺步骤中形成所述第一导电、所述第二导电部以及第三导电部。
  18. 根据权利要求12-17任一项所述的存储器的制备方法，其中，在每个所述存储区内，多个所述第一有源区沿第二方向排布成若干列，任意相邻两行 中的所述第一有源区中，其中一行的所有第一有源区所在列与另一行的所有有源区所在列交替间隔设置，且同一列中的各所述第一有源区与两条字线交错设置，任意相邻列的所述第一有源区中，其中一列第一有源区与另一列第一有源区彼此靠近的端部与一根字线连接；
    在同一列中的每个所述第一有源区形成两个第二栅极，将两个所述第二栅极分别与该第一有源区交错设置的两条所述字线连接。
  19. 根据权利要求18所述的存储器的制备方法，其中，每个所述第一有源区上的所述第一接触区位于与两个所述第二栅极之间。
  20. 根据权利要求18所述的存储器的制备方法，其中，在同一工艺步骤中设置所述第一栅极和所述第二栅极。
  21. 根据权利要求18所述的存储器的制备方法，其中，在每个所述第一有源区还形成位于每个所述第二栅极的背离所述第一接触区一侧的第二接触区，将每个所述第二接触区与对应的电荷存储元件连接。
  22. 根据权利要求12-17任一项所述的存储器的制备方法，其中，在所述基底上形成多个所述控制区以及多个所述存储区，且将各所述控制区与各所述存储区交替间隔排布。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN116648071B (zh) * 2023-07-27 2023-10-20 上海领耐半导体技术有限公司 组对结构非易失性存储器及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359499A (zh) * 2007-07-30 2009-02-04 松下电器产业株式会社 半导体存储装置
WO2009064619A1 (en) * 2007-11-16 2009-05-22 Rambus Inc. Apparatus and method for segmentation of a memory device
CN103366789A (zh) * 2012-04-01 2013-10-23 南亚科技股份有限公司 分层式位线架构的存储器阵列
US20200176455A1 (en) * 2014-08-21 2020-06-04 Samsung Electronics Co., Ltd. Semiconductor devices
CN111640749A (zh) * 2019-11-14 2020-09-08 福建省晋华集成电路有限公司 存储器及其形成方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1114335A (en) * 1910-07-08 1914-10-20 Ingersoll Rand Co Pressure-fluid tool.
DE10117037A1 (de) * 2001-04-05 2002-10-17 Infineon Technologies Ag Speicherzellenarray mit einzeln adressierbaren Speicherzellen und Verfahren zur Herstellung desselben
KR100539232B1 (ko) * 2003-03-15 2005-12-27 삼성전자주식회사 디램 메모리 셀 및 그 제조방법
US7241655B2 (en) * 2004-08-30 2007-07-10 Micron Technology, Inc. Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
US7274060B2 (en) * 2005-06-15 2007-09-25 Infineon Technologies, Ag Memory cell array and method of forming the same
US7851356B2 (en) * 2007-09-28 2010-12-14 Qimonda Ag Integrated circuit and methods of manufacturing the same
KR101434401B1 (ko) * 2007-12-17 2014-08-27 삼성전자주식회사 집적 회로 메모리 장치
KR101529867B1 (ko) * 2008-10-27 2015-06-18 삼성전자주식회사 자기정열 이중 패터닝 기술을 이용한 매립형 게이트 전극 및 소자 분리막을 갖는 반도체 및 그 반도체 제조 방법
KR20120128518A (ko) * 2011-05-17 2012-11-27 에스케이하이닉스 주식회사 반도체 소자의 제조 방법
JP2013038095A (ja) * 2011-08-03 2013-02-21 Elpida Memory Inc 半導体装置の製造方法
US9218881B2 (en) * 2012-10-23 2015-12-22 Sandisk Technologies Inc. Flash memory blocks with extended data retention
KR102266709B1 (ko) * 2014-09-22 2021-06-22 삼성전자주식회사 반도체 메모리 장치
CN108695325B (zh) * 2017-04-07 2019-08-23 联华电子股份有限公司 动态随机存取存储器元件
CN108172577A (zh) * 2017-12-22 2018-06-15 睿力集成电路有限公司 存储器及其制备方法、半导体器件
US11423951B2 (en) * 2020-01-12 2022-08-23 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Semiconductor structure and method for fabricating the same
US11502087B2 (en) * 2020-01-21 2022-11-15 Xia Tai Xin Semiconductor (Qing Dao) Ltd. Semiconductor structure and method for fabricating the same
CN211789013U (zh) * 2020-05-28 2020-10-27 福建省晋华集成电路有限公司 存储器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101359499A (zh) * 2007-07-30 2009-02-04 松下电器产业株式会社 半导体存储装置
WO2009064619A1 (en) * 2007-11-16 2009-05-22 Rambus Inc. Apparatus and method for segmentation of a memory device
CN103366789A (zh) * 2012-04-01 2013-10-23 南亚科技股份有限公司 分层式位线架构的存储器阵列
US20200176455A1 (en) * 2014-08-21 2020-06-04 Samsung Electronics Co., Ltd. Semiconductor devices
CN111640749A (zh) * 2019-11-14 2020-09-08 福建省晋华集成电路有限公司 存储器及其形成方法

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