WO2022011777A1 - 像素电路及显示装置 - Google Patents

像素电路及显示装置 Download PDF

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Publication number
WO2022011777A1
WO2022011777A1 PCT/CN2020/110213 CN2020110213W WO2022011777A1 WO 2022011777 A1 WO2022011777 A1 WO 2022011777A1 CN 2020110213 W CN2020110213 W CN 2020110213W WO 2022011777 A1 WO2022011777 A1 WO 2022011777A1
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Prior art keywords
transistor
electrically connected
signal input
unit
control unit
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Ceased
Application number
PCT/CN2020/110213
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English (en)
French (fr)
Inventor
王选芸
赵晟焕
戴超
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/262,668 priority Critical patent/US20220301504A1/en
Publication of WO2022011777A1 publication Critical patent/WO2022011777A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel circuit and a display device.
  • the realization of the display function of the display device is inseparable from the driving of the pixel circuit.
  • the pixel circuit is an important element for driving the light-emitting unit of the display device to emit light, and the stability and sensitivity of its working performance directly affect the display effect of the display device.
  • the pixel circuit contains multiple transistor elements.
  • the more common transistor types are amorphous silicon (a-Si) thin film transistors, low temperature polysilicon (LTPS) thin film transistors, and metal oxide (Metal Oxide) thin films. transistor.
  • amorphous silicon thin film transistors and low temperature polysilicon thin film transistors are silicon-based thin film transistors, which have the advantages of fast switching speed and large driving current, but are prone to large leakage current; Good uniformity and so on.
  • Two problems are prone to occur in the existing design of the pixel circuit: one is that there is a large leakage current at the control terminal of the driving transistor of the pixel circuit, which causes the light-emitting unit to emit light abnormally and causes the display device to flicker;
  • the transistor for driving the anode to reset is not turned on in time or the turn-on time is too short, which leads to the problem of poor image quality in the dark state of the display device.
  • the present application provides a pixel circuit, including:
  • the light-emitting control unit is arranged between the first power signal input end and the light-emitting unit, and is electrically connected with the control signal input end;
  • a reset unit arranged between the reset signal input end and the light-emitting unit, and electrically connected with the control signal input end;
  • a compensation unit electrically connected to the first scan signal input end
  • an initialization unit electrically connected to the second scan signal input end
  • both the compensation unit and the initialization unit include metal oxide transistors.
  • control terminal of the light-emitting control unit is electrically connected to the control signal input terminal, and under the action of the signal output from the control signal input terminal, the light-emitting control unit is turned on and off. transition between the two states.
  • control terminal of the reset unit is electrically connected to the control signal input terminal, and under the action of the signal output from the control signal input terminal, the reset unit can be turned on or off. transition between states.
  • the reset unit includes a metal oxide transistor.
  • the light emission control unit includes a low temperature polysilicon transistor.
  • the light-emitting control unit includes a first light-emitting control unit and a second light-emitting control unit, and both the first light-emitting control unit and the second light-emitting control unit are electrically connected to the control signal input terminal. sexual connection.
  • both the first light emission control unit and the second light emission control unit include metal oxide transistors.
  • the reset unit includes a low temperature polysilicon transistor.
  • control signal input terminal includes a first control signal input terminal and a second control signal input terminal.
  • the first light-emitting control unit is electrically connected to the first control signal input terminal, and the second light-emitting control unit and the reset unit are both connected to the second control signal input terminal Electrical connection.
  • both the first light emission control unit and the reset unit include metal oxide transistors.
  • the second light emission control unit includes a low temperature polysilicon transistor.
  • both the first light emission control unit and the reset unit are electrically connected to the first control signal input end, and the second light emission control unit and the second control signal input end Electrical connection.
  • both the first light emission control unit and the second light emission control unit include metal oxide transistors.
  • the reset unit includes a low temperature polysilicon transistor.
  • the pixel circuit further includes:
  • a data transmission unit arranged between the data signal input end and the light-emitting control unit
  • a driving unit arranged between the first lighting control unit and the second lighting control unit;
  • the storage unit is arranged between the first power signal input end and the driving unit.
  • the first light-emitting control unit includes a fifth transistor, a gate of the fifth transistor is electrically connected to the control signal input terminal, and a source of the fifth transistor is electrically connected to the a first power signal input end, the drain of the fifth transistor is electrically connected to the first node;
  • the second light-emitting control unit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the control signal input terminal, the source of the sixth transistor is electrically connected to the second node, and the sixth transistor is electrically connected to the second node.
  • the drain is electrically connected to the light-emitting unit;
  • the reset unit includes a seventh transistor, the gate of the seventh transistor is electrically connected to the control signal input terminal, the source of the seventh transistor is electrically connected to the reset signal input terminal, and the seventh transistor The drain is electrically connected to the light-emitting unit;
  • the compensation unit includes a third transistor, the gate of the third transistor is electrically connected to the first scan signal input terminal, the source of the third transistor is electrically connected to the second node, and the third transistor is electrically connected to the second node.
  • the drain of the transistor is electrically connected to the third node;
  • the initialization unit includes a fourth transistor, the gate of the fourth transistor is electrically connected to the second scan signal input terminal, the source of the fourth transistor is electrically connected to the reset signal input terminal, and the fourth transistor is electrically connected to the reset signal input terminal. the drain of the transistor is electrically connected to the third node;
  • the data transmission unit includes a second transistor, the gate of the second transistor is electrically connected to the third scan signal input terminal, the source of the second transistor is electrically connected to the data signal input terminal, and the second transistor is electrically connected to the data signal input terminal. the drain of the transistor is electrically connected to the first node;
  • the driving unit includes a first transistor, a gate of the first transistor is electrically connected to the third node, a source of the first transistor is electrically connected to the first node, and a drain of the first transistor is electrically connected to the third node. a pole is electrically connected to the second node;
  • the storage unit includes a storage capacitor, a first pole of the storage capacitor is electrically connected to the first power signal input terminal, and a second pole of the storage capacitor is electrically connected to the third node.
  • the present application also provides a display device, which includes a pixel circuit, and the pixel circuit includes:
  • the light-emitting control unit is arranged between the first power signal input end and the light-emitting unit, and is electrically connected with the control signal input end;
  • a reset unit arranged between the reset signal input end and the light-emitting unit, and electrically connected with the control signal input end;
  • a compensation unit electrically connected to the first scan signal input end
  • an initialization unit electrically connected to the second scan signal input end
  • both the compensation unit and the initialization unit include metal oxide transistors.
  • the reset unit includes a metal oxide transistor
  • the light emission control unit includes a low temperature polysilicon transistor
  • the reset unit includes a low temperature polysilicon transistor
  • the light emission control unit includes a metal oxide transistor
  • the reset unit of the pixel circuit is directly electrically connected to the control signal input terminal, and the signal output from the control signal input terminal is used to control the opening of the reset unit, so as to increase the reset time of the light-emitting unit , to improve the dark-state image quality of the display device; meanwhile, metal oxide transistors are arranged in the compensation unit and the initialization unit of the pixel circuit, so that the leakage current in the circuit and the screen flash problem caused by the leakage current are significantly improved.
  • FIG. 1 is a schematic structural diagram of a first implementation manner of a pixel circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a second implementation manner of a pixel circuit provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a third implementation manner of a pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a fourth implementation manner of a pixel circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional structure diagram of an organic light emitting diode display device including a low temperature polysilicon transistor and a metal oxide transistor provided by an embodiment of the present application.
  • An embodiment of the present application provides a pixel circuit.
  • a light-emitting control unit and a reset unit of the pixel circuit By directly electrically connecting a light-emitting control unit and a reset unit of the pixel circuit to a control signal input end, and using a signal output from the control signal input end to control the reset unit to turn on, to increase the number of light-emitting units
  • the reset time of the pixel circuit can be shortened to improve the dark-state image quality of the display device; meanwhile, metal oxide transistors are arranged in the compensation unit and the initialization unit of the pixel circuit to improve the leakage current in the circuit and the screen flash problem caused by the leakage current.
  • FIG. 1 is a schematic structural diagram of a first implementation manner of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit includes a light emission control unit 10 , a reset unit 17 , a compensation unit 13 and an initialization unit 14 .
  • the light-emitting control unit 10 is arranged between the first power signal input terminal VDD and the light-emitting unit L, and realizes the control of the electrical conduction state between the first power-supply signal input terminal VDD and the light-emitting unit L by controlling the electrical conduction state between the first power signal input terminal VDD and the light-emitting unit L. Control of the light-emitting time of the light-emitting unit L. For example, when the light-emitting control unit 10 is turned on, current can flow from the first power signal input terminal VDD to the light-emitting unit L, and the light-emitting unit L emits light; otherwise, the light-emitting unit L does not emit light.
  • the light-emitting control unit 10 is electrically connected to the control signal input end 102 , and the light-emitting control unit 10 switches between two states of on and off under the action of the signal output from the control signal input end 102 .
  • the reset unit 17 is disposed between the reset signal input end 103 and the light emitting unit L, and is used to control the electrical conduction state between the reset signal input end 103 and the light emitting unit L.
  • the reset unit 17 When the reset unit 17 is turned on, the reset signal input terminal 103 and the light-emitting unit L are directly electrically connected, and the reset signal sent by the reset signal input terminal 103 is transmitted to the light-emitting unit L, to realize the reset operation of the light-emitting unit L.
  • the light-emitting unit L changes from a light-emitting state to a dark state, if there is some unstable current in the circuit, it will cause abnormal flickering of the light-emitting unit L.
  • by transmitting a reset to the light-emitting unit L signal eliminate the unstable current, and make the light-emitting unit L in a stable dark state, thereby improving the image quality in the dark state.
  • the reset unit 17 is electrically connected to the control signal input end 102 , and the reset unit 17 realizes its on and off states under the action of the signal output from the control signal input end 102 convert. It should be noted that, in the traditional design, the reset unit controls the opening and closing of the reset unit through the scanning signal. At this time, the problem of not being turned on in time or the opening time is too short, resulting in poor image quality in the dark state; in this embodiment, the The reset unit 17 is controlled by the signal output from the control signal input end 102.
  • the control signal input end 102 controls the light emitting control unit 10 to turn off and controls the reset unit 17 to turn on, so as to realize the control of the light emitting unit L.
  • the reset unit 17 is continuously turned on during the entire dark state time of the light emitting unit L, which effectively eliminates dark state flicker and improves the dark state image quality.
  • the compensation unit 13 is electrically connected to the first scan signal input end 104 , and the scan signal output from the first scan signal input end 104 controls the compensation unit 13 to be turned on or off.
  • the initialization unit 14 is electrically connected to the second scan signal input terminal 105 , and the scan signal output from the second scan signal input terminal 105 controls the initialization unit 14 to be turned on or off.
  • Both the compensation unit 13 and the initialization unit 14 include metal oxide transistors. It should be noted that the metal oxide transistor has the advantage of low leakage; in this embodiment, by setting the metal oxide transistor in the compensation unit 13 and the initialization unit 14, the leakage current in the pixel circuit is reduced. The problem is significantly improved, which in turn improves the splash screen problem caused by excessive leakage current.
  • the reset unit 17 includes a metal oxide transistor, so as to improve the leakage current problem of the reset unit 17 itself, and further promote the improvement of the leakage current problem of the entire pixel circuit.
  • the light emission control unit 10 includes a low temperature polysilicon transistor.
  • the metal oxide transistor refers to a transistor using metal oxide as a semiconductor material
  • the metal oxide may be zinc oxide (ZnO), zinc tin oxide (ZTO), Zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO) and other semiconductor materials
  • the metal oxide transistor usually adopts an N-type transistor, That is, it is turned on or turned on under the action of a high level, and turned off or turned off under the action of a low level.
  • the low-temperature polysilicon transistor refers to a transistor using polysilicon as a semiconductor material; the low-temperature polysilicon transistor usually adopts a P-type transistor, that is, it is turned on or turned on under the action of a low level, and is turned on under the action of a high level. Cut off or close under the action.
  • the lighting control unit 10 includes a first lighting control unit 15 and a second lighting control unit 16, the first lighting control unit 15, the second lighting control unit 16 and the reset unit 17 are all connected with the The control signal input end 102 is electrically connected.
  • the first light-emitting control unit 15 and the second light-emitting control unit 16 both include low temperature polysilicon transistors, using P-type transistors; and the reset unit 17 includes metal oxide transistors, using N-type transistors.
  • the pixel circuit further includes a data transmission unit 12 , a driving unit 11 and a storage unit 18 .
  • the data transmission unit 12 is arranged between the data signal input end 101 and the light emission control unit 10, and is used to control the electrical conduction state between the data signal input end 101 and the light emission control unit 10;
  • the data transmission unit 12 is further electrically connected to a third scan signal input terminal 106 , and the third scan signal input terminal 106 outputs a scan signal to control the data transmission unit 12 to be turned on or off.
  • the driving unit 11 is arranged between the first lighting control unit 15 and the second lighting control unit 16 , and is used to control the connection between the first lighting control unit 15 and the second lighting control unit 16 . electrical conduction state.
  • the storage unit 18 is disposed between the first power signal input terminal VDD and the driving unit 11 , and is used for storing the voltage state of the control terminal of the driving unit 11 .
  • the first lighting control unit 15 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the control signal input end 102, and the source of the fifth transistor T5 is electrically connected The first power signal input terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the first node Q1.
  • the fifth transistor T5 is a low temperature polysilicon transistor.
  • the second lighting control unit 16 includes a sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the control signal input end 102, and the source of the sixth transistor T6 is electrically connected At the second node Q2, the drain of the sixth transistor T6 is electrically connected to the light-emitting unit L; the other end of the light-emitting unit L is electrically connected to the second power signal input terminal VSS.
  • the voltage input by the first power signal input terminal VDD is greater than the voltage input by the second power signal input terminal VSS.
  • the sixth transistor T6 is a low temperature polysilicon transistor.
  • the reset unit 17 includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the control signal input end 102, and the source of the seventh transistor T7 is electrically connected to the reset The signal input terminal 103, the drain of the seventh transistor T7 is electrically connected to the light-emitting unit L.
  • the seventh transistor T7 is a metal oxide transistor.
  • the compensation unit 13 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the first scan signal input terminal 104, and the source of the third transistor T3 is electrically connected to the The second node Q2, the drain of the third transistor T3 is electrically connected to the third node Q3.
  • the third transistor T3 is a metal oxide transistor.
  • the initialization unit 14 includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the second scan signal input terminal 105, and the source of the fourth transistor T4 is electrically connected to the The reset signal input terminal 103, the drain of the fourth transistor T4 is electrically connected to the third node Q3.
  • the fourth transistor T4 is a metal oxide transistor.
  • the data transmission unit 12 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the third scan signal input terminal 106, and the source of the second transistor T2 is electrically connected The data signal input terminal 101 and the drain of the second transistor T2 are electrically connected to the first node Q1.
  • the driving unit 11 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the third node Q3, and the source of the first transistor T1 is electrically connected to the first transistor T1 Node Q1, the drain of the first transistor T1 is electrically connected to the second node Q2.
  • the storage unit 18 includes a storage capacitor Cst, a first pole of the storage capacitor Cst is electrically connected to the first power signal input terminal VDD, and a second pole of the storage capacitor Cst is electrically connected to the The third node Q3.
  • the storage capacitor Cst is used to store the threshold voltage of the first transistor T1.
  • the first scan signal input terminal 104, the second scan signal input terminal 105, and the third scan signal input terminal 106 are respectively electrically connected to different scan signal lines;
  • the device will include multiple stages of the pixel circuits provided in this embodiment, the first scan signal input end 104 and the third scan signal input end 106 are respectively electrically connected to the scan signal lines of this level, and the second scan signal The input end 105 is electrically connected to the scanning signal line of the previous stage.
  • the embodiments of the present application improve the dark-state image quality of the display device by directly electrically connecting the reset unit in the pixel circuit to the control signal input end, and use metal oxide in the compensation unit and the initialization unit of the pixel circuit
  • the transistor can be used to improve the leakage current in the circuit and the flickering screen problem caused by the leakage current.
  • FIG. 2 is a schematic structural diagram of a second implementation manner of a pixel circuit provided by an embodiment of the present application.
  • the differences between this embodiment and the embodiment shown in FIG. 1 include but not only include: in this embodiment, the light emission control unit 10 includes a metal oxide transistor.
  • the pixel circuit includes a light emission control unit 10 , a reset unit 17 , a compensation unit 13 and an initialization unit 14 .
  • the light-emitting control unit 10 is arranged between the first power signal input terminal VDD and the light-emitting unit L, and realizes the control of the electrical conduction state between the first power-supply signal input terminal VDD and the light-emitting unit L by controlling the electrical conduction state between the first power signal input terminal VDD and the light-emitting unit L.
  • the light-emitting control unit 10 is electrically connected to the control signal input end 102, and the signal output from the control signal input end 102 controls the light-emitting control unit 10 to be turned on or off.
  • the reset unit 17 is arranged between the reset signal input end 103 and the light-emitting unit L, and is used to control the electrical conduction state between the reset signal input end 103 and the light-emitting unit L; the reset unit 17 is electrically connected to the control signal input end 102 , and the signal output from the control signal input end 102 controls the opening or closing of the reset unit 17 .
  • the compensation unit 13 is electrically connected to the first scan signal input end 104 , and the scan signal output from the first scan signal input end 104 controls the compensation unit 13 to be turned on or off.
  • the initialization unit 14 is electrically connected to the second scan signal input terminal 105 , and the scan signal output from the second scan signal input terminal 105 controls the initialization unit 14 to be turned on or off. Both the compensation unit 13 and the initialization unit 14 include metal oxide transistors.
  • the lighting control unit 10 includes a first lighting control unit 15 and a second lighting control unit 16, the first lighting control unit 15, the second lighting control unit 16 and the reset unit 17 are all connected with the The control signal input end 102 is electrically connected.
  • the first light emission control unit 15 and the second light emission control unit 16 both include metal oxide transistors; the reset unit 17 includes low temperature polysilicon transistors.
  • the pixel circuit further includes a data transmission unit 12 , a driving unit 11 and a storage unit 18 .
  • the data transmission unit 12 is arranged between the data signal input end 101 and the light emission control unit 10, and is used to control the electrical conduction state between the data signal input end 101 and the light emission control unit 10;
  • the data transmission unit 12 is further electrically connected to a third scan signal input terminal 106 , and the third scan signal input terminal 106 outputs a scan signal to control the data transmission unit 12 to be turned on or off.
  • the driving unit 11 is arranged between the first lighting control unit 15 and the second lighting control unit 16 , and is used to control the connection between the first lighting control unit 15 and the second lighting control unit 16 . electrical conduction state.
  • the storage unit 18 is disposed between the first power signal input terminal VDD and the driving unit 11 , and is used for storing the voltage state of the control terminal of the driving unit 11 .
  • the first lighting control unit 15 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the control signal input end 102, and the source of the fifth transistor T5 is electrically connected The first power signal input terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the first node Q1.
  • the fifth transistor T5 is a metal oxide transistor.
  • the second lighting control unit 16 includes a sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the control signal input end 102, and the source of the sixth transistor T6 is electrically connected At the second node Q2, the drain of the sixth transistor T6 is electrically connected to the light-emitting unit L; the other end of the light-emitting unit L is electrically connected to the second power signal input terminal VSS.
  • the sixth transistor T6 is a metal oxide transistor.
  • the reset unit 17 includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the control signal input end 102, and the source of the seventh transistor T7 is electrically connected to the reset The signal input terminal 103, the drain of the seventh transistor T7 is electrically connected to the light-emitting unit L.
  • the seventh transistor T7 is a low temperature polysilicon transistor.
  • the compensation unit 13 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the first scan signal input terminal 104, and the source of the third transistor T3 is electrically connected to the The second node Q2, the drain of the third transistor T3 is electrically connected to the third node Q3.
  • the third transistor T3 is a metal oxide transistor.
  • the initialization unit 14 includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the second scan signal input terminal 105, and the source of the fourth transistor T4 is electrically connected to the The reset signal input terminal 103, the drain of the fourth transistor T4 is electrically connected to the third node Q3.
  • the fourth transistor T4 is a metal oxide transistor.
  • the data transmission unit 12 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the third scan signal input terminal 106, and the source of the second transistor T2 is electrically connected The data signal input terminal 101 and the drain of the second transistor T2 are electrically connected to the first node Q1.
  • the driving unit 11 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the third node Q3, and the source of the first transistor T1 is electrically connected to the first transistor T1 Node Q1, the drain of the first transistor T1 is electrically connected to the second node Q2.
  • the storage unit 18 includes a storage capacitor Cst, a first pole of the storage capacitor Cst is electrically connected to the first power signal input terminal VDD, and a second pole of the storage capacitor Cst is electrically connected to the The third node Q3.
  • the storage capacitor Cst is used to store the threshold voltage of the first transistor T1.
  • the embodiments of the present application improve the dark-state image quality of the display device by directly electrically connecting the reset unit in the pixel circuit to the control signal input end, and use metal oxide in the compensation unit and the initialization unit of the pixel circuit
  • the transistor can be used to improve the leakage current in the circuit and the flickering screen problem caused by the leakage current.
  • FIG. 3 is a schematic structural diagram of a third implementation manner of a pixel circuit provided by an embodiment of the present application.
  • the differences between this embodiment and the embodiment shown in FIG. 1 include but not only include: in this embodiment, the control signal input end 102 includes a first control signal input end 1021 and a second control signal input end 1022 .
  • the pixel circuit includes a light emission control unit 10 , a reset unit 17 , a compensation unit 13 and an initialization unit 14 .
  • the light-emitting control unit 10 is arranged between the first power signal input terminal VDD and the light-emitting unit L, and realizes the control of the electrical conduction state between the first power-supply signal input terminal VDD and the light-emitting unit L by controlling the electrical conduction state between the first power signal input terminal VDD and the light-emitting unit L.
  • the light-emitting control unit 10 is electrically connected to the control signal input end 102, and the signal output from the control signal input end 102 controls the light-emitting control unit 10 to be turned on or off.
  • the reset unit 17 is arranged between the reset signal input end 103 and the light-emitting unit L, and is used to control the electrical conduction state between the reset signal input end 103 and the light-emitting unit L; the reset unit 17 is electrically connected to the control signal input end 102 , and the signal output from the control signal input end 102 controls the opening or closing of the reset unit 17 .
  • the compensation unit 13 is electrically connected to the first scan signal input end 104 , and the scan signal output from the first scan signal input end 104 controls the compensation unit 13 to be turned on or off.
  • the initialization unit 14 is electrically connected to the second scan signal input terminal 105 , and the scan signal output from the second scan signal input terminal 105 controls the initialization unit 14 to be turned on or off. Both the compensation unit 13 and the initialization unit 14 include metal oxide transistors.
  • the lighting control unit 10 includes a first lighting control unit 15 and a second lighting control unit 16 ;
  • the control signal input terminal 102 includes a first control signal input terminal 1021 and a second control signal input terminal 1022 .
  • the first lighting control unit 15 is electrically connected to the first control signal input terminal 1021
  • the second lighting control unit 16 and the reset unit 17 are both electrically connected to the second control signal input terminal 1022 .
  • the first light emission control unit 15 and the reset unit 17 both include metal oxide transistors; the second light emission control unit 16 includes low temperature polysilicon transistors.
  • the first light emission control unit 15 includes a metal oxide transistor, which is beneficial to reduce the leakage current in the pixel circuit.
  • the pixel circuit further includes a data transmission unit 12 , a driving unit 11 and a storage unit 18 .
  • the data transmission unit 12 is arranged between the data signal input end 101 and the light emission control unit 10, and is used to control the electrical conduction state between the data signal input end 101 and the light emission control unit 10;
  • the data transmission unit 12 is further electrically connected to a third scan signal input terminal 106 , and the third scan signal input terminal 106 outputs a scan signal to control the data transmission unit 12 to be turned on or off.
  • the driving unit 11 is arranged between the first lighting control unit 15 and the second lighting control unit 16 , and is used to control the connection between the first lighting control unit 15 and the second lighting control unit 16 . electrical conduction state.
  • the storage unit 18 is disposed between the first power signal input terminal VDD and the driving unit 11 , and is used for storing the voltage state of the control terminal of the driving unit 11 .
  • the first light-emitting control unit 15 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the first control signal input terminal 1021, and the source of the fifth transistor T5 is electrically connected is electrically connected to the first power signal input terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the first node Q1.
  • the fifth transistor T5 is a metal oxide transistor.
  • the second lighting control unit 16 includes a sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the second control signal input terminal 1022, and the source of the sixth transistor T6 is electrically connected.
  • the drain of the sixth transistor T6 is electrically connected to the light-emitting unit L; the other end of the light-emitting unit L is electrically connected to the second power signal input terminal VSS.
  • the sixth transistor T6 is a low temperature polysilicon transistor.
  • the reset unit 17 includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the second control signal input terminal 1022, and the source of the seventh transistor T7 is electrically connected to the second control signal input terminal 1022.
  • the reset signal input terminal 103, the drain of the seventh transistor T7 is electrically connected to the light-emitting unit L.
  • the seventh transistor T7 is a metal oxide transistor.
  • the compensation unit 13 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the first scan signal input terminal 104, and the source of the third transistor T3 is electrically connected to the The second node Q2, the drain of the third transistor T3 is electrically connected to the third node Q3.
  • the third transistor T3 is a metal oxide transistor.
  • the initialization unit 14 includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the second scan signal input terminal 105, and the source of the fourth transistor T4 is electrically connected to the The reset signal input terminal 103, the drain of the fourth transistor T4 is electrically connected to the third node Q3.
  • the fourth transistor T4 is a metal oxide transistor.
  • the data transmission unit 12 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the third scan signal input terminal 106, and the source of the second transistor T2 is electrically connected The data signal input terminal 101 and the drain of the second transistor T2 are electrically connected to the first node Q1.
  • the driving unit 11 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the third node Q3, and the source of the first transistor T1 is electrically connected to the first transistor T1 Node Q1, the drain of the first transistor T1 is electrically connected to the second node Q2.
  • the storage unit 18 includes a storage capacitor Cst, a first pole of the storage capacitor Cst is electrically connected to the first power signal input terminal VDD, and a second pole of the storage capacitor Cst is electrically connected to the The third node Q3.
  • the storage capacitor Cst is used to store the threshold voltage of the first transistor T1.
  • the embodiments of the present application improve the dark-state image quality of the display device by directly electrically connecting the reset unit in the pixel circuit to the second control signal input terminal, and are used in the compensation unit and the initialization unit of the pixel circuit Metal oxide transistors to improve the leakage current in the circuit and the flickering problem caused by the leakage current.
  • FIG. 4 is a schematic structural diagram of a fourth implementation manner of a pixel circuit provided by an embodiment of the present application.
  • the differences between this embodiment and the embodiment shown in FIG. 1 include but not only include: in this embodiment, the control signal input end 102 includes a first control signal input end 1021 and a second control signal input end 1022 .
  • the pixel circuit includes a light emission control unit 10 , a reset unit 17 , a compensation unit 13 and an initialization unit 14 .
  • the light-emitting control unit 10 is arranged between the first power signal input terminal VDD and the light-emitting unit L, and realizes the control of the electrical conduction state between the first power-supply signal input terminal VDD and the light-emitting unit L by controlling the electrical conduction state between the first power signal input terminal VDD and the light-emitting unit L.
  • the light-emitting control unit 10 is electrically connected to the control signal input end 102, and the signal output from the control signal input end 102 controls the light-emitting control unit 10 to be turned on or off.
  • the reset unit 17 is arranged between the reset signal input end 103 and the light-emitting unit L, and is used to control the electrical conduction state between the reset signal input end 103 and the light-emitting unit L; the reset unit 17 is electrically connected to the control signal input end 102 , and the signal output from the control signal input end 102 controls the opening or closing of the reset unit 17 .
  • the compensation unit 13 is electrically connected to the first scan signal input end 104 , and the scan signal output from the first scan signal input end 104 controls the compensation unit 13 to be turned on or off.
  • the initialization unit 14 is electrically connected to the second scan signal input terminal 105 , and the scan signal output from the second scan signal input terminal 105 controls the initialization unit 14 to be turned on or off. Both the compensation unit 13 and the initialization unit 14 include metal oxide transistors.
  • the lighting control unit 10 includes a first lighting control unit 15 and a second lighting control unit 16 ;
  • the control signal input terminal 102 includes a first control signal input terminal 1021 and a second control signal input terminal 1022 .
  • the first lighting control unit 15 and the reset unit 17 are both electrically connected to the first control signal input terminal 1021
  • the second lighting control unit 16 is electrically connected to the second control signal input terminal 1022 .
  • the first light emission control unit 15 and the second light emission control unit 16 both include metal oxide transistors; the reset unit 17 includes low temperature polysilicon transistors.
  • the above setting can ensure that when the first lighting control unit 15 is on, the reset unit 17 is off; otherwise, when the first lighting control unit 15 is off, the reset unit 17 is on, Therefore, the turn-on period of the reset unit 17 always corresponds to the dark state period of the light-emitting unit L.
  • the first light emission control unit 15 and the second light emission control unit 16 both include metal oxide transistors, which is beneficial to reduce the leakage current in the pixel circuit.
  • the pixel circuit further includes a data transmission unit 12 , a driving unit 11 and a storage unit 18 .
  • the data transmission unit 12 is arranged between the data signal input end 101 and the light emission control unit 10, and is used to control the electrical conduction state between the data signal input end 101 and the light emission control unit 10;
  • the data transmission unit 12 is further electrically connected to a third scan signal input terminal 106 , and the third scan signal input terminal 106 outputs a scan signal to control the data transmission unit 12 to be turned on or off.
  • the driving unit 11 is arranged between the first lighting control unit 15 and the second lighting control unit 16 , and is used to control the connection between the first lighting control unit 15 and the second lighting control unit 16 . electrical conduction state.
  • the storage unit 18 is disposed between the first power signal input terminal VDD and the driving unit 11 , and is used for storing the voltage state of the control terminal of the driving unit 11 .
  • the first light-emitting control unit 15 includes a fifth transistor T5, the gate of the fifth transistor T5 is electrically connected to the first control signal input terminal 1021, and the source of the fifth transistor T5 is electrically connected is electrically connected to the first power signal input terminal VDD, and the drain of the fifth transistor T5 is electrically connected to the first node Q1.
  • the fifth transistor T5 is a metal oxide transistor.
  • the second lighting control unit 16 includes a sixth transistor T6, the gate of the sixth transistor T6 is electrically connected to the second control signal input terminal 1022, and the source of the sixth transistor T6 is electrically connected.
  • the drain of the sixth transistor T6 is electrically connected to the light-emitting unit L; the other end of the light-emitting unit L is electrically connected to the second power signal input terminal VSS.
  • the sixth transistor T6 is a metal oxide transistor.
  • the reset unit 17 includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the first control signal input terminal 1021, and the source of the seventh transistor T7 is electrically connected to the first control signal input terminal 1021.
  • the reset signal input terminal 103, the drain of the seventh transistor T7 is electrically connected to the light-emitting unit L.
  • the seventh transistor T7 is a low temperature polysilicon transistor.
  • the compensation unit 13 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the first scan signal input terminal 104, and the source of the third transistor T3 is electrically connected to the The second node Q2, the drain of the third transistor T3 is electrically connected to the third node Q3.
  • the third transistor T3 is a metal oxide transistor.
  • the initialization unit 14 includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the second scan signal input terminal 105, and the source of the fourth transistor T4 is electrically connected to the The reset signal input terminal 103, the drain of the fourth transistor T4 is electrically connected to the third node Q3.
  • the fourth transistor T4 is a metal oxide transistor.
  • the data transmission unit 12 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the third scan signal input terminal 106, and the source of the second transistor T2 is electrically connected The data signal input terminal 101 and the drain of the second transistor T2 are electrically connected to the first node Q1.
  • the driving unit 11 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the third node Q3, and the source of the first transistor T1 is electrically connected to the first transistor T1 Node Q1, the drain of the first transistor T1 is electrically connected to the second node Q2.
  • the storage unit 18 includes a storage capacitor Cst, a first pole of the storage capacitor Cst is electrically connected to the first power signal input terminal VDD, and a second pole of the storage capacitor Cst is electrically connected to the The third node Q3.
  • the storage capacitor Cst is used to store the threshold voltage of the first transistor T1.
  • the pixel circuits provided in the embodiments of the present application may be applied to pixel driving of an organic light emitting diode display device.
  • an organic light emitting diode display device including low temperature polysilicon transistors and metal oxide transistors as shown in FIG.
  • the substrate body 100 may include an insulating material, which may be glass, quartz, ceramic or plastic; the buffer layer 110 is arranged on the substrate body 100, the buffer layer 110 may include, for example, various organic materials and inorganic materials; the first semiconductor layer 120 is arranged on the buffer layer 110, the substrate material of the semiconductor may be N-type or P-type polysilicon semiconductor, and the material of the first gate insulating layer 130 is arranged on the first semiconductor 120, and its material may include silicon nitride or silicon oxide; the material of the first gate 140 may be a metal material Mo, and the first semiconductor 120 may be divided into a source electrode 121, a channel portion 122 and a The drain 123, the first gate 140 and the source 121, the channel 122 and the drain 123 constitute the gate, source and drain of the low temperature polysilicon transistor.
  • the buffer layer 110 is arranged on the substrate body 100, the buffer layer 110 may include, for example, various organic materials and inorganic materials
  • the first semiconductor layer 120 is arranged on the buffer layer 110,
  • the second insulating layer 150 is arranged on the first gate 140, and its material may include silicon nitride or silicon oxide; the second gate 160, the material may be metal Mo, and 161 in the second gate and the first gate 140 constitutes the upper and lower electrodes of the storage capacitor in the pixel circuit.
  • the third insulating layer 170 covers the second gate 160, and its material can include silicon nitride or silicon oxide; the second semiconductor layer 180 is arranged on the third insulating layer 170, and its material is oxide semiconductor, and the second semiconductor layer 180 can be divided into a source electrode 181, a channel 182 and a drain electrode 183; the fourth gate insulating layer 190 is arranged on the second semiconductor 180, and its material can include silicon nitride or silicon oxide; the material of the third gate 200 can be Metal Mo, the third gate 200 and the source 181, channel 182, and drain 183 of the second semiconductor layer form the gate, source, and drain of the metal oxide transistor, wherein 162 in the second gate constitutes a metal In the bottom gate part of the oxide transistor, the fifth insulating layer 210 is arranged on the third gate 200, and its material may include silicon nitride or silicon oxide; the first metal conductive material 220 is arranged on the fifth insulating layer 210, Its materials are gold, silver, copper, lithium, sodium, potassium
  • the first metal conductive material 220 is connected to the gates of the low-temperature polysilicon transistor and the metal oxide transistor through the opening of the insulating layer below.
  • the electrode, the source electrode and the drain electrode are electrically connected;
  • the sixth insulating layer 230 is arranged on the first metal conductive material 220, and its material can be an organic material or an inorganic material and a mixture thereof;
  • the second metal conductive material 240 is arranged on the sixth insulating layer On the layer 230, its materials are gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, zinc and combinations thereof, which are electrically connected to the first metal conductive material 220 through the opening of the sixth insulating layer 230;
  • the seventh The insulating layer 250 is arranged on the second conductive material 240, and its material can be an organic material or an inorganic material and a mixture thereof;
  • the anode 260 is arranged on the seventh insulating layer 250, and its material is a combination of ITO and Ag, and the an
  • the embodiments of the present application improve the dark-state image quality of the display device by directly electrically connecting the reset unit in the pixel circuit to the first control signal input terminal, and are used in the compensation unit and the initialization unit of the pixel circuit Metal oxide transistors to improve the leakage current in the circuit and the flickering problem caused by the leakage current.
  • An embodiment of the present application further provides a display device, where the display device includes the pixel circuit described in any one of the foregoing embodiments. It should be understood that the display device exhibits better dark-state image quality due to the inclusion of the pixel circuit, and compared with the prior art, the leakage current of the internal circuit of the display device and the leakage current caused by the leakage current The splash screen issue has been significantly improved.

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Abstract

一种像素电路及显示装置，像素电路包括发光控制单元（10）、复位单元（17）、补偿单元（13）和初始化单元（14），发光控制单元（10）设置在第一电源信号输入端（VDD）和发光单元（L）之间，复位单元（17）设置在复位信号输入端（103）和发光单元（L）之间，发光控制单元（10）和复位单元（17）共同电性连接控制信号输入端（102），补偿单元（13）和初始化单元（14）均包括金属氧化物晶体管。

Description

像素电路及显示装置
本申请要求于2020年07月14日提交中国专利局、申请号为202010676996.3、发明名称为“像素电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及显示装置。
 背景技术
随着多媒体的发展，显示装置变得越来越重要。相应地，对各种类型的显示装置的要求也越来越高，尤其是智能手机领域，超高频驱动显示、低功耗驱动显示以及低频驱动显示都是现阶段和未来的重要发展方向。
显示装置实现其显示功能离不开像素电路的驱动。像素电路作为驱动显示装置的发光单元进行发光的重要元件，其工作性能的稳定性及灵敏性直接影响显示装置的显示效果。像素电路中包含有多个晶体管元件，较为常见的晶体管类型有非晶硅（a-Si）薄膜晶体管、低温多晶硅（Low Temperature Poly-silicon，LTPS）薄膜晶体管、及金属氧化物（Metal Oxide）薄膜晶体管。其中，非晶硅薄膜晶体管和低温多晶硅薄膜晶体管为硅基薄膜晶体管，具有开关速度快、驱动电流大的优点，但是容易产生较大的漏电流；而金属氧化物薄膜晶体管则具有漏电流小、均一性良好等优点。
 技术问题
像素电路的现有设计中容易出现两个问题：一是像素电路的驱动晶体管的控制端存在较大的漏电流，导致发光单元异常发光而使显示装置出现闪屏的问题；二是像素电路中用于驱动阳极进行复位的晶体管开启不及时或开启时间过短而导致显示装置的暗态画质差的问题。
 技术解决方案
为了解决上述技术问题，本申请提供的解决方案如下：
本申请提供一种像素电路，包括：
发光控制单元，设置在第一电源信号输入端和发光单元之间，并与控制信号输入端电性连接；
复位单元，设置在复位信号输入端和所述发光单元之间，并与所述控制信号输入端电性连接；
补偿单元，与第一扫描信号输入端电性连接；
初始化单元，与第二扫描信号输入端电性连接；
其中，所述补偿单元和所述初始化单元均包括金属氧化物晶体管。
在本申请的像素电路中，所述发光控制单元的控制端电性连接所述控制信号输入端，并在所述控制信号输入端输出的信号作用下，实现所述发光控制单元在开启和关闭两种状态之间转换。
在本申请的像素电路中，所述复位单元的控制端电性连接所述控制信号输入端，并在所述控制信号输入端输出的信号作用下，实现所述复位单元在开启和关闭两种状态之间转换。
在本申请的像素电路中，所述复位单元包括金属氧化物晶体管。
在本申请的像素电路中，所述发光控制单元包括低温多晶硅晶体管。
在本申请的像素电路中，所述发光控制单元包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元和所述第二发光控制单元均与所述控制信号输入端电性连接。
在本申请的像素电路中，所述第一发光控制单元和所述第二发光控制单元均包括金属氧化物晶体管。
在本申请的像素电路中，所述复位单元包括低温多晶硅晶体管。
在本申请的像素电路中，所述控制信号输入端包括第一控制信号输入端和第二控制信号输入端。
在本申请的像素电路中，所述第一发光控制单元与所述第一控制信号输入端电性连接，所述第二发光控制单元和所述复位单元均与所述第二控制信号输入端电性连接。
在本申请的像素电路中，所述第一发光控制单元和所述复位单元均包括金属氧化物晶体管。
在本申请的像素电路中，所述第二发光控制单元包括低温多晶硅晶体管。
在本申请的像素电路中，所述第一发光控制单元和所述复位单元均与所述第一控制信号输入端电性连接，所述第二发光控制单元与所述第二控制信号输入端电性连接。
在本申请的像素电路中，所述第一发光控制单元和所述第二发光控制单元均包括金属氧化物晶体管。
在本申请的像素电路中，所述复位单元包括低温多晶硅晶体管。
在本申请的像素电路中，所述像素电路还包括：
数据传输单元，设置于数据信号输入端和所述发光控制单元之间；
驱动单元，设置于所述第一发光控制单元和所述第二发光控制单元之间；
存储单元，设置于所述第一电源信号输入端和所述驱动单元之间。
根据本申请一实施例，所述第一发光控制单元包括第五晶体管，所述第五晶体管的栅极电性连接所述控制信号输入端，所述第五晶体管的源极电性连接所述第一电源信号输入端，所述第五晶体管的漏极电性连接第一节点；
所述第二发光控制单元包括第六晶体管，所述第六晶体管的栅极电性连接所述控制信号输入端，所述第六晶体管的源极电性连接第二节点，所述第六晶体管的漏极电性连接所述发光单元；
所述复位单元包括第七晶体管，所述第七晶体管的栅极电性连接所述控制信号输入端，所述第七晶体管的源极电性连接所述复位信号输入端，所述第七晶体管的漏极电性连接所述发光单元；
所述补偿单元包括第三晶体管，所述第三晶体管的栅极电性连接所述第一扫描信号输入端，所述第三晶体管的源极电性连接所述第二节点，所述第三晶体管的漏极电性连接第三节点；
所述初始化单元包括第四晶体管，所述第四晶体管的栅极电性连接所述第二扫描信号输入端，所述第四晶体管源极电性连接所述复位信号输入端，所述第四晶体管的漏极电性连接所述第三节点；
所述数据传输单元包括第二晶体管，所述第二晶体管的栅极电性连接第三扫描信号输入端，所述第二晶体管的源极电性连接所述数据信号输入端，所述第二晶体管的漏极电性连接所述第一节点；
所述驱动单元包括第一晶体管，所述第一晶体管的栅极电性连接所述第三节点，所述第一晶体管的源极电性连接所述第一节点，所述第一晶体管的漏极电性连接所述第二节点；
所述存储单元包括存储电容，所述存储电容的第一极电性连接所述第一电源信号输入端，所述存储电容的第二极电性连接所述第三节点。
本申请还提供一种显示装置，其包括像素电路，所述像素电路包括：
发光控制单元，设置在第一电源信号输入端和发光单元之间，并与控制信号输入端电性连接；
复位单元，设置在复位信号输入端和所述发光单元之间，并与所述控制信号输入端电性连接；
补偿单元，与第一扫描信号输入端电性连接；
初始化单元，与第二扫描信号输入端电性连接；
其中，所述补偿单元和所述初始化单元均包括金属氧化物晶体管。
在本申请的显示装置中，所述复位单元包括金属氧化物晶体管，所述发光控制单元包括低温多晶硅晶体管。
在本申请的显示装置中，所述复位单元包括低温多晶硅晶体管，所述发光控制单元包括金属氧化物晶体管。
 有益效果
本申请提供的像素电路及显示装置，通过将所述像素电路的复位单元直接电性连接至控制信号输入端，利用控制信号输入端输出的信号控制复位单元的开启，以增加发光单元的复位时间，改善显示装置的暗态画质；同时，在所述像素电路的补偿单元和初始化单元中设置金属氧化物晶体管，使电路中的漏电流和因漏电流而导致的闪屏问题得到显著改善。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的像素电路的第一种实施方式的结构示意图；
图2是本申请实施例提供的像素电路的第二种实施方式的结构示意图；
图3是本申请实施例提供的像素电路的第三种实施方式的结构示意图；
图4是本申请实施例提供的像素电路的第四种实施方式的结构示意图。
图5是本申请实施例提供的包含低温多晶硅晶体管和金属氧化物晶体管的有机发光二极管显示装置的截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种像素电路，通过将所述像素电路的发光控制单元和复位单元直接电性连接至控制信号输入端，利用控制信号输入端输出的信号控制复位单元开启，以增加发光单元的复位时间，改善显示装置的暗态画质；同时，在所述像素电路的补偿单元和初始化单元中设置金属氧化物晶体管，改善电路中的漏电流及因漏电流而导致的闪屏问题。
根据本申请一实施例，图1是本申请实施例提供的像素电路的第一种实施方式的结构示意图。所述像素电路包括发光控制单元10、复位单元17、补偿单元13和初始化单元14。
所述发光控制单元10设置于第一电源信号输入端VDD和发光单元L之间，通过控制所述第一电源信号输入端VDD和所述发光单元L之间的电性导通状态，实现对所述发光单元L的发光时间的控制。例如，当所述发光控制单元10为开启状态时，电流可由所述第一电源信号输入端VDD流向所述发光单元L，所述发光单元L发光；反之，则所述发光单元L不发光。所述发光控制单元10与控制信号输入端102电性连接，所述发光控制单元10在所述控制信号输入端102输出的信号作用下，实现其在开启和关闭两种状态之间转换。
所述复位单元17设置在复位信号输入端103和所述发光单元L之间，用于控制所述复位信号输入端103和所述发光单元L之间的电性导通状态。当所述复位单元17为开启状态时，所述复位信号输入端103与所述发光单元L之间直接电性导通，由所述复位信号输入端103发出的复位信号传输至所述发光单元L，实现对所述发光单元L的复位操作。应当理解的是，当所述发光单元L由发光状态转变为暗态时，若电路中存在一些不稳定电流，则会导致发光单元L的异常闪烁，此时通过向所述发光单元L传输复位信号，消除不稳定电流，使发光单元L处于稳定暗态，进而改善暗态画质。
进一步地，所述复位单元17与所述控制信号输入端102电性连接，所述复位单元17在所述控制信号输入端102输出的信号作用下，实现其在开启和关闭两种状态之间转换。需要说明的是，传统设计中，复位单元通过扫描信号控制其开启和关闭，此时容易出现开启不及时或开启时间过短的问题，导致暗态画质差；在本实施例中，所述复位单元17通过所述控制信号输入端102输出的信号进行控制，所述控制信号输入端102控制所述发光控制单元10关闭的同时，控制所述复位单元17开启，实现对所述发光单元L的及时复位，同时在所述发光单元L的整个暗态时间内，所述复位单元17持续保持开启状态，有效消除暗态闪烁，改善暗态画质。
所述补偿单元13与第一扫描信号输入端104电性连接，所述第一扫描信号输入端104输出的扫描信号控制所述补偿单元13的开启或关闭。所述初始化单元14与第二扫描信号输入端105电性连接，所述第二扫描信号输入端105输出的扫描信号控制所述初始化单元14的开启或关闭。所述补偿单元13和所述初始化单元14中均包括金属氧化物晶体管。需要说明的是，金属氧化物晶体管具有低漏电的优势；在本实施例中，通过在所述补偿单元13和所述初始化单元14中设置金属氧化物晶体管，使所述像素电路中的漏电流问题得到显著改善，进而改善因漏电流过大而导致的闪屏问题。
可选地，所述复位单元17包括金属氧化物晶体管，以改善所述复位单元17本身的漏电流问题，进一步促进整个所述像素电路的漏电流问题的改善。可选地，所述发光控制单元10包括低温多晶硅晶体管。
需要说明的是，在本申请实施例中，所述金属氧化物晶体管是指采用金属氧化物作为半导体材料的晶体管，所述金属氧化物可以是氧化锌（ZnO）、氧化锌锡（ZTO）、氧化锌铟（ZIO）、氧化铟（InO）、氧化钛（TiO）、氧化铟镓锌（IGZO）、氧化铟锌锡（IZTO）等半导体材料；所述金属氧化物晶体管通常采用N型晶体管，即：在高电平作用下导通或开启，在低电平作用下截止或关闭。在本申请实施例中，所述低温多晶硅晶体管是指采用多晶硅作为半导体材料的晶体管；所述低温多晶硅晶体管通常采用P型晶体管，即：在低电平作用下导通或开启，在高电平作用下截止或关闭。
可选地，所述发光控制单元10包括第一发光控制单元15和第二发光控制单元16，所述第一发光控制单元15、所述第二发光控制单元16和所述复位单元17均与所述控制信号输入端102电性连接。可选地，所述第一发光控制单元15和所述第二发光控制单元16均包括低温多晶硅晶体管，采用P型晶体管；而所述复位单元17包括金属氧化物晶体管，采用N型晶体管。通过上述设置可以保证所述第一发光控制单元15和所述第二发光控制单元16为开启状态时，所述复位单元17为关闭状态；反之，所述第一发光控制单元15和所述第二发光控制单元16为关闭状态时，所述复位单元17为开启状态，进而使所述复位单元17的开启时段始终对应所述发光单元L的暗态阶段。
进一步地，所述像素电路还包括数据传输单元12、驱动单元11和存储单元18。所述数据传输单元12设置于数据信号输入端101和所述发光控制单元10之间，用于控制所述数据信号输入端101和所述发光控制单元10之间的电性导通状态；可选地，所述数据传输单元12还与第三扫描信号输入端106电性连接，所述第三扫描信号输入端106输出扫描信号以控制所述数据传输单元12的开启或关闭。所述驱动单元11设置于所述第一发光控制单元15和所述第二发光控制单元16之间，用于控制所述第一发光控制单元15和所述第二发光控制单元16之间的电性导通状态。所述存储单元18设置于所述第一电源信号输入端VDD和所述驱动单元11之间，用于存储所述驱动单元11的控制端的电压状态。
可选地，所述第一发光控制单元15包括第五晶体管T5，所述第五晶体管T5的栅极电性连接所述控制信号输入端102，所述第五晶体管T5的源极电性连接所述第一电源信号输入端VDD，所述第五晶体管T5的漏极电性连接第一节点Q1。可选地，所述第五晶体管T5为低温多晶硅晶体管。
可选地，所述第二发光控制单元16包括第六晶体管T6，所述第六晶体管T6的栅极电性连接所述控制信号输入端102，所述第六晶体管T6的源极电性连接第二节点Q2，所述第六晶体管T6的漏极电性连接所述发光单元L；所述发光单元L的另一端电性连接第二电源信号输入端VSS。可选地，所述第一电源信号输入端VDD输入的电压大于所述第二电源信号输入端VSS输入的电压。可选地，所述第六晶体管T6为低温多晶硅晶体管。
可选地，所述复位单元17包括第七晶体管T7，所述第七晶体管T7的栅极电性连接所述控制信号输入端102，所述第七晶体管T7的源极电性连接所述复位信号输入端103，所述第七晶体管T7的漏极电性连接所述发光单元L。可选地，所述第七晶体管T7为金属氧化物晶体管。
可选地，所述补偿单元13包括第三晶体管T3，所述第三晶体管T3的栅极电性连接所述第一扫描信号输入端104，所述第三晶体管T3的源极电性连接所述第二节点Q2，所述第三晶体管T3的漏极电性连接第三节点Q3。可选地，所述第三晶体管T3为金属氧化物晶体管。
可选地，所述初始化单元14包括第四晶体管T4，所述第四晶体管T4的栅极电性连接所述第二扫描信号输入端105，所述第四晶体管T4源极电性连接所述复位信号输入端103，所述第四晶体管T4的漏极电性连接所述第三节点Q3。可选地，所述第四晶体管T4为金属氧化物晶体管。
可选地，所述数据传输单元12包括第二晶体管T2，所述第二晶体管T2的栅极电性连接所述第三扫描信号输入端106，所述第二晶体管T2的源极电性连接所述数据信号输入端101，所述第二晶体管T2的漏极电性连接所述第一节点Q1。
可选地，所述驱动单元11包括第一晶体管T1，所述第一晶体管T1的栅极电性连接所述第三节点Q3，所述第一晶体管T1的源极电性连接所述第一节点Q1，所述第一晶体管T1的漏极电性连接所述第二节点Q2。
可选地，所述存储单元18包括存储电容Cst，所述存储电容Cst的第一极电性连接所述第一电源信号输入端VDD，所述存储电容Cst的第二极电性连接所述第三节点Q3。所述存储电容Cst用于存储所述第一晶体管T1的阈值电压。
可选地，所述第一扫描信号输入端104、所述第二扫描信号输入端105和所述第三扫描信号输入端106分别电性连接不同的扫描信号线；应当理解的是，在显示装置中会包含多级本实施例所提供的像素电路，所述第一扫描信号输入端104和所述第三扫描信号输入端106分别电性连接本级扫描信号线，所述第二扫描信号输入端105电性连接前一级扫描信号线。
综上所述，本申请实施例通过将像素电路中的复位单元直接电性连接至控制信号输入端来改善显示装置的暗态画质，并在像素电路的补偿单元和初始化单元中使用金属氧化物晶体管来改善电路中的漏电流及因漏电流而导致的闪屏问题。
根据本申请一实施例，图2是本申请实施例提供的像素电路的第二种实施方式的结构示意图。本实施例与图1所示的实施例的区别包括且不仅包括：在本实施例中，所述发光控制单元10包括金属氧化物晶体管。
具体地，在本实施例中，所述像素电路包括发光控制单元10、复位单元17、补偿单元13和初始化单元14。所述发光控制单元10设置于第一电源信号输入端VDD和发光单元L之间，通过控制所述第一电源信号输入端VDD和所述发光单元L之间的电性导通状态，实现对所述发光单元L的发光时间的控制；所述发光控制单元10与控制信号输入端102电性连接，所述控制信号输入端102输出的信号控制所述发光控制单元10的开启或关闭。所述复位单元17设置在复位信号输入端103和所述发光单元L之间，用于控制所述复位信号输入端103和所述发光单元L之间的电性导通状态；所述复位单元17与所述控制信号输入端102电性连接，所述控制信号输入端102输出的信号控制所述复位单元17的开启或关闭。所述补偿单元13与第一扫描信号输入端104电性连接，所述第一扫描信号输入端104输出的扫描信号控制所述补偿单元13的开启或关闭。所述初始化单元14与第二扫描信号输入端105电性连接，所述第二扫描信号输入端105输出的扫描信号控制所述初始化单元14的开启或关闭。所述补偿单元13和所述初始化单元14中均包括金属氧化物晶体管。
可选地，所述发光控制单元10包括第一发光控制单元15和第二发光控制单元16，所述第一发光控制单元15、所述第二发光控制单元16和所述复位单元17均与所述控制信号输入端102电性连接。所述第一发光控制单元15和所述第二发光控制单元16均包括金属氧化物晶体管；所述复位单元17包括低温多晶硅晶体管。通过上述设置可以保证所述第一发光控制单元15和所述第二发光控制单元16为开启状态时，所述复位单元17为关闭状态；反之，所述第一发光控制单元15和所述第二发光控制单元16为关闭状态时，所述复位单元17为开启状态，进而使所述复位单元17的开启时段始终对应所述发光单元L的暗态阶段。
进一步地，所述像素电路还包括数据传输单元12、驱动单元11和存储单元18。所述数据传输单元12设置于数据信号输入端101和所述发光控制单元10之间，用于控制所述数据信号输入端101和所述发光控制单元10之间的电性导通状态；可选地，所述数据传输单元12还与第三扫描信号输入端106电性连接，所述第三扫描信号输入端106输出扫描信号以控制所述数据传输单元12的开启或关闭。所述驱动单元11设置于所述第一发光控制单元15和所述第二发光控制单元16之间，用于控制所述第一发光控制单元15和所述第二发光控制单元16之间的电性导通状态。所述存储单元18设置于所述第一电源信号输入端VDD和所述驱动单元11之间，用于存储所述驱动单元11的控制端的电压状态。
可选地，所述第一发光控制单元15包括第五晶体管T5，所述第五晶体管T5的栅极电性连接所述控制信号输入端102，所述第五晶体管T5的源极电性连接所述第一电源信号输入端VDD，所述第五晶体管T5的漏极电性连接第一节点Q1。所述第五晶体管T5为金属氧化物晶体管。
可选地，所述第二发光控制单元16包括第六晶体管T6，所述第六晶体管T6的栅极电性连接所述控制信号输入端102，所述第六晶体管T6的源极电性连接第二节点Q2，所述第六晶体管T6的漏极电性连接所述发光单元L；所述发光单元L的另一端电性连接第二电源信号输入端VSS。所述第六晶体管T6为金属氧化物晶体管。
可选地，所述复位单元17包括第七晶体管T7，所述第七晶体管T7的栅极电性连接所述控制信号输入端102，所述第七晶体管T7的源极电性连接所述复位信号输入端103，所述第七晶体管T7的漏极电性连接所述发光单元L。所述第七晶体管T7为低温多晶硅晶体管。
可选地，所述补偿单元13包括第三晶体管T3，所述第三晶体管T3的栅极电性连接所述第一扫描信号输入端104，所述第三晶体管T3的源极电性连接所述第二节点Q2，所述第三晶体管T3的漏极电性连接第三节点Q3。所述第三晶体管T3为金属氧化物晶体管。
可选地，所述初始化单元14包括第四晶体管T4，所述第四晶体管T4的栅极电性连接所述第二扫描信号输入端105，所述第四晶体管T4源极电性连接所述复位信号输入端103，所述第四晶体管T4的漏极电性连接所述第三节点Q3。所述第四晶体管T4为金属氧化物晶体管。
可选地，所述数据传输单元12包括第二晶体管T2，所述第二晶体管T2的栅极电性连接所述第三扫描信号输入端106，所述第二晶体管T2的源极电性连接所述数据信号输入端101，所述第二晶体管T2的漏极电性连接所述第一节点Q1。
可选地，所述驱动单元11包括第一晶体管T1，所述第一晶体管T1的栅极电性连接所述第三节点Q3，所述第一晶体管T1的源极电性连接所述第一节点Q1，所述第一晶体管T1的漏极电性连接所述第二节点Q2。
可选地，所述存储单元18包括存储电容Cst，所述存储电容Cst的第一极电性连接所述第一电源信号输入端VDD，所述存储电容Cst的第二极电性连接所述第三节点Q3。所述存储电容Cst用于存储所述第一晶体管T1的阈值电压。
综上所述，本申请实施例通过将像素电路中的复位单元直接电性连接至控制信号输入端来改善显示装置的暗态画质，并在像素电路的补偿单元和初始化单元中使用金属氧化物晶体管来改善电路中的漏电流及因漏电流而导致的闪屏问题。
根据本申请一实施例，图3是本申请实施例提供的像素电路的第三种实施方式的结构示意图。本实施例与图1所示的实施例的区别包括且不仅包括：在本实施例中，所述控制信号输入端102包括第一控制信号输入端1021和第二控制信号输入端1022。
具体地，在本实施例中，所述像素电路包括发光控制单元10、复位单元17、补偿单元13和初始化单元14。所述发光控制单元10设置于第一电源信号输入端VDD和发光单元L之间，通过控制所述第一电源信号输入端VDD和所述发光单元L之间的电性导通状态，实现对所述发光单元L的发光时间的控制；所述发光控制单元10与控制信号输入端102电性连接，所述控制信号输入端102输出的信号控制所述发光控制单元10的开启或关闭。所述复位单元17设置在复位信号输入端103和所述发光单元L之间，用于控制所述复位信号输入端103和所述发光单元L之间的电性导通状态；所述复位单元17与所述控制信号输入端102电性连接，所述控制信号输入端102输出的信号控制所述复位单元17的开启或关闭。所述补偿单元13与第一扫描信号输入端104电性连接，所述第一扫描信号输入端104输出的扫描信号控制所述补偿单元13的开启或关闭。所述初始化单元14与第二扫描信号输入端105电性连接，所述第二扫描信号输入端105输出的扫描信号控制所述初始化单元14的开启或关闭。所述补偿单元13和所述初始化单元14中均包括金属氧化物晶体管。
可选地，所述发光控制单元10包括第一发光控制单元15和第二发光控制单元16；所述控制信号输入端102包括第一控制信号输入端1021和第二控制信号输入端1022。所述第一发光控制单元15与所述第一控制信号输入端1021电性连接，所述第二发光控制单元16和所述复位单元17均与所述第二控制信号输入端1022电性连接。所述第一发光控制单元15和所述复位单元17均包括金属氧化物晶体管；所述第二发光控制单元16包括低温多晶硅晶体管。通过上述设置可以保证所述第二发光控制单元16为开启状态时，所述复位单元17为关闭状态；反之，所述第二发光控制单元16为关闭状态时，所述复位单元17为开启状态，进而使所述复位单元17的开启时段始终对应所述发光单元L的暗态阶段。并且所述第一发光控制单元15包括金属氧化物晶体管，有利于减小像素电路中的漏电流。
进一步地，所述像素电路还包括数据传输单元12、驱动单元11和存储单元18。所述数据传输单元12设置于数据信号输入端101和所述发光控制单元10之间，用于控制所述数据信号输入端101和所述发光控制单元10之间的电性导通状态；可选地，所述数据传输单元12还与第三扫描信号输入端106电性连接，所述第三扫描信号输入端106输出扫描信号以控制所述数据传输单元12的开启或关闭。所述驱动单元11设置于所述第一发光控制单元15和所述第二发光控制单元16之间，用于控制所述第一发光控制单元15和所述第二发光控制单元16之间的电性导通状态。所述存储单元18设置于所述第一电源信号输入端VDD和所述驱动单元11之间，用于存储所述驱动单元11的控制端的电压状态。
可选地，所述第一发光控制单元15包括第五晶体管T5，所述第五晶体管T5的栅极电性连接所述第一控制信号输入端1021，所述第五晶体管T5的源极电性连接所述第一电源信号输入端VDD，所述第五晶体管T5的漏极电性连接第一节点Q1。所述第五晶体管T5为金属氧化物晶体管。
可选地，所述第二发光控制单元16包括第六晶体管T6，所述第六晶体管T6的栅极电性连接所述第二控制信号输入端1022，所述第六晶体管T6的源极电性连接第二节点Q2，所述第六晶体管T6的漏极电性连接所述发光单元L；所述发光单元L的另一端电性连接第二电源信号输入端VSS。所述第六晶体管T6为低温多晶硅晶体管。
可选地，所述复位单元17包括第七晶体管T7，所述第七晶体管T7的栅极电性连接所述第二控制信号输入端1022，所述第七晶体管T7的源极电性连接所述复位信号输入端103，所述第七晶体管T7的漏极电性连接所述发光单元L。所述第七晶体管T7为金属氧化物晶体管。
可选地，所述补偿单元13包括第三晶体管T3，所述第三晶体管T3的栅极电性连接所述第一扫描信号输入端104，所述第三晶体管T3的源极电性连接所述第二节点Q2，所述第三晶体管T3的漏极电性连接第三节点Q3。所述第三晶体管T3为金属氧化物晶体管。
可选地，所述初始化单元14包括第四晶体管T4，所述第四晶体管T4的栅极电性连接所述第二扫描信号输入端105，所述第四晶体管T4源极电性连接所述复位信号输入端103，所述第四晶体管T4的漏极电性连接所述第三节点Q3。所述第四晶体管T4为金属氧化物晶体管。
可选地，所述数据传输单元12包括第二晶体管T2，所述第二晶体管T2的栅极电性连接所述第三扫描信号输入端106，所述第二晶体管T2的源极电性连接所述数据信号输入端101，所述第二晶体管T2的漏极电性连接所述第一节点Q1。
可选地，所述驱动单元11包括第一晶体管T1，所述第一晶体管T1的栅极电性连接所述第三节点Q3，所述第一晶体管T1的源极电性连接所述第一节点Q1，所述第一晶体管T1的漏极电性连接所述第二节点Q2。
可选地，所述存储单元18包括存储电容Cst，所述存储电容Cst的第一极电性连接所述第一电源信号输入端VDD，所述存储电容Cst的第二极电性连接所述第三节点Q3。所述存储电容Cst用于存储所述第一晶体管T1的阈值电压。
综上所述，本申请实施例通过将像素电路中的复位单元直接电性连接至第二控制信号输入端来改善显示装置的暗态画质，并在像素电路的补偿单元和初始化单元中使用金属氧化物晶体管来改善电路中的漏电流及因漏电流而导致的闪屏问题。
根据本申请一实施例，图4是本申请实施例提供的像素电路的第四种实施方式的结构示意图。本实施例与图1所示的实施例的区别包括且不仅包括：在本实施例中，所述控制信号输入端102包括第一控制信号输入端1021和第二控制信号输入端1022。
具体地，在本实施例中，所述像素电路包括发光控制单元10、复位单元17、补偿单元13和初始化单元14。所述发光控制单元10设置于第一电源信号输入端VDD和发光单元L之间，通过控制所述第一电源信号输入端VDD和所述发光单元L之间的电性导通状态，实现对所述发光单元L的发光时间的控制；所述发光控制单元10与控制信号输入端102电性连接，所述控制信号输入端102输出的信号控制所述发光控制单元10的开启或关闭。所述复位单元17设置在复位信号输入端103和所述发光单元L之间，用于控制所述复位信号输入端103和所述发光单元L之间的电性导通状态；所述复位单元17与所述控制信号输入端102电性连接，所述控制信号输入端102输出的信号控制所述复位单元17的开启或关闭。所述补偿单元13与第一扫描信号输入端104电性连接，所述第一扫描信号输入端104输出的扫描信号控制所述补偿单元13的开启或关闭。所述初始化单元14与第二扫描信号输入端105电性连接，所述第二扫描信号输入端105输出的扫描信号控制所述初始化单元14的开启或关闭。所述补偿单元13和所述初始化单元14中均包括金属氧化物晶体管。
可选地，所述发光控制单元10包括第一发光控制单元15和第二发光控制单元16；所述控制信号输入端102包括第一控制信号输入端1021和第二控制信号输入端1022。所述第一发光控制单元15和所述复位单元17均与所述第一控制信号输入端1021电性连接，所述第二发光控制单元16与所述第二控制信号输入端1022电性连接。所述第一发光控制单元15和所述第二发光控制单元16均包括金属氧化物晶体管；所述复位单元17包括低温多晶硅晶体管。通过上述设置可以保证述第一发光控制单元15为开启状态时，所述复位单元17为关闭状态；反之，所述第一发光控制单元15为关闭状态时，所述复位单元17为开启状态，进而使所述复位单元17的开启时段始终对应所述发光单元L的暗态阶段。并且所述第一发光控制单元15和所述第二发光控制单元16均包括金属氧化物晶体管，有利于减小像素电路中的漏电流。
进一步地，所述像素电路还包括数据传输单元12、驱动单元11和存储单元18。所述数据传输单元12设置于数据信号输入端101和所述发光控制单元10之间，用于控制所述数据信号输入端101和所述发光控制单元10之间的电性导通状态；可选地，所述数据传输单元12还与第三扫描信号输入端106电性连接，所述第三扫描信号输入端106输出扫描信号以控制所述数据传输单元12的开启或关闭。所述驱动单元11设置于所述第一发光控制单元15和所述第二发光控制单元16之间，用于控制所述第一发光控制单元15和所述第二发光控制单元16之间的电性导通状态。所述存储单元18设置于所述第一电源信号输入端VDD和所述驱动单元11之间，用于存储所述驱动单元11的控制端的电压状态。
可选地，所述第一发光控制单元15包括第五晶体管T5，所述第五晶体管T5的栅极电性连接所述第一控制信号输入端1021，所述第五晶体管T5的源极电性连接所述第一电源信号输入端VDD，所述第五晶体管T5的漏极电性连接第一节点Q1。所述第五晶体管T5为金属氧化物晶体管。
可选地，所述第二发光控制单元16包括第六晶体管T6，所述第六晶体管T6的栅极电性连接所述第二控制信号输入端1022，所述第六晶体管T6的源极电性连接第二节点Q2，所述第六晶体管T6的漏极电性连接所述发光单元L；所述发光单元L的另一端电性连接第二电源信号输入端VSS。所述第六晶体管T6为金属氧化物晶体管。
可选地，所述复位单元17包括第七晶体管T7，所述第七晶体管T7的栅极电性连接所述第一控制信号输入端1021，所述第七晶体管T7的源极电性连接所述复位信号输入端103，所述第七晶体管T7的漏极电性连接所述发光单元L。所述第七晶体管T7为低温多晶硅晶体管。
可选地，所述补偿单元13包括第三晶体管T3，所述第三晶体管T3的栅极电性连接所述第一扫描信号输入端104，所述第三晶体管T3的源极电性连接所述第二节点Q2，所述第三晶体管T3的漏极电性连接第三节点Q3。所述第三晶体管T3为金属氧化物晶体管。
可选地，所述初始化单元14包括第四晶体管T4，所述第四晶体管T4的栅极电性连接所述第二扫描信号输入端105，所述第四晶体管T4源极电性连接所述复位信号输入端103，所述第四晶体管T4的漏极电性连接所述第三节点Q3。所述第四晶体管T4为金属氧化物晶体管。
可选地，所述数据传输单元12包括第二晶体管T2，所述第二晶体管T2的栅极电性连接所述第三扫描信号输入端106，所述第二晶体管T2的源极电性连接所述数据信号输入端101，所述第二晶体管T2的漏极电性连接所述第一节点Q1。
可选地，所述驱动单元11包括第一晶体管T1，所述第一晶体管T1的栅极电性连接所述第三节点Q3，所述第一晶体管T1的源极电性连接所述第一节点Q1，所述第一晶体管T1的漏极电性连接所述第二节点Q2。
可选地，所述存储单元18包括存储电容Cst，所述存储电容Cst的第一极电性连接所述第一电源信号输入端VDD，所述存储电容Cst的第二极电性连接所述第三节点Q3。所述存储电容Cst用于存储所述第一晶体管T1的阈值电压。
可选地，本申请实施例提供的像素电路可应用于有机发光二极管显示装置的像素驱动中。如图5所示的包含低温多晶硅晶体管和金属氧化物晶体管的有机发光二极管显示装置截面图中，基板主体100可包括绝缘材料，可以为玻璃、石英、陶瓷或者塑料；缓冲层110布置在基板主体100上，缓冲层110可包括例如多种有机材料与无机材料；第一半导体层120布置在缓冲层110上，半导体的衬底材料可以为N型或者P型多晶硅半导体，第一栅绝缘层材料130布置在第一半导体120之上，其材质可以为包括氮化硅或者氧化硅；第一栅极140材料可以为金属材料Mo，第一半导体120可以划分为源极121、沟道部分122和漏极123，第一栅极140与源极121，沟道122及漏极123构成低温多晶硅晶体管的栅极、源极、漏极。第二绝缘层150布置在第一栅极140上，其材质可以为包括氮化硅或者氧化硅；第二栅极160，材料可以为金属Mo，第二栅极中的161与第一栅极140构成像素电路中存储电容的上下电极。第三绝缘层170覆盖在第二栅极160上，其材质可以为包括氮化硅或者氧化硅；第二半导体层180布置在第三绝缘层170上，其材质氧化物半导体，第二半导体层180可以划分为源极181、沟道182和漏极183；第四栅绝缘层190布置在第二半导体180上，其材质可以为包括氮化硅或者氧化硅；第三栅极200材料可以为金属Mo，第三栅极200与第二半导体层的源极181，沟道182，漏极183形成金属氧化物晶体管的栅极、源极、漏极，其中第二栅极中的162构成金属氧化物晶体管中的底栅部分，第五绝缘层210布置在第三栅极200上，其材质可以为包括氮化硅或者氧化硅；第一金属导电材料220布置在第五绝缘层210上，其材料采用金、银、铜、锂、钠、钾、镁、铝、锌及其组合，第一金属导电材料220通过对下方绝缘层的开孔，与低温多晶硅晶体管和金属氧化物晶体管的栅极、源极、漏极电连接；第六绝缘层230布置在第一金属导电材料220上，其材质可以为采用有机材料或者无机材料及其混合物；第二金属导电材料240布置在第六绝缘层230上，其材料采用金、银、铜、锂、钠、钾、镁、铝、锌及其组合，其通过第六绝缘层230的开孔与第一金属导电材料220电连接；第七绝缘层250布置在第二导电材料240上，其材质可以为采用有机材料或者无机材料及其混合物；阳极260布置在第七绝缘层250上，其材质为ITO与Ag的组合，阳极260通过下方第七绝缘层250的开孔与第二金属导电材料240电连接；像素定义层280布置在阳极260上，像素定义层280的开孔形状与显示装置子像素的图案一致，有机发光材料270通过像素定义层280的开孔与下方的阳极260接触，最上方为封装层290，其材质包括有机材料与无机材料的组合。
综上所述，本申请实施例通过将像素电路中的复位单元直接电性连接至第一控制信号输入端来改善显示装置的暗态画质，并在像素电路的补偿单元和初始化单元中使用金属氧化物晶体管来改善电路中的漏电流及因漏电流而导致的闪屏问题。
本申请实施例还提供一种显示装置，所述显示装置包括上述任一实施例所述像素电路。应当理解的是，所述显示装置因包含所述像素电路而表现出较好的暗态画质，并且相较于现有技术，所述显示装置的内部电路的漏电流和因漏电流而导致的闪屏问题得到显著改善。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素电路，其包括：
    发光控制单元，设置在第一电源信号输入端和发光单元之间，并与控制信号输入端电性连接；
    复位单元，设置在复位信号输入端和所述发光单元之间，并与所述控制信号输入端电性连接；
    补偿单元，与第一扫描信号输入端电性连接；
    初始化单元，与第二扫描信号输入端电性连接；
    其中，所述补偿单元和所述初始化单元均包括金属氧化物晶体管。
  2. 根据权利要求1所述的像素电路，其中，所述发光控制单元的控制端电性连接所述控制信号输入端，并在所述控制信号输入端输出的信号作用下，实现所述发光控制单元在开启和关闭两种状态之间转换。
  3. 根据权利要求1所述的像素电路，其中，所述复位单元的控制端电性连接所述控制信号输入端，并在所述控制信号输入端输出的信号作用下，实现所述复位单元在开启和关闭两种状态之间转换。
  4. 根据权利要求1所述的像素电路，其中，所述复位单元包括金属氧化物晶体管。
  5. 根据权利要求4所述的像素电路，其中，所述发光控制单元包括低温多晶硅晶体管。
  6. 根据权利要求1所述的像素电路，其中，所述发光控制单元包括第一发光控制单元和第二发光控制单元，所述第一发光控制单元和所述第二发光控制单元均与所述控制信号输入端电性连接。
  7. 根据权利要求6所述的像素电路，其中，所述第一发光控制单元和所述第二发光控制单元均包括金属氧化物晶体管。
  8. 根据权利要求7所述的像素电路，其中，所述复位单元包括低温多晶硅晶体管。
  9. 根据权利要求6所述的像素电路，其中，所述控制信号输入端包括第一控制信号输入端和第二控制信号输入端。
  10. 根据权利要求9所述的像素电路，其中，所述第一发光控制单元与所述第一控制信号输入端电性连接，所述第二发光控制单元和所述复位单元均与所述第二控制信号输入端电性连接。
  11. 根据权利要求10所述的像素电路，其中，所述第一发光控制单元和所述复位单元均包括金属氧化物晶体管。
  12. 根据权利要求11所述的像素电路，其中，所述第二发光控制单元包括低温多晶硅晶体管。
  13. 根据权利要求9所述的像素电路，其中，所述第一发光控制单元和所述复位单元均与所述第一控制信号输入端电性连接，所述第二发光控制单元与所述第二控制信号输入端电性连接。
  14. 根据权利要求13所述的像素电路，其中，所述第一发光控制单元和所述第二发光控制单元均包括金属氧化物晶体管。
  15. 根据权利要求14所述的像素电路，其中，所述复位单元包括低温多晶硅晶体管。
  16. 根据权利要求6所述的像素电路，其还包括：
    数据传输单元，设置于数据信号输入端和所述发光控制单元之间；
    驱动单元，设置于所述第一发光控制单元和所述第二发光控制单元之间；
    存储单元，设置于所述第一电源信号输入端和所述驱动单元之间。
  17. 根据权利要求16所述的像素电路，其中，
    所述第一发光控制单元包括第五晶体管，所述第五晶体管的栅极电性连接所述控制信号输入端，所述第五晶体管的源极电性连接所述第一电源信号输入端，所述第五晶体管的漏极电性连接第一节点；
    所述第二发光控制单元包括第六晶体管，所述第六晶体管的栅极电性连接所述控制信号输入端，所述第六晶体管的源极电性连接第二节点，所述第六晶体管的漏极电性连接所述发光单元；
    所述复位单元包括第七晶体管，所述第七晶体管的栅极电性连接所述控制信号输入端，所述第七晶体管的源极电性连接所述复位信号输入端，所述第七晶体管的漏极电性连接所述发光单元；
    所述补偿单元包括第三晶体管，所述第三晶体管的栅极电性连接所述第一扫描信号输入端，所述第三晶体管的源极电性连接所述第二节点，所述第三晶体管的漏极电性连接第三节点；
    所述初始化单元包括第四晶体管，所述第四晶体管的栅极电性连接所述第二扫描信号输入端，所述第四晶体管源极电性连接所述复位信号输入端，所述第四晶体管的漏极电性连接所述第三节点；
    所述数据传输单元包括第二晶体管，所述第二晶体管的栅极电性连接第三扫描信号输入端，所述第二晶体管的源极电性连接所述数据信号输入端，所述第二晶体管的漏极电性连接所述第一节点；
    所述驱动单元包括第一晶体管，所述第一晶体管的栅极电性连接所述第三节点，所述第一晶体管的源极电性连接所述第一节点，所述第一晶体管的漏极电性连接所述第二节点；
    所述存储单元包括存储电容，所述存储电容的第一极电性连接所述第一电源信号输入端，所述存储电容的第二极电性连接所述第三节点。
  18. 一种显示装置，其包括像素电路，所述像素电路包括：
    发光控制单元，设置在第一电源信号输入端和发光单元之间，并与控制信号输入端电性连接；
    复位单元，设置在复位信号输入端和所述发光单元之间，并与所述控制信号输入端电性连接；
    补偿单元，与第一扫描信号输入端电性连接；
    初始化单元，与第二扫描信号输入端电性连接；
    其中，所述补偿单元和所述初始化单元均包括金属氧化物晶体管。
  19. 根据权利要求18所述的显示装置，其中，所述复位单元包括金属氧化物晶体管，所述发光控制单元包括低温多晶硅晶体管。
  20. 根据权利要求18所述的显示装置，其中，所述复位单元包括低温多晶硅晶体管，所述发光控制单元包括金属氧化物晶体管。
PCT/CN2020/110213 2020-07-14 2020-08-20 像素电路及显示装置 Ceased WO2022011777A1 (zh)

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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11974463B2 (en) * 2020-10-19 2024-04-30 Chengdu Boe Optoelectronics Technology Co., Ltd. Array substrate and display apparatus
CN112289269A (zh) * 2020-10-30 2021-01-29 合肥维信诺科技有限公司 一种像素电路及其控制方法和显示面板
CN112397031B (zh) * 2020-11-16 2022-02-22 武汉华星光电半导体显示技术有限公司 像素驱动电路和显示面板
CN112397030A (zh) * 2020-11-17 2021-02-23 武汉华星光电半导体显示技术有限公司 像素驱动电路及oled显示面板
CN112397029B (zh) * 2020-11-17 2022-04-08 武汉华星光电半导体显示技术有限公司 像素驱动电路及ltpo显示面板
CN112397025A (zh) * 2020-11-24 2021-02-23 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN112365849A (zh) * 2020-12-03 2021-02-12 武汉华星光电半导体显示技术有限公司 一种像素驱动电路及显示面板
CN114974122A (zh) * 2021-02-26 2022-08-30 华为技术有限公司 像素驱动电路、阵列基板及显示器
GB2609816A (en) 2021-03-19 2023-02-15 Boe Technology Group Co Ltd Light-emitting substrate and display apparatus
WO2022193300A1 (zh) 2021-03-19 2022-09-22 京东方科技集团股份有限公司 发光基板和显示装置
CN113066434B (zh) * 2021-03-24 2023-07-18 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
WO2022241798A1 (zh) 2021-05-21 2022-11-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN113707089B (zh) * 2021-09-02 2023-06-23 合肥维信诺科技有限公司 一种像素驱动电路、显示面板及显示装置
CN114038384B (zh) * 2021-11-30 2024-04-02 厦门天马显示科技有限公司 显示面板及显示装置
KR102884569B1 (ko) * 2021-12-09 2025-11-12 삼성디스플레이 주식회사 화소 회로 및 이를 포함하는 표시 장치
CN117461075A (zh) * 2022-05-26 2024-01-26 京东方科技集团股份有限公司 一种像素电路、其驱动方法及显示装置
CN115331634B (zh) * 2022-08-30 2025-04-11 京东方科技集团股份有限公司 像素电路、像素驱动方法、显示基板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140139502A1 (en) * 2012-11-20 2014-05-22 Samsung Display Co., Ltd. Pixel, display device including the same, and driving method thereof
CN109064972A (zh) * 2018-08-30 2018-12-21 云谷（固安）科技有限公司 像素结构、驱动方法、像素电路和显示面板
CN109801596A (zh) * 2019-01-31 2019-05-24 京东方科技集团股份有限公司 一种像素电路、显示面板及其驱动方法
CN110264946A (zh) * 2019-05-21 2019-09-20 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110322842A (zh) * 2019-05-21 2019-10-11 合肥维信诺科技有限公司 一种像素驱动电路及显示装置
CN110599964A (zh) * 2019-06-26 2019-12-20 合肥维信诺科技有限公司 像素驱动电路及显示装置
CN110782838A (zh) * 2019-11-13 2020-02-11 京东方科技集团股份有限公司 像素驱动电路、驱动方法、显示面板及显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103927984B (zh) * 2014-04-01 2017-07-28 深圳市华星光电技术有限公司 一种oled显示器的像素驱动电路及其驱动方法
KR102566477B1 (ko) * 2014-12-31 2023-08-10 엘지디스플레이 주식회사 다수의 타입들의 박막 트랜지스터들을 갖는 디스플레이 백플레인
KR102439225B1 (ko) * 2015-08-31 2022-09-01 엘지디스플레이 주식회사 유기 발광 표시장치와 그 구동 장치 및 방법
CN106847183B (zh) * 2015-12-03 2020-04-24 群创光电股份有限公司 具有混合晶体管的主动矩阵有机发光二极管的驱动电路
KR102514174B1 (ko) * 2015-12-15 2023-03-28 엘지디스플레이 주식회사 유기 발광 표시장치와 그 구동 장치
CN105679236B (zh) * 2016-04-06 2018-11-30 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板和显示装置
CN106875894B (zh) * 2017-03-13 2019-01-18 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN106910468B (zh) * 2017-04-28 2019-05-10 上海天马有机发光显示技术有限公司 显示面板、显示装置及像素电路的驱动方法
CN107358918B (zh) * 2017-08-25 2023-11-21 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN107591124B (zh) * 2017-09-29 2019-10-01 上海天马微电子有限公司 像素补偿电路、有机发光显示面板及有机发光显示装置
CN208335702U (zh) * 2018-05-14 2019-01-04 北京京东方技术开发有限公司 显示面板及显示装置
CN108399895B (zh) * 2018-05-31 2024-02-13 京东方科技集团股份有限公司 显示面板及其驱动方法、显示装置
KR102620228B1 (ko) * 2018-08-16 2024-01-02 삼성디스플레이 주식회사 표시 장치
CN110910815A (zh) * 2018-09-14 2020-03-24 群创光电股份有限公司 电子装置
US11145241B2 (en) * 2018-09-14 2021-10-12 Innolux Corporation Electronic device and pixel thereof
CN109285500B (zh) * 2018-12-05 2020-11-13 武汉天马微电子有限公司 像素驱动电路和有机发光显示装置
KR102639309B1 (ko) * 2019-06-12 2024-02-23 삼성디스플레이 주식회사 표시 장치
CN212276787U (zh) * 2020-07-14 2021-01-01 武汉华星光电半导体显示技术有限公司 像素电路及显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140139502A1 (en) * 2012-11-20 2014-05-22 Samsung Display Co., Ltd. Pixel, display device including the same, and driving method thereof
CN109064972A (zh) * 2018-08-30 2018-12-21 云谷（固安）科技有限公司 像素结构、驱动方法、像素电路和显示面板
CN109801596A (zh) * 2019-01-31 2019-05-24 京东方科技集团股份有限公司 一种像素电路、显示面板及其驱动方法
CN110264946A (zh) * 2019-05-21 2019-09-20 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110322842A (zh) * 2019-05-21 2019-10-11 合肥维信诺科技有限公司 一种像素驱动电路及显示装置
CN110599964A (zh) * 2019-06-26 2019-12-20 合肥维信诺科技有限公司 像素驱动电路及显示装置
CN110782838A (zh) * 2019-11-13 2020-02-11 京东方科技集团股份有限公司 像素驱动电路、驱动方法、显示面板及显示装置

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