WO2023155917A1 - 双栅晶体管、像素驱动电路和显示面板 - Google Patents

双栅晶体管、像素驱动电路和显示面板 Download PDF

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Publication number
WO2023155917A1
WO2023155917A1 PCT/CN2023/077357 CN2023077357W WO2023155917A1 WO 2023155917 A1 WO2023155917 A1 WO 2023155917A1 CN 2023077357 W CN2023077357 W CN 2023077357W WO 2023155917 A1 WO2023155917 A1 WO 2023155917A1
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WIPO (PCT)
Prior art keywords
transistor
gate
pole
double
insulating layer
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PCT/CN2023/077357
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English (en)
French (fr)
Inventor
周雷
陈禧
徐苗
李洪濛
梁苑茹
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广州新视界光电科技有限公司
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Publication of WO2023155917A1 publication Critical patent/WO2023155917A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance

Definitions

  • the embodiments of the present application relate to the technical field of display, for example, to a double-gate transistor, a pixel driving circuit and a display panel.
  • a related display panel generally uses a pixel driving circuit to drive a light-emitting device to emit light, so as to realize the display of the display panel.
  • the pixel driving circuit generally includes a thin film transistor (Thin Film Transistor, TFT), and the thin film transistor is configured to provide a driving current for a light emitting device.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided in the related art. As shown in FIG. 1, the pixel driving circuit includes a switching transistor M1, a driving transistor M2 and a storage capacitor Cst. The gate of the switching transistor M1 is connected to the scanning signal terminal SCAN, and the first pole of the switching transistor M1 is connected to the data signal terminal data.
  • the second pole of the switching transistor M1 is connected to the gate of the driving transistor M2 and the first pole of the storage capacitor Cst
  • the first pole of the driving transistor M2 is connected to the second pole of the storage capacitor Cst and the first power supply terminal VDD
  • the driving transistor M2 The second pole of the light-emitting device is connected to the anode of the organic light-emitting diode (Organic Light-Emitting Diode, OLED), and the cathode of the light-emitting device OLED is connected to the second power supply terminal VSS.
  • FIG. 1 exemplarily shows that the switching transistor M1 and the driving transistor M2 are P-type transistors.
  • the switching transistor M1 When the scanning signal provided by the scanning signal terminal SCAN is at a low level, the switching transistor M1 is turned on, and the data voltage provided by the data signal terminal data is transmitted to the gate of the driving transistor M2 through the switching transistor M1, so that the driving transistor M2 is connected according to the data voltage and the first voltage.
  • a first voltage provided by a power supply terminal VDD generates a driving current to drive the light emitting device OLED to emit light.
  • different TFTs have different functions, so that different TFTs have different characteristic requirements.
  • the switching transistor M1 mainly has a pixel switching function, so the switching transistor M1 has a high requirement on the response rate.
  • the driving transistor M2 is mainly configured to drive the light-emitting device OLED to emit light, so the driving transistor M2 has a high requirement on grayscale control capability.
  • the driving transistor M2 has higher requirements on grayscale control capability, so that the display panel can display images with more grayscales.
  • FIG. 2 is a schematic structural diagram of a transistor provided in the related art. As shown in FIG. 2, the transistor is an indium gallium zinc oxide (IGZO) double-gate transistor.
  • the double-gate transistor includes a substrate 00, a bottom gate BG disposed on the substrate 00, and a bottom gate BG disposed on the substrate away from the substrate.
  • IGZO indium gallium zinc oxide
  • the bottom gate insulating layer BGI on the side of 00 is disposed on the IGZO semiconductor layer 01 on the side of the bottom gate insulating layer BGI away from the substrate 00,
  • the IGZO semiconductor layer 01 includes a channel region vertically opposite to the bottom gate BG and the source region and drain region on both sides of the channel region, and the source S and drain D arranged on the side of the IGZO semiconductor layer 01 away from the substrate 00 , the source S and the drain D are respectively connected to the source region and the drain region of the IGZO semiconductor layer 01, arranged on the top gate insulating layer TGI on the side where the source S and the drain D are away from the substrate 00, and arranged on the top gate insulating layer TGI
  • the layer TGI is away from the top gate TG on the side of the substrate 00 .
  • FIG. 3 is a schematic structural diagram of another pixel driving circuit provided in the related art.
  • the switch transistor M1 adopts a double-gate transistor
  • the high mobility characteristic of the double-gate transistor can improve the response rate of the switch transistor M1 .
  • Both the top gate and the bottom gate of the switching transistor M1 are connected to the scanning signal terminal SCAN to form a "synchronous" double-gate TFT.
  • the on-off state of the switching transistor M1 can be controlled synchronously by the double-gate of the switching transistor M1, which can reduce the size of the switching transistor M1.
  • the driving transistor M2 adopts a double-gate transistor
  • the relatively small sub-threshold swing characteristic of the double-gate transistor can improve the gray scale control capability of the driving transistor M2.
  • the second pole and the bottom gate of the driving transistor M2 are connected to the cathode of the light-emitting device OLED to form an "asynchronous" double-gate TFT, thereby suppressing the threshold voltage drift of the driving transistor M2 and improving the stability of the driving current formed by the driving transistor M2.
  • the stability of the light-emitting brightness of the light-emitting device OLED is improved.
  • the grayscale control capability of the driving transistor M2 is still relatively low.
  • the pixel driving circuit is configured as a display panel equipped with HDR, the grayscale control capability of the driving transistor M2 cannot meet the display requirements of the display panel.
  • the present application provides a double-gate transistor, a pixel driving circuit and a display panel, so as to improve the subthreshold slope of the double-gate transistor, thereby improving the gray scale control capability of the double-gate transistor.
  • An embodiment of the present application provides a double-gate transistor, including:
  • first gate a first gate, a first pole and a second pole; the first gate, the first pole and the second pole are arranged in the same layer;
  • the first insulating layer is disposed on one side of the first gate
  • the active layer is disposed on a side of the first insulating layer away from the first gate, the active layer includes a channel region, a first region and a second region, the channel a zone is disposed between the first zone and the second zone, the first zone is connected to the first pole, and the second zone is connected to the second pole;
  • the second insulating layer, the second insulating layer is arranged on the side of the active layer away from the first insulating layer, the capacitance per unit area of the second insulating layer is greater than or equal to the unit area of the first insulating layer Twice the area capacitance;
  • the second gate is disposed on a side of the second insulating layer away from the active layer,
  • the second grid is electrically connected to the first electrode.
  • the embodiment of the present application also provides a pixel driving circuit, including a writing transistor, a driving transistor, a first capacitor and a light emitting device; the driving transistor adopts the double-gate transistor provided in the above embodiment;
  • the first pole of the writing transistor is connected to the data signal input end
  • the gate of the writing transistor is connected to the first scanning signal input end
  • the second pole of the writing transistor is connected to the first scanning signal input end of the driving transistor.
  • the gate is connected to the first pole of the first capacitor
  • the second gate of the driving transistor is connected to the first voltage terminal
  • the second pole of the driving transistor is connected to the anode of the light emitting device
  • the light emitting The cathode of the device and the second pole of the first capacitor are connected to the second voltage terminal.
  • the embodiment of the present application also provides a display panel, including the pixel driving circuit provided in the above embodiment.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided in the related art
  • FIG. 2 is a schematic structural diagram of a transistor provided in the related art
  • FIG. 3 is a schematic structural diagram of another pixel driving circuit provided by the related art.
  • FIG. 4 is a schematic structural diagram of a double-gate transistor provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another double-gate transistor provided in the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a double-gate transistor provided in an embodiment of the present application.
  • the double-gate transistor includes: a first gate G1, a first pole 11, and a second pole 12; the first gate G1, the first pole 11, and the second pole 12 are arranged in the same layer; Layer 13, the first insulating layer 13 is arranged on one side of the first grid G1; the active layer 14, the active layer 14 is arranged on the side of the first insulating layer 13 away from the first grid G1, and the active layer 14 includes The channel region 141, the first region 142 and the second region 143, the channel region 141 is set in Between the first region 142 and the second region 143, the first region 142 is connected to the first pole 11, and the second region 143 is connected to the second pole 12; the second insulating layer 15 is arranged on the active layer 14 on the side away from the first insulating layer 13, the capacitance per unit area of the second insulating layer 15 is greater than or equal to twice the capacitance per unit
  • FIG. 4 is a cross-sectional view of a double-gate transistor with the bottom gate on the bottom and the top gate on top
  • the first gate G1 shown in FIG. 4 is the bottom gate
  • the second gate G2 is the top gate.
  • a first conductive layer may be formed.
  • the first conductive layer may be a metal layer.
  • the first conductive layer is patterned to form the first gate G1.
  • the first pole 11 and the second pole 12 can be patterned and formed on both sides of the first grid G1, so that the first pole 11 and the second pole 12 are connected with the first grid G1 Same level settings.
  • the first pole 11 can be the source of the double-gate transistor
  • the second pole 12 can be the drain of the double-gate transistor
  • the first pole 11 can be the drain of the double-gate transistor
  • the second pole 12 can be the drain of the double-gate transistor. source.
  • a first insulating layer 13 is formed on one side of the first gate G1, and the first insulating layer 13 serves as a gate insulating layer of the first gate G1.
  • the first insulating layer 13 is on one side of the first gate G1 and covers the first pole 11 and the second pole 12 , so that the first gate G1 , the first pole 11 and the second pole 12 are insulated from subsequent film layers.
  • An active layer 14 is formed on the side of the first insulating layer 13 away from the first gate G1.
  • the active layer 14 includes a channel region 141 and a first region 142 and a second region 143 arranged on both sides of the channel region 141, the first region 142 and the first electrode 11, and the second region 143 is connected to the second electrode 12, so that the first region 142 and the second region 143 serve as a source region and a drain region, respectively.
  • the first pole 11 is the source and the second pole 12 is the drain
  • the first region 142 is the source region
  • the second region 143 is the drain region.
  • the first pole 11 is a drain and the second pole 12 is a source
  • the first region 142 is a drain region
  • the second region 143 is a source region.
  • the second insulating layer 15 is formed on the side of the active layer 14 away from the first insulating layer 13, and then the second gate G2 is formed on the side of the second insulating layer 15 away from the active layer 14 , so that the second gate G2 is insulated from other film layers by the second insulating layer 15, thereby forming a double-gate transistor.
  • the second grid G2 is electrically connected to the first pole 11, and the capacitance per unit area of the second insulating layer 15 is greater than or equal to twice the capacitance per unit area of the first insulating layer 13, so that the load of the second insulating layer 15 is transferred rate is greater than the load mobility of the first insulating layer 13, so that the current control capability of the second gate G2 to the double-gate transistor is greater than the current control capability of the first gate G1 to the double-gate transistor, thereby increasing the subthreshold value of the double-gate transistor
  • the slope makes it easier to realize the linear change of the subthreshold slope of the double-gate transistor when the double-gate transistor is switched from the off state to the on state, so that the gate of the double-gate transistor can be controlled
  • the voltage difference between the source and the source more precisely controls the output current of the double-gate transistor.
  • Table 1 is a table of performance parameters of a double-gate transistor provided in the embodiment of the present application.
  • the average value of the subthreshold slope of the double-gate transistor provided by the embodiment of the present application can reach 0.47, and the subthreshold slope of the IGZO double-gate transistor provided by the related technology is generally in the range of 0.1 to 0.3, mostly around 0.2 , compared with the IGZO double-gate transistor provided in the related art, the subthreshold slope of the double-gate transistor provided by the embodiment of the present application is significantly increased.
  • Table 1 also shows the difference between the maximum value and the minimum value of each parameter in multiple parameters, through the difference between the maximum value and the minimum value of each parameter, the degree of dispersion of each parameter can be determined, which is beneficial to determine the
  • the setting range of each parameter is convenient for determining the parameter range of the double-gate transistor during the experiment.
  • Table 1 shows the difference between the maximum value and the minimum value of the sub-threshold slope, through the difference between the maximum value and the minimum value of the sub-threshold slope, the dispersion of the sub-threshold slope can be determined, thereby facilitating the determination of the sub-threshold slope
  • the range is convenient to determine the accurate range of the subthreshold slope of the double-gate transistor during the experiment.
  • Table 1 The performance parameter table of a double-gate transistor provided in the embodiment of the present application
  • Figure 4 exemplarily shows that the second grid G2 can be electrically connected to the first electrode 11 through the via hole on the film layer between the second grid G2 and the first electrode 11, and the via hole is connected to the active layer 14 No contact.
  • the second gate is electrically connected to the first pole, and the capacitance per unit area of the second insulating layer is greater than or equal to that of the first pole.
  • the current control capability of the gate transistor increases the sub-threshold slope of the double-gate transistor, making it easier to achieve a linear change in the sub-threshold slope of the double-gate transistor when the double-gate transistor is switched from the off state to the on state. Therefore, the magnitude of the current output by the double-gate transistor can be controlled more precisely by controlling the voltage difference between the gate and the source of the double-gate transistor.
  • the double-gate transistor When the double-gate transistor is used in the driving transistor in the pixel driving circuit, the current output by the pixel driving circuit can be controlled more accurately through the double-gate transistor, thereby improving the gray-scale control capability of the double-gate transistor, which is beneficial to the realization of the pixel driving circuit.
  • the vertical projection of the second gate G2 in the thickness direction X of the double-gate transistor coincides with the vertical projection of the second insulating layer 15 in the thickness direction X of the double-gate transistor.
  • the pattern of the second gate G2 and the pattern of the second insulating layer 15 can be made the same by self-alignment technology, so that the second gate G2 is in the double gate
  • the vertical projection in the thickness direction X of the transistor coincides with the vertical projection of the second insulating layer 15 in the thickness direction X of the double-gate transistor, which is beneficial to reducing the volume of the double-gate transistor.
  • FIG. 5 is a schematic structural diagram of another double-gate transistor provided in an embodiment of the present application.
  • the double-gate transistor further includes a conductive layer 16, which is arranged on the side of the second gate G2 away from the second insulating layer 15, and the conductive layer 16 is respectively connected to the second gate G2 and the second gate G2 through the via hole H1.
  • the first pole 11 is electrically connected.
  • the double-gate transistor can also be additionally provided with a conductive layer 16, and the conductive layer 16 realizes the electrical connection between the second gate G2 and the first electrode 11, which is beneficial to Reduce the size of double-gate transistors.
  • the conductive layer 16 is disposed on the side of the second grid G2 away from the second insulating layer 15, and an insulating layer is provided between the conductive layer 16 and the second grid G2.
  • a via hole H1 is provided on it, so that the conductive layer 16 is electrically connected to the second gate G2.
  • a via hole H1 is provided on the film layer between the conductive layer 16 and the first pole 11 to realize the electrical connection between the conductive layer 16 and the first pole 11, thereby realizing the electrical connection between the second grid G2 and the first pole 11 , the pattern of the second gate G2 can be reduced as much as possible, which is beneficial to reduce the volume of the double-gate transistor.
  • the double-gate transistor further includes a planarization layer, and the planarization layer is disposed on a side of the second gate G2 away from the second insulating layer 15 .
  • the planarization layer can be disposed on a side of the conductive layer 16 close to the second gate G2 .
  • the planarization layer is disposed on a side of the second gate G2 away from the second insulating layer 15 .
  • the double-gate transistor further includes a signal output terminal 17 electrically connected to the second electrode 12 , and the signal output terminal 17 is set on the same layer as the conductive layer 16 .
  • the double gate transistor When the double gate transistor is used in the driving transistor of the pixel driving circuit in the display panel, the double gate transistor
  • the second pole 12 of the tube is connected to the power signal line or data line of the display panel, and the power signal line and data line are generally arranged on the third conductive layer or the fourth conductive layer in the display panel.
  • the signal output terminal 17 and the conductive The layers 16 are arranged in the same layer, so that an additional conductive layer can be avoided.
  • the signal output end 17 can be connected to the second pole 12 through the via hole, so that the second pole 12 is connected to the power signal line or data line on the display panel through the signal input end 17, which simplifies the line connection process on the display panel.
  • FIG. 6 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • the pixel drive circuit includes a writing transistor T1, a driving transistor T2, a first capacitor C1, and a light emitting device D1;
  • the driving transistor T2 adopts the double-gate transistor provided by the embodiment of the present application;
  • the first The pole is connected to the data signal input terminal VDATA, the gate of the writing transistor T1 is connected to the first scan signal input terminal S1, and the second pole of the writing transistor T1 is connected to the first gate of the driving transistor T2 and the second pole of the first capacitor C1.
  • One pole is connected, the second gate of the driving transistor T2 is connected to the first voltage terminal V1, the second pole of the driving transistor T2 is connected to the anode of the light emitting device D1, the cathode of the light emitting device D1 is connected to the second pole of the first capacitor C1 The second voltage terminal V2 is connected.
  • FIG. 6 exemplarily shows that the writing transistor T1 and the driving transistor T2 are N-type transistors.
  • the driving transistor T2 is the double-gate transistor provided in the embodiment of the present application, the second gate of the driving transistor T2 may be connected to the first electrode.
  • the writing transistor T1 is controlled to be turned on, and the data signal provided by the data signal input terminal VDATA passes through the writing transistor T1
  • the transmission is transmitted to the first gate of the driving transistor T2, so that the driving transistor T2 is turned on, and a driving current is formed according to the voltage difference between the first gate and the first electrode of the driving transistor T2 to drive the light emitting device D1 to emit light.
  • the driving transistor in the pixel driving circuit as the double-gate transistor provided in the embodiment of the present application, during the working process of the pixel driving circuit, the direct voltage difference between the gate and the first electrode can be
  • the light-emitting device provides more accurate driving current, thereby improving the gray scale control capability of the driving transistor, which is beneficial to realizing the display effect of the display panel where the pixel driving circuit is located.
  • FIG. 7 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the writing transistor T1 is a double-gate transistor.
  • the writing transistor T1 is a switch transistor, and by setting the writing transistor T1 as a double-gate transistor, the requirement of the writing transistor T1 on the response rate can be guaranteed, and the working performance of the pixel driving circuit can be guaranteed.
  • the double-gate transistor may be an IGZO double-gate transistor in the related art, so as to ensure the response rate of the writing transistor T1.
  • FIG. 8 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit further includes a compensation transistor T3, an emission control transistor T4, a reset transistor T5 and a second capacitor C2; the second capacitor C2 is connected in series between the second pole of the writing transistor T1 and the first gate of the driving transistor T2 , the gate of the compensation transistor T3 is connected to the second scanning signal input terminal S2, the first pole of the compensation transistor T3 is connected to the first gate of the driving transistor T2, the second pole of the compensation transistor T3 is connected to the second gate of the driving transistor T2 pole is connected to the second pole of the light-emitting control transistor T4, the first pole of the light-emitting control transistor T4 is connected to the first voltage terminal V1, the gate of the light-emitting control transistor T4 is connected to the light-emitting control signal input terminal EM, and the gate of the reset transistor T5 It is connected to the first scan signal input terminal S1, the first pole of the reset transistor
  • FIG. 8 exemplarily shows that the compensation transistor T3 , the light emission control transistor T4 and the reset transistor T5 are all N-type transistors.
  • the first scan signal provided by the first scan signal input terminal S1 is at a high level, which controls the writing transistor T1 and the reset transistor T5 to be turned on, and the data signal input terminal VDATA provides The data signal is transmitted to the first electrode of the second capacitor C2 through the writing transistor T1, and is transmitted to the first gate of the driving transistor T2 through the second capacitor C2, and the driving transistor T2 is controlled to be turned on.
  • the reset signal provided by the reset signal input terminal RES is transmitted to the anode of the light emitting device D1 through the reset transistor T5 to reset the anode of the light emitting device D1.
  • the second scanning signal provided by the second scanning signal input terminal S2 is at a high level, and the compensation transistor T3 is controlled to be turned on, and the potential of the second capacitor C2 is transmitted to the first electrode and the first electrode of the driving transistor T2 through the compensation transistor T3.
  • the second gate realizes threshold compensation of the driving transistor T2 until the driving transistor T2 is turned off.
  • the light emission control signal provided by the light emission control signal input terminal EM controls the light emission control transistor T4 to be turned on, so that the first voltage provided by the first voltage terminal V1 is transmitted to the first pole of the driving transistor T2, and the driving transistor T2 is turned on. and a driving current is formed according to the first voltage and the threshold-compensated data voltage to drive the light-emitting device D1 to emit light.
  • the driving transistor is also set as the double-gate transistor provided in the embodiment of the present application, so that the driving transistor can provide a more accurate driving current for the light-emitting device according to the voltage difference between the gate and the first electrode, thereby improving
  • the grayscale control capability of the driving transistor is improved, which is beneficial to realize the display effect of the display panel where the pixel driving circuit is located.
  • FIG. 9 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application. As shown in FIG. 9, the compensation transistor T3 is a double-gate transistor.
  • the compensation transistor T3 is a switch transistor, and by setting the compensation transistor T3 as a double-gate transistor, the response rate requirement of the compensation transistor T3 can be guaranteed, and the working performance of the pixel driving circuit can be guaranteed.
  • the double-gate transistor may be an IGZO double-gate transistor in the related art, so as to ensure the response rate of the compensation transistor T3.
  • all transistors except the driving transistor T2 are switching transistors.
  • the light emission control crystal The transistor T4 and the reset transistor T5 can also be configured as double-gate transistors to further improve the performance of the pixel driving circuit.
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 10 , the display panel includes a pixel driving circuit 10 provided in any embodiment of the present application.
  • the display panel may include a display area AA and a non-display area NAA
  • the display area AA may include a plurality of pixel drive circuits 10 arranged in an array
  • the non-display area NAA includes a data driver and timing control module 101, a row driver circuit 102 , data line 103 , multiplexing circuit 104 and scan line 105 .
  • the data driving and timing control module 101 can provide data signals for the data line 103 .
  • Each data line 103 is connected to an input terminal of a multiplexing circuit 104, and each output terminal in a plurality of output terminals of each multiplexing circuit 104 is connected to a column of pixel driving circuits 10, which is a column of pixel driving circuits 10 provides a data signal.
  • the row driving circuit 102 is connected to the data driving and timing control module 101 , and the row driving circuit 102 is configured to output scanning signals row by row under the control of the data driving and timing controlling module 101 .
  • the row driving circuit 102 has a plurality of output terminals, each output terminal is connected to a scanning line 105, and each scanning line 105 is correspondingly connected to a row of pixel driving circuits 10, so that the pixel driving circuit 10 sequentially displays according to the scanning signal and the data signal to realize Display panel display.
  • the display panel since the display panel includes the pixel driving circuit provided by any embodiment of the present application, the pixel driving circuit has good gray scale control capability, so that the pixel driving circuit can more accurately drive the light-emitting devices in the display panel emit light, thereby improving the display effect of the display panel.

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Abstract

本申请公开了一种双栅晶体管、像素驱动电路和显示面板。该双栅晶体管包括第一栅极、第一极和第二极；第一栅极、第一极和第二极同层设置；第一绝缘层，第一绝缘层设置于第一栅极的一侧；有源层，有源层设置于第一绝缘层远离第一栅极的一侧，有源层包括沟道区、第一区和第二区，沟道区设置于第一区和第二区之间，第一区与第一极连接，第二区与第二极连接；第二绝缘层，第二绝缘层的单位面积电容大于或等于第一绝缘层的单位面积电容的2倍；第二栅极，第二栅极与第一极电连接。

Description

双栅晶体管、像素驱动电路和显示面板
本申请要求在2022年02月21日提交中国专利局、申请号为202210165861.X的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示的技术领域，例如涉及一种双栅晶体管、像素驱动电路和显示面板。
背景技术
相关的显示面板一般采用像素驱动电路驱动发光器件发光，以实现显示面板的显示。像素驱动电路通常包括薄膜晶体管(Thin Film Transistor，TFT)，薄膜晶体管设置为为发光器件提供驱动电流。示例性地，图1为相关技术提供的一种像素驱动电路的结构示意图。如图1所示，该像素驱动电路包括开关晶体管M1、驱动晶体管M2和存储电容Cst，开关晶体管M1的栅极与扫描信号端SCAN连接，开关晶体管M1的第一极与数据信号端data连接，开关晶体管M1的第二极与驱动晶体管M2的栅极和存储电容Cst的第一极连接，驱动晶体管M2的第一极与存储电容Cst的第二极和第一电源端VDD连接，驱动晶体管M2的第二极与发光器件有机发光二极管(Organic Light-Emitting Diode，OLED)的阳极连接，发光器件OLED的阴极与第二电源端VSS连接。图1中示例性地示出了开关晶体管M1和驱动晶体管M2为P型晶体管。当扫描信号端SCAN提供的扫描信号为低电平时，开关晶体管M1导通，数据信号端data提供的数据电压通过开关晶体管M1传输至驱动晶体管M2的栅极，使得驱动晶体管M2根据数据电压和第一电源端VDD提供的第一电压产生驱动电流，驱动发光器件OLED发光。在像素驱动电路中，不同的TFT具有不同的作用，使得不同的TFT具有不同的特性需求。示例性地，如图1所示，开关晶体管M1主要具有像素开关作用，因此开关晶体管M1对响应速率有很高的要求。驱动晶体管M2主要设置为驱动发光器件OLED发光，因此驱动晶体管M2对灰阶控制能力有很高的要求。显示面板采用高动态范围成像(High Dynamic Range Imaging，HDR)技术显示时，驱动晶体管M2对灰阶控制能力要求更高，使得显示面板能够显示更多灰阶数的画面。
图2为相关技术提供的一种晶体管的结构示意图。如图2所示，晶体管为铟镓锌氧化物(indium gallium zinc oxide，IGZO)双栅晶体管，该双栅晶体管包括基板00，设置于基板00上的底栅BG，设置于底栅BG远离基板00一侧的底栅绝缘层BGI，设置于底栅绝缘层BGI远离基板00一侧的IGZO半导体层01， IGZO半导体层01包括与底栅BG垂直相对设置的沟道区和沟道区两侧的源极区和漏极区，设置于IGZO半导体层01远离基板00一侧的源极S和漏极D，源极S和漏极D分别与IGZO半导体层01的源极区和漏极区连接，设置于源极S和漏极D远离基板00一侧的顶栅绝缘层TGI，设置于顶栅绝缘层TGI远离基板00一侧的顶栅TG。该双栅晶体管具有较高的迁移率、较大的开态电流、比较小的亚阈值摆幅以及稳定性比较好的阈值电压的特性。当该双栅晶体管应用于像素驱动电路中，图3为相关技术提供的另一像素驱动电路的结构示意图。如图3所示，当开关晶体管M1采用双栅晶体管时，双栅晶体管的高迁移率特性可以提高开关晶体管M1的响应速率。开关晶体管M1的顶栅和底栅均与扫描信号端SCAN连接，形成“同步”双栅TFT，通过开关晶体管M1的双栅同步控制开关晶体管M1的导通或截止状态，可以减小开关晶体管M1的漏电流。当驱动晶体管M2采用双栅晶体管时，双栅晶体管的比较小的亚阈值摆幅特性可以提高驱动晶体管M2的灰阶控制能力。驱动晶体管M2的第二极和底栅与发光器件OLED的阴极连接，形成“异步”双栅TFT，从而抑制了驱动晶体管M2的阈值电压漂移，提高了驱动晶体管M2形成的驱动电流的稳定性，提高了发光器件OLED的发光亮度的稳定性。然而，驱动晶体管M2的灰阶控制能力仍然比较低，当像素驱动电路设置为搭载HDR的显示面板时，驱动晶体管M2的灰阶控制能力无法满足显示面板的显示需求。
发明内容
本申请提供一种双栅晶体管、像素驱动电路和显示面板，以提高双栅晶体管的亚阈值斜率，进而提高了双栅晶体管的灰阶控制能力。
本申请实施例提供了一种双栅晶体管，包括：
第一栅极、第一极和第二极；所述第一栅极、所述第一极和所述第二极同层设置；
第一绝缘层，所述第一绝缘层设置于所述第一栅极的一侧；
有源层，所述有源层设置于所述第一绝缘层远离所述第一栅极的一侧，所述有源层包括沟道区、第一区和第二区，所述沟道区设置于所述第一区和所述第二区之间，所述第一区与所述第一极连接，所述第二区与所述第二极连接；
第二绝缘层，所述第二绝缘层设置于所述有源层远离所述第一绝缘层的一侧，所述第二绝缘层的单位面积电容大于或等于所述第一绝缘层的单位面积电容的2倍；
第二栅极，所述第二栅极设置于所述第二绝缘层远离所述有源层的一侧， 所述第二栅极与所述第一极电连接。
本申请实施例还提供了一种像素驱动电路，包括写入晶体管、驱动晶体管、第一电容和发光器件；所述驱动晶体管采用上述实施例提供的双栅晶体管；
所述写入晶体管的第一极与数据信号输入端连接，所述写入晶体管的栅极与第一扫描信号输入端连接，所述写入晶体管的第二极与所述驱动晶体管的第一栅极和所述第一电容的第一极连接，所述驱动晶体管的第二栅极与第一电压端连接，所述驱动晶体管的第二极与所述发光器件的阳极连接，所述发光器件的阴极和所述第一电容的第二极与第二电压端连接。
本申请实施例还提供了一种显示面板，包括上述实施例提供的像素驱动电路。
附图说明
图1为相关技术提供的一种像素驱动电路的结构示意图；
图2为相关技术提供的一种晶体管的结构示意图；
图3为相关技术提供的另一像素驱动电路的结构示意图；
图4为本申请实施例提供的一种双栅晶体管的结构示意图；
图5为本申请实施例提供的另一种双栅晶体管的结构示意图；
图6为本申请实施例提供的一种像素驱动电路的结构示意图；
图7为本申请实施例提供的另一种像素驱动电路的结构示意图；
图8为本申请实施例提供的另一种像素驱动电路的结构示意图；
图9为本申请实施例提供的另一种像素驱动电路的结构示意图；
图10为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。
图4为本申请实施例提供的一种双栅晶体管的结构示意图。如图4所示，该双栅晶体管包括：第一栅极G1、第一极11和第二极12；第一栅极G1、第一极11和第二极12同层设置；第一绝缘层13，第一绝缘层13设置于第一栅极G1的一侧；有源层14，有源层14设置于第一绝缘层13远离第一栅极G1的一侧，有源层14包括沟道区141、第一区142和第二区143，沟道区141设置于 第一区142和第二区143之间，第一区142与第一极11连接，第二区143与第二极12连接；第二绝缘层15，第二绝缘层15设置于有源层14远离第一绝缘层13的一侧，第二绝缘层15的单位面积电容大于或等于第一绝缘层13的单位面积电容的2倍；第二栅极G2，第二栅极G2设置于第二绝缘层15远离有源层14的一侧，第二栅极G2与第一极11电连接。
当图4为底栅在下顶栅在上的双栅晶体管的剖面图时，则图4中示例性示出的第一栅极G1为底栅，第二栅极G2为顶栅。在其他实施例中，还可以设置第一栅极G1为顶栅，第二栅极G2为底栅。在形成第一栅极G1时，可以形成第一导电层。示例性的，第一导电层可以为金属层。然后对第一导电层进行图案化，形成第一栅极G1。在对第一导电层进行图案化时，可以在第一栅极G1的两侧图案化形成第一极11和第二极12，使得第一极11和第二极12与第一栅极G1同层设置。其中，第一极11可以为双栅晶体管的源极，第二极12为双栅晶体管的漏极，或者，第一极11可以为双栅晶体管的漏极，第二极12为双栅晶体管的源极。在形成第一栅极G1后，在第一栅极G1的一侧形成第一绝缘层13，第一绝缘层13作为第一栅极G1的栅极绝缘层。第一绝缘层13在第一栅极G1的一侧且覆盖第一极11和第二极12，使得第一栅极G1、第一极11和第二极12与后续的膜层绝缘。在第一绝缘层13远离第一栅极G1的一侧形成有源层14，示例性的，有源层14可以为IGZO半导体层，其中，构成IGZO半导体层的半导体材料可以是金属氧化物(In2O3)x(MO)y(ZnO)z，其中0≤x≤1，0≤y≤1，0≤z≤1，且x+y+z＝1，M为镓、锡、硅、铝、镁、钽、铪、钇、镍、锆或镧系稀土元素中的一种或两种以上的任意组合。通过对有源层14进行不同的掺杂，使得有源层14包括沟道区141和设置于沟道区141两侧的第一区142和第二区143，第一区142与第一极11连接，第二区143与第二极12连接，使得第一区142和第二区143分别作为源极区和漏极区。其中，当第一极11为源极，第二极12为漏极时，第一区142为源极区，第二区143为漏极区。当第一极11为漏极，第二极12为源极时，第一区142为漏极区，第二区143为源极区。在形成有源层14后，在有源层14远离第一绝缘层13的一侧形成第二绝缘层15，然后在第二绝缘层15远离有源层14的一侧形成第二栅极G2，使得第二栅极G2通过第二绝缘层15与其他膜层绝缘，从而形成双栅晶体管。
另外，第二栅极G2与第一极11电连接，且第二绝缘层15的单位面积电容大于或等于第一绝缘层13的单位面积电容的2倍，使得第二绝缘层15的载荷迁移率大于第一绝缘层13的载荷迁移率，从而使得第二栅极G2对双栅晶体管的电流控制能力大于第一栅极G1对双栅晶体管的电流控制能力，进而增加双栅晶体管的亚阈值斜率，使得双栅晶体管由截止状态切换为导通状态时，更容易实现双栅晶体管的亚阈值斜率线性变化，从而可以通过控制双栅晶体管的栅极 和源极的压差，更精确的控制了双栅晶体管输出的电流大小。当双栅晶体管用于像素驱动电路中的驱动晶体管中时，可以通过双栅晶体管更准确的控制像素驱动电路输出的电流，从而提高了双栅晶体管的灰阶控制能力，有利于实现像素驱动电路所在的显示面板的显示效果。示例性的，表1为本申请实施例提供的一种双栅晶体管的性能参数表。如表1所示，本申请实施例提供的双栅晶体管的亚阈值斜率的平均值可以达到0.47，相关技术提供的IGZO双栅晶体管的亚阈值斜率一般在0.1～0.3范围内，大多位于0.2左右，相对于相关技术提供的IGZO双栅晶体管，本申请实施例提供的双栅晶体管的亚阈值斜率明显增加。另外，表1还示出了多个参数中每个参数的最大值和最小值之差，通过每参数的最大值和最小值之差，可以确定每个参数的离散度，从而有利于确定每个参数的设置范围，方便实验过程中确定双栅晶体管的参数范围。示例性的，表1示出了亚阈值斜率的最大值和最小值之差，通过亚阈值斜率的最大值和最小值之差，可以确定亚阈值斜率的离散度，从而有利于确定亚阈值斜率的范围，方便实验过程中确定双栅晶体管的亚阈值斜率的准确范围。
表1本申请实施例提供的一种双栅晶体管的性能参数表
图4中示例性的示出了第二栅极G2可以通过第二栅极G2和第一极11之间的膜层上的过孔与第一极11电连接，且过孔与有源层14不接触。
本实施例的技术方案，通过设置第一栅极、第一极和第二极同层设置，第二栅极与第一极电连接，且第二绝缘层的单位面积电容大于或等于第一绝缘层的单位面积电容的2倍，使得第二绝缘层的载荷迁移率大于第一绝缘层的载荷迁移率，从而使得第二栅极对双栅晶体管的电流控制能力大于第一栅极对双栅晶体管的电流控制能力，进而增加双栅晶体管的亚阈值斜率，使得双栅晶体管由截止状态切换为导通状态时，更容易实现双栅晶体管的亚阈值斜率线性变化， 从而可以通过控制双栅晶体管的栅极和源极的压差，更精确的控制了双栅晶体管输出的电流大小。当双栅晶体管用于像素驱动电路中的驱动晶体管中时，可以通过双栅晶体管更准确的控制像素驱动电路输出的电流，从而提高了双栅晶体管的灰阶控制能力，有利于实现像素驱动电路所在的显示面板的显示效果。
继续参考图4，第二栅极G2在双栅晶体管厚度方向X的垂直投影与第二绝缘层15在双栅晶体管厚度方向X的垂直投影重合。
在形成第二绝缘层15和第二栅极G2时，可以通过自对准技术，使得第二栅极G2的图形与第二绝缘层15的图形相同，从而使得第二栅极G2在双栅晶体管厚度方向X的垂直投影与第二绝缘层15在双栅晶体管厚度方向X的垂直投影重合，有利于减小双栅晶体管的体积。
图5为本申请实施例提供的另一种双栅晶体管的结构示意图。如图5所示，双栅晶体管还包括导电层16，导电层16设置于第二栅极G2远离第二绝缘层15的一侧，导电层16通过过孔H1分别与第二栅极G2和第一极11电连接。
如图5所示，当第二栅极G2的图形比较小时，双栅晶体管还可以额外设置一层导电层16，导电层16实现第二栅极G2与第一极11的电连接，有利于减小双栅晶体管的体积。示例性的，如图5所示，导电层16设置于第二栅极G2远离第二绝缘层15的一侧，且导电层16和第二栅极G2之间具有绝缘层，通过在绝缘层上设置过孔H1，使得导电层16与第二栅极G2电连接。在导电层16和第一极11之间的膜层上设置过孔H1，可以实现导电层16与第一极11的电连接，进而实现了第二栅极G2与第一极11的电连接，可以尽可能的减小第二栅极G2的图形，有利于减小双栅晶体管的体积。
在上述多个技术方案的基础上，双栅晶体管还包括平坦化层，平坦化层设置于第二栅极G2远离第二绝缘层15的一侧。
当双栅晶体管包括导电层16时，平坦化层可以设置于导电层16靠近第二栅极G2的一侧。当双栅晶体管不包括导电层16时，平坦化层设置于第二栅极G2远离第二绝缘层15的一侧。通过在第二栅极G2远离第二绝缘层15的一侧设置平坦化层或者在导电层16远离第二栅极G2的一侧设置平坦化层，可以平坦化第二栅极G2所在的膜层或者导电层16所在的膜层，使得双栅晶体管用于显示面板时，有利于在平坦化层远离第二栅极G2的一侧形成发光器件，简化了显示面板的制作过程。
继续参考图5，双栅晶体管还包括信号输出端17，信号输出端17与第二极12电连接，信号输出端17与导电层16同层设置。
当双栅晶体管用于显示面板中像素驱动电路的驱动晶体管中时，双栅晶体 管的第二极12与显示面板的电源信号线或数据线连接，而电源信号线和数据线一般设置于显示面板中的第三导电层或第四导电层，通过设置信号输出端17与导电层16同层设置，可以避免额外设置一层导电层。且信号输出端17可以通过过孔与第二极12连接，从而使得第二极12通过信号输入端17与显示面板上的电源信号线或数据线连接，简化了显示面板上的线路连接过程。
本申请实施例还提供了一种像素驱动电路。图6为本申请实施例提供的一种像素驱动电路的结构示意图。如图6所示，该像素驱动电路包括写入晶体管T1、驱动晶体管T2、第一电容C1和发光器件D1；驱动晶体管T2采用本申请实施例提供的双栅晶体管；写入晶体管T1的第一极与数据信号输入端VDATA连接，写入晶体管T1的栅极与第一扫描信号输入端S1连接，写入晶体管T1的第二极与驱动晶体管T2的第一栅极和第一电容C1的第一极连接，驱动晶体管T2的第二栅极与第一电压端V1连接，驱动晶体管T2的第二极与发光器件D1的阳极连接，发光器件D1的阴极和第一电容C1的第二极与第二电压端V2连接。
图6中示例性的示出了写入晶体管T1和驱动晶体管T2为N型晶体管。其中，驱动晶体管T2为本申请实施例提供的双栅晶体管时，可以设置驱动晶体管T2的第二栅极与第一极连接。在像素驱动电路工作的过程中，当第一扫描信号输入端S1提供的第一扫描信号为高电平时，控制写入晶体管T1导通，数据信号输入端VDATA提供的数据信号通过写入晶体管T1传输到驱动晶体管T2的第一栅极，使得驱动晶体管T2导通，并根据驱动晶体管T2的第一栅极和第一极之间的压差形成驱动电流，驱动发光器件D1发光。
本实施例的技术方案，通过设置像素驱动电路中的驱动晶体管为本申请实施例提供的双栅晶体管，可以在像素驱动电路的工作过程中，可以根据栅极和第一极直接的压差为发光器件提供更精确的驱动电流，从而提高了驱动晶体管的灰阶控制能力，有利于实现像素驱动电路所在的显示面板的显示效果。
在上述技术方案的基础上，图7为本申请实施例提供的另一种像素驱动电路的结构示意图。如图7所示，写入晶体管T1为双栅晶体管。
写入晶体管T1为开关晶体管，通过设置写入晶体管T1为双栅晶体管，可以保证写入晶体管T1对响应速率的需求，保证像素驱动电路的工作性能。
写入晶体管T1为双栅晶体管时，该双栅晶体管可以为相关技术中的IGZO双栅晶体管，以保证写入晶体管T1的响应速率。
图8为本申请实施例提供的另一种像素驱动电路的结构示意图。如图8所 示，像素驱动电路还包括补偿晶体管T3、发光控制晶体管T4、复位晶体管T5和第二电容C2；第二电容C2串联于写入晶体管T1的第二极和驱动晶体管T2的第一栅极之间，补偿晶体管T3的栅极与第二扫描信号输入端S2连接，补偿晶体管T3的第一极与驱动晶体管T2的第一栅极连接，补偿晶体管T3的第二极与驱动晶体管T2的第二栅极和发光控制晶体管T4的第二极连接，发光控制晶体管T4的第一极与第一电压端V1连接，发光控制晶体管T4的栅极与发光控制信号输入端EM连接，复位晶体管T5的栅极与第一扫描信号输入端S1连接，复位晶体管T5的第一极与复位信号输入端RES连接，复位晶体管T5的第二极与发光器件D1的阳极连接。
图8中示例性的示出了补偿晶体管T3、发光控制晶体管T4和复位晶体管T5均为N型晶体管。在像素驱动电路工作的过程中，在第一阶段，第一扫描信号输入端S1提供的第一扫描信号为高电平，控制写入晶体管T1和复位晶体管T5导通，数据信号输入端VDATA提供的数据信号通过写入晶体管T1传输到第二电容C2的第一极，并通过第二电容C2传输至驱动晶体管T2的第一栅极，控制驱动晶体管T2导通。复位信号输入端RES提供的复位信号通过复位晶体管T5传输至发光器件D1的阳极，对发光器件D1的阳极进行复位。在第二阶段，第二扫描信号输入端S2提供的第二扫描信号为高电平，控制补偿晶体管T3导通，第二电容C2的电位通过补偿晶体管T3传输至驱动晶体管T2的第一极和第二栅极，实现驱动晶体管T2的阈值补偿，直至驱动晶体管T2截止。在第三阶段，发光控制信号输入端EM提供的发光控制信号控制发光控制晶体管T4导通，使得第一电压端V1提供的第一电压传输至驱动晶体管T2的第一极，使得驱动晶体管T2导通，并根据第一电压和阈值补偿后的数据电压形成驱动电流，驱动发光器件D1发光。
本实施例的技术方案，同样设置驱动晶体管为本申请实施例提供的双栅晶体管，使得驱动晶体管可以根据栅极和第一极之间的压差为发光器件提供更精确的驱动电流，从而提高了驱动晶体管的灰阶控制能力，有利于实现像素驱动电路所在的显示面板的显示效果。
图9为本申请实施例提供的另一种像素驱动电路的结构示意图。如图9所示，补偿晶体管T3为双栅晶体管。
补偿晶体管T3为开关晶体管，通过设置补偿晶体管T3为双栅晶体管，可以保证补偿晶体管T3对响应速率的需求，保证像素驱动电路的工作性能。
补偿晶体管T3为双栅晶体管时，该双栅晶体管可以为相关技术中的IGZO双栅晶体管，以保证补偿晶体管T3的响应速率。另外，在像素驱动电路中，除驱动晶体管T2以外的晶体管均为开关晶体管，在其他实施例中，发光控制晶体 管T4和复位晶体管T5也可以设置为双栅晶体管，以进一步的提高像素驱动电路的工作性能。
本申请实施例还提供一种显示面板。图10为本申请实施例提供的一种显示面板的结构示意图。如图10所示，该显示面板包括本申请任意实施例提供的像素驱动电路10。
如图10所示，显示面板可以包括显示区AA和非显示区NAA，显示区AA可以包括阵列排布的多个像素驱动电路10，非显示区NAA包括数据驱动及时序控制模块101、行驱动电路102、数据线103、多路复用电路104和扫描线105。数据驱动及时序控制模块101可以为数据线103提供数据信号。每条数据线103与一个多路复用电路104的输入端连接，每个多路复用电路104的多个输出端中的每个输出端与一列像素驱动电路10连接，为一列像素驱动电路10提供数据信号。行驱动电路102与数据驱动及时序控制模块101连接，行驱动电路102设置为在数据驱动及时序控制模块101的控制下逐行输出扫描信号。行驱动电路102具有多个输出端，每个输出端与一条扫描线105连接，每条扫描线105对应连接一行像素驱动电路10，从而使得像素驱动电路10依次根据扫描信号和数据信号显示，实现显示面板的显示。
本实施例的技术方案，由于显示面板包括本申请任意实施例提供的像素驱动电路，使得像素驱动电路具有很好的灰阶控制能力，使得像素驱动电路能够更精确的驱动显示面板中的发光器件发光，从而提高了显示面板的显示效果。

Claims (10)

  1. 一种双栅晶体管，包括：
    第一栅极、第一极和第二极；所述第一栅极、所述第一极和所述第二极同层设置；
    第一绝缘层，所述第一绝缘层设置于所述第一栅极的一侧；
    有源层，所述有源层设置于所述第一绝缘层远离所述第一栅极的一侧，所述有源层包括沟道区、第一区和第二区，所述沟道区设置于所述第一区和所述第二区之间，所述第一区与所述第一极连接，所述第二区与所述第二极连接；
    第二绝缘层，所述第二绝缘层设置于所述有源层远离所述第一绝缘层的一侧，所述第二绝缘层的单位面积电容大于或等于所述第一绝缘层的单位面积电容的2倍；
    第二栅极，所述第二栅极设置于所述第二绝缘层远离所述有源层的一侧，所述第二栅极与所述第一极电连接。
  2. 根据权利要求1所述的双栅晶体管，其中，所述第二栅极在所述双栅晶体管厚度方向的垂直投影与所述第二绝缘层在所述双栅晶体管厚度方向的垂直投影重合。
  3. 根据权利要求2所述的双栅晶体管，还包括导电层，所述导电层设置于所述第二栅极远离所述第二绝缘层的一侧，所述导电层通过过孔分别与所述第二栅极和所述第一极电连接。
  4. 根据权利要求1-3任一项所述的双栅晶体管，还包括平坦化层，所述平坦化层设置于所述第二栅极远离所述第二绝缘层的一侧。
  5. 根据权利要求3所述的双栅晶体管，还包括信号输出端，所述信号输出端与所述第二极电连接，所述信号输出端与所述导电层同层设置。
  6. 一种像素驱动电路，包括写入晶体管、驱动晶体管、第一电容和发光器 件；所述驱动晶体管采用权利要求1-5任一项所述的双栅晶体管；
    所述写入晶体管的第一极与数据信号输入端连接，所述写入晶体管的栅极与第一扫描信号输入端连接，所述写入晶体管的第二极与所述驱动晶体管的第一栅极和所述第一电容的第一极连接，所述驱动晶体管的第二栅极与第一电压端连接，所述驱动晶体管的第二极与所述发光器件的阳极连接，所述发光器件的阴极和所述第一电容的第二极与第二电压端连接。
  7. 根据权利要求6所述的像素驱动电路，其中，所述写入晶体管为双栅晶体管。
  8. 根据权利要求6所述的像素驱动电路，还包括补偿晶体管、发光控制晶体管、复位晶体管和第二电容；
    所述第二电容串联于所述写入晶体管的第二极和所述驱动晶体管的第一栅极之间，所述补偿晶体管的栅极与第二扫描信号输入端连接，所述补偿晶体管的第一极与所述驱动晶体管的第一栅极连接，所述补偿晶体管的第二极与所述驱动晶体管的第二栅极和所述发光控制晶体管的第二极连接，所述发光控制晶体管的第一极与所述第一电压端连接，所述发光控制晶体管的栅极与发光控制信号输入端连接，所述复位晶体管的栅极与所述第一扫描信号输入端连接，所述复位晶体管的第一极与复位信号输入端连接，所述复位晶体管的第二极与所述发光器件的阳极连接。
  9. 根据权利要求8所述的像素驱动电路，其中，所述补偿晶体管为双栅晶体管。
  10. 一种显示面板，包括权利要求6-9任一项所述的像素驱动电路。
PCT/CN2023/077357 2022-02-21 2023-02-21 双栅晶体管、像素驱动电路和显示面板 WO2023155917A1 (zh)

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