WO2021164431A1 - 像素驱动电路、像素结构及显示面板 - Google Patents

像素驱动电路、像素结构及显示面板 Download PDF

Info

Publication number
WO2021164431A1
WO2021164431A1 PCT/CN2020/140891 CN2020140891W WO2021164431A1 WO 2021164431 A1 WO2021164431 A1 WO 2021164431A1 CN 2020140891 W CN2020140891 W CN 2020140891W WO 2021164431 A1 WO2021164431 A1 WO 2021164431A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
node
pixel
transistor
signal
Prior art date
Application number
PCT/CN2020/140891
Other languages
English (en)
French (fr)
Inventor
刘利宾
冯宇
史世明
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/415,758 priority Critical patent/US11869424B2/en
Publication of WO2021164431A1 publication Critical patent/WO2021164431A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a pixel structure, and a display panel.
  • the camera of a display device such as a mobile phone is usually hidden in the display area of the display panel.
  • the pixel density of the display area with the camera hidden needs to be set to be smaller than the pixel density of the normal display area to increase its light transmittance, so as to facilitate the camera to collect the light of the object to be photographed.
  • the high pixel density area and the low pixel density area of the display panel will have different display brightness when displaying images.
  • a pixel driving circuit including a plurality of driving transistors, a first terminal of each driving transistor is connected to a first power terminal, a second terminal is connected to a first node, and a control terminal It is connected to the second node for inputting current to the first node under the action of the voltage of the second node.
  • the pixel driving circuit further includes: a first switching circuit, a data writing circuit, a compensation circuit, a second switching circuit, a storage circuit, a first reset circuit, a second reset circuit, and a light emitting circuit. unit.
  • the first switch circuit is connected to the first power terminal, the first terminal of each drive transistor, and the enable signal terminal, and is configured to respond to the signal of the enable signal terminal to turn on the first power terminal and each The first terminal of each of the driving transistors;
  • the data writing circuit is connected to the first terminal, the data signal terminal, the gate signal terminal of each of the driving transistors, and is used to respond to the signal of the gate signal terminal to transfer the data signal
  • the signal at the terminal is transmitted to the first terminal of each of the driving transistors;
  • the compensation circuit is connected to the first node, the second node, and the gate signal terminal, and is used to turn on the first node in response to the signal at the gate signal terminal And a second node;
  • a second switch circuit is connected to the first node, the enable signal terminal, and the third node, and is used to transmit the signal of the second node to the third node in response to the signal of the enable signal terminal
  • a storage circuit is connected between the second node and the first power supply terminal, and is used
  • the first switch circuit includes a first transistor, a first terminal of the first transistor is connected to the first power supply terminal, and a second terminal is connected to the first terminal of each driving transistor.
  • the control terminal is connected to the enable signal terminal;
  • the data writing circuit includes a second transistor, the first terminal of the second transistor is connected to the data signal terminal, and the second terminal is connected to the first terminal of each driving transistor, The control terminal is connected to the gate signal terminal;
  • the compensation circuit includes a third transistor, the first terminal of the third transistor is connected to the first node, the second terminal is connected to the second node, and the control terminal is connected to the gate Signal terminal;
  • the second switch circuit includes a fourth transistor, the first terminal of the fourth transistor is connected to the first node, the second terminal is connected to the third node, and the control terminal is connected to the enable signal terminal;
  • the storage circuit includes a capacitor, the capacitor is connected between the second node and the first power terminal;
  • the first reset circuit includes a fifth transistor, the first terminal of the fifth transistor is connected
  • the pixel driving circuit further includes a seventh transistor, an eighth transistor, a capacitor, and a light-emitting unit.
  • the first terminal of the seventh transistor is connected to the data signal terminal, the second section is connected to the second node, and the control terminal is connected to the first gate signal terminal; the first terminal of the eighth transistor is connected to the sensing signal terminal, and the second terminal is connected to the In the first node, the control terminal is connected to the second gate signal terminal; the capacitor is connected between the first node and the second node; the light-emitting unit is connected between the first node and the second power terminal.
  • a pixel structure including the above-mentioned pixel driving circuit.
  • the pixel driving circuit includes a capacitor; each of the driving transistors includes a gate portion, and a plurality of the gate portions together form an electrode of the capacitor.
  • the pixel structure includes a gate layer, a source-drain layer, and a conductive layer located between the gate layer and the source-drain layer, and part of the conductive layer forms the capacitance of the capacitor. Another electrode.
  • the pixel structure includes a data line extending along a first direction; and a plurality of the driving transistors are sequentially arranged in parallel along the first direction.
  • a display panel including a low pixel density area and a high pixel density area, the low pixel density area being provided with the above-mentioned pixel driving circuit.
  • the display area of the display panel includes the pixel density of the high pixel density area which is n times the pixel density of the low pixel density area, and the pixel drive in the high pixel density area
  • the circuit has the same structure as the pixel drive circuit in the low pixel density area; the pixel drive circuit in the high pixel density area includes m drive transistors, and the pixel drive circuit in the low pixel density area includes X drive transistors , Where m is a positive integer, X is a positive integer less than or equal to n 2 m and greater than n 2 m-1, or X is a positive integer greater than or equal to n 2 m and less than n 2 m+1;
  • the capacitance value of the capacitor in the pixel drive circuit is p, and in the low pixel density area, the capacitance value of the pixel drive circuit capacitor is n 2 p; and, the drive transistors in the high pixel density area and the low pixel density
  • the pixel driving circuit in the high pixel density area, includes a driving transistor.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in the related art
  • FIG. 2 is a timing diagram of some nodes in the pixel driving circuit of FIG. 1;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure.
  • FIG. 6 is a schematic structural diagram of an exemplary embodiment of the pixel structure of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an active layer in an exemplary embodiment of the pixel structure of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a gate layer in an exemplary embodiment of the pixel structure of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a conductive layer in an exemplary embodiment of the pixel structure of the present disclosure.
  • FIG. 10 is a schematic diagram of the structure of the source and drain layers in an exemplary embodiment of the pixel structure of the present disclosure
  • FIG. 11 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 12 is a pixel structure corresponding to the pixel driving circuit of FIG. 1;
  • FIG. 13 is a schematic diagram of the structure of an active layer in the pixel structure of FIG. 12;
  • FIG. 14 is a schematic diagram of the structure of the gate layer in the pixel structure of FIG. 12;
  • FIG. 15 is a schematic diagram of the structure of the conductive layer in the pixel structure of FIG. 12;
  • FIG. 16 is a schematic diagram of the structure of the active drain layer in the pixel structure of FIG. 12.
  • the pixel density of the display area with the camera hidden needs to be set to be smaller than the pixel density of the normal display area to increase its light transmittance, so as to facilitate the camera to collect the light of the object to be photographed.
  • the low pixel density area where the camera is hidden and the high pixel density area of the normal display have different pixel densities, the high pixel density area and the low pixel density area have different display brightness when the display panel displays images.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit in the related art.
  • FIG. 2 is a timing diagram of some nodes in the pixel driving circuit of FIG. 1.
  • the pixel driving circuit includes first to sixth transistors T1-T6, a driving transistor DT, a capacitor C, and a light-emitting unit OLED.
  • the first to sixth transistors T1-T6 and the driving transistor DT can all be P-type transistors, and the light-emitting unit
  • the OLED is connected between the third node and the second power terminal VSS.
  • the driving method of the pixel driving circuit includes three stages: a reset stage, a compensation stage and a light-emitting stage.
  • the enable signal terminal EM is a high-level signal
  • the reset signal terminal Reset is a low-level signal
  • the gate drive signal terminal Gate is a high-level signal
  • the fifth transistor T5 the first The six transistors T6 are turned on
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off
  • the initial signal terminal Vinit inputs a reset signal to the first node N1 and the third node N3.
  • the enable signal terminal EM is a high level signal
  • the reset signal terminal Reset is a high level signal
  • the gate drive signal terminal Gate is a low level signal
  • the transistor T5 and the sixth transistor T6 are turned off
  • the second transistor T2 and the third transistor T3 are turned on
  • the signal voltage of the terminal Vdata, Vth is the threshold voltage of the third transistor T3.
  • the enable signal terminal EM is a low-level signal
  • the reset signal terminal Reset is a high-level signal
  • the gate drive signal terminal Gate is a high-level signal
  • the second transistor T2 the third transistor T3, and the fifth transistor T5 and the sixth transistor T6 are turned off
  • the first transistor T1 and the fourth transistor T4 are turned on
  • the light-emitting unit OLED emits light under the control of the output current of the driving transistor DT.
  • the output current of the driving transistor DT I 0.5*W/L*Cox*(Vgs-Vth) 2
  • Vg is the gate voltage of the driving transistor DT
  • Vs is the source voltage of the driving transistor DT
  • Vth is the driving transistor DT W is the channel width of the drive transistor DT
  • L is the channel length of the drive transistor DT
  • Cox is the capacitance per unit area of the gate of the drive transistor.
  • the exemplary embodiment provides a pixel driving circuit, as shown in FIG. 3, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the pixel driving circuit includes a plurality of driving transistors DT1, DT2, DT3, and DT4.
  • the first end of each driving transistor is connected to the first power supply terminal VDD, the second end is connected to the first node N1, and the control end is connected to the second node N2. , Used for inputting current to the first node N1 under the action of the voltage of the second node N2.
  • the first node may be connected to the light-emitting unit for providing driving current to the light-emitting unit.
  • the pixel driving circuit increases the current input to the first node N1 by providing multiple driving transistors without changing the size of the driving transistor and the voltage of the first power supply terminal VDD, thereby improving the brightness of the light-emitting unit.
  • the pixel driving circuit may also be provided with other numbers of driving transistors.
  • Transistor The driving transistor in FIG. 3 may be a P-type transistor or an N-type transistor.
  • the pixel driving circuit may further include: a first switching circuit 1, a data writing circuit 2, a compensation circuit 3, a second switching circuit 4, a storage circuit 5, a first reset circuit 6, a second reset Circuit 7, light-emitting unit 8.
  • the first switch circuit 1 is connected to the first power supply terminal VDD, the first terminal of each of the driving transistors, and the enable signal terminal EM, and is used to respond to the signal of the enable signal terminal EM to turn on the first power terminal EM.
  • the data writing circuit 2 is connected to the first terminal of each of the driving transistors, the data signal terminal Data, and the gate signal terminal Gate for responding to the gate
  • the signal of the polar signal terminal Gate transmits the signal of the data signal terminal Data to the first terminal of each driving transistor
  • the compensation circuit 3 is connected to the first node N1, the second node N2, and the gate signal terminal Gate, The first node N1 and the second node N2 are turned on in response to the signal of the gate signal terminal Gate
  • the second switch circuit 4 is connected to the first node N1, the enable signal terminal EM, and the third node N3, Used to transmit the signal of the first node N1 to the third node N3 in response to the signal of the enable signal terminal EM
  • the storage circuit 5 is connected to the second node N2 and the first power terminal VDD Is used to store the voltage of the second node N2
  • the first reset circuit 6 is connected to the second node N2, the initial signal terminal Vinit, and the reset
  • the first switch circuit 1 may include a first transistor T1, a first terminal of the first transistor T1 is connected to the first power supply terminal VDD, and a second terminal is connected to each The first terminal of the driving transistor, the control terminal is connected to the enable signal terminal EM;
  • the data writing circuit 2 may include a second transistor T2, the first terminal of the second transistor T2 is connected to the data signal terminal Data, the second The terminal is connected to the first terminal of each of the driving transistors, and the control terminal is connected to the gate signal terminal Gate;
  • the compensation circuit 3 may include a third transistor T3, and the first terminal of the third transistor T3 is connected to the first node N1, the second terminal is connected to the second node N2, the control terminal is connected to the gate signal terminal Gate;
  • the second switch circuit 4 may include a fourth transistor T4, and the first terminal of the fourth transistor T4 is connected to the first terminal A node N1, the second terminal is connected to the third node N3, the control terminal is connected to the enable signal terminal EM;
  • the first reset circuit 6 may include a fifth transistor T5, the first terminal of the fifth transistor T5 is connected to the second node N2, the second terminal is connected to the initial signal terminal Vinit, the control terminal Is connected to the reset signal terminal Reset;
  • the second reset circuit 7 may include a sixth transistor T6, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal is connected to the initial signal terminal Vinit to control The terminal is connected to the reset signal terminal Reset;
  • the light-emitting unit 8 may include a light-emitting diode OLED, which is connected between the third node N3 and the second power terminal VSS.
  • the first transistor T1 to the sixth transistor T6 and the driving transistor may be P-type transistors.
  • the pixel driving circuit shown in FIG. 4 is basically the same as the driving method of the driving circuit shown in FIG. 1, except that the pixel driving circuit in FIG. 4 inputs current to the first node through four driving transistors, so that the The pixel driving circuit can improve the light-emitting brightness of the pixel unit without changing the size of the first power supply terminal VDD and the driving transistor.
  • the pixel driving circuit may also have other structures to choose from.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit of the present disclosure. Based on the pixel driving circuit shown in FIG. 3, the pixel driving circuit may further include a seventh transistor T7, an eighth transistor T8, a capacitor C, and a light-emitting unit OLED.
  • the first terminal of the seventh transistor T7 is connected to the data signal terminal Data
  • the second section is connected to the second node N2
  • the control terminal is connected to the first gate signal terminal G1
  • the first terminal of the eighth transistor T8 is connected to the sensing signal terminal Sense
  • the second terminal is connected to the first node N1, the control terminal is connected to the second gate signal terminal G2
  • the capacitor C is connected between the first node N1 and the second node N2
  • the light-emitting unit is connected to the first node Between N1 and the second power supply terminal VSS.
  • the sensing signal terminal Sense can be used to sense the output current of the driving transistor when the driving transistor is turned on, so as to detect the threshold voltage and mobility of the driving transistor.
  • the driving method of the pixel driving circuit shown in FIG. 5 generally includes: a data writing phase and a light emitting phase.
  • the data writing stage the data signal terminal Data inputs a data signal to the gate of the driving transistor through the seventh transistor T7 and is stored in the storage capacitor C.
  • the sensing signal terminal Sense can also be driven to each through the eighth transistor T8 The source of the transistor inputs the initial signal.
  • each driving transistor is turned on under the action of the storage capacitor C to drive the light-emitting unit OLED to emit light through the first power supply terminal VDD.
  • the exemplary embodiment also provides a pixel structure including the above-mentioned pixel driving circuit.
  • FIG. 6 it is a schematic structural diagram of an exemplary embodiment of the pixel structure of the present disclosure.
  • FIG. 6 specifically includes the pixel driving circuit shown in FIG. 4.
  • the pixel structure includes an active layer ACT, a gate layer Gate, a conductive layer EC, a source-drain layer SD, the active layer ACT, a gate layer Gate, a conductive layer EC, and a source-drain layer SD are stacked in sequence, and adjacent film layers An insulating layer is provided between.
  • the active layer ACT includes two first active portions 71, two second active portions 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, and a sixth active portion 76 , Four seventh active parts 77.
  • the first active part 71 is used to form the channel layer of the first transistor
  • the second active part 72 is used to form the channel layer of the second transistor
  • the two third active parts 73 form the third transistor (double Gate structure)
  • the fourth active portion 74 is used to form the channel layer of the fourth transistor
  • the two fifth active portions 75 are used to form the channel layer of the fifth transistor (dual gate structure).
  • the six active parts 76 are used to form the channel layer of the sixth transistor, and the four seventh active parts 77 respectively form the channel layer of the driving transistor.
  • the gate layer Gate includes a first gate section 81, a second gate section 82, a third gate section 83, a fourth gate section 84, and a fifth gate section 85.
  • the orthographic projection of part of the first gate part 81 covers the two fifth active parts 75 to form the gate layer of the fifth transistor T5, while the first gate part 81 is connected to the reset signal terminal Reset; part of the second gate part
  • the orthographic projection of 82 covers the second active part 72 to form the gate layer of the second transistor;
  • the orthographic projection of part of the second gate part 82 covers the third active part 73 to form the gate layer of the third transistor, and at the same time
  • the second gate portion 82 is connected to the gate driving signal terminal Gate;
  • a part of the third gate portion 83 covers the four seventh active portions to form the gates of the four driving transistors, wherein the third gate portion 83 may be an integral structure
  • the third gate portion 83 can form an electrode of the capacitor C in FIG.
  • a part of the fourth gate portion 84 covers the fourth active portion 74 to form the gate of the fourth transistor, and a portion of the fourth gate portion 84 covers the first
  • An active portion 71 is used to form the gate of the first transistor, while the fourth gate portion 84 is connected to the enable signal terminal EM;
  • part of the fifth gate portion 85 covers the sixth active portion 76 to form the gate of the sixth transistor T6 At the same time, the fifth gate portion 85 is connected to the reset signal terminal Reset.
  • the conductive layer EC includes a first conductive portion 91, a second conductive portion 92, a third conductive portion 93, and a fourth conductive portion 94.
  • the first conductive portion 91 and the third conductive portion 93 may be connected to the initial signal terminal Vinit; the second conductive portion 92 may form another electrode of the capacitor C in FIG. 4; the fourth conductive portion is used to shield the adjacent pixel structure on the right side Middle the channel layer of the third transistor T3 to avoid leakage of the third transistor.
  • the source drain layer may include a first source drain portion 11, a second source drain portion 12, a third source drain portion 13, a fourth source drain portion 14, a fifth source drain portion 15, and a sixth source drain portion 16.
  • the first source and drain portion 11 is connected to the first conductive portion 91 through the via hole 21, and is connected to the active layer on the side of the fifth active portion 75 through the via hole 22 to connect the initial signal terminal Vinit and the fifth transistor The second end.
  • the second source/drain portion 12 is connected to the first power terminal VDD, and is connected to the fourth conductive portion 94 through the via 23, so that the fourth conductive portion maintains the voltage of the first power terminal VDD.
  • the second source and drain portion 12 is also connected to the second conductive portion 92 through the via holes 27 and 28, so that the second conductive portion 92 forms an electrode of the capacitor C.
  • the second source/drain portion 12 is also connected to the active layer on the side of the first active portion 71 through the via 29 so that the first terminal of the first transistor is connected to the first power terminal VDD.
  • the third source-drain portion 13 is connected to the data signal terminal Data, wherein the third source-drain portion 13 is connected to the active layer on the side of the second active portion 72 through the via 24, so that the data signal terminal Data is connected to the second transistor of the second transistor.
  • the fourth source-drain portion 14 is connected to the active layer on the side of the fourth active portion 74 through the via 33, so that the fourth source-drain portion 14 is connected to the second end of the fourth transistor.
  • the light emitting diode OLED can pass through the fourth transistor.
  • the source drain 14 is connected to the second end of the fourth transistor.
  • the fifth source/drain portion 15 is connected to the third conductive portion 93 through the via hole 31, and is connected to the active layer on the side of the sixth active portion 76 through the via hole 32, so that the second terminal of the sixth transistor is connected to the initial signal terminal Vinit.
  • the sixth source and drain portion 16 is connected to the active layer on the side of the third active portion 73 through the via hole 25, and is connected to the third gate portion 83 through the via hole 26, so that the gate of each driving transistor is connected to the third The second end of the transistor, where, as shown in FIG.
  • the second conductive portion 92 is provided with a hollow hole 921 at the position of the via 26 in its orthographic projection, so that the sixth source and drain portion 16 can pass through the via 26 and the third
  • the gate portion 83 is connected, and is not connected to the second conductive portion 92.
  • the active layer ACT may be indium gallium zinc oxide.
  • the active layer may be subjected to a conductive treatment, so that the non-channel layer in the active layer forms a conductor.
  • the conductive treatment can be achieved by hydrogen ion implantation.
  • the active layer ACT can also be a polysilicon layer.
  • the active layer can be treated with semiconductor doping, so that the non-channel layer in the active layer forms a conductor, where the semiconductor doping can be N Type semiconductor doping or P-type semiconductor doping.
  • the conductive layer EC can also share other conductive film layers in the pixel structure, for example, a light-shielding metal layer.
  • the pixel structure includes a data line (the third source and drain portion 13), the data line extends in the first direction X;
  • the first direction X is arranged side by side in sequence.
  • the exemplary embodiment also provides a display panel, as shown in FIG. 11, which is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure.
  • the display area of the display panel includes a low pixel density area 111 and a high pixel density area 112, and the low pixel density area is provided with the aforementioned pixel driving circuit.
  • the pixel density of the high pixel density area is twice the pixel density of the low pixel density area as an example for description.
  • the high pixel density area of the display panel may be provided with the pixel driving circuit shown in FIG. 1, and the low pixel density area may be provided with the pixel driving circuit shown in FIG. 4.
  • the capacitance in FIG. 4 should be four times the capacitance value of the capacitor in FIG. Since the number of driving transistors in the pixel driving circuit in FIG. 4 is four times that in FIG. 1, the luminous intensity of the light-emitting unit in FIG.
  • the light-emitting brightness of the pixel unit in the low pixel density area is enhanced, thereby avoiding The phenomenon that the display brightness is inconsistent in the high pixel density area and the low pixel density area of the display panel is solved.
  • FIG. 12 is a pixel structure corresponding to the pixel driving circuit described in FIG. 1, and FIG. 13 is a schematic structural diagram of an active layer in the pixel structure of FIG. 12; A schematic diagram of the structure of the gate layer in the pixel structure; FIG. 15 is a schematic diagram of the structure of the conductive layer in the pixel structure of FIG. 12; and FIG. 16 is a schematic diagram of the active drain layer in the pixel structure of FIG. 12.
  • the pixel structure shown in FIG. 12 is similar to the pixel structure shown in FIG. 6.
  • the pixel structure also includes an active layer ACT, a gate layer Gate, a conductive layer EC, a source and drain layer SD, an active layer ACT, a gate layer Gate ,
  • the conductive layer EC, the source drain layer SD are stacked in sequence, and an insulating layer is provided between adjacent film layers.
  • the annotations Gate, Data, Vinit, Reset, VDD, T1, T2, T3, T4, T5, T6, DT in Figure 12 and the annotations Gate, Data, Vinit, Reset, VDD, T1, T2, T3, T4, T5, T6, and DT correspond respectively.
  • the black squares in FIG. 12 indicate vias located on the insulating layer, and the vias are used to connect the above four film layers.
  • the pixel structure shown in FIG. 12 and the pixel structure shown in FIG. 6 also have the same interlayer connection mode, the difference is only that the pixel structure shown in FIG. 12 includes one driving transistor, and the pixel structure shown in FIG. 6 includes four driving transistors. .
  • the pixel structure in the low pixel density area of the display panel may adopt the pixel structure shown in FIG. 6, and the pixel structure in the high pixel density area of the display panel may adopt the pixel structure shown in FIG. 12.
  • the ratio of the light-transmitting area using the pixel structure of FIG. 12 is 32.57% and the transmittance is 9.77%
  • the ratio of the light-transmitting area using the pixel structure of FIG. 6 is 30.29% and the transmittance is 9.09%. It shows that the use of the pixel structure shown in FIG. 6 in the low pixel density area has minimal impact on its transmittance, which can fully satisfy the camera lighting.
  • the pixel density of the high pixel density area may be another multiple of the pixel density of the low pixel density area.
  • the pixel density of the high pixel density area is n times the pixel density of the low pixel density area
  • the pixel drive circuit in the high pixel density area has the same structure as the pixel drive circuit in the low pixel density area
  • the pixel drive circuit in the high pixel density area includes m drive transistors
  • the capacitance value of the capacitor in the pixel driving circuit is p
  • the capacitance value of the pixel driving circuit capacitor is n 2 p
  • the size of the driving transistors in the high pixel density area and the low pixel density area are the same.
  • the pixel drive circuit in the high pixel density area and the pixel drive circuit in the low pixel density area have the same structure, which means that the two pixel drive circuits have different structures except for the number of drive transistors and the different capacitance values. All the same.
  • m can be an integer greater than or equal to 1.
  • the display panel provided by this exemplary embodiment can be applied to display devices such as mobile phones, VRs, and tablet computers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素驱动电路、像素结构及显示面板，像素驱动电路包括多个驱动晶体管，每个驱动晶体管的第一端连接第一电源端，第二端连接第一节点，控制端连接第二节点，用于在第二节点电压作用下向第一节点输入电流。显示面板的低像素密度区可以应用上述像素驱动电路，从而能够避免低像素密度区和高像素密度区之间的亮度差异。

Description

像素驱动电路、像素结构及显示面板
相关申请的交叉引用
本申请要求于2020年02月20日递交的、名称为《像素驱动电路、像素结构及显示面板》的中国专利申请第202010103609.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、像素结构及显示面板。
背景技术
在相关技术中，为了实现手机等显示装置全面屏设计，通常将手机等显示装置的摄像头隐藏于显示面板的显示区内。隐藏有摄像头的显示区需要将其像素密度设置为小于正常显示区的像素密度以提高其透光率，从而有利于摄像头采集待拍摄物体的光线。
然而，由于隐藏有摄像头的低像素密度区和正常显示的高像素密度区具有不同的像素密度，显示面板在显示画面时高像素密度区和低像素密度区会具有不同显示亮度。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种像素驱动电路，该像素驱动电路包括多个驱动晶体管，每个所述驱动晶体管的第一端连接第一电源端，第二端连接第一节点，控制端连接第二节点，用于在第二节点电压作用下向所述第一节点输入电流。
本公开的一种示例性实施例中，该像素驱动电路还包括：第一开关电路、数据写入电路、补偿电路、第二开关电路、存储电路、第一复位电路、第二复位电路、发光单元。第一开关电路连接所述第一电源端、每个所述驱动晶体管的第一端、使能信号端，用于响应于所述使能信号端的信号以导通所述第一电源端和每个所述驱动晶体管的第一端；数据写入电路连接每个所述驱动晶体管的第一端、数据信号端、栅极信号端、用于响应所述栅极信号端的信号将所述数据信号端的信号传输到每个所述驱动晶体管的第一端；补偿电路连接所述第一节点、第二节点、栅极信号端，用于响应所述栅极信号端的信号导通所述第一节点和第二节点；第二开关电路连接所述第一节点、使能信号端、第三节点，用于响应所述使能信号端的信号将所述第二节点的信号传输到所述第三节点；存储电路连接于所述第二节点和所述第一电源端之间，用于存储所述第二节点的电压；第一复位电路连接第二节 点、初始信号端、复位信号端，用于响应所述复位信号端的信号将所述初始信号端的信号传输到所述第二节点；第二复位电路连接第三节点、初始信号端、复位信号端，用于响应所述复位信号端的信号将所述初始信号端的信号传输到所述第三节点；发光单元连接于所述第三节点和第二电源端之间。
本公开的一种示例性实施例中，所述第一开关电路包括第一晶体管，第一晶体管的第一端连接所述第一电源端，第二端连接每个所述驱动晶体管的第一端，控制端连接使能信号端；所述数据写入电路包括第二晶体管，第二晶体管的第一端连接所述数据信号端，第二端连接每个所述驱动晶体管的第一端，控制端连接所述栅极信号端；所述补偿电路包括第三晶体管，第三晶体管的第一端连接所述第一节点，第二端连接所述第二节点，控制端连接所述栅极信号端；所述第二开关电路包括第四晶体管，第四晶体管的第一端连接所述第一节点，第二端连接所述第三节点，控制端连接所述使能信号端；所述存储电路包括电容，电容连接于所述第二节点和所述第一电源端之间；所述第一复位电路包括第五晶体管，第五晶体管的第一端连接所述第二节点，第二端连接所述初始信号端，控制端连接所述复位信号端；所述第二复位电路包括第六晶体管，第六晶体管的第一端连接所述第三节点，第二端连接所述初始信号端，控制端连接所述复位信号端；所述发光单元包括发光二极管，发光二极管连接于所述第三节点和第二电源端之间。
本公开的一种示例性实施例中，所述像素驱动电路还包括第七晶体管、第八晶体管、电容、发光单元。第七晶体管的第一端连接数据信号端，第二段连接所述第二节点，控制端连接第一栅极信号端；第八晶体管的第一端连接感测信号端，第二端连接所述第一节点，控制端连接第二栅极信号端；电容连接于所述第一节点和第二节点之间；发光单元连接于所述第一节点和第二电源端之间。
根据本公开的一个方面，提供一种像素结构，该像素结构包括上述的像素驱动电路。
本公开的一种示例性实施例中，所述像素驱动电路包括电容；每个所述驱动晶体管包括栅极部，多个所述栅极部共同形成所述电容的一个电极。
本公开的一种示例性实施例中，所述像素结构包括栅极层、源漏层以及位于所述栅极层和源漏层之间的导电层，部分所述导电层形成所述电容的另一电极。
本公开的一种示例性实施例中，所述像素结构包括数据线，所述数据线沿第一方向延伸；多个所述驱动晶体管沿所述第一方向依次并列分布。
根据本公开的一个方面，提供一种显示面板，包括低像素密度区和高像素密度区，所述低像素密度区设置有上述的像素驱动电路。
本公开的一种示例性实施例中，所述显示面板的显示区包括所述高像素密度区的像素密度是低像素密度区像素密度的n倍，且所述高像素密度区内的像素驱动电路与所述低像 素密度区内的像素驱动电路具有相同的架构；所述高像素密度区中的像素驱动电路包括m个驱动晶体管，所述低像素密度区中像素驱动电路包括X个驱动晶体管，其中，m为正整数，X为小于等于n 2m且大于n 2m-1的正整数，或X为大于等于n 2m且小于n 2m+1的正整数；在所述高像素密度区，像素驱动电路中电容的电容值为p，在所述低像素密度区，像素驱动电路电容的电容值为n 2p；且，所述高像素密度区和低像素密度区中驱动晶体管的尺寸相同。
本公开的一种示例性实施例中，在所述高像素密度区中，像素驱动电路包括一个驱动晶体管。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种像素驱动电路的结构示意图；
图2为图1像素驱动电路中部分节点的时序图；
图3为本公开像素驱动电路一种示例性实施例的结构示意图；
图4为本公开像素驱动电路另一种示例性实施例的结构示意图；
图5为本公开像素驱动电路另一种示例性实施例的结构示意图；
图6为本公开像素结构一种示例性实施例的结构示意图；
图7为本公开像素结构一种示例性实施例中有源层的结构示意图；
图8为本公开像素结构一种示例性实施例中栅极层的结构示意图；
图9为本公开像素结构一种示例性实施例中导电层的结构示意图；
图10为本公开像素结构一种示例性实施例中源漏层的结构示意图；
图11为本公开显示面板一种示例性实施例的结构示意图；
图12为图1所述像素驱动电路所对应的像素结构；
图13为图12像素结构中有源层的结构示意图；
图14为图12像素结构中栅极层的结构示意图；
图15为图12像素结构中导电层的结构示意图；
图16为图12像素结构中有源漏层的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”和“第二”等仅作为标记使用，不是对其对象的数量限制。
为了实现手机等显示装置全面屏设计，相关技术通常将手机等显示装置的摄像头隐藏于显示面板的显示区内。隐藏有摄像头的显示区需要将其像素密度设置为小于正常显示区的像素密度以提高其透光率，从而有利于摄像头采集待拍摄物体的光线。然而，由于隐藏有摄像头的低像素密度区和正常显示的高像素密度区具有不同的像素密度，显示面板在显示画面时会出现高像素密度区和低像素密度区具有不同显示亮度。
如图1、2所示，图1为相关技术中一种像素驱动电路的结构示意图。图2为图1像素驱动电路中部分节点的时序图。该像素驱动电路包括第一到第六晶体管T1-T6、驱动晶体管DT、电容C、发光单元OLED，其中，第一到第六晶体管T1-T6、驱动晶体管DT均可以为P型晶体管，发光单元OLED连接于第三节点和第二电源端VSS之间。该像素驱动电路驱动方法包括三个阶段：复位阶段、补偿阶段和发光阶段。如图2所示，在复位阶段T1：使能信号端EM为高电平信号，复位信号端Reset为低电平信号，栅极驱动信号端Gate为高电平信号，第五晶体管T5、第六晶体管T6导通，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4关断，初始信号端Vinit向第一节点N1和第三节点N3输入复 位信号。在补偿阶段T2：使能信号端EM为高电平信号，复位信号端Reset为高电平信号，栅极驱动信号端Gate为低电平信号，第一晶体管T1、第四晶体管T4、第五晶体管T5、第六晶体管T6关断，第二晶体管T2、第三晶体管T3导通，数据信号端Vdata向第一节点N1输入补偿电压V，其中，补偿电压V＝Vdata+Vth，Vdata为数据信号端Vdata的信号电压，Vth为第三晶体管T3的阈值电压。在发光阶段：使能信号端EM为低电平信号，复位信号端Reset为高电平信号，栅极驱动信号端Gate为高电平信号，第二晶体管T2、第三晶体管T3、第五晶体管T5、第六晶体管T6关断，第一晶体管T1、第四晶体管T4导通，发光单元OLED在驱动晶体管DT输出电流控制下发光。其中，驱动晶体管DT输出端电流I＝0.5*W/L*Cox*(Vgs-Vth) 2，Vg为驱动晶体管DT的栅极电压，Vs为驱动晶体管DT的源极电压，Vth为驱动晶体管DT的阈值电压，W为驱动晶体管DT沟道宽度，L为驱动晶体管DT沟道长度，Cox为驱动晶体管栅极单位面积电容量。则驱动晶体管DT输出端电流I＝0.5*W/L*Cox*(Vgs-Vth) 2＝0.5*W/L*Cox*(Vdata+Vth-VDD-Vth) 2＝0.5*W/L*Cox*(Vdata-VDD) 2。由该公式可知，发光单元OLED的发光状态与驱动晶体管的阈值电压不相关，从而避免驱动晶体管DT阈值电压对发光亮度造成影响。
基于此，本示例性实施例提供一种像素驱动电路，如图3所示，为本公开像素驱动电路一种示例性实施例的结构示意图。该像素驱动电路包括多个驱动晶体管DT1、DT2、DT3、DT4，每个所述驱动晶体管的第一端连接第一电源端VDD，第二端连接第一节点N1，控制端连接第二节点N2，用于在第二节点N2电压作用下向所述第一节点N1输入电流。
本示例性实施例中，第一节点可以与发光单元连接，用于向发光单元提供驱动电流。该像素驱动电路在不改变驱动晶体管尺寸和第一电源端VDD电压的情况下，通过设置多个驱动晶体管，增加了输入到第一节点N1的电流，从而提高了发光单元的亮度。
本示例性实施例中，如图3所示，本实施例示例性的画出了四个驱动晶体管，应该理解的是，在其他示例性实施例中，像素驱动电路还可以设置其他数量的驱动晶体管。图3中驱动晶体管可以为P型晶体管也可以为N型晶体管。
如图4所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。本示例性实施例中，该像素驱动电路还可以包括：第一开关电路1、数据写入电路2、补偿电路3、第二开关电路4、存储电路5、第一复位电路6、第二复位电路7、发光单元8。第一开关电路1连接所述第一电源端VDD、每个所述驱动晶体管的第一端、使能信号端EM，用于响应于所述使能信号端EM的信号以导通所述第一电源端VDD和每个所述驱动晶体管的第一端；数据写入电路2连接每个所述驱动晶体管的第一端、数据信号端Data、栅极信号端Gate、用于响应所述栅极信号端Gate的信号将所述数据信号端Data的信号传输到每个所述驱动晶体管的第一端；补偿电路3连接所述第一节点N1、第二节点N2、栅极信号端Gate，用 于响应所述栅极信号端Gate的信号导通所述第一节点N1和第二节点N2；第二开关电路4连接所述第一节点N1、使能信号端EM、第三节点N3，用于响应所述使能信号端EM的信号将所述第一节点N1的信号传输到所述第三节点N3；存储电路5连接于所述第二节点N2和所述第一电源端VDD之间，用于存储所述第二节点N2的电压；第一复位电路6连接第二节点N2、初始信号端Vinit、复位信号端Reset，用于响应所述复位信号端Reset的信号将所述初始信号端Vinit的信号传输到所述第二节点N2；第二复位电路7连接第三节点N3、初始信号端Vinit、复位信号端Reset，用于响应所述复位信号端Reset的信号将所述初始信号端Vinit的信号传输到所述第三节点N3；发光单元8连接于所述第三节点N3和第二电源端VSS之间。
本示例性实施例中，如图4所示，所述第一开关电路1可以包括第一晶体管T1，第一晶体管T1的第一端连接所述第一电源端VDD，第二端连接每个所述驱动晶体管的第一端，控制端连接使能信号端EM；所述数据写入电路2可以包括第二晶体管T2，第二晶体管T2的第一端连接所述数据信号端Data，第二端连接每个所述驱动晶体管的第一端，控制端连接所述栅极信号端Gate；所述补偿电路3可以包括第三晶体管T3，第三晶体管T3的第一端连接所述第一节点N1，第二端连接所述第二节点N2，控制端连接所述栅极信号端Gate；所述第二开关电路4可以包括第四晶体管T4，第四晶体管T4的第一端连接所述第一节点N1，第二端连接所述第三节点N3，控制端连接所述使能信号端EM；所述存储电路5可以包括电容C，电容C连接于所述第二节点N2和所述第一电源端VDD之间；所述第一复位电路6可以包括第五晶体管T5，第五晶体管T5的第一端连接所述第二节点N2，第二端连接所述初始信号端Vinit，控制端连接所述复位信号端Reset；所述第二复位电路7可以包括第六晶体管T6，第六晶体管T6的第一端连接所述第三节点N3，第二端连接所述初始信号端Vinit，控制端连接所述复位信号端Reset；所述发光单元8可以包括发光二极管OLED，发光二极管OLED连接于所述第三节点N3和第二电源端VSS之间。
本示例性实施例中，第一晶体管T1到第六晶体管T6以及驱动晶体管可以为P型晶体管。图4所示的像素驱动电路与图1所示的驱动电路驱动方法基本相同，仅区别在于在图4中的像素驱动电路通过4个驱动晶体管向第一节点输入电流，从而图4所示的像素驱动电路能够在不改变第一电源端VDD和驱动晶体管尺寸的情况下，提高像素单元发光亮度。
应该理解的是，在其他示例性实施例中，像素驱动电路还可以有其他的结构可供选择。例如，如图5所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。基于图3所示的像素驱动电路，所述像素驱动电路还可以包括第七晶体管T7、第八晶体管T8、电容C、发光单元OLED。第七晶体管T7的第一端连接数据信号端Data，第二段连接所述第二节点N2，控制端连接第一栅极信号端G1；第八晶体管T8的第一端连接感测信号端Sense， 第二端连接所述第一节点N1，控制端连接第二栅极信号端G2；电容C连接于所述第一节点N1和第二节点N2之间；发光单元连接于所述第一节点N1和第二电源端VSS之间。
其中，感测信号端Sense可以用于在驱动晶体管导通时感测驱动晶体管的输出电流，以检测驱动晶体管的阈值电压和迁移率。图5所示像素驱动电路的驱动方法一般包括有：数据写入阶段和发光阶段。在数据写入阶段：数据信号端Data通过第七晶体管T7向驱动晶体管的栅极输入数据信号，并存储于存储电容C，同时，感测信号端Sense还可以通过第八晶体管T8向每个驱动晶体管的源极输入初始信号。在发光阶段：每个驱动晶体管在存储电容C作用下导通，以通过第一电源端VDD驱动发光单元OLED发光。其中，每个驱动晶体管输出电流I＝w(Vg-Vs-Vth) 2，w为驱动晶体管的迁移率，Vg为驱动晶体管的栅极电压，Vs为驱动晶体管的源极电压。由于驱动晶体管的源极和栅极连接于存储电容C的两端，虽然驱动晶体管的源极电压在发光阶段有所上升，但是驱动晶体管的栅极在存储电容C自举作用下也会上升相同的电压，即驱动晶体管在发光阶段的栅极和源极电压差等于在数据写入阶段的栅极和源极电压差。从而可以仅仅通过控制数据信号端Data控制发光单元的亮度。由于该像素驱动电路设置有多个驱动晶体管，从而可以增加在发光阶段发光单元的发光亮度。
本示例性实施例还提供一种像素结构，该像素结构包括上述的像素驱动电路。
如图6所示，为本公开像素结构一种示例性实施例的结构示意图。图6具体包括图4所示的像素驱动电路。该像素结构包括有源层ACT、栅极层Gate、导电层EC、源漏层SD，有源层ACT、栅极层Gate、导电层EC、源漏层SD依次层叠设置，且相邻膜层之间设置有绝缘层。图6中的批注Gate、Data、Vinit、Reset、VDD、T1、T2、T3、T4、T5、T6、DT1、DT2、DT3、DT4与图4中的批注Gate、Data、Vinit、Reset、VDD、T1、T2、T3、T4、T5、T6、DT1、DT2、DT3、DT4分别相对应。图6中黑色方框表示位于绝缘层上的过孔，过孔用于连接上述四个膜层。
如图7所示，为本公开像素结构一种示例性实施例中有源层的结构示意图。有源层ACT包括两个第一有源部71、两个第二有源部72、第三有源部73、第四有源部74、第五有源部75、第六有源部76，四个第七有源部77。其中，第一有源部71用于形成第一晶体管的沟道层，第二有源部72用于形成第二晶体管的沟道层，两个第三有源部73形成第三晶体管(双栅结构)的沟道层，第四有源部74用于形成第四晶体管的沟道层，两个第五有源部75用于形成第五晶体管(双栅结构)的沟道层，第六有源部76用于形成第六晶体管的沟道层，四个第七有源部77分别形成驱动晶体管的沟道层。
如图8所示，为本公开像素结构一种示例性实施例中栅极层的结构示意图。栅极层Gate包括有第一栅极部81、第二栅极部82、第三栅极部83、第四栅极部84、第五栅极部85。 其中，部分第一栅极部81的正投影覆盖两第五有源部75以形成第五晶体管T5的栅极层，同时第一栅极部81连接复位信号端Reset；部分第二栅极部82的正投影覆盖第二有源部72以形成第二晶体管的栅极层；部分第二栅极部82的正投影覆盖第三有源部73以形成第三晶体管的栅极层，同时第二栅极部82连接栅极驱动信号端Gate；部分第三栅极部83覆盖四个第七有源部以形成四个驱动晶体管的栅极，其中，第三栅极部83可以为一体结构，第三栅极部83可以形成图4中电容C的一电极；部分第四栅极部84覆盖第四有源部74以形成第四晶体管的栅极，部分第四栅极部84覆盖第一有源部71以形成第一晶体管的栅极，同时第四栅极部84连接使能信号端EM；部分第五栅极部85覆盖第六有源部76以形成第六晶体管T6的栅极，同时第五栅极部85连接复位信号端Reset。
如图9所示，为本公开像素结构一种示例性实施例中导电层的结构示意图。导电层EC包括第一导电部91、第二导电部92、第三导电部93、第四导电部94。其中，第一导电部91、第三导电部93可以连接初始信号端Vinit；第二导电部92可以形成图4中电容C的另一电极；第四导电部用于遮挡右侧相邻像素结构中第三晶体管T3的沟道层，以避免第三晶体管漏电。
如图10所示，为本公开像素结构一种示例性实施例中源漏层的结构示意图。源漏层可以包括第一源漏部11、第二源漏部12、第三源漏部13、第四源漏部14、第五源漏部15、第六源漏部16。其中，第一源漏部11通过过孔21与第一导电部91连接，通过过孔22与第五有源部75一侧的有源层连接，以连接初始信号端Vinit和第五晶体管的第二端。第二源漏部12连接第一电源端VDD，且通过过孔23与第四导电部94连接，以使第四导电部保持第一电源端VDD电压。第二源漏部12还通过过孔27、28与第二导电部92连接，以使第二导电部92形成电容C的一个电极。第二源漏部12还通过过孔29与第一有源部71一侧的有源层连接以使第一晶体管的第一端连接第一电源端VDD。第三源漏部13连接数据信号端Data，其中，第三源漏部13通过过孔24连接第二有源部72一侧的有源层，以使数据信号端Data连接第二晶体管的第一端。第四源漏部14通过过孔33连接第四有源部74一侧的有源层，以使第四源漏部14连接第四晶体管的第二端，其中，发光二极管OLED可以通过第四源漏部14与第四晶体管的第二端连接。第五源漏部15通过过孔31与第三导电部93连接，通过过孔32与第六有源部76一侧的有源层连接，以使第六晶体管的第二端连接初始信号端Vinit。第六源漏部16通过过孔25与第三有源部73一侧的有源层连接，通过过孔26与第三栅极部83连接，以使每个驱动晶体管的栅极连接第三晶体管的第二端，其中，如图9所示，第二导电部92在过孔26位于其正投影位置设置有镂空孔921，以使第六源漏部16能够通过过孔26与第三栅极部83连接，且不与第二导电部92连接。
本示例性实施例中，有源层ACT可以为铟镓锌氧化物，在形成栅极层后可以对有源层 进行导体化处理，以使有源层中的非沟道层形成导体。其中，导体化处理可以通过氢离子注入实现。此外，有源层ACT还可以为多晶硅层，在形成栅极层后可以对有源层进行半导体参杂处理，以使有源层中的非沟道层形成导体，其中半导体参杂可以为N型半导体参杂或P型半导体参杂。本示例性实施例中，导电层EC还可以共用像素结构中的其他导电膜层，例如，遮光金属层等。
本示例性实施例中，如图6、10所示，所述像素结构包括数据线(第三源漏部13)，所述数据线沿第一方向X延伸；多个所述驱动晶体管沿所述第一方向X依次并列分布。
本示例性实施例还提供一种显示面板，如图11所示，为本公开显示面板一种示例性实施例的结构示意图。所述显示面板的显示区包括低像素密度区111和高像素密度区112，所述低像素密度区设置有上述的像素驱动电路。
本示例性实施例中，以高像素密度区的像素密度是低像素密度区像素密度的两倍为例进行说明。显示面板的高像素密度区可以设置图1所示的像素驱动电路，低像素密度区可以设置图4所示的像素驱动电路。在图4所示的像素驱动电路中，为满足四个驱动晶体管的栅极导通电压，图4中电容应该为图1中电容电容值的四倍。由于图4中像素驱动电路的驱动晶体管数量是图1中的四倍，图4中发光单元发光强度也近似是图1中发光单元发光强度的四倍。经实验可知，此时，高像素密度区和低像素密度区的发光亮度相近似，显示面板的显示区不易出现亮暗交界线。
本示例性实施例通过在低像素密度区设置上述像素驱动电路，在不改变驱动晶体管尺寸和像素驱动电路第一电源端电压的情况下，增强了低像素密度区像素单元的发光亮度，从而避免了显示面板高像素密度区和低像素密度区显示亮度不一致的现象。
本示例性实施例中，图12-16所示，图12为图1所述像素驱动电路所对应的像素结构，图13为图12像素结构中有源层的结构示意图；图14为图12像素结构中栅极层的结构示意图；图15为图12像素结构中导电层的结构示意图；图16为图12像素结构中有源漏层的结构示意图。图12所示的像素结构与图6所示的像素结构相似，该像素结构也包括有源层ACT、栅极层Gate、导电层EC、源漏层SD，有源层ACT、栅极层Gate、导电层EC、源漏层SD依次层叠设置，且相邻膜层之间设置有绝缘层。图12中的批注Gate、Data、Vinit、Reset、VDD、T1、T2、T3、T4、T5、T6、DT与图1中的批注Gate、Data、Vinit、Reset、VDD、T1、T2、T3、T4、T5、T6、DT分别相对应。图12中黑色方框表示位于绝缘层上的过孔，过孔用于连接上述四个膜层。图12所示的像素结构与图6所示的像素结构还具有相同的层间连接方式，其区别仅在于图12所示像素结构包括一个驱动晶体管，图6所示像素结构包括四个驱动晶体管。
本示例性实施例中，显示面板低像素密度区的像素结构可以采用图6所示的像素结构， 显示面板高像素密度区的像素结构可以采用图12所示的像素结构。根据测试可知，采用图12像素结构的透光区域比例为32.57％，透过率为9.77％，采用图6像素结构的透光区域比例为30.29％，透过率为9.09％。其表明，在低像素密度区采用图6所示的像素结构对其透过率影响极小，完全可以满足摄像头采光。
在其他示例性实施例中，高像素密度区的像素密度可以是低像素密度区像素像素密度的其他倍数。例如，所述高像素密度区的像素密度是低像素密度区像素密度的n倍，且所述高像素密度区内的像素驱动电路与所述低像素密度区内的像素驱动电路具有相同的架构；所述高像素密度区中的像素驱动电路包括m个驱动晶体管，所述低像素密度区中像素驱动电路包括X个驱动晶体管，其中，m为正整数，X为小于等于n 2m且大于n 2m-1的正整数，或X为大于等于n 2m且小于n 2m+1的正整数，例如，当m＝1，n＝2.5时，n 2m＝6.25，X可以为6或7，当m＝1，n＝2时，n 2m＝4，X为4；在所述高像素密度区，像素驱动电路中电容的电容值为p，在所述低像素密度区，像素驱动电路电容的电容值为n 2p；且，所述高像素密度区和低像素密度区中驱动晶体管的尺寸相同。其中，且所述高像素密度区内的像素驱动电路与所述低像素密度区内的像素驱动电路具有相同的架构，表示：两像素驱动电路除驱动晶体管数量和电容电容值不同以外，其他结构均相同。其中，m可以为大于等于1的整数。
本示例性实施例提供的显示面板可以应用于手机、VR、平板电脑等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (11)

  1. 一种像素驱动电路，其中，包括：
    多个驱动晶体管，每个所述驱动晶体管的第一端连接第一电源端，第二端连接第一节点，控制端连接第二节点，用于在第二节点电压作用下向所述第一节点输入电流。
  2. 根据权利要求1所述的像素驱动电路，其中，还包括：
    第一开关电路，连接所述第一电源端、每个所述驱动晶体管的第一端、使能信号端，用于响应于所述使能信号端的信号以导通所述第一电源端和每个所述驱动晶体管的第一端；
    数据写入电路，连接每个所述驱动晶体管的第一端、数据信号端、栅极信号端、用于响应所述栅极信号端的信号将所述数据信号端的信号传输到每个所述驱动晶体管的第一端；
    补偿电路，连接所述第一节点、第二节点、栅极信号端，用于响应所述栅极信号端的信号导通所述第一节点和第二节点；
    第二开关电路，连接所述第一节点、使能信号端、第三节点，用于响应所述使能信号端的信号将所述第一节点的信号传输到所述第三节点；
    存储电路，连接于所述第二节点和所述第一电源端之间，用于存储所述第一节点的电压；
    第一复位电路，连接第二节点、初始信号端、复位信号端，用于响应所述复位信号端的信号将所述初始信号端的信号传输到所述第二节点；
    第二复位电路，连接第三节点、初始信号端、复位信号端，用于响应所述复位信号端的信号将所述初始信号端的信号传输到所述第三节点；
    发光单元，连接于所述第三节点和第二电源端之间。
  3. 根据权利要求2所述的像素驱动电路，其中，
    所述第一开关电路包括：
    第一晶体管，第一端连接所述第一电源端，第二端连接每个所述驱动晶体管的第一端，控制端连接使能信号端；
    所述数据写入电路包括：
    第二晶体管，第一端连接所述数据信号端，第二端连接每个所述驱动晶体管的第一端，控制端连接所述栅极信号端；
    所述补偿电路包括：
    第三晶体管，第一端连接所述第一节点，第二端连接所述第二节点，控制端连接所述栅极信号端；
    所述第二开关电路包括：
    第四晶体管，第一端连接所述第一节点，第二端连接所述第三节点，控制端连 接所述使能信号端；
    所述存储电路包括：
    电容，连接于所述第二节点和所述第一电源端之间；
    所述第一复位电路包括：
    第五晶体管，第一端连接所述第二节点，第二端连接所述初始信号端，控制端连接所述复位信号端；
    所述第二复位电路包括：
    第六晶体管，第一端连接所述第三节点，第二端连接所述初始信号端，控制端连接所述复位信号端；
    所述发光单元包括：
    发光二极管，连接于所述第三节点和第二电源端之间。
  4. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括：
    第七晶体管，第一端连接数据信号端，第二段连接所述第二节点，控制端连接第一栅极信号端；
    第八晶体管，第一端连接感测信号端，第二端连接所述第一节点，控制端连接第二栅极信号端；
    电容，连接于所述第一节点和第二节点之间；
    发光单元，连接于所述第一节点和第二电源端之间。
  5. 一种像素结构，其中，包括：权利要求1-4任一项所述的像素驱动电路。
  6. 根据权利要求5所述的像素结构，其中，所述像素驱动电路包括电容；
    每个所述驱动晶体管包括栅极部，多个所述栅极部共同形成所述电容的一个电极。
  7. 根据权利要求6所述的像素结构，其中，所述像素结构包括栅极层、源漏层以及位于所述栅极层和源漏层之间的导电层，部分所述导电层形成所述电容的另一电极。
  8. 根据权利要求5所述的像素结构，其中，所述像素结构包括数据线，所述数据线沿第一方向延伸；
    多个所述驱动晶体管沿所述第一方向依次并列分布。
  9. 一种显示面板，所述显示面板的显示区包括低像素密度区和高像素密度区，其中，所述低像素密度区设置有权利要求1-3任一项所述的像素驱动电路。
  10. 根据权利要求9所述的显示面板，其中，所述高像素密度区的像素密度是低像素密度区像素密度的n倍，且所述高像素密度区内的像素驱动电路与所述低像素密度区内的像素驱动电路具有相同的架构；
    所述高像素密度区中的像素驱动电路包括m个驱动晶体管，所述低像素密度区中像素驱动电路包括X个驱动晶体管，其中，m为正整数，X为小于等于n 2m且大 于n 2m-1的正整数，或X为大于等于n 2m且小于n 2m+1的正整数；
    在所述高像素密度区，像素驱动电路中电容的电容值为p，在所述低像素密度区，像素驱动电路电容的电容值为n 2p；
    且，所述高像素密度区和低像素密度区中驱动晶体管的尺寸相同。
  11. 根据权利要求9所述的显示面板，其中，
    在所述高像素密度区中，像素驱动电路包括一个驱动晶体管。
PCT/CN2020/140891 2020-02-20 2020-12-29 像素驱动电路、像素结构及显示面板 WO2021164431A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/415,758 US11869424B2 (en) 2020-02-20 2020-12-29 Pixel driving circuit, pixel structure, and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010103609.7A CN111292687A (zh) 2020-02-20 2020-02-20 像素驱动电路、像素结构及显示面板
CN202010103609.7 2020-02-20

Publications (1)

Publication Number Publication Date
WO2021164431A1 true WO2021164431A1 (zh) 2021-08-26

Family

ID=71024684

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/140891 WO2021164431A1 (zh) 2020-02-20 2020-12-29 像素驱动电路、像素结构及显示面板

Country Status (3)

Country Link
US (1) US11869424B2 (zh)
CN (1) CN111292687A (zh)
WO (1) WO2021164431A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111292687A (zh) 2020-02-20 2020-06-16 京东方科技集团股份有限公司 像素驱动电路、像素结构及显示面板
CN111768740B (zh) * 2020-06-17 2022-04-19 厦门天马微电子有限公司 显示面板及其驱动方法、显示装置
CN113936604B (zh) * 2020-06-29 2022-12-27 京东方科技集团股份有限公司 显示基板及显示装置
KR20220042843A (ko) * 2020-09-28 2022-04-05 엘지디스플레이 주식회사 표시패널과 이를 이용한 표시장치
CN112186119B (zh) * 2020-09-29 2023-06-30 京东方科技集团股份有限公司 有机发光显示面板及其制备方法、显示装置和电子设备
US20230351958A1 (en) * 2021-02-10 2023-11-02 Boe Technology Group Co., Ltd. Array substrate, display panel comprising the array substrate, and display device
CN114724516B (zh) * 2022-04-26 2024-02-27 云谷（固安）科技有限公司 显示面板及其控制方法、显示装置
CN114927095A (zh) * 2022-05-25 2022-08-19 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003114644A (ja) * 2001-10-03 2003-04-18 Matsushita Electric Ind Co Ltd アクティブマトリクス型表示装置及びその駆動方法
CN109754744A (zh) * 2019-03-18 2019-05-14 昆山国显光电有限公司 一种显示面板和显示装置
WO2019196925A1 (zh) * 2018-04-12 2019-10-17 京东方科技集团股份有限公司 像素电路单元及驱动方法、显示面板、显示装置
CN110400542A (zh) * 2019-08-30 2019-11-01 武汉天马微电子有限公司 像素驱动电路、显示面板及显示装置
CN111292687A (zh) * 2020-02-20 2020-06-16 京东方科技集团股份有限公司 像素驱动电路、像素结构及显示面板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW531901B (en) * 2000-04-27 2003-05-11 Semiconductor Energy Lab Light emitting device
KR20030086168A (ko) * 2002-05-03 2003-11-07 엘지.필립스 엘시디 주식회사 유기전계 발광소자와 그 제조방법
TW200428688A (en) * 2003-06-05 2004-12-16 Au Optronics Corp Organic light-emitting display and its pixel structure
KR101142996B1 (ko) * 2004-12-31 2012-05-08 재단법인서울대학교산학협력재단 표시 장치 및 그 구동 방법
KR102083458B1 (ko) * 2013-12-26 2020-03-02 엘지디스플레이 주식회사 유기발광 표시장치
CN104005420B (zh) 2014-06-10 2016-05-11 中石化上海工程有限公司 独立式固定管架钢筋混凝土t形肋板式基础
CN107342050B (zh) * 2017-08-30 2019-08-30 上海天马有机发光显示技术有限公司 一种显示基板及显示装置
CN110390900B (zh) * 2018-04-19 2023-10-13 群创光电股份有限公司 显示器装置以及拼接式电子装置
KR102651651B1 (ko) * 2018-11-09 2024-03-28 엘지디스플레이 주식회사 표시장치 및 이의 구동방법
CN110299107B (zh) * 2019-06-28 2021-01-29 上海天马有机发光显示技术有限公司 一种有机发光显示面板及有机发光显示装置
CN110379350B (zh) * 2019-07-25 2022-09-09 京东方科技集团股份有限公司 一种色偏校正信息设定方法及装置、图像处理方法及装置、显示设备
CN111128079B (zh) * 2020-01-02 2021-04-30 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003114644A (ja) * 2001-10-03 2003-04-18 Matsushita Electric Ind Co Ltd アクティブマトリクス型表示装置及びその駆動方法
WO2019196925A1 (zh) * 2018-04-12 2019-10-17 京东方科技集团股份有限公司 像素电路单元及驱动方法、显示面板、显示装置
CN109754744A (zh) * 2019-03-18 2019-05-14 昆山国显光电有限公司 一种显示面板和显示装置
CN110400542A (zh) * 2019-08-30 2019-11-01 武汉天马微电子有限公司 像素驱动电路、显示面板及显示装置
CN111292687A (zh) * 2020-02-20 2020-06-16 京东方科技集团股份有限公司 像素驱动电路、像素结构及显示面板

Also Published As

Publication number Publication date
US11869424B2 (en) 2024-01-09
CN111292687A (zh) 2020-06-16
US20220327997A1 (en) 2022-10-13

Similar Documents

Publication Publication Date Title
WO2021164431A1 (zh) 像素驱动电路、像素结构及显示面板
US10417960B2 (en) Organic electroluminescent display panel and display device
CN104867442B (zh) 一种像素电路及显示装置
WO2021227788A1 (zh) 像素驱动电路及其驱动方法、显示面板
WO2020001027A1 (zh) 像素驱动电路及方法、显示装置
WO2022160873A1 (zh) 显示面板、显示装置
EP2960943B1 (en) Thin film transistor of display apparatus
CN110322842B (zh) 一种像素驱动电路及显示装置
TWI696990B (zh) 像素驅動電路及其驅動方法和電晶體的版圖結構
CN113035133A (zh) 像素驱动电路、像素驱动电路的驱动方法和显示面板
WO2018214533A1 (zh) 显示装置以及像素电路及其控制方法
WO2021057611A1 (zh) 像素电路、驱动方法及显示装置
CN114550653B (zh) 像素驱动电路以及显示装置
WO2020186396A1 (zh) 像素阵列基板及其驱动方法、显示面板、显示装置
CN113066434B (zh) 像素驱动电路及其驱动方法、显示面板
WO2021175150A1 (zh) 像素驱动电路及其控制方法、显示面板
CN112365844A (zh) 像素驱动电路及显示面板
US10977990B2 (en) Pixel and organic light emitting display device comprising the same
WO2019047584A1 (zh) 像素补偿电路单元、像素电路和显示装置
CN113744683A (zh) 像素电路、驱动方法和显示装置
US11501713B2 (en) Pixel circuit, driving method thereof and display device
CN113936606A (zh) 显示装置
CN106847190B (zh) 像素充电电路及其驱动方法、有机发光显示装置
WO2022227492A1 (zh) 显示面板及显示装置
WO2023216823A1 (zh) 像素驱动电路及其驱动方法、显示面板、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20920211

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20920211

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20920211

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 31-03-2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20920211

Country of ref document: EP

Kind code of ref document: A1