WO2019196925A1 - 像素电路单元及驱动方法、显示面板、显示装置 - Google Patents

像素电路单元及驱动方法、显示面板、显示装置 Download PDF

Info

Publication number
WO2019196925A1
WO2019196925A1 PCT/CN2019/082416 CN2019082416W WO2019196925A1 WO 2019196925 A1 WO2019196925 A1 WO 2019196925A1 CN 2019082416 W CN2019082416 W CN 2019082416W WO 2019196925 A1 WO2019196925 A1 WO 2019196925A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
voltage
transistor
circuit
data
Prior art date
Application number
PCT/CN2019/082416
Other languages
English (en)
French (fr)
Inventor
徐攀
盖翠丽
林奕呈
王玲
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/607,286 priority Critical patent/US10984719B2/en
Publication of WO2019196925A1 publication Critical patent/WO2019196925A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Embodiments of the present disclosure relate to a pixel circuit unit and a driving method, a display panel, and a display device.
  • OLED organic light emitting diode
  • At least one embodiment of the present disclosure provides a pixel circuit unit including a plurality of pixel driving circuits and a voltage control circuit.
  • the voltage control circuit includes a first end and a second end, the first end of the voltage control circuit is coupled to the first voltage terminal to receive the first power voltage provided by the first voltage terminal; each of the pixels
  • the driving circuit includes a light emitting driving circuit, and the light emitting driving circuit includes a power voltage receiving end and a control end, and a power voltage receiving end of each of the pixel driving circuit is electrically connected to the second end of the voltage control circuit,
  • the power supply voltage receiving end of the light emitting driving circuit of each of the pixel driving circuits may receive the first power supply voltage; and the voltage control circuit is configured to be turned off during a data voltage writing phase such that each of the The power supply voltage receiving end of the light emitting driving circuit of the pixel driving circuit does not receive the first power supply voltage during the data voltage writing phase.
  • the pixel circuit unit further includes a common trace.
  • the second end of the voltage control circuit and the power supply voltage receiving end of the plurality of light emitting driving circuits of the pixel driving circuit are all connected to the common trace.
  • the common trace extends in the same direction as the arrangement of the plurality of pixel driving circuits; the common trace includes a first end and a second end; a second end of the voltage control circuit is coupled to the common trace at a first location on the common trace; the first location is located at a first end of the common trace and the common trace Between the second ends, and being a resistance midpoint between the first end and the second end of the common trace; and illuminating the two outermost two pixel drive circuits of the plurality of pixel drive circuits A power voltage receiving end of the driving circuit is respectively connected to the first end of the common trace and the second end of the common trace.
  • the voltage control circuit includes a common transistor including a first pole, a second pole, and a gate; a first pole of the common transistor as the a first end of the voltage control circuit is coupled to the first voltage terminal; a second pole of the common transistor is used as a second terminal of the voltage control circuit and a power supply voltage receiving circuit of the plurality of pixel driving circuits And electrically connecting the gate of the common transistor to the third scan signal line to receive the signal provided by the third scan signal line.
  • the light emitting driving circuit includes a driving transistor including a first pole, a second pole, and a gate; a first pole of the driving transistor as the a power supply voltage receiving end of the light emitting driving circuit is connected to the voltage control circuit; a second electrode of the driving transistor is connected to the first node as a signal output end of the light emitting driving circuit; and a gate of the driving transistor is used as The control end of the illumination driving circuit is configured to receive a data voltage.
  • the light emitting driving circuit further includes a switching transistor and a storage capacitor; the switching transistor includes a gate, a first pole, and a second pole; and the storage capacitor includes the first And a second end; the gate of the switching transistor is connected to the second scan signal line to receive the signal provided by the second scan signal line; the first pole of the switching transistor is connected to the data signal line to receive The data voltage; the second pole of the switching transistor is connected to the second node and connected to the gate of the driving transistor; and the first end of the storage capacitor is connected to the first node, the storage capacitor The second end is connected to the second pole of the switching transistor and the second node.
  • the first poles of the switching transistors of the light-emitting driving circuits of the different pixel driving circuits are connected to different data signal lines.
  • each of the pixel driving circuits further includes a detecting transistor, wherein the detecting transistor includes a first pole, a second pole, and a gate; The gate is connected to the first scan signal line to receive the signal provided by the first scan signal line; the first pole of the detection transistor is connected to the signal output end of the illumination driving circuit; and
  • the second pole of the detecting transistor of each of the pixel driving circuits is connected to the first pole of the detecting transistor of the next pixel driving circuit, and the last one of the pixel driving circuits is detected The second pole of the measuring transistor is connected to the sensing signal line.
  • the detection transistor is a bottom gate transistor.
  • the pixel circuit unit includes 3, 4, or 5 of the pixel drive circuits.
  • each of the pixel driving circuits further includes a light emitting diode, and an anode of the light emitting diode is connected to a signal output end of the light emitting driving circuit of the pixel driving circuit.
  • At least one embodiment of the present disclosure provides another pixel circuit unit including a plurality of sequentially connected pixel driving circuits and a voltage control circuit connected to the pixel driving circuit.
  • Each of the pixel driving circuits includes: a light emitting driving circuit, a detecting transistor, and a light emitting diode, and the first pole of the detecting transistor, the light emitting driving circuit, and the anode of the light emitting diode are connected through the first node;
  • the second pole of the detecting transistor in each of the pixel driving circuits is connected to the first node in the next pixel driving circuit, and the last pixel driving circuit detects
  • the second pole of the measuring transistor is connected to the sensing signal line; the gates of all the detecting transistors in the pixel circuit unit are connected to the first scanning signal line; all the light emitting driving circuits in the pixel circuit unit are the second Scanning signal lines are connected, and all of the light-emitting driving circuits are connected to the first voltage terminal through the voltage control circuit,
  • At least one embodiment of the present disclosure provides a driving method for driving the pixel circuit unit described above, including: providing an invalid signal to a control terminal of the voltage control circuit during a data voltage writing phase, such that the voltage control The circuit is disconnected during the data voltage writing phase, and the power supply voltage receiving ends of the plurality of the light emitting driving circuits do not receive the first power voltage during the data voltage writing phase.
  • the voltage control circuit includes a common transistor including a gate, a first pole and a second pole, and the first pole of the common transistor serves as the voltage
  • a first end of the control circuit is coupled to the first voltage terminal
  • a second pole of the common transistor is electrically coupled to a power supply voltage receiving end of the plurality of the light emitting driving circuits as a second end of the voltage control circuit.
  • Providing the invalid signal to the control terminal of the voltage control circuit during the data voltage writing phase includes: providing the invalid signal to a gate of the common transistor during the data voltage writing phase, such that The first end and the second end of the voltage control circuit are disconnected.
  • each of the pixel driving circuits further includes a detecting transistor, wherein the detecting transistor includes a first pole, a second pole, and a gate; and a gate of the detecting transistor
  • the pole is connected to the first scan signal line to receive the signal provided by the first scan signal; the first pole of the detecting transistor is connected to the signal output end of the light emitting driving circuit; and the last one of the pixel driving circuits
  • the second pole of the detecting transistor of each of the pixel driving circuits is connected to the first pole of the detecting transistor of the next pixel driving circuit, and the detecting transistor of the last one of the pixel driving circuits The second pole is connected to the sensing signal line.
  • the detecting phase of the pixel circuit unit includes a plurality of detecting sub-phases configured to detect a plurality of the pixel driving circuits respectively Pixel compensation data.
  • the driving method further includes: providing a detection to a control end of the illumination driving circuit of the pixel driving circuit to be detected in the plurality of pixel driving circuits during a data voltage writing phase of each of the detecting sub-phases Measuring a data voltage, and providing a shutdown data voltage to a control end of the illumination driving circuit of the other pixel driving circuits of the plurality of pixel driving circuits to acquire pixel compensation data of the pixel driving circuit to be detected.
  • the driving method further includes: providing a corresponding to a control end of the light emitting driving circuit of the plurality of pixel driving circuits, respectively, in a display phase of the pixel circuit unit Compensating pixel data, wherein the corresponding compensated pixel data is: pixel data obtained by compensating initial pixel data based on corresponding pixel compensation data.
  • At least one embodiment of the present disclosure provides another driving method for driving the pixel circuit unit described above, including: inputting a first scan to the first scan signal line during a data voltage writing phase of a detecting phase a signal, a second scan signal is input to the second scan signal line, an invalid signal is input to the third scan signal line, and a first reference voltage is input to the sense signal line to one of the plurality of data signal lines
  • the signal line inputs a detection data signal, and stores the detected data signal, and inputs a closed data signal to the remaining data signal lines of the plurality of data signal lines; during the sensing phase of the detecting phase, Inputting, by the first scan signal line, the first scan signal, inputting an invalid signal to the second scan signal line, and inputting a third scan signal to the third scan signal line to pass the first node to the sense signal Line charging; obtaining pixel compensation data via the sensing signal line during a sampling phase of the detecting phase; and at the data voltage writing phase of the display phase, to the first a scan signal line is
  • At least one embodiment of the present disclosure provides a display panel including a pixel circuit unit provided by any of the embodiments of the present disclosure.
  • the display panel includes a plurality of sub-pixels arranged in a matrix, and a plurality of pixel driving circuits in the pixel circuit unit are in one-to-one correspondence with the plurality of sub-pixels;
  • adjacent sub-pixels of different colors constitute one pixel unit; and a plurality of sub-pixels in one of the pixel units are in one-to-one correspondence with a plurality of pixel driving circuits in one of the pixel circuit units;
  • the pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel; or the pixel unit includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel; or the pixel unit includes a red sub-pixel Pixels, green sub-pixels, blue sub-pixels, cyan sub-pixels, yellow sub-pixels.
  • At least one embodiment of the present disclosure further provides a display device including a pixel circuit unit or a display panel provided by any of the embodiments of the present disclosure.
  • 1 is a schematic structural view of a pixel driving circuit
  • FIG. 2 is a schematic structural diagram of a pixel circuit unit according to an embodiment of the present disclosure
  • FIG. 3 is a driving timing diagram of a pixel circuit unit according to an embodiment of the present disclosure.
  • FIG. 4 is a voltage analog signal diagram of a first node of a pixel circuit unit according to an embodiment of the present disclosure
  • FIG. 5 is an equivalent circuit of a voltage terminal, a driving transistor, and a detecting transistor according to an embodiment of the present disclosure
  • FIG. 6 is another schematic structural diagram of a pixel circuit unit according to an embodiment of the present disclosure.
  • a pixel drive circuit e.g., a pixel circuit
  • OLED display devices For display devices (e.g., OLED display devices), a pixel drive circuit (e.g., a pixel circuit) needs to be provided for each sub-pixel to drive OLED illumination in a sub-pixel to achieve normal display.
  • a pixel drive circuit e.g., a pixel circuit
  • OLED display devices have problems of display unevenness and/or slower compensation speed. An exemplary explanation will be given below in conjunction with FIG. 1.
  • FIG. 1 shows a pixel circuit unit of a display device (eg, OLED) display device.
  • the pixel circuit unit includes a plurality of pixel driving circuits 10, such as a 3T1C pixel circuit, that is, a pixel circuit including three transistors and one capacitor.
  • the pixel driving circuit includes a switching transistor SW, a driving transistor DR, a detecting transistor SE, and a storage capacitor Cst.
  • the pixel driving circuit shown in FIG. 1 also shows a light emitting element OLED.
  • the second electrode of the driving transistor DR, the first electrode of the detecting transistor SE, the first end of the storage capacitor Cst, and the anode of the light emitting element OLED are both connected to the first node S;
  • the first of the driving transistor DR a gate of the switching transistor SW and a gate of the detecting transistor SE are respectively connected to the first voltage terminal, the first scanning signal line and the second scanning signal line, and the cathode of the light emitting element OLED can be connected to the second voltage terminal (in the figure) Connected, not connected, the second voltage provided by the second voltage terminal is less than the first voltage provided by the second voltage terminal.
  • a plurality of detection transistors SE in the plurality of pixel driving circuits 10 may be respectively connected to the sensing line Sense_Line, and the sensing line Sense_Line has a parasitic capacitance (not labeled in FIG. 1).
  • One end of the sense line Sense_Line can be connected to a reference voltage terminal or an analog to digital converter ADC.
  • one end of the sensing line Sense_Line may be connected to the reference voltage terminal to write the reference voltage (for example, the standard voltage Vref in the following) provided by the reference voltage terminal to the first a node S; at the sensing signal sampling stage of the pixel circuit unit, one end of the sensing line Sense_Line may be connected to the analog to digital converter to convert the sensing signal (analog signal) acquired from the first node S into a digital signal .
  • the reference voltage for example, the standard voltage Vref in the following
  • the OLED display device may have display abnormality (for example, display unevenness) due to a change in characteristics of the thin film transistor (for example, a driving transistor) or a different driving transistor characteristic, and therefore, in the related art,
  • the pixel driving circuit in each sub-pixel can be compensated (for example, the threshold voltage of the driving transistor of the pixel driving circuit is compensated by an electrical compensation method), as shown in FIG. 1, the sensing signal line Sense_Line and the detecting transistor can be controlled.
  • the SE compensates for the threshold voltage of the driving transistor of each pixel driving circuit in the pixel circuit unit to reduce display unevenness.
  • the inventors of the present disclosure have noticed that there is a problem that the voltage of the first node S of the pixel circuit unit shown in FIG. 1 is inaccurate and/or not fixed.
  • the specific analysis is as follows. When a voltage is written to the first node S of the pixel circuit unit as shown in FIG. 1, the plurality of pixel driving circuits 10 in the pixel circuit unit are directly connected to the first voltage terminal ELVDD through different driving transistors DR, respectively. Connecting, so that a current is generated in the driving transistor DR at the moment when the pixel data is written by the switching transistor SW, respectively.
  • the generated current flows from the driving transistor DR through the detecting transistor SE and the sensing line, and flows to a sensing module (eg, a sensing integrated chip) or a reference voltage terminal (eg, a potential of the sensing module or the reference voltage terminal is a standard voltage Vref); for example, the generated current may also flow through the light emitting element OLED; in this case,
  • the equivalent circuit of the voltage terminal ELVDD, the driving transistor DR and the detecting transistor SE is as shown in FIG. 5 (R_D and R_S shown in FIG.
  • the driving transistor DR and the detecting transistor SE are equivalent resistances of the driving transistor DR and the detecting transistor SE, respectively), that is, driving The transistor DR and the detecting transistor SE divide a voltage difference between the first voltage terminal ELVDD and the sensing module such that the voltage of the first node S (the anode voltage of the OLED) and the sensing module or the reference power
  • the voltage terminals are not equal by the standard voltage Vref provided by the Sense_Line (the voltage of the first node S is greater than the standard voltage Vref), thereby causing the gray scale inaccuracy of the actual display of the display pixels including the pixel circuit unit.
  • the inventors of the present disclosure also note that the voltage of the first node S (the anode voltage of the OLED) will also increase as the data voltage increases (this is because the drive current increases as the data voltage increases) This causes the voltage of the first node S to be unfixed and deteriorates the inaccuracy of the gray scale displayed by the display pixels including the pixel circuit unit.
  • the inventors of the present disclosure also note that since the plurality of pixel driving circuits 10 in the pixel circuit unit are respectively connected to the same Sense_Line in parallel by different detecting transistors SE, and the detecting transistor SE itself has a certain parasitic
  • the capacitance (gate-source capacitance Cgs, gate-drain capacitance Cgd) causes the total capacitance on the Sense_Line to increase, causing the time required for the capacitor on the Sense_Line to charge to the target capacitance to increase, which in turn causes the actual compensation speed to decrease, resulting in electrical compensation.
  • the method has limited ability to improve the display picture unevenness problem.
  • At least one embodiment of the present disclosure provides a pixel circuit unit including a pixel driving circuit and a voltage control module.
  • the voltage control circuit includes a first end and a second end, the first end of the voltage control circuit is connected to the first voltage end to receive the first power voltage provided by the first voltage terminal;
  • the pixel driving circuit comprises a light emitting driving circuit, and the light emitting driving circuit
  • the power voltage receiving end and the control end are included, and the power voltage receiving end of the light emitting driving circuit is electrically connected to the second end of the voltage control circuit, so that the power voltage receiving end of the light emitting driving circuit can receive the first power voltage;
  • the voltage control circuit is configured to The data voltage writing phase is turned off so that the power supply voltage receiving end of the light emitting driving circuit does not receive the first power supply voltage during the data voltage writing phase.
  • pixel circuit units provided by the embodiments of the present disclosure are described below by way of a few examples, and as described below, different features in these specific examples may be combined with each other without conflicting with each other, thereby obtaining a new example. These new examples are also within the scope of the disclosure.
  • FIG. 2 shows a schematic diagram of a pixel circuit unit provided by an embodiment of the present disclosure
  • FIG. 6 shows another schematic diagram of a pixel circuit unit according to an embodiment of the present disclosure.
  • the pixel circuit unit 01 includes a plurality of sequentially connected pixel driving circuits 10 and a voltage control module 20 (for example, a voltage control circuit) connected to the plurality of pixel driving circuits 10.
  • a voltage control module 20 for example, a voltage control circuit
  • the pixel circuit unit 01 includes four pixel driving circuits 10, but the embodiment of the present disclosure is not limited thereto.
  • the pixel circuit unit 01 may also include three or five or other applications.
  • a number of pixel drive circuits 10. The following examples are all further illustrating the embodiment of the present disclosure by taking the pixel circuit unit 01 of FIG. 2 including four pixel driving circuits 10 as an example.
  • each pixel driving circuit 10 includes: a light emitting driving module 101 (for example, a light emitting driving circuit), a detecting transistor SE, and a light emitting diode 102 (ie, an organic light emitting diode OLED), and detecting a transistor.
  • a light emitting driving module 101 for example, a light emitting driving circuit
  • a detecting transistor SE for example, a detecting transistor
  • a light emitting diode 102 ie, an organic light emitting diode OLED
  • the first pole of the SE, the light-emitting drive module 101, and the anode of the light-emitting diode 102 are connected by a first node S.
  • the pixel circuit unit may also not include the light emitting diode 102.
  • the above four pixel driving circuits 10 may be respectively used to drive a light emitting diode emitting red light, a light emitting diode emitting green light, a light emitting diode emitting blue light, and a light emitting diode emitting white light.
  • the pixel circuit unit can also be used to drive other suitable light-emitting elements.
  • the anode end of the light-emitting element is connected to the first node S.
  • a plurality of detecting transistors SE in the plurality of pixel driving circuits 10 may be connected in series to each other and to the sensing line Sense_Line.
  • the second node of the detecting transistor SE of all the pixel driving circuits 10 and the first node S of the next pixel driving circuit 10 The second pole of the detecting transistor SE in the last pixel driving circuit 10 is connected to the sensing signal line Sense_Line; that is, the detecting transistor SE in the pixel driving circuit 10 sequentially disposed in the pixel circuit unit 01 is a serial structure.
  • the source of one of the plurality of detection transistors SE of the plurality of pixel driving circuits 10 is connected to the drain of the detection transistor SE adjacent thereto.
  • the capacitance on the sensing signal lines is reduced, thereby increasing the compensation speed.
  • M detection transistors SE are connected to each sensing line, and the gate-source capacitance of each detection transistor is Cgs
  • each of the M detection transistors SE is connected to each sensing line.
  • the line and the detecting transistor are M ⁇ Cgs; when the M detecting transistors SE are connected in series to each sensing line, each sensing line and the detecting transistor are Cgs, and therefore, by setting each pixel
  • the detecting transistor in the driving circuit is connected in series with the sensing signal line, which reduces the capacitance on the sensing signal line.
  • the sensing line Sense_Line has a parasitic capacitance Line_Cap.
  • One end of the sensing line Sense_Line may be connected to the reference voltage terminal Vref or an analog to digital converter, and a switch EN is disposed between one end of the sensing line Sense_Line and the reference voltage terminal Vref, and one end of the sensing line Sense_Line and the analog to digital converter A switch SA is provided.
  • the switch EN can be turned on, and one end of the sensing line Sense_Line is connected to the reference voltage terminal to write the reference voltage provided by the reference voltage terminal to the first node S;
  • the sensing signal sampling phase of the pixel circuit unit may cause the switch SA to be turned on, and one end of the sensing line Sense_Line is connected to the analog-to-digital converter to convert the sensing signal (analog signal) acquired from the first node S into a digital signal.
  • the gates of all the detecting transistors SE may be connected to the first scanning signal line G1 to receive the signal supplied from the first scanning signal line G1 (for example, The first scan signal), the signal provided by the first scan signal line G1 can be used to control the on state (on or off) of the plurality of detection transistors SE.
  • the first scan signal is a valid signal (active level).
  • the effective signal (active level) refers to a signal (level) at which a transistor that receives the effective signal (active level) is turned on.
  • all the light-emitting driving modules 101 are connected to the second scanning signal line G2 to receive the signal (for example, the second scanning signal) provided by the second scanning signal line G2; all the light-emitting driving modules 101 is electrically connected to the first voltage terminal ELVDD through the voltage control module 20, and the voltage control module 20 is connected to the third scan signal line G3 to control the illumination in response to a signal (eg, a third scan signal) provided by the third scan signal line G3.
  • the first scan signal and the third scan signal are both valid signals (active levels).
  • different illumination driving modules 101 can be connected to different data signal lines DAT.
  • the size simplification circuit of the wiring area can be reduced.
  • the gates of all the detecting transistors SE are not limited to the same first scanning signal line G1, and the gates of the different detecting transistors SE may be different from the first scanning signal lines, as long as different first scanning signal lines are present.
  • the signals are provided identical to each other.
  • the different light-emitting driving modules 101 are connected to different second scanning signal lines G2 as long as the signals provided on the different second scanning signal lines G2 are identical to each other.
  • the light-emitting driving module shown in FIG. 1 is directly connected to the first voltage terminal, and the detection transistor in each pixel driving circuit is connected in parallel with the sensing signal line.
  • the embodiment of the present disclosure passes through the problem that the voltage of the anode of the diode has an error (the actual luminance of the light is inaccurate) and the compensation speed due to the excessive capacitance on the line of the sensing signal due to the parasitic capacitance of each detecting transistor itself is low.
  • a voltage control module is disposed between the light-emitting driving module and the first voltage end to avoid or reduce the error of the voltage of the anode of the light-emitting diode, so that the actual light-emitting brightness of the light-emitting diode is more accurate; and, by setting the detection in each pixel driving circuit
  • the measuring transistor is connected in series with the sensing signal line, which reduces the capacitance on the sensing signal line, thereby improving the compensation speed; that is, the pixel circuit unit provided by some examples of the present disclosure can accurately and quickly perform sub-pixels. Effective electrical compensation.
  • voltage control module 20 can include a common transistor COM.
  • the gate of the common transistor COM is connected to the third scan signal line G3 to receive the signal provided by the third scan signal line G3, and the first end of the common transistor COM is connected to the first voltage terminal ELVDD as the first end of the voltage control circuit.
  • the second pole of the common transistor COM serves as the second end of the voltage control circuit and all the light emitting driving modules 10 in the pixel circuit unit 01 (the power voltage receiving of all the light emitting driving modules 10)
  • the terminals are connected such that the power supply voltage receiving ends of all of the light-emitting drive modules 10 can receive the first power supply voltage.
  • the common transistor COM is configured to control whether the first voltage supplied from the first voltage terminal ELVDD is supplied to the power source voltage receiving end of all of the light-emitting driving modules 10 in the pixel circuit unit 01 in response to a signal supplied from the third scanning signal line G3. For example, when the signal supplied from the third scan signal line G3 is a valid signal (for example, a third scan signal), the common transistor COM is configured to supply the first voltage supplied from the first voltage terminal ELVDD to all of the pixel circuit units 01.
  • the common transistor COM when the signal supplied from the third scanning signal line G3 is an invalid signal, the common transistor COM is configured to not supply the first voltage supplied from the first voltage terminal ELVDD to the pixel circuit unit 01 The power supply voltage receiving end of any of the light-emitting drive modules 10.
  • a transistor may be separately provided for each of the light-emitting driving modules to control the switching between the light-emitting driving module 101 and the first voltage terminal ELVDD.
  • the above-mentioned one common transistor COM and all may be used. The manner in which the light-emitting drive module 101 is connected.
  • the light-emitting diode connected to the signal output end of the light-emitting driving module 101 can be controlled by controlling the intensity of the driving current generated in the light-emitting driving module 101.
  • the brightness of the anode of the light emitting diode ie, the first node
  • the light emitting driving module 101 can be implemented as 2T1C (ie, The two capacitors and one storage capacitor circuit structure can also be implemented as a 3T1C circuit structure or other suitable circuit structure according to actual needs.
  • the specific arrangement of the light-emitting driving module 101 is not specifically limited in the embodiment of the present disclosure.
  • an embodiment of the present disclosure provides an illumination driving module implemented as a 2T1C circuit.
  • the illumination driving module includes a switching transistor SW, a driving transistor DR, and a storage capacitor Cst.
  • the gate of the switching transistor SW is connected to the second scanning signal line G2 to receive a signal (for example, a second scanning signal) provided by the second scanning signal line; and the first pole of the switching transistor SW Connected to the data signal line DAT to receive a data voltage (eg, detecting a data voltage, turning off the data voltage, or compensating for a pixel voltage); the second pole of the switching transistor SW is coupled to the second node G.
  • a signal for example, a second scanning signal
  • a data voltage eg, detecting a data voltage, turning off the data voltage, or compensating for a pixel voltage
  • the gate of the driving transistor DR (as a control terminal of the light emitting driving circuit) is connected to the second node G and the second electrode of the switching transistor, and is configured to receive a data voltage (for example, detecting a data voltage, a data voltage is turned off, or a pixel voltage is compensated;
  • the first pole of the driving transistor DR is connected to the power source voltage receiving end of the light emitting driving circuit and the second end of the voltage control module (for example, the second pole of the common transistor COM)
  • the second pole of the drive transistor DR is connected to the first node S as a signal output terminal of the light-emitting drive circuit.
  • the first end of the storage capacitor Cst is connected to the first node S, and the second end of the storage capacitor Cst is connected to the second pole of the switching transistor and the second node G.
  • the voltage control circuit is configured to be turned off during the data voltage writing phase such that the power supply voltage receiving end of the light emitting driving circuit does not receive the first power supply voltage during the data voltage writing phase.
  • a valid signal may be supplied to the gate of the detecting transistor SE via the first scan line G1
  • a valid signal may be supplied to the gate of the switching transistor SW via the second scan line G2, and may be via the third
  • the scan line G3 provides an invalid signal to the control terminal of the voltage control circuit; in this case, the data voltage received by the first end of the switching transistor SW (eg, detecting the data voltage, turning off the data voltage, or compensating the pixel voltage) can be turned on.
  • the switching transistor SW is supplied to the gate of the driving transistor DR, and the reference voltage supplied from the reference voltage terminal can be supplied to the second pole of the driving transistor DR via the sensing signal line and the conducting detecting transistor SE; since the voltage control circuit is disconnected, The power supply voltage receiving end of the light emitting driving circuit is not capable of receiving the first power supply voltage during the data voltage writing phase, so no driving current is generated in the driving transistor DR, and therefore, the voltage of the first node S and the first end of the switching transistor SW and the driving
  • the data voltage received by the gate of the transistor DR is independent, and the voltage difference between the gate and the second pole of the driving transistor DR is more accurate. Indeed, in turn, the gray scale accuracy of the display pixels including the pixel circuit unit and the brightness accuracy of the display panel and the display device including the pixel circuit unit can be improved.
  • the pixel circuit unit further includes a common trace 110.
  • the second end of the voltage control circuit eg, the second pole of the common transistor COM
  • the power supply voltage receiving end of the light emitting driving circuit of the plurality of pixel driving circuits eg, the first pole of the driving transistor DR
  • the trace design of the pixel circuit unit can be simplified.
  • the direction in which the common traces 110 extend may be the same as the direction in which the plurality of pixel drive circuits 10 are arranged (for example, both in the horizontal direction shown in FIG. 6).
  • the direction in which the plurality of pixel drive circuits 10 are arranged for example, both in the horizontal direction shown in FIG. 6.
  • the common trace 110 includes a first end 111 and a second end 112; the second end of the voltage control circuit is connected to the common trace 110 at a first location 113 on the common trace; Between the first end of the common trace and the second end of the common trace; the first end of the plurality of pixel drive circuits at the power supply voltage receiving end of the outermost two pixel drive circuits and the first end of the common trace Connected to the second end of the common trace; the power supply voltage receiving ends of the remaining pixel drive circuits of the plurality of pixel drive circuits are respectively connected to the common terminal between the first end of the common trace and the second end of the common trace line.
  • the first location may be the midpoint of the resistance between the first end and the second end of the common trace.
  • the "resistance midpoint" refers to a point between two points on the trace such that the resistances to the two points are equal.
  • the first end and the second end of the common trace may be two physical ends of the common trace, but embodiments of the present disclosure are not limited thereto, the first end of the common trace and the first The two ends can also be located between the two physical ends of the common trace.
  • the first position of the common trace may be the physical midpoint of the common trace, that is, the point on the common trace that is equal to the distance between the first end and the second end of the common trace.
  • the light-emitting drive circuit of the plurality of pixel drive circuits can be made in the case of simplifying the trace design of the pixel circuit unit
  • the voltage received by the power supply voltage receiving terminal is closer, whereby the display uniformity of the display panel and the display device including the pixel circuit unit can be further improved.
  • the detection transistor SE may be a bottom gate transistor or a top gate transistor. This embodiment of the present disclosure does not limit this; however, both the bottom gate transistor and the top gate transistor have parasitic capacitance.
  • the detecting transistor SE is a bottom gate type transistor
  • the source drain and the gate there is a registration error between the source drain and the gate, taking into account the critical dimension deviation (CD BIAS) caused by the wet etching process, and to ensure source leakage.
  • CD BIAS critical dimension deviation
  • the source drain and the gate have a large overlap area in the design, resulting in a parasitic gate source capacitance Cgs and gate in the transistor.
  • the leakage capacitance Cgd will be relatively large.
  • the parasitic gate-source capacitance Cgs and the gate-drain capacitance Cgd are also present in the transistor due to the problem of the accuracy of the conductor process. .
  • the parasitic capacitance C Sense on the sense signal line Sense_Line satisfies the following relationship:
  • C Line is a capacitance formed by the intersection of the sensing signal line Sense_Line and other metal wires;
  • C SE-Cgs is a parasitic capacitance (at least one of Cgs and Cgd) of the detecting transistor SE connected to the sensing signal line Sense_Line.
  • C SE-Cgs C SE4-Cgs , also That is, among the four detecting transistors SE of the four pixel driving circuits in the pixel circuit unit, only one detecting transistor SE connected to the sensing signal line Sense_Line (for example, the fourth from left to right in FIG. 2) The parasitic capacitance is applied to the sense signal line Sense_Line; the parasitic capacitance of the other detection transistors SE is not applied to the sense signal line Sense_Line.
  • the parasitic capacitance of the detecting transistor SE connected to the sensing signal line Sense_Line can be reduced by about 75%.
  • the parasitic capacitance of the detecting transistor SE in the bottom gate type detecting transistor SE accounts for more than 50% of the total parasitic capacitance on the sensing signal line Sense_Line
  • the pixel circuit unit including the bottom gate type detecting transistor SE is particularly applicable.
  • the design in the disclosed embodiment For example, for the two pixel circuit units of Figures 1 and 2, the C Lines of the two are approximately equal.
  • the line capacitance on the sensing signal line Sense_Line can be reduced, thereby increasing the charging speed of the sensing signal line Sense_Line, thereby increasing the compensation speed.
  • the process (ie, the detection process) is performed in a blank period, and the more times the battery is charged to the target voltage during that time period, the faster the compensation speed can be made.
  • the capacitance on the sensing signal line Sense_Line is large, so that the time to charge to the target voltage is long, it may be performed, for example, only once in a blank period (Blank).
  • Charging that is, detecting a pixel driving circuit in the pixel circuit unit; in contrast, since the capacitance on the sensing signal line Sense_Line shown in FIG. 2 and FIG. 6 is small, the time for charging to the target voltage is compared. Short, then multiple charges (eg, 4 or more times) can be completed within a blank period, that is, four pixel drive circuits in the pixel circuit unit can be completed in one blank period (Blank) Detection.
  • the driving transistor DR since the driving transistor DR is directly connected to the first voltage terminal ELVDD, the data voltage (for example, pixel data) is written at the moment of writing the data signal line DAT.
  • a current is generated in the transistor DR, for example, a generated current flows from the driving transistor DR through the detecting transistor SE and the sensing line, and flows to a sensing module (eg, a sensing integrated chip) or a reference voltage terminal (eg, sensing)
  • the potential of the module or the reference voltage terminal is the standard voltage Vref); for example, the generated current may also flow through the light emitting element OLED, and the driving transistor DR and the detecting transistor SE divide the voltage difference between the first voltage terminal ELVDD and the sensing module.
  • the driving transistor DR in the pixel circuit unit in some embodiments of the present disclosure
  • the common transistor COM is connected to the first voltage terminal ELVDD, and the common transistor COM is used to control the on and off between the driving transistor DR and the first voltage terminal ELVDD, thereby avoiding or suppressing the occurrence of the pixel circuit unit shown in FIG.
  • the compensation signal obtained during the sensing phase is inaccurate due to a change (or not fixed) of the voltage of one node S and/or the inaccuracy of the gate-source voltage during the writing phase, thereby alleviating the problem of inaccurate gray scale display.
  • a common transistor can be made by writing a pixel data (eg, a data voltage) through the data signal line DAT by causing the driving transistor DR to be connected to the first voltage terminal ELVDD through the common transistor COM.
  • the COM is in an off state, at which time no current flows through the driving transistor DR, and the voltage of the first node S is independent of the pixel data (for example, data voltage) written by the data signal line DAT.
  • the voltage of the first node S can be fixed. The voltage, which improves the accuracy of displaying grayscale writes.
  • the voltages of the first nodes S of all the pixel driving circuits 10 are fixed voltages, and the voltages of the first nodes S of the different pixel driving circuits 10 are different from each other.
  • FIG. 2 and FIG. 6 can be made.
  • the second poles of the plurality of detecting transistors are respectively connected to the sensing signal lines; correspondingly, the plurality of pixel driving circuits 10 included in the pixel circuit unit 01 are arranged side by side without being sequentially connected.
  • the pixel circuit unit 01 is not limited to include a plurality of pixel driving circuits 10. According to actual application requirements, the pixel circuit unit 01 may further include only one pixel driving circuit 10 provided by the embodiment of the present disclosure. In this case, the pixel circuit The compensation effect of unit 01 is still improved. For example, the pixel circuit unit 01 may further include a plurality of associated pixel circuits directly connected to the first voltage terminal.
  • the power supply voltage receiving end of the light emitting driving circuit of the plurality of pixel driving circuits 10 and the second end of the voltage control circuit 20 provided by some embodiments of the present disclosure are not limited to being connected to the common trace 110, respectively, in the light emitting driving circuit. In the case where the voltage drop between the power supply voltage receiving end and the voltage control circuit 20 is small, the common trace 110 may not be provided. In this case, the power supply voltage receiving end of the light emitting driving circuit of the plurality of pixel driving circuits 10 is directly Connected to the second end of voltage control circuit 20.
  • the voltage control circuit 20 is not limited to being implemented as a common transistor, and the voltage control circuit 20 can also be implemented such that the other end having the control voltage control circuit 20 is electrically connected to the power supply voltage receiving end of the light emitting driving circuit of the pixel driving circuit 10. Functional circuit.
  • the pixel driving circuit 10 provided by some embodiments of the present disclosure is not limited to the 3T1C pixel circuit shown in FIG. 2 and FIG. 6, and may be implemented as a 3T2C pixel circuit, a 7T1C pixel circuit, or other applicable pixels according to actual application requirements.
  • the circuit is electrically connected to the first voltage terminal via the voltage control circuit as long as the power supply voltage receiving end of the light emitting driving circuit of the pixel driving circuit 10.
  • Vref represents both a reference voltage terminal and a reference voltage.
  • At least one embodiment of the present disclosure also provides another pixel circuit unit.
  • the method includes a plurality of pixel driving circuits, each of the pixel driving circuits includes a light emitting driving circuit and a detecting transistor, and the light emitting driving circuit includes a signal output end, the detecting transistor includes a first pole, a second pole and a gate; and the gate of the detecting transistor
  • the pole is connected to the first scan signal line to receive the signal provided by the first scan signal line; the first pole of the detecting transistor is connected to the signal output end of the light emitting driving circuit; and each pixel except the last pixel driving circuit
  • the second pole of the detecting transistor of the driving circuit is connected to the first pole of the detecting transistor of the next pixel driving circuit, and the second pole of the detecting transistor of the last pixel driving circuit is connected with the sensing signal line.
  • At least one embodiment of the present disclosure also provides a driving method of a pixel circuit unit that supplies an invalid signal to a control terminal of a voltage control circuit during a data voltage writing phase, so that the voltage control circuit is disconnected during a data voltage writing phase.
  • the power supply voltage receiving end of the light-emitting drive circuit does not receive the first power supply voltage during the data voltage writing phase.
  • providing an invalid signal to the control terminal of the voltage control circuit includes: providing an invalid signal to the gate of the common transistor during the data voltage writing phase, so that the first end and the second of the voltage control circuit The end is disconnected.
  • the detection phase of the pixel circuit unit includes a plurality of detection sub-phases, and the plurality of detection sub-phases are configured to respectively detect pixel compensation data of the plurality of pixel driving circuits; and the driving method includes: data in each detection sub-phase In the voltage writing phase, the detection data voltage is supplied to the control terminal of the light-emitting driving circuit of the pixel driving circuit to be detected in the plurality of pixel driving circuits, and is applied to the light-emitting driving circuit of the other pixel driving circuit of the plurality of pixel driving circuits.
  • the control terminal provides a shutdown data voltage. For example, turning off the data voltage is a voltage that causes the light-emitting drive circuit (drive transistor) to be turned off, and the off data voltage is, for example, an invalid voltage.
  • the driving method further includes: providing compensation pixel data to the control ends of the light emitting driving circuits of the plurality of pixel driving circuits respectively in the display phase of the pixel circuit unit, wherein the compensation pixel data of each of the light emitting driving circuits is: based on pixel compensation Pixel data obtained after the data is compensated for the initial pixel data.
  • FIG. 3 is a driving timing chart of the pixel circuit unit shown in FIGS. 2 and 6.
  • the pixel circuit unit includes a display phase and a detection phase
  • the detection phase includes a plurality of detection sub-phases, each of which is used for detecting pixel compensation of a pixel driving circuit of the plurality of pixel driving circuits.
  • Data for example, a threshold voltage of a driving transistor of a pixel driving circuit.
  • each detection sub-phase includes a data writing phase, a sensing phase, and a sampling phase.
  • FIG. 3 only shows one detection sub-phase of the detection phase (that is, the detection phase shown in FIG. 3).
  • multiple detection sub-phases are sequentially arranged in time (eg, consecutively arranged).
  • the driving method includes the following steps 101, 102, 103, 201, and 202.
  • Step 101 Input a first scan signal (a valid signal) to the first scan signal line G1 during a data writing phase (ie, a DAT_IN' phase) of the detection phase (in a detection sub-phase of the detection phase), Inputting a second scan signal (active signal) to the second scan signal line G2, inputting an invalid signal to the third scan signal line G3, and inputting a first reference voltage (for example, a reference voltage Vref) to the sense signal line Sense_Line to a plurality of data
  • a first reference voltage for example, a reference voltage Vref
  • the first scan signal is input to the first scan signal line G1
  • the second scan signal is input to the second scan signal line G2
  • the switch transistor SW and The detecting transistor SE is turned on, at which time the reference voltage Vref input to the sensing signal line Sense_Line is written to the first node S, and one of the four data signal lines connected to the four pixel driving circuits (driven with the pixel to be detected)
  • the data signal line connected to the circuit is input to the storage capacitor Cst; the remaining data signal lines are input with a 0V voltage signal.
  • the first electrode of the driving transistor DR does not receive the first voltage, and the driving transistor DR does not generate a driving current, thereby being able to improve writing to the pixel via the sensing signal line Sense_Line
  • the accuracy of the voltage at the signal output end of the driving circuit that is, the voltage of the first node S
  • the pixel compensation data of the pixel driving circuit acquired via the sensing signal line Sense_Line for example, the threshold voltage of the driving transistor of the pixel driving circuit
  • the accuracy can thereby improve the accuracy of the gate-source voltage Vgs of the driving transistor DR during the data writing phase DAT_IN of the display phase.
  • Step 102 In the sensing phase of the detecting phase (in a detecting sub-phase of the detecting phase), input a first scan signal (active signal) to the first scan signal line G1, and input invalid to the second scan signal line G2. a signal, a third scan signal (effective signal) is input to the third scan signal line G3, and the drive transistor DR charges the sense signal line Sense_Line through the first node S so that the detection phase can be detected (a detection phase is detected) The sampling phase of the sub-phase can acquire pixel compensation data via the sensing signal line Sense_Line.
  • the detection transistor is enabled by inputting the first scan signal to the first scan signal line G1 and the third scan signal to the third scan signal line G3.
  • the SE and the common transistor COM are turned on.
  • the sensing signal line Sense_Line can be charged through the first node S based on the data voltage stored in the storage capacitor Cst, so that the detection connected to the sensing signal line Sense_Line can be utilized after the charging is completed.
  • the IC Integrated Circuit
  • Step 103 In the sampling phase Samp of the detection phase (in a detection sub-phase of the detection phase), input an invalid signal to the first scanning signal line G1, and input an invalid signal to the second scanning signal line G2 to the third scanning.
  • the signal line G3 inputs a third scan signal (a valid signal).
  • the detecting transistor SE can be turned off during the sampling phase, so that the pixel compensation data acquired via the sensing signal line Sense_Line is more accurate.
  • steps 101-103 may be separately performed for the plurality of pixel driving circuits to obtain pixel compensation of the plurality of pixel driving circuits.
  • Data for example, a threshold voltage of a driving transistor of a plurality of pixel driving circuits.
  • Step 201 In the data writing phase DAT_IN of the display phase, input a first scan signal (effective signal) to the first scan signal line G1, and input a second scan signal (effective signal) to the second scan signal line G2, to the third
  • the scanning signal line G2 inputs an invalid signal, and inputs a second reference voltage (for example, a reference voltage Vref) to the sensing signal line Sense_Line, and inputs corresponding compensation pixel data to different data signal lines DAT and stores them respectively;
  • the pixel data is compensated (
  • the compensated pixel data voltage is: pixel data obtained by compensating the initial pixel data according to the corresponding pixel compensation data.
  • the initial pixel data is pixel data before compensation.
  • the first scan signal is input to the first scan signal line G1
  • the second scan signal is input to the second scan signal line G2
  • the switch transistor SW and the detection are performed.
  • the transistor SE is turned on
  • the reference voltage Vref input to the sensing signal line Sense_Line is written to the first node S
  • the compensation pixel data respectively input to the four data signal lines connected to the four pixel driving circuits are respectively stored and corresponding.
  • the compensation pixel data is: pixel data obtained by compensating the initial pixel data according to the pixel compensation data acquired in the detection phase.
  • the first electrode of the driving transistor DR does not receive the first voltage, and the driving transistor DR does not generate the driving current, thereby improving
  • the accuracy of the voltage (ie, the voltage of the first node S) written to the signal output terminal of the pixel driving circuit via the sensing signal line Sense_Line can thereby further improve the accuracy of the gate voltage Vgs of the driving transistor DR.
  • Step 202 In the effective display phase of the display phase (ie, the Disp phase), input an invalid signal to the first scan signal line G1, an invalid signal to the second scan signal line G2, and a third input to the third scan signal line G3.
  • the scanning signal (effective signal) is used to drive the LEDs of the plurality of pixel driving circuits to emit light according to the corresponding compensation pixel data.
  • a third scan signal is input to the third scan signal line G3, and the common transistor COM is turned on.
  • the compensated pixel data stored by the drive transistor DR at the storage capacitor Cst is The conduction is turned on, whereby the light emitting diode can be driven to emit light.
  • the above description of the transistor turning on and off in FIG. 2 is performed by taking all transistors as N-type transistors as an example, but the embodiments of the present disclosure are not limited thereto, and all the transistors in FIG. 2 are also It can be a P-type transistor.
  • the control signals in Figure 3 need to be flipped at this time.
  • FIG. 3 only shows a display phase and a detection phase. It should be understood that the display phase is still after the detection phase, and the compensation pixel data used in the display phase is according to the display phase. Obtained in the previous detection phase; in addition, the sample phase and the display phase in FIG. 3 are independent in timing, and FIG. 3 is only a schematic illustration.
  • the third scan signal line does not provide a scan signal (ie, the signal on the third scan signal line is not invalid).
  • the common transistor COM is in an off state.
  • the voltage Vs of the different first node S is independent of the size of the pixel data input by the data signal line DAT, and does not change with the change of the pixel data (for example, the data voltage). That is, the voltage Vs of the first node S is a fixed voltage, whereby the accuracy of displaying gray scale writing can be ensured.
  • the voltage of the first node S of the pixel circuit unit shown in FIG. 1 is changed by the change of the pixel data input by the data signal line DAT, for example, when the pixel data input by the data signal line DAT is large, the driving transistor DR
  • the larger the generated current for example, the larger the current flowing through the OLED
  • the larger the voltage of the first node S is, thereby making the error of the voltage of the first node S larger.
  • the pixel circuit unit shown in FIG. 1 needs to debug each gray scale (for example, 0 to 255 gray scale);
  • the pixel circuit unit (FIG. 2 or FIG. 6) in some embodiments of the present disclosure only needs to debug one of the gray levels to ensure the accuracy of other gray levels; for example, the gray level of the selected debugging may be 127.
  • the inventors of the present disclosure further confirmed by actual simulation that the voltage Vs of the first node S is independent of the size of the pixel data input by the data signal line DAT in the embodiment of the present disclosure, and is specifically analyzed as follows.
  • Vs1, Vs2, Vs3, and Vs4 in FIG. 4 are fixed voltages of 0.2V, 0.3V, 0.4V, and 0.5V, respectively.
  • Vs1, Vs2, Vs3, and Vs4 represent the voltages of the first node S of the pixel driving circuit at the right position, the right two position, the right three position, and the right four positions in FIGS. 2 and 6, respectively. That is, the voltage value corresponding to the intersection of the vertical dotted line in FIG. 4 and the intersection of the curves in the four sub-pictures above FIG. 4).
  • Embodiments of the present disclosure also provide a display panel including the aforementioned pixel circuit unit.
  • the display panel includes a plurality of sub-pixels arranged in a matrix, and the plurality of pixel driving circuits in the pixel circuit unit are in one-to-one correspondence with the plurality of sub-pixels.
  • each of the plurality of sub-pixels includes a corresponding pixel drive circuit.
  • the structure and advantageous effects of the pixel circuit unit have been described in detail since the foregoing embodiments, and are not described herein again.
  • the display panel may specifically include at least an organic light emitting diode display panel, for example, the display panel may be applied to any display function, such as a display, a television, a digital photo frame, a mobile phone, or a tablet computer. Or in the part.
  • adjacent sub-pixels of different colors constitute one pixel unit; a plurality of sub-pixels in one pixel unit are in one-to-one correspondence with a plurality of pixel driving circuits in one pixel circuit unit; implementation of the present disclosure
  • the number of sub-pixels in the pixel unit is not limited, and the actual setting may be selected as needed.
  • the one pixel unit may include three sub-pixels of red sub-pixel R, green sub-pixel G, and blue sub-pixel B.
  • the pixel circuit unit includes three sequentially arranged pixel driving circuits, respectively It is in one-to-one correspondence with the adjacent red sub-pixel R, green sub-pixel G, and blue sub-pixel B.
  • the pixel unit further includes sub-pixels of four colors of red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W.
  • the pixel circuit unit includes four sequentially arranged pixels.
  • the driving circuit is in one-to-one correspondence with the adjacent red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W, respectively.
  • the pixel unit further includes sub-pixels of five colors of red sub-pixel R, green sub-pixel G, blue sub-pixel B, cyan sub-pixel C, and yellow sub-pixel Y.
  • the pixel circuit unit includes 5 The sequentially arranged pixel driving circuits respectively correspond to the adjacent red sub-pixel R, green sub-pixel G, blue sub-pixel B, cyan sub-pixel C, and yellow sub-pixel Y.
  • a plurality of pixel circuit units corresponding to a plurality of pixel units located in a peer may respectively adopt the same first scan signal line, the same second scan signal line, and the same third scan signal line;
  • the pixel circuit units corresponding to the pixel units of the same column may share a sensing signal line.
  • Embodiments of the present disclosure provide a display device including the foregoing display panel including the foregoing pixel circuit unit or display panel, and the structure and advantageous effects of the pixel circuit unit have been described in detail since the foregoing embodiments , will not repeat them here.

Abstract

一种像素电路单元(01)及驱动方法、显示面板、显示装置，像素电路单元(01)包括多个像素驱动电路(10)以及电压控制电路(20)，电压控制电路(20)包括第一端和第二端，电压控制电路(20)的第一端与第一电压端(ELVDD)相连，以接收第一电压端(ELVDD)提供的第一电源电压；每个像素驱动电路(10)包括发光驱动电路(101)，发光驱动电路(101)包括电源电压接收端和控制端，每个像素驱动电路(10)的发光驱动电路(101)的电源电压接收端与电压控制电路(20)的第二端电连接，以使得每个像素驱动电路(10)的发光驱动电路(101)的电源电压接收端可接收第一电源电压；电压控制电路(20)配置为在数据电压写入阶段(DAT_IN,DAT_IN')断开，以使得每个像素驱动电路(10)的发光驱动电路(101)的电源电压接收端在数据电压写入阶段(DAT_IN,DAT_IN')不接收第一电源电压，像素电路单元(01)可以提升写入到发光驱动电路(101)的信号输出端的电压的准确度。

Description

像素电路单元及驱动方法、显示面板、显示装置
对相关申请的交叉参考
本申请要求于2018年4月12日递交的中国专利申请第201810326602.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种像素电路单元及驱动方法、显示面板、显示装置。
背景技术
随着显示技术的不断提高，人们对于显示装置的要求也在不断提高，在各种显示装置中，有机发光二极管(Organic Light Emitting Diode，简称OLED)显示装置因其具有自发光、轻薄、功耗低、高对比度、大色域、可实现柔性显示等优点，已被广泛地应用于包括电脑、手机等在内的各种电子设备中。
发明内容
本公开的至少一个实施例提供了一种像素电路单元，其包括多个像素驱动电路以及电压控制电路。所述电压控制电路包括第一端和第二端，所述电压控制电路的第一端与第一电压端相连，以接收所述第一电压端提供的第一电源电压；每个所述像素驱动电路包括发光驱动电路，所述发光驱动电路包括电源电压接收端和控制端，每个所述像素驱动电路的发光驱动电路的电源电压接收端与所述电压控制电路的第二端电连接，以使得每个所述像素驱动电路的发光驱动电路的电源电压接收端可接收所述第一电源电压；以及所述电压控制电路配置为在数据电压写入阶段断开，以使得每个所述像素驱动电路的发光驱动电路的电源电压接收端在所述数据电压写入阶段不接收所述第一电源电压。
例如，在所述像素电路单元的至少一个示例中，所述像素电路单元还包 括公共走线。所述电压控制电路的第二端以及多个所述像素驱动电路的发光驱动电路的电源电压接收端均与所述公共走线相连。
例如，在所述像素电路单元的至少一个示例中，所述公共走线的延伸方向与多个所述像素驱动电路的排布方向相同；所述公共走线包括第一端和第二端；所述电压控制电路的第二端在所述公共走线上的第一位置与所述公共走线相连；所述第一位置位于所述公共走线的第一端和所述公共走线的第二端之间，且为所述公共走线的第一端和第二端之间的电阻中点；以及多个所述像素驱动电路的中排在最外侧的两个像素驱动电路的发光驱动电路的电源电压接收端分别与所述公共走线的第一端和所述公共走线的第二端相连。
例如，在所述像素电路单元的至少一个示例中，所述电压控制电路包括公共晶体管，所述公共晶体管包括第一极、第二极和栅极；所述公共晶体管的第一极作为所述电压控制电路的第一端与所述第一电压端连接；所述公共晶体管的第二极作为所述电压控制电路的第二端与多个所述像素驱动电路的发光驱动电路的电源电压接收端电连接；以及所述公共晶体管的栅极与第三扫描信号线连接，以接收所述第三扫描信号线提供的信号。
例如，在所述像素电路单元的至少一个示例中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管包括第一极、第二极和栅极；所述驱动晶体管的第一极作为所述发光驱动电路的电源电压接收端与所述电压控制电路连接；所述驱动晶体管的第二极作为所述发光驱动电路的信号输出端与第一节点连接；以及所述驱动晶体管的栅极，作为所述发光驱动电路的控制端，配置为可接收数据电压。
例如，在所述像素电路单元的至少一个示例中，所述发光驱动电路还包括开关晶体管和存储电容；所述开关晶体管包括栅极、第一极和第二极；所述存储电容包括第一端和第二端；所述开关晶体管的栅极与第二扫描信号线连接，以接收所述第二扫描信号线提供的信号；所述开关晶体管的第一极与数据信号线连接，以接收所述数据电压；所述开关晶体管的第二极与第二节点连接并与所述驱动晶体管的栅极连接；以及所述存储电容的第一端与所述第一节点连接，所述存储电容的第二端与所述开关晶体管的第二极以及所述第二节点连接。
例如，在所述像素电路单元的至少一个示例中，不同的所述像素驱动电 路的发光驱动电路的开关晶体管的第一极与不同的数据信号线连接。
例如，在所述像素电路单元的至少一个示例中，每个所述像素驱动电路还包括侦测晶体管，所述侦测晶体管包括第一极、第二极和栅极；所述侦测晶体管的栅极与第一扫描信号线连接，以接收所述第一扫描信号线提供的信号；所述侦测晶体管的第一极与所述发光驱动电路的信号输出端相连；以及除最后一个所述像素驱动电路之外，每个所述像素驱动电路的侦测晶体管的第二极与下一个所述像素驱动电路的侦测晶体管的第一极相连，所述最后一个所述像素驱动电路的侦测晶体管的第二极与感应信号线连接。
例如，在所述像素电路单元的至少一个示例中，所述侦测晶体管为底栅型晶体管。
例如，在所述像素电路单元的至少一个示例中，所述像素电路单元包括3、4或5个所述像素驱动电路。
例如，在所述像素电路单元的至少一个示例中，每个所述像素驱动电路还包括发光二极管，所述发光二极管的阳极与所述像素驱动电路的发光驱动电路的信号输出端相连。
本公开的至少一个实施例提供了另一种像素电路单元，其包括多个依次连接的像素驱动电路以及与所述像素驱动电路连接的电压控制电路。每一所述像素驱动电路包括：发光驱动电路、侦测晶体管以及发光二极管，且所述侦测晶体管的第一极、所述发光驱动电路以及所述发光二极管的阳极通过第一节点连接；除最后一个所述像素驱动电路之外，每个所述像素驱动电路中侦测晶体管的第二极与下一个像素驱动电路中的所述第一节点连接，所述最后一个像素驱动电路中的侦测晶体管的第二极与感应信号线连接；所述像素电路单元中的所有侦测晶体管的栅极均与第一扫描信号线连接；所述像素电路单元中的所有发光驱动电路均与第二扫描信号线连接，且所有发光驱动电路通过所述电压控制电路与第一电压端连接，所述电压控制电路与第三扫描信号线连接，以通过所述第三扫描信号线控制所述发光驱动电路与所述第一电压端之间的通断；不同的所述发光驱动电路与不同的数据信号线连接。
本公开的至少一个实施例提供了用于驱动上述的像素电路单元的驱动方法，其包括：在数据电压写入阶段，向所述电压控制电路的控制端提供无效信号，以使得所述电压控制电路在所述数据电压写入阶段断开，多个所述发 光驱动电路的电源电压接收端在所述数据电压写入阶段不接收所述第一电源电压。
例如，在所述驱动方法的至少一个示例中，所述电压控制电路包括公共晶体管，所述公共晶体管包括栅极，第一极和第二极，所述公共晶体管的第一极作为所述电压控制电路的第一端与所述第一电压端连接，所述公共晶体管的第二极作为所述电压控制电路的第二端与多个所述发光驱动电路的电源电压接收端电连接。在所述数据电压写入阶段，向所述电压控制电路的控制端提供所述无效信号包括：在所述数据电压写入阶段，向所述公共晶体管的栅极提供所述无效信号，以使得所述电压控制电路的第一端和第二端断开。
例如，在所述驱动方法的至少一个示例中，每个所述像素驱动电路还包括侦测晶体管，所述侦测晶体管包括第一极、第二极和栅极；所述侦测晶体管的栅极与第一扫描信号线连接，以接收第一扫描信号提供的信号；所述侦测晶体管的第一极与所述发光驱动电路的信号输出端相连；以及除最后一个所述像素驱动电路之外，每个所述像素驱动电路的所述侦测晶体管的第二极与下一个所述像素驱动电路的侦测晶体管的第一极相连，所述最后一个所述像素驱动电路的侦测晶体管的第二极与感应信号线连接。
例如，在所述驱动方法的至少一个示例中，所述像素电路单元的侦测阶段包括多个侦测子阶段，所述多个侦测子阶段配置为分别检测多个所述像素驱动电路的像素补偿数据。所述驱动方法还包括：在每个所述侦测子阶段的数据电压写入阶段，向多个所述像素驱动电路中的待检测的像素驱动电路的所述发光驱动电路的控制端提供侦测数据电压，并向多个所述像素驱动电路中的其它像素驱动电路的所述发光驱动电路的控制端提供关闭数据电压，以获取所述待检测的像素驱动电路的像素补偿数据。
例如，在所述驱动方法的至少一个示例中，所述驱动方法还包括：在所述像素电路单元的显示阶段，分别向多个所述像素驱动电路的所述发光驱动电路的控制端提供对应的补偿像素数据，其中，所述对应的补偿像素数据为：基于对应的像素补偿数据对初始像素数据进行补偿之后得到的像素数据。
本公开的至少一个实施例提供了另一种用于驱动上述的像素电路单元的驱动方法，其包括：在侦测阶段的数据电压写入阶段，向所述第一扫描信号线输入第一扫描信号，向所述第二扫描信号线输入第二扫描信号，向所述第 三扫描信号线输入无效信号，向所述感应信号线输入第一参考电压，向多个数据信号线中的一个数据信号线输入侦测数据信号，并存储所述侦测数据信号，向所述多个数据信号线中的其余数据信号线均输入关闭数据信号；在所述侦测阶段的感测阶段，向所述第一扫描信号线输入所述第一扫描信号，向所述第二扫描信号线输入无效信号，向所述第三扫描信号线输入第三扫描信号，以通过第一节点向所述感应信号线充电；在所述侦测阶段的采样阶段，经由所述感应信号线获取像素补偿数据；在显示阶段的数据电压写入阶段，向所述第一扫描信号线输入所述第一扫描信号，向所述第二扫描信号线输入所述第二扫描信号，向所述第三扫描信号线输入无效信号；向所述感应信号线输入第二参考电压，分别向不同的数据信号线输入对应的补偿像素数据，并存储所述对应的补偿像素数据；其中，所述对应的补偿像素数据为：根据对应的所述像素补偿数据对初始像素数据进行补偿后得到的像素数据；在所述显示阶段的有效显示阶段，向所述第一扫描信号线输入无效信号，向所述第二扫描信号线输入无效信号，向所述第三扫描信号线输入所述第三扫描信号，以控制所述像素电路单元驱动的发光二极管按照所述对应的补偿像素数据进行发光。
本公开的至少一个实施例提供了一种显示面板，所述显示面板包括本公开任一实施例提供的像素电路单元。
例如，在所述显示面板的至少一个示例中，所述显示面板包括呈矩阵排列的多个亚像素，所述像素电路单元中的多个像素驱动电路与所述多个亚像素一一对应；位于同行的亚像素中，相邻的不同颜色的亚像素构成一个像素单元；一个所述像素单元中多个亚像素与一个所述像素电路单元中的多个像素驱动电路一一对应；以及所述像素单元包括红色亚像素、绿色亚像素、蓝色亚像素；或者，所述像素单元包括红色亚像素、绿色亚像素、蓝色亚像素、白色亚像素；或者，所述像素单元包括红色亚像素、绿色亚像素、蓝色亚像素、青色亚像素、黄色亚像素。
本公开的至少一个实施例又再提供了一种显示装置，其包括本公开任一实施例提供的像素电路单元或者显示面板。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1为一种像素驱动电路的结构示意图；
图2为本公开的实施例提供的一种像素电路单元的结构示意图；
图3为本公开的实施例提供的一种像素电路单元的驱动时序图；
图4为本公开的实施例提供的一种像素电路单元的第一节点的电压模拟信号图；
图5为本公开的实施例提供的电压端、驱动晶体管和侦测晶体管的一种等效电路；以及
图6为本公开的实施例提供的一种像素电路单元的另一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
对于显示装置(例如，OLED显示装置)而言，需要针对每个亚像素设 置像素驱动电路(例如，像素电路)来驱动亚像素中的OLED发光，以实现正常的显示。然而，本公开的发明人在研究中注意到，一些OLED显示装置存在显示的不均匀性问题和/或补偿速度较慢的问题。下面结合图1进行示例性说明。
图1示出了一种显示装置(例如，OLED)显示装置的像素电路单元。如图1所示，该像素电路单元中包括多个像素驱动电路10，该像素驱动电路例如为3T1C像素电路，也即，包括3个晶体管和1个电容的像素电路。如图1所示，该像素驱动电路包括开关晶体管SW、驱动晶体管DR、侦测晶体管SE和存储电容Cst。为描述方便，图1所示的像素驱动电路还示出了发光元件OLED。
如图1所示，驱动晶体管DR的第二极、侦测晶体管SE的第一极、存储电容Cst的第一端以及发光元件OLED的阳极均连接至第一节点S；驱动晶体管DR的第一极、开关晶体管SW的栅极以及侦测晶体管SE的栅极分别与第一电压端、第一扫描信号线和第二扫描信号线相连，发光元件OLED的阴极可以与第二电压端(图中未示出)相连，第二电压端提供的第二电压小于第二电压端提供的第一电压。
例如，如图1所示，多个像素驱动电路10中多个侦测晶体管SE可以分别连接至感测线Sense_Line，感测线Sense_Line具有寄生电容(图1未标注)。感测线Sense_Line的一端可连接至参考电压端或模数转换器ADC。例如，在像素电路单元的数据电压写入阶段，可以使得感测线Sense_Line的一端与参考电压端相连，以将参考电压端提供的参考电压(例如，下文中的标准电压Vref)写入到第一节点S；在像素电路单元的感测信号采样阶段，可以使得感测线Sense_Line的一端与模数转换器相连，以将从第一节点S获取的感测信号(模拟信号)转换为数字信号。
在显示装置的实际的显示中，由于薄膜晶体管(例如，驱动晶体管)特性改变或者不同的驱动晶体管的特性不同，OLED显示装置可能存在显示异常(例如，显示不均匀)，因此，相关技术中，可以对各亚像素中的像素驱动电路进行补偿(例如，采用电学补偿方式对像素驱动电路的驱动晶体管的阈值电压进行补偿)，如图1所示，可以通过控制感应信号线Sense_Line和侦测晶体管SE来实现对该像素电路单元中各像素驱动电路的驱动晶体管的 阈值电压进行补偿，以降低显示的不均匀性。
然而，本公开的发明人注意到，在如图1所示的像素电路单元的第一节点S的电压存在不准确和/或不固定的问题。具体分析如下，在向如图1所示的像素电路单元的第一节点S写入电压时，由于像素电路单元中多个像素驱动电路10分别通过不同的驱动晶体管DR直接与第一电压端ELVDD连接，这样一来，在分别通过开关晶体管SW写入像素数据的瞬间，驱动晶体管DR中有电流产生，例如，产生的电流从驱动晶体管DR流经侦测晶体管SE和感测线，并流到感测模块(例如，感测集成芯片)或参考电压端(例如，感测模块或参考电压端的电位为标准电压Vref)；例如，产生的电流还可能流过发光元件OLED；此种情况下，电压端ELVDD、驱动晶体管DR和侦测晶体管SE的等效电路如图5所示(图5所示的R_D和R_S分别为驱动晶体管DR和侦测晶体管SE的等效电阻)，也即，驱动晶体管DR和侦测晶体管SE对第一电压端ELVDD和感测模块之间的电压差发生分压，使得第一节点S的电压(OLED的阳极电压)与感测模块或参考电压端通过Sense_Line提供的标准电压Vref不等(第一节点S的电压大于标准电压Vref)，进而导致包括该像素电路单元的显示像素实际显示的灰阶不准确。本公开的发明人还注意到，第一节点S的电压(OLED的阳极电压)还将随着数据电压的增大而增大(这是因为，驱动电流随着数据电压的增大而增大)，这使得第一节点S的电压不固定，并使得包括该像素电路单元的显示像素显示的灰阶的不准确问题恶化。
此外，本公开的发明人还注意到，由于像素电路单元中多个像素驱动电路10分别通过不同的侦测晶体管SE以并联的形式与同一条Sense_Line连接，以及侦测晶体管SE自身具有一定的寄生电容(栅源电容Cgs、栅漏电容Cgd)，导致Sense_Line上的总电容加大，使得Sense_Line上的电容充电至目标电容所需的时间增加，进而导致实际的补偿速度下降，造成通过该电学补偿方法对显示画面不均匀性问题的改善能力有限。
本公开的至少一个实施例提供了一种像素电路单元，其包括像素驱动电路以及电压控制模块。电压控制电路包括第一端和第二端，电压控制电路的第一端与第一电压端相连，以接收第一电压端提供的第一电源电压；像素驱动电路包括发光驱动电路，发光驱动电路包括电源电压接收端和控制端，发 光驱动电路的电源电压接收端与电压控制电路的第二端电连接，以使得发光驱动电路的电源电压接收端可接收第一电源电压；电压控制电路配置为在数据电压写入阶段断开，以使得发光驱动电路的电源电压接收端在数据电压写入阶段不接收第一电源电压。
下面通过几个示例对本公开的实施例提供的像素电路单元进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例中不同特征可以相互组合，从而得到新的示例，这些新的示例也都属于本公开保护的范围。
本公开的实施例提供一种像素电路单元，图2示出了本公开的实施例提供的像素电路单元一种示意图，图6示出了本公开的实施例提供的像素电路单元另一种示意图。
如图2和图6所示，该像素电路单元01包括多个依次连接的像素驱动电路10以及与多个像素驱动电路10连接的电压控制模块20(例如，电压控制电路)。图2是以像素电路单元01包括4个像素驱动电路10为例进行说明的，但本公开的实施例并不限制于此，例如，像素电路单元01也可以包括3个或者5个或其它适用数目的像素驱动电路10。以下示例均是以图2中像素电路单元01包括4个像素驱动电路10为例对本公开的实施例做进一步的说明。
如图2和图6所示，每一像素驱动电路10包括：发光驱动模块101(例如，发光驱动电路)、侦测晶体管SE以及发光二极管102(也即有机发光二极管OLED)，且侦测晶体管SE的第一极、发光驱动模块101以及发光二极管102的阳极通过第一节点S连接。在一些示例中，像素电路单元还可以不包括发光二极管102。例如，上述4个像素驱动电路10可以分别用于驱动发射红光的发光二极管、发射绿光的发光二极管、发射蓝光的发光二极管以及发射白光的发光二极管。需要说明的是，像素电路单元还可以用于驱动其它适用的发光元件，此种情况下，发光元件的阳极端与第一节点S连接。
如图2和图6所示，多个像素驱动电路10中多个侦测晶体管SE可以彼此串联后连接至感测线Sense_Line。如图2所示，多个像素驱动电路10中除最后一个像素驱动电路10之外，所有像素驱动电路10的侦测晶体管SE的第二极与下一个像素驱动电路10中的第一节点S连接，最后一个像素驱动电路10中的侦测晶体管SE的第二 极与感应信号线Sense_Line连接；也即，该像素电路单元01中依次设置的像素驱动电路10中的侦测晶体管SE为串联结构，多个像素驱动电路10中多个侦测晶体管SE中的一个侦测晶体管SE的源极和与其相邻的侦测晶体管SE的漏极连接。
例如，通过使得设置各像素驱动电路中的侦测晶体管以串联的形式与感应信号线连接，减小了感应信号线上的电容，从而提高了补偿速度。例如，在每根感应线上连接M个侦测晶体管SE，且每个侦测晶体管的栅源电容为Cgs时，在M个侦测晶体管SE分别连接至每根感应线上时，每根感应线上与侦测晶体管为M×Cgs；在M个侦测晶体管SE彼此串联之后再连接至每根感应线上时，每根感应线上与侦测晶体管为Cgs，因此，通过使得设置各像素驱动电路中的侦测晶体管以串联的形式与感应信号线连接，减小了感应信号线上的电容。
例如，如图6所示，感测线Sense_Line具有寄生电容Line_Cap。感测线Sense_Line的一端可连接至参考电压端Vref或模数转换器，感测线Sense_Line的一端与参考电压端Vref之间设置有开关EN，感测线Sense_Line的一端与模数转换器之间设置有开关SA。例如，在像素电路单元的数据电压写入阶段，可以使得开关EN导通，感测线Sense_Line的一端与参考电压端相连，以将参考电压端提供的参考电压写入到第一节点S；在像素电路单元的感测信号采样阶段，可以使得开关SA导通，感测线Sense_Line的一端与模数转换器相连，以将从第一节点S获取的感测信号(模拟信号)转换为数字信号。
例如，如图2和图6所示，在像素电路单元01中，所有侦测晶体管SE的栅极可以均与第一扫描信号线G1连接，以接收第一扫描信号线G1提供的信号(例如，第一扫描信号)，第一扫描信号线G1提供对的信号可用于控制多个侦测晶体管SE的导通状态(导通或截止)。例如，第一扫描信号为有效信号(有效电平)。需要说明的是，在本公开的至少一个示例中，有效信号(有效电平)是指使得接收该有效信号(有效电平)的晶体管导通的信号(电平)。
例如，如图2和图6所示，所有发光驱动模块101均与第二扫描信号线G2连接，以接收第二扫描信号线G2提供的信号(例如，第二扫描信号)；所有发光驱动模块101通过电压控制模块20与第一电压端ELVDD电连接，电压控制模块20与第三扫描信号线G3 连接，以响应于第三扫描信号线G3提供的信号(例如，第三扫描信号)控制发光驱动模块101与第一电压端ELVDD之间的导通状态(导通或断开)。例如，第一扫描信号和第三扫描信号均为有效信号(有效电平)。例如，不同的发光驱动模块101可以与不同的数据信号线DAT连接。
例如，通过使得所有侦测晶体管SE的栅极可以均与第一扫描信号线G1连接和/或使得所有发光驱动模块101均与第二扫描信号线G2连接，可以减小布线区域的尺寸简化电路结构。尽管如此，所有侦测晶体管SE的栅极不限于与同一第一扫描信号线G1，不同侦测晶体管SE的栅极还可以与不同的第一扫描信号线，只要不同的第一扫描信号线上提供信号彼此相同。类似地，不同的发光驱动模块101均与不同的第二扫描信号线G2连接，只要不同的第二扫描信号线G2上提供信号彼此相同。
在一些示例中，相比于图1所示的发光驱动模块与第一电压端直接连接，且各像素驱动电路中的侦测晶体管以并联的形式与感应信号线连接的技术方案可能导致的发光二极管的阳极的电压存在误差(实际发光亮度不准确)以及因各侦测晶体管自身的寄生电容造成感应信号线上电容过大而导致的补偿速度低的问题而言，本公开的实施例通过在发光驱动模块与第一电压端之间设置电压控制模块，避免或降低了发光二极管阳极的电压存在的误差，使得发光二极管的实际发光亮度更准确；并且，通过使得设置各像素驱动电路中的侦测晶体管以串联的形式与感应信号线连接，减小了感应信号线上的电容，从而提高了补偿速度；也即采用本公开的一些示例提供的像素电路单元能够准确、快速的对亚像素进行有效的电学补偿。
以下对上述电压控制模块20以及发光驱动模块101的具体设置结构做进一步的说明。
在一些示例中，如图2所示，电压控制模块20可以包括公共晶体管COM。公共晶体管COM的栅极与第三扫描信号线G3连接，以接收第三扫描信号线G3提供的信号，公共晶体管COM的第一极作为电压控制电路的第一端与第一电压端ELVDD连接，以接收第一电压端ELVDD提供的第一电压，公共晶体管COM的第二极作为电压控制电路的第二端与像素电路单元01中的所有发光驱动模块10(所有发光驱动模块10的电源电压接收端)连接，以使得所有发光驱动 模块10的电源电压接收端可接收第一电源电压。公共晶体管COM配置为响应于第三扫描信号线G3提供的信号控制是否将第一电压端ELVDD提供的第一电压提供给像素电路单元01中的所有发光驱动模块10的电源电压接收端。例如，在第三扫描信号线G3提供的信号为有效信号(例如，第三扫描信号)时，公共晶体管COM配置为将第一电压端ELVDD提供的第一电压提供给像素电路单元01中的所有发光驱动模块10的电源电压接收端；在第三扫描信号线G3提供的信号为无效信号时，公共晶体管COM配置为将第一电压端ELVDD提供的第一电压不提供给像素电路单元01中的任一发光驱动模块10的电源电压接收端。
例如，也可以针对每一个发光驱动模块单独设置晶体管以控制发光驱动模块101与第一电压端ELVDD之间的通断，实际中，为了简化工艺降低制作成本，可以采用上述一个公共晶体管COM与所有发光驱动模块101连接的设置方式。
另外，应当理解到，对于发光驱动模块101而言，在实际应用中，可以通过控制发光驱动模块101中产生的驱动电流的强度来控制与发光驱动模块101的信号输出端相连的发光二极管的发光亮度；又例如，还可以通过控制发光驱动模块101来控制发光二极管的阳极(也即第一节点)的电压大小，来控制其发光的亮度，例如，发光驱动模块101可以实现为2T1C(也即两个晶体管一个存储电容)电路结构，还可以根据实际的需要实现为3T1C电路结构或其它适用的电路结构，本公开的实施例对于发光驱动模块101的具体设置情况不作具体限定。
示意的，本公开的实施例提供一种实现为2T1C电路的发光驱动模块，如图2和图6所示，该发光驱动模块包括开关晶体管SW、驱动晶体管DR和存储电容Cst。
如图2和图6所示，开关晶体管SW的栅极与第二扫描信号线G2连接，以接收第二扫描信号线提供的信号(例如，第二扫描信号)；开关晶体管SW的第一极与数据信号线DAT连接，以接收数据电压(例如，侦测数据电压、关闭数据电压或补偿像素电压)；开关晶体管SW的第二极与第二节点G连接。
如图2和图6所示，驱动晶体管DR的栅极(作为发光驱动电路的控制端)与第二节点G和开关晶体管的第二极连接，且配置为可 接收数据电压(例如，侦测数据电压、关闭数据电压或补偿像素电压)；驱动晶体管DR的第一极作为发光驱动电路的电源电压接收端与电压控制模块的第二端(例如，前述公共晶体管COM的第二极)连接，驱动晶体管DR的第二极作为发光驱动电路的信号输出端与第一节点S连接。
如图2和图6所示，存储电容Cst的第一端与第一节点S连接，存储电容Cst的第二端与开关晶体管的第二极与第二节点G连接。
例如，电压控制电路配置为在数据电压写入阶段断开，以使得发光驱动电路的电源电压接收端在数据电压写入阶段不接收第一电源电压。例如，在数据电压写入阶段，可以经由第一扫描线G1向侦测晶体管SE的栅极提供有效信号，经由第二扫描线G2向开关晶体管SW的栅极提供有效信号，且可以经由第三扫描线G3向电压控制电路的控制端提供无效信号；此种情况下，开关晶体管SW的第一端接收的数据电压(例如，侦测数据电压、关闭数据电压或补偿像素电压)可以经由导通的开关晶体管SW提供至驱动晶体管DR的栅极，参考电压端提供的参考电压可以经由感应信号线和导通的侦测晶体管SE提供至驱动晶体管DR的第二极；由于电压控制电路断开，发光驱动电路的电源电压接收端在数据电压写入阶段不能够接收第一电源电压，因此驱动晶体管DR中不产生驱动电流，因此，第一节点S的电压与开关晶体管SW的第一端和驱动晶体管DR的栅极接收的数据电压无关，驱动晶体管DR的栅极和第二极之间的电压差更为准确，进而，可以提升包括该像素电路单元的显示像素的灰阶准确性以及包括该像素电路单元的显示面板和显示装置的亮度准确性。
例如，如图6所示，像素电路单元还包括公共走线110。电压控制电路的第二端(例如，公共晶体管COM的第二极)以及多个像素驱动电路的发光驱动电路的电源电压接收端(例如，驱动晶体管DR的第一极)均与公共走线110相连。例如，通过使得像素电路单元还包括公共走线110，可以简化像素电路单元的走线设计。
例如，如图6所示，公共走线110的延伸方向可以与多个像素驱动电路10的排布方向相同(例如，均沿图6所示水平方向)。例如，如图6所示，公共走线110包括第一端111和第二端112；电压控制电路的第二端在公共走线上的第一位置113与公共走线110相连；第一位置位于公共走线的第一端和公共走线的第二端之间；多 个像素驱动电路的中排在最外侧的两个像素驱动电路的电源电压接收端分别与公共走线的第一端和公共走线的第二端相连；多个像素驱动电路的中其余的像素驱动电路的电源电压接收端分别在公共走线的第一端和公共走线的第二端之间与相连公共走线。
例如，如图6所示，第一位置可以为公共走线的第一端和第二端之间的电阻中点。需要说明的是，在本公开的一些实施例中，“电阻中点”指的是走线上两点之间使得到该两点的电阻相等的点。例如，如图6所示，公共走线的第一端和第二端可以为公共走线的两个物理端部，但本公开的实施例不限于此，公共走线的第一端和第二端还可以位于公共走线的两个物理端部之间。例如，如图6所示，公共走线的第一位置可以为公共走线的物理中点，也即，公共走线上与公共走线的第一端和第二端的距离均相等的点。
例如，通过使得第一位置可以为公共走线的第一端和第二端之间的电阻中点，可以在简化像素电路单元的走线设计的情况下使得多个像素驱动电路的发光驱动电路的电源电压接收端接收的电压更为接近，由此可以进一步地提升包括该像素电路单元的显示面板和显示装置的显示均匀性。
以下通过与图1中的像素电路单元的对比，对本公开的一些实施例中的像素电路单元相关有益效果做进一步的分析说明。
首先，对于侦测晶体管SE而言，可以为底栅型晶体管，也可以为顶栅型晶体管，本公开的实施例对此不作限定；但底栅型晶体管和顶栅型晶体管均存在寄生电容。
例如，在侦测晶体管SE为底栅型晶体管的情况下，由于源漏极与栅极存在对位误差，同时考虑到湿刻过程造成图形关键尺寸的偏差(CD BIAS)，以及为了保证源漏电极和栅极之间不存在非交叠区，因此在实际中，会在设计中使得源漏极与栅极具有较大的交叠面积，从而导致该晶体管中存在寄生栅源电容Cgs和栅漏电容Cgd会比较大。例如，在侦测晶体管SE为顶栅型晶体管的情况下，因导体化工艺精度的问题，同样会导致晶体管中存在寄生栅源电容Cgs和栅漏电容Cgd(相比于底栅型较小)。
例如，在像素电路单元(图1和图2)处于正常的工作状态下，感应信号线Sense_Line上的寄生电容C Sense满足以下关系式：
C Sense＝C Line+C SE-Cgs
这里，C Line为感应信号线Sense_Line与其他金属导线交叠处形成的电容；C SE-Cgs为与感应信号线Sense_Line连接的侦测晶体管SE的寄生电容(Cgs和Cgd中的至少一个)。
在此情况下，在图1的像素电路单元中4个像素驱动电路(从左到右依次为第一像素驱动电路、第二像素驱动电路、第三像素驱动电路、第四像素驱动电路)中的侦测晶体管SE以并联的形式与感应信号线Sense_Line连接的情况下，感应信号线Sense_Line上的寄生电容CSense满足以下关系式：C SE-Cgs＝C SE1-Cgs+C SE2-Cgs+C SE3-Cgs+C SE4-Cgs；也即，该像素电路单元中4个像素驱动电路的四个侦测晶体管SE的寄生电容C SE1-Cgs、C SE2-Cgs、C SE3-Cgs、C SE4-Cgs均会加载至感应信号线Sense_Line(作为感应信号线Sense_Line上的寄生电容CSense的一部分)。
相比之下，在图2中的像素电路单元中4个像素驱动电路中的侦测晶体管SE以串联的形式与感应信号线Sense_Line连接的情况下，C SE-Cgs＝C SE4-Cgs，也即，该像素电路单元中4个像素驱动电路的四个侦测晶体管SE中，仅与感应信号线Sense_Line连接的一个侦测晶体管SE(例如图2中的从左到右的第四个)的寄生电容会加载至感应信号线Sense_Line；其他的侦测晶体管SE的寄生电容均不会加载至感应信号线Sense_Line上。
以上可以看出，相比于图1所示的像素电路单元而言，采用本公开的一些实施例的像素电路单元设计方案，感应信号线Sense_Line连接的侦测晶体管SE的寄生电容可以减小约75％。例如，由于底栅型侦测晶体管SE中侦测晶体管SE的寄生电容占到感应信号线Sense_Line上总寄生电容的50％以上，因此，包括底栅型侦测晶体管SE的像素电路单元尤为适用本公开的实施例中的设计方案。例如，对于图1和图2的两种像素电路单元而言，两者的C Line近似相等。在此情况下，由于感应信号线Sense_Line上的寄生电容降低，从而可以减小感应信号线Sense_Line上电容(Line Cap)，进而使得感应信号线Sense_Line的充电速度提高，也就提高了补偿速度。
此处，应当理解到，在实际的显示过程中，在一帧的显示时段内，一般包括带有显示电压的显示阶段和无显示电压的空白阶段 (Blank)，对上述感应信号线Sense_Line的充电过程(也即侦测过程)在空白时段(Blank)进行，在该时段内充电到目标电压的次数越多，也就可以使得补偿速度越快。
例如，对于图1中的像素电路单元而言，由于感应信号线Sense_Line上的电容较大，从而使得充电到目标电压的时间较长，那么在一个空白时段(Blank)内可能例如仅能进行一次充电，也即对像素电路单元中一个像素驱动电路完成侦测；相比之下，由于图2和图6所示的感应信号线Sense_Line上的电容较小，从而使得充电到目标电压的时间较短，那么在一个空白时段(Blank)内能够完成多次充电(例如，4次或更多次)，也即，可以在一个空白时段(Blank)内对像素电路单元中四个像素驱动电路完成侦测。
还需要说明的是，在图1所示的像素电路单元中，由于驱动晶体管DR与第一电压端ELVDD直接连接，在通过数据信号线DAT写入数据电压(例如，像素数据)的瞬间，驱动晶体管DR中有电流产生，例如，产生的电流从驱动晶体管DR流经侦测晶体管SE和感测线，并流到感测模块(例如，感测集成芯片)或参考电压端(例如，感测模块或参考电压端的电位为标准电压Vref)；例如，产生的电流还可能流过发光元件OLED，驱动晶体管DR和侦测晶体管SE对第一电压端ELVDD和感测模块之间的电压差发生分压，使得第一节点S的电压(OLED的阳极电压)与感测模块或参考电压端通过Sense_Line提供的标准电压Vref不等(第一节点S的电压大于标准电压Vref)，进而导致包括该像素电路单元的显示像素实际显示的灰阶不准确；例如，如图2和图6所示，本公开的一些实施例中的像素电路单元中驱动晶体管DR通过公共晶体管COM与第一电压端ELVDD连接，通过公共晶体管COM来控制驱动晶体管DR与第一电压端ELVDD之间的通断，避免或抑制了图1所示的像素电路单元中出现的因第一节点S的电压发生变化(或不固定)而导致的在感测阶段获取的补偿信号不准确和/或在写入阶段栅源电压不准确问题，进而可以缓解显示灰阶不准确的问题。
例如，在本公开的一些实施例中，通过使得驱动晶体管DR通过公共晶体管COM与第一电压端ELVDD连接，在通过数据信号线DAT写入像素数据(例如，数据电压)时，可以使得公共晶体管COM处于截止状态，此时没有电流流过驱动晶体管DR，第一节点S的电 压与数据信号线DAT写入的像素数据(例如，数据电压)无关，例如，第一节点S的电压可以为固定电压，从而提高了显示灰阶写入的准确性。例如，所有像素驱动电路10的第一节点S的电压均为固定电压，并且不同像素驱动电路10的第一节点S的电压彼此不同。
有以下几点需要说明。
(1)在对补偿速率要求较低的情况下，无需将图2和图6所示的多个侦测晶体管彼此串联后连接至感应信号线，此种情况下，可以使得图2和图6所示的多个侦测晶体管的第二极分别连接至感应信号线；对应地，像素电路单元01包括的多个像素驱动电路10彼此并列布置，而无需依次连接。
(2)像素电路单元01不限于包括多个像素驱动电路10，根据实际应用需求，像素电路单元01还可以仅包括一个本公开的实施例提供的像素驱动电路10，此种情况下，像素电路单元01的补偿效果依然得到一定的提升。例如，像素电路单元01还可以包括多个相关的像素电路，上述多个相关的像素电路直接与第一电压端相连。
(3)本公开的一些实施例提供的多个像素驱动电路10的发光驱动电路的电源电压接收端以及电压控制电路20的第二端不限于均连接至公共走线110，在发光驱动电路的电源电压接收端以及电压控制电路20之间的电压降较小的情况下，还可以不设置公共走线110，此种情况下，多个像素驱动电路10的发光驱动电路的电源电压接收端直接连接至电压控制电路20的第二端。
(4)电压控制电路20不限于实现为公共晶体管，电压控制电路20还可以实现为其它具有控制电压控制电路20的第二端是否与像素驱动电路10的发光驱动电路的电源电压接收端电连接功能的电路。
(5)本公开的一些实施例提供的像素驱动电路10不限于图2和图6所示的3T1C像素电路，根据实际应用需求，还可以实现为3T2C像素电路、7T1C像素电路或其它适用的像素电路，只要像素驱动电路10的发光驱动电路的电源电压接收端经由电压控制电路与第一电压端电连接。
(6)本公开的一些实施例中，为描述方便，Vref既表示参考电压端，也表示参考电压。
本公开的至少一个实施例还提供另一种像素电路单元。其包括 多个像素驱动电路，每个像素驱动电路包括发光驱动电路和侦测晶体管，发光驱动电路包括信号输出端，侦测晶体管包括第一极、第二极和栅极；侦测晶体管的栅极与第一扫描信号线连接，以接收第一扫描信号线提供的信号；侦测晶体管的第一极与发光驱动电路的信号输出端相连；以及除最后一个像素驱动电路之外，每个像素驱动电路的侦测晶体管的第二极与下一个像素驱动电路的侦测晶体管的第一极相连，最后一个像素驱动电路的侦测晶体管的第二极与感应信号线连接。
本公开的至少一个实施例还提供一种像素电路单元的驱动方法，在数据电压写入阶段，向电压控制电路的控制端提供无效信号，以使得电压控制电路在数据电压写入阶段断开，发光驱动电路的电源电压接收端在数据电压写入阶段不接收第一电源电压。
例如，在数据电压写入阶段，向电压控制电路的控制端提供无效信号包括：在数据电压写入阶段，向公共晶体管的栅极提供无效信号，以使得电压控制电路的第一端和第二端断开。
例如，像素电路单元的侦测阶段包括多个侦测子阶段，多个侦测子阶段配置为分别检测多个像素驱动电路的像素补偿数据；驱动方法包括：在每个侦测子阶段的数据电压写入阶段，向多个像素驱动电路中的待检测的像素驱动电路的发光驱动电路的控制端提供侦测数据电压，并向多个像素驱动电路中的其它像素驱动电路的发光驱动电路的控制端提供关闭数据电压。例如，关闭数据电压是使得发光驱动电路(驱动晶体管)关闭的电压，关闭数据电压例如为无效电压。
例如，驱动方法还包括：在像素电路单元的显示阶段，分别向多个像素驱动电路的发光驱动电路的控制端提供补偿像素数据，其中，每个发光驱动电路的补偿像素数据为：基于像素补偿数据对初始像素数据进行补偿之后得到的像素数据。
下面结合图3对本公开的至少一个实施例提供的像素电路单元的驱动方法的一个示例做示例性说明。图3是图2和图6所示的像素电路单元的驱动时序图。
如图3所示，像素电路单元包括显示阶段和侦测阶段，侦测阶段包括多个侦测子阶段，每个侦测子阶段用于检测多个像素驱动电路中一个像素驱动电路的像素补偿数据(例如，像素驱动电路的驱 动晶体管的阈值电压)。例如，每个侦测子阶段包括数据写入阶段、感测阶段和采样阶段。需要说明的是，为了清楚起见，图3仅示出了侦测阶段的一个侦测子阶段(也即，图3所示的侦测阶段)。例如，多个侦测子阶段在时间上顺次排布(例如，连续排布)。
该驱动方法包括以下的步骤101、步骤102、步骤103、步骤201和步骤202。
步骤101：在侦测阶段(在侦测阶段的一个侦测子阶段)的数据写入阶段(也即，DAT_IN’阶段)，向第一扫描信号线G1输入第一扫描信号(有效信号)，向第二扫描信号线G2输入第二扫描信号(有效信号)，向第三扫描信号线G3输入无效信号，向感应信号线Sense_Line输入第一参考电压(例如，参考电压Vref)，向多个数据信号线中的一个数据信号线DAT(在该侦测子阶段被检测的像素驱动电路连接的数据信号线)输入侦测数据信号(侦测数据信号例如存储在存储电容Cst中)，多个数据信号线中的其余数据信号线均输入关闭数据信号(一般为0V电压信号)。
示意的，参考图2以及参考图3中侦测阶段中的DAT_IN’阶段，向第一扫描信号线G1输入第一扫描信号，向第二扫描信号线G2输入第二扫描信号，开关晶体管SW和侦测晶体管SE开启，此时向感应信号线Sense_Line输入的参考电压Vref写入至第一节点S，向四个像素驱动电路中连接的四个数据信号线中的一个(与待检测的像素驱动电路连接的数据信号线)输入的侦测数据信号储至存储电容Cst；其余数据信号线均输入0V电压信号。例如，由于向第三扫描信号线G3输入无效信号，因此，驱动晶体管DR的第一极未接收第一电压，驱动晶体管DR未产生驱动电流，由此可以提升经由感应信号线Sense_Line写入至像素驱动电路的信号输出端的电压(也即，第一节点S的电压)的准确度以及提升经由感应信号线Sense_Line获取的像素驱动电路的像素补偿数据(例如，像素驱动电路的驱动晶体管的阈值电压)的准确度，由此可以提升在显示阶段的数据写入阶段DAT_IN，驱动晶体管DR栅源电压Vgs的准确度。
步骤102：在侦测阶段(在侦测阶段的一个侦测子阶段)的感测阶段，向第一扫描信号线G1输入第一扫描信号(有效信号)，向第二扫描信号线G2输入无效信号，向第三扫描信号线G3输入第三扫描信号(有效信号)，驱动晶体管DR通过第一节点S向感应信号线 Sense_Line充电，以使得可以在侦测阶段(在侦测阶段的一个侦测子阶段)的采样阶段可经由感应信号线Sense_Line获取像素补偿数据。
示意的，参考图2以及参考图3中侦测阶段中的Sens阶段，通过向第一扫描信号线G1输入第一扫描信号以及向第三扫描信号线G3输入第三扫描信号，使得侦测晶体管SE和公共晶体管COM开启，此时，可以基于存储电容Cst中存储的数据电压，并通过第一节点S对感应信号线Sense_Line充电，以使得充电完成后可以利用与感应信号线Sense_Line连接的侦测IC(集成电路)进行取样(Sample)，由此可以获取像素补偿数据。
步骤103：在侦测阶段(在侦测阶段的一个侦测子阶段)的采样阶段Samp，向第一扫描信号线G1输入无效信号，向第二扫描信号线G2输入无效信号，向第三扫描信号线G3输入第三扫描信号(有效信号)。
例如，通过向第二扫描信号线G2输入无效信号，可以使得侦测晶体管SE在采样阶段关闭，以使得经由感应信号线Sense_Line获取的像素补偿数据更为准确。
例如，在像素电路单元包括多个像素驱动电路，侦测阶段包括多个侦测子阶段时，可以针对多个像素驱动电路分别执行步骤101-步骤103，以获得多个像素驱动电路的像素补偿数据(例如，多个像素驱动电路的驱动晶体管的阈值电压)。
例如，，需要通过重复多次侦测过程(也即，多次执行步骤101-步骤103)，以完成对像素电路单元的多个像素驱动电路的侦测，从而在后续完成对各亚像素的像素数据补偿。
步骤201：在显示阶段的数据写入阶段DAT_IN，向第一扫描信号线G1输入第一扫描信号(有效信号)，向第二扫描信号线G2输入第二扫描信号(有效信号)，向第三扫描信号线G2输入无效信号，向感应信号线Sense_Line输入第二参考电压(例如，参考电压Vref)，分别向不同的数据信号线DAT输入对应的补偿像素数据并进行存储；这里，补偿像素数据(例如，补偿像素数据电压)为：根据对应的像素补偿数据对初始像素数据进行补偿后得到的像素数据。例如，初始像素数据为补偿前的像素数据。
示意的，参考图2以及参考图3中显示阶段中的DAT_IN阶段， 向第一扫描信号线G1输入第一扫描信号，向第二扫描信号线G2输入第二扫描信号，开关晶体管SW和侦测晶体管SE开启，此时向感应信号线Sense_Line输入的参考电压Vref写入至第一节点S，向四个像素驱动电路中连接的四个数据信号线中分别输入的补偿像素数据，分别存储至对应的存储电容Cst中，这里，补偿像素数据为：根据侦测阶段获取到的像素补偿数据对初始像素数据进行补偿后得到的像素数据。
例如，由于在显示阶段的数据写入阶段DAT_IN向第三扫描信号线G3输入无效信号，因此，驱动晶体管DR的第一极未接收第一电压，驱动晶体管DR未产生驱动电流，由此可以提升经由感应信号线Sense_Line写入至像素驱动电路的信号输出端的电压(也即，第一节点S的电压)的准确度，由此可以进一步地提升驱动晶体管DR栅源电压Vgs的准确度。
步骤202：在显示阶段的有效显示阶段(也即，Disp阶段)，向第一扫描信号线G1输入无效信号，向第二扫描信号线G2输入无效信号，向第三扫描信号线G3输入第三扫描信号(有效信号)，以驱动多个像素驱动电路的发光二极管按照对应的补偿像素数据进行发光。
示意的，参考图2结合图3中显示阶段中的Disp阶段，向第三扫描信号线G3输入第三扫描信号，公共晶体管COM开启，此时，驱动晶体管DR在存储电容Cst存储的补偿像素数据的作用下导通，由此可以驱动发光二极管进行发光。
有以下两点需要说明。
第一，上述关于图2中的晶体管导通、断开过程均是以所有晶体管为N型晶体管为例进行的说明，但本公开的实施例并不限制于此，图2中的所有晶体管也可以为P型晶体管，当然，此时需要对图3中各个控制信号进行翻转。
第二，上述图3仅是示意的给出了一个显示阶段和一个侦测阶段，应当理解到，在侦测阶段之后仍为显示阶段，且显示阶段中采用的补偿像素数据是根据该显示阶段前的侦测阶段中获取得到的；另外，图3中的取样(Sample)阶段与显示阶段在时序上为独立的阶段，图3仅是示意的说明。
此外，还应当理解到，在显示阶段中的DAT IN阶段和侦测阶段 中的DAT IN’阶段中，第三扫描信号线未提供扫描信号(也即，第三扫描信号线上的信号无无效信号)，公共晶体管COM处于截止状态，在此情况下，不同第一节点S的电压Vs与数据信号线DAT输入的像素数据的大小无关，不随像素数据(例如，数据电压)的变化而变化，也即，第一节点S的电压Vs为一固定电压，由此能够保证显示灰阶写入的准确性。
图1中示出的像素电路单元的第一节点S的电压会受到数据信号线DAT输入的像素数据的变化而发生变化，例如，当数据信号线DAT输入的像素数据较大时，驱动晶体管DR产生的电流越大(例如，流经OLED的电流就越大)，从而导致第一节点S的电压较大，由此使得第一节点S的电压的误差较大。
例如，像素电路单元在应用于显示面板时，在显示面板出厂前的驱动信号的调试中，图1所示的像素电路单元需要对每一灰阶(例如0～255灰阶)进行调试；而采用本公开的一些实施例中的像素电路单元(图2或图6)仅需要对其中的一个灰阶进行调试，即可保证其他灰阶的准确性；例如，选择调试的灰阶可以是127灰阶或者64灰阶，但并不限制于此。
例如，本公开的发明人通过实际的模拟进一步的证实本公开的实施例中，第一节点S的电压Vs与数据信号线DAT输入的像素数据的大小无关，具体分析如下。
图4示出了图2和图6的像素电路单元的第一节点S的电压信号模拟图。如图4所示，由于像素电路单元中四个侦测晶体管SE为串联结构(源、漏极依次连接)，侦测晶体管SE自身具有一定的电阻，从而使得像素电路单元中不同的侦测晶体管SE连接的第一节点S的电压Vs具有一定的差异，例如图4中Vs1、Vs2、Vs3、Vs4分别为0.2V、0.3V、0.4V、0.5V的固定电压。例如，Vs1、Vs2、Vs3、Vs4分别表示图2和图6中位于右一位置处、右二位置处、右三位置处和右四位置处的像素驱动电路的第一节点S的电压(也即，图4中竖向的虚线与图4上方四个子图中曲线的交点对应的电压值)。
例如，参考图4，示意的，向像素电路单元中的(每一)数据信号线DAT输入2V、4V、6V、8V的像素数据，可以看出在像素数据的输入阶段(也即对应图3中DAT_IN阶段)，不同的像素数据下，第一节点S的电压Vs(也即OLED阳极电压)对应的曲线基本重合， 也即证明了第一节点S的电压Vs不受像素数据的影响。
本公开的实施例还提供一种显示面板，该显示面板包括前述的像素电路单元。例如，该显示面板包括呈矩阵排列的多个亚像素，像素电路单元中的多个像素驱动电路与多个亚像素一一对应。例如，多个亚像素的每个包括一个对应的像素驱动电路。例如，由于前述实施例已经对像素电路单元的结构和有益效果进行了详细的描述，此处不再赘述。
需要说明的是，在本公开的实施例中，显示面板具体至少可以包括有机发光二极管显示面板，例如该显示面板可以应用至显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件中。
例如，位于同行的亚像素中，相邻的不同颜色的亚像素构成一个像素单元；一个像素单元中多个亚像素与一个像素电路单元中的多个像素驱动电路一一对应；本公开的实施例中对于像素单元中亚像素的个数不做限定，实际中根据需要选择设置即可。
例如，上述一个像素单元可以包括红色亚像素R、绿色亚像素G、蓝色亚像素B三个颜色的亚像素，在此情况下，像素电路单元包括的3个依次设置的像素驱动电路，分别与相邻的红色亚像素R、绿色亚像素G、蓝色亚像素B一一对应。
又例如，上述像素单元还包括红色亚像素R、绿色亚像素G、蓝色亚像素B、白色亚像素W四个颜色的亚像素，在此情况下，像素电路单元包括4个依次设置的像素驱动电路，分别与相邻红色亚像素R、绿色亚像素G、蓝色亚像素B、白色亚像素W一一对应。
再例如，上述像素单元还包括红色亚像素R、绿色亚像素G、蓝色亚像素B、青色亚像素C、黄色亚像素Y五个颜色的亚像素，在此情况下，像素电路单元包括5个依次设置的像素驱动电路分别与相邻的红色亚像素R、绿色亚像素G、蓝色亚像素B、青色亚像素C、黄色亚像素Y一一对应。
例如，在实际的排布中，位于同行的多个像素单元对应的多个像素电路单元可以分别采用相同的第一扫描信号线、相同的第二扫描信号线、相同的第三扫描信号线；同列的像素单元对应的像素电路单元可以共用一感应信号线。
本公开的实施例该提供一种显示装置，该显示装置包括前述的 显示面板，包括前述的像素电路单元或显示面板，由于前述实施例已经对像素电路单元的结构和有益效果进行了详细的描述，此处不再赘述。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开的实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (21)

  1. 一种像素电路单元，包括多个像素驱动电路以及电压控制电路，
    其中，所述电压控制电路包括第一端和第二端，所述电压控制电路的第一端与第一电压端相连，以接收所述第一电压端提供的第一电源电压；
    每个所述像素驱动电路包括发光驱动电路，所述发光驱动电路包括电源电压接收端和控制端，每个所述像素驱动电路的发光驱动电路的电源电压接收端与所述电压控制电路的第二端电连接，以使得每个所述像素驱动电路的发光驱动电路的电源电压接收端可接收所述第一电源电压；以及
    所述电压控制电路配置为在数据电压写入阶段断开，以使得每个所述像素驱动电路的发光驱动电路的电源电压接收端在所述数据电压写入阶段不接收所述第一电源电压。
  2. 根据权利要求1所述的像素电路单元，还包括公共走线，其中，所述电压控制电路的第二端以及多个所述像素驱动电路的发光驱动电路的电源电压接收端均与所述公共走线相连。
  3. 根据权利要求2所述的像素电路单元，其中，所述公共走线的延伸方向与多个所述像素驱动电路的排布方向相同；
    所述公共走线包括第一端和第二端；
    所述电压控制电路的第二端在所述公共走线上的第一位置与所述公共走线相连；
    所述第一位置位于所述公共走线的第一端和所述公共走线的第二端之间，且为所述公共走线的第一端和第二端之间的电阻中点；以及
    多个所述像素驱动电路的中排在最外侧的两个像素驱动电路的发光驱动电路的电源电压接收端分别与所述公共走线的第一端和所述公共走线的第二端相连。
  4. 根据权利要求1-3任一所述的像素电路单元，其中，所述电压控制电路包括公共晶体管，所述公共晶体管包括第一极、第二极和栅极；
    所述公共晶体管的第一极作为所述电压控制电路的第一端与所述第一电压端连接；
    所述公共晶体管的第二极作为所述电压控制电路的第二端与多个所述像 素驱动电路的发光驱动电路的电源电压接收端电连接；以及
    所述公共晶体管的栅极与第三扫描信号线连接，以接收所述第三扫描信号线提供的信号。
  5. 根据权利要求1-4任一所述的像素电路单元，其中，所述发光驱动电路包括驱动晶体管，所述驱动晶体管包括第一极、第二极和栅极；
    所述驱动晶体管的第一极作为所述发光驱动电路的电源电压接收端与所述电压控制电路连接；
    所述驱动晶体管的第二极作为所述发光驱动电路的信号输出端与第一节点连接；以及
    所述驱动晶体管的栅极，作为所述发光驱动电路的控制端，配置为可接收数据电压。
  6. 根据权利要求5所述的像素电路单元，其中，所述发光驱动电路还包括开关晶体管和存储电容；
    所述开关晶体管包括栅极、第一极和第二极；
    所述存储电容包括第一端和第二端；
    所述开关晶体管的栅极与第二扫描信号线连接，以接收所述第二扫描信号线提供的信号；
    所述开关晶体管的第一极与数据信号线连接，以接收所述数据电压；
    所述开关晶体管的第二极与第二节点连接并与所述驱动晶体管的栅极连接；以及
    所述存储电容的第一端与所述第一节点连接，所述存储电容的第二端与所述开关晶体管的第二极以及所述第二节点连接。
  7. 根据权利要求6所述的像素电路单元，其中，不同的所述像素驱动电路的发光驱动电路的开关晶体管的第一极与不同的数据信号线连接。
  8. 根据权利要求1-7任一所述的像素电路单元，其中，每个所述像素驱动电路还包括侦测晶体管，所述侦测晶体管包括第一极、第二极和栅极；
    所述侦测晶体管的栅极与第一扫描信号线连接，以接收所述第一扫描信号线提供的信号；
    所述侦测晶体管的第一极与所述发光驱动电路的信号输出端相连；以及
    除最后一个所述像素驱动电路之外，每个所述像素驱动电路的侦测晶体 管的第二极与下一个所述像素驱动电路的侦测晶体管的第一极相连，所述最后一个所述像素驱动电路的侦测晶体管的第二极与感应信号线连接。
  9. 根据权利要求8所述的像素电路单元，其中，所述侦测晶体管为底栅型晶体管。
  10. 根据权利要求1-9任一所述的像素电路单元，其中，所述像素电路单元包括3、4或5个所述像素驱动电路。
  11. 根据权利要求1-10任一所述的像素电路单元，其中，每个所述像素驱动电路还包括发光二极管，所述发光二极管的阳极与所述像素驱动电路的发光驱动电路的信号输出端相连。
  12. 一种像素电路单元，包括多个依次连接的像素驱动电路以及与所述像素驱动电路连接的电压控制电路；
    其中，每一所述像素驱动电路包括：发光驱动电路、侦测晶体管以及发光二极管，且所述侦测晶体管的第一极、所述发光驱动电路以及所述发光二极管的阳极通过第一节点连接；
    除最后一个所述像素驱动电路之外，每个所述像素驱动电路中侦测晶体管的第二极与下一个像素驱动电路中的所述第一节点连接，所述最后一个像素驱动电路中的侦测晶体管的第二极与感应信号线连接；所述像素电路单元中的所有侦测晶体管的栅极均与第一扫描信号线连接；
    所述像素电路单元中的所有发光驱动电路均与第二扫描信号线连接，且所有发光驱动电路通过所述电压控制电路与第一电压端连接，所述电压控制电路与第三扫描信号线连接，以通过所述第三扫描信号线控制所述发光驱动电路与所述第一电压端之间的通断；
    不同的所述发光驱动电路与不同的数据信号线连接。
  13. 一种如权利要求1-12任一项所述的像素电路单元的驱动方法，包括：
    在数据电压写入阶段，向所述电压控制电路的控制端提供无效信号，以使得所述电压控制电路在所述数据电压写入阶段断开，多个所述发光驱动电路的电源电压接收端在所述数据电压写入阶段不接收所述第一电源电压。
  14. 根据权利要求13所述的驱动方法，其中，所述电压控制电路包括公共晶体管，所述公共晶体管包括栅极，第一极和第二极，
    所述公共晶体管的第一极作为所述电压控制电路的第一端与所述第一电 压端连接，所述公共晶体管的第二极作为所述电压控制电路的第二端与多个所述发光驱动电路的电源电压接收端电连接；以及
    在所述数据电压写入阶段，向所述电压控制电路的控制端提供所述无效信号包括：
    在所述数据电压写入阶段，向所述公共晶体管的栅极提供所述无效信号，以使得所述电压控制电路的第一端和第二端断开。
  15. 根据权利要求13或14所述的驱动方法，其中，每个所述像素驱动电路还包括侦测晶体管，所述侦测晶体管包括第一极、第二极和栅极；
    所述侦测晶体管的栅极与第一扫描信号线连接，以接收第一扫描信号提供的信号；
    所述侦测晶体管的第一极与所述发光驱动电路的信号输出端相连；以及
    除最后一个所述像素驱动电路之外，每个所述像素驱动电路的所述侦测晶体管的第二极与下一个所述像素驱动电路的侦测晶体管的第一极相连，所述最后一个所述像素驱动电路的侦测晶体管的第二极与感应信号线连接。
  16. 根据权利要求15所述的驱动方法，其中，所述像素电路单元的侦测阶段包括多个侦测子阶段，所述多个侦测子阶段配置为分别检测多个所述像素驱动电路的像素补偿数据；
    所述驱动方法还包括：
    在每个所述侦测子阶段的数据电压写入阶段，向多个所述像素驱动电路中的待检测的像素驱动电路的所述发光驱动电路的控制端提供侦测数据电压，并向多个所述像素驱动电路中的其它像素驱动电路的所述发光驱动电路的控制端提供关闭数据电压，以获取所述待检测的像素驱动电路的像素补偿数据。
  17. 根据权利要求13-16任一所述的驱动方法，还包括：在所述像素电路单元的显示阶段，分别向多个所述像素驱动电路的所述发光驱动电路的控制端提供对应的补偿像素数据，其中，所述对应的补偿像素数据为：基于对应的像素补偿数据对初始像素数据进行补偿之后得到的像素数据。
  18. 一种如权利要求12所述的像素电路单元的驱动方法，包括：
    在侦测阶段的数据电压写入阶段，向所述第一扫描信号线输入第一扫描信号，向所述第二扫描信号线输入第二扫描信号，向所述第三扫描信号线输 入无效信号，向所述感应信号线输入第一参考电压，向多个数据信号线中的一个数据信号线输入侦测数据信号，并存储所述侦测数据信号，向所述多个数据信号线中的其余数据信号线均输入关闭数据信号；
    在所述侦测阶段的感测阶段，向所述第一扫描信号线输入所述第一扫描信号，向所述第二扫描信号线输入无效信号，向所述第三扫描信号线输入第三扫描信号，以通过第一节点向所述感应信号线充电；
    在所述侦测阶段的采样阶段，经由所述感应信号线获取像素补偿数据；
    在显示阶段的数据电压写入阶段，向所述第一扫描信号线输入所述第一扫描信号，向所述第二扫描信号线输入所述第二扫描信号，向所述第三扫描信号线输入无效信号；向所述感应信号线输入第二参考电压，分别向不同的数据信号线输入对应的补偿像素数据，并存储所述对应的补偿像素数据；其中，所述对应的补偿像素数据为：根据对应的所述像素补偿数据对初始像素数据进行补偿后得到的像素数据；
    在所述显示阶段的有效显示阶段，向所述第一扫描信号线输入无效信号，向所述第二扫描信号线输入无效信号，向所述第三扫描信号线输入所述第三扫描信号，以控制所述像素电路单元驱动的发光二极管按照所述对应的补偿像素数据进行发光。
  19. 一种显示面板，所述显示面板包括如权利要求1-12任一项所述的像素电路单元。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板包括呈矩阵排列的多个亚像素，所述像素电路单元中的多个像素驱动电路与所述多个亚像素一一对应；
    位于同行的亚像素中，相邻的不同颜色的亚像素构成一个像素单元；
    一个所述像素单元中多个亚像素与一个所述像素电路单元中的多个像素驱动电路一一对应；以及
    所述像素单元包括红色亚像素、绿色亚像素、蓝色亚像素；或者，所述像素单元包括红色亚像素、绿色亚像素、蓝色亚像素、白色亚像素；或者，所述像素单元包括红色亚像素、绿色亚像素、蓝色亚像素、青色亚像素、黄色亚像素。
  21. 一种显示装置，包括权利要求1-12任一项所述的像素电路单元或者 权利要求19或20所述的显示面板。
PCT/CN2019/082416 2018-04-12 2019-04-12 像素电路单元及驱动方法、显示面板、显示装置 WO2019196925A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/607,286 US10984719B2 (en) 2018-04-12 2019-04-12 Pixel circuit unit, driving method thereof, display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810326602.4 2018-04-12
CN201810326602.4A CN108520716B (zh) 2018-04-12 2018-04-12 一种像素电路单元及驱动方法、显示面板、显示装置

Publications (1)

Publication Number Publication Date
WO2019196925A1 true WO2019196925A1 (zh) 2019-10-17

Family

ID=63432249

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/082416 WO2019196925A1 (zh) 2018-04-12 2019-04-12 像素电路单元及驱动方法、显示面板、显示装置

Country Status (3)

Country Link
US (1) US10984719B2 (zh)
CN (1) CN108520716B (zh)
WO (1) WO2019196925A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021164431A1 (zh) * 2020-02-20 2021-08-26 京东方科技集团股份有限公司 像素驱动电路、像素结构及显示面板
CN114220379A (zh) * 2021-09-07 2022-03-22 友达光电股份有限公司 控制电路、显示面板及像素电路驱动方法
CN114399974A (zh) * 2021-09-28 2022-04-26 友达光电股份有限公司 显示面板及其操作方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108520716B (zh) * 2018-04-12 2019-10-01 京东方科技集团股份有限公司 一种像素电路单元及驱动方法、显示面板、显示装置
CN110910806B (zh) * 2018-09-17 2023-05-23 群创光电股份有限公司 显示设备
CN111244124B (zh) * 2018-11-12 2021-09-03 惠科股份有限公司 显示面板及显示装置
US11062648B2 (en) * 2019-05-13 2021-07-13 Novatek Microelectronics Corp. Display device and method of sensing the same
CN110349542A (zh) * 2019-07-15 2019-10-18 京东方科技集团股份有限公司 一种显示面板、显示装置及其控制方法
KR20220050591A (ko) * 2020-10-16 2022-04-25 엘지디스플레이 주식회사 표시장치, 구동회로 및 구동방법
US11749201B2 (en) * 2020-10-28 2023-09-05 Hefei Xinsheng Optoelectronics Technology Co., Ltd Display device, and circuit and method for acquiring voltages
CN112735341A (zh) * 2020-12-30 2021-04-30 Tcl华星光电技术有限公司 像素驱动电路及显示装置
CN113138477B (zh) * 2021-04-23 2022-05-03 深圳市华星光电半导体显示技术有限公司 显示面板及电子设备
JP7276948B1 (ja) 2022-04-26 2023-05-18 株式会社セレブレクス 映像データ識別回路及びパネルシステムコントローラ
CN116030763B (zh) * 2023-03-30 2023-06-06 惠科股份有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203931451U (zh) * 2014-05-26 2014-11-05 京东方科技集团股份有限公司 像素电路和显示装置
CN106023893A (zh) * 2016-08-08 2016-10-12 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置和电流测量方法
CN107016964A (zh) * 2017-04-25 2017-08-04 京东方科技集团股份有限公司 像素电路、其驱动方法和显示装置
CN107170408A (zh) * 2017-06-27 2017-09-15 上海天马微电子有限公司 像素电路、驱动方法、有机电致发光显示面板及显示装置
US20180012550A1 (en) * 2016-07-07 2018-01-11 Samsung Display Co., Ltd. Integration driver and a display device having the same
CN108520716A (zh) * 2018-04-12 2018-09-11 京东方科技集团股份有限公司 一种像素电路单元及驱动方法、显示面板、显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753654B2 (en) * 2001-02-21 2004-06-22 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and electronic appliance
JP2007310628A (ja) * 2006-05-18 2007-11-29 Hitachi Displays Ltd 画像表示装置
US8405582B2 (en) * 2008-06-11 2013-03-26 Samsung Display Co., Ltd. Organic light emitting display and driving method thereof
TWI477865B (zh) * 2009-12-28 2015-03-21 Au Optronics Corp 具有觸控功能之液晶顯示器及觸控面板
KR101223488B1 (ko) * 2010-05-11 2013-01-17 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그의 구동방법
KR101528148B1 (ko) * 2012-07-19 2015-06-12 엘지디스플레이 주식회사 화소 전류 측정을 위한 유기 발광 다이오드 표시 장치 및 그의 화소 전류 측정 방법
KR20140133189A (ko) * 2013-05-10 2014-11-19 삼성디스플레이 주식회사 유기 발광 표시 장치의 화소 및 유기 발광 표시 장치
KR102183494B1 (ko) * 2014-08-21 2020-11-27 엘지디스플레이 주식회사 유기 발광 표시 장치
KR102417266B1 (ko) * 2015-01-27 2022-07-05 삼성디스플레이 주식회사 표시 장치 및 그 접촉 감지 방법
KR102216705B1 (ko) * 2015-06-30 2021-02-18 엘지디스플레이 주식회사 소스 드라이버 집적회로, 컨트롤러, 유기발광표시패널, 유기발광표시장치 및 그 구동방법
CN105185311B (zh) * 2015-10-10 2018-03-30 深圳市华星光电技术有限公司 Amoled显示装置及其驱动方法
KR102527727B1 (ko) * 2016-08-30 2023-05-02 엘지디스플레이 주식회사 데이터 드라이버, 유기발광표시장치 및 유기발광표시장치의 구동 방법
CN106940984B (zh) * 2017-05-17 2019-12-13 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
CN107134258B (zh) * 2017-06-26 2019-10-08 京东方科技集团股份有限公司 Oled补偿电路及其制作方法、oled补偿装置和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203931451U (zh) * 2014-05-26 2014-11-05 京东方科技集团股份有限公司 像素电路和显示装置
US20180012550A1 (en) * 2016-07-07 2018-01-11 Samsung Display Co., Ltd. Integration driver and a display device having the same
CN106023893A (zh) * 2016-08-08 2016-10-12 京东方科技集团股份有限公司 阵列基板、显示面板、显示装置和电流测量方法
CN107016964A (zh) * 2017-04-25 2017-08-04 京东方科技集团股份有限公司 像素电路、其驱动方法和显示装置
CN107170408A (zh) * 2017-06-27 2017-09-15 上海天马微电子有限公司 像素电路、驱动方法、有机电致发光显示面板及显示装置
CN108520716A (zh) * 2018-04-12 2018-09-11 京东方科技集团股份有限公司 一种像素电路单元及驱动方法、显示面板、显示装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021164431A1 (zh) * 2020-02-20 2021-08-26 京东方科技集团股份有限公司 像素驱动电路、像素结构及显示面板
US11869424B2 (en) 2020-02-20 2024-01-09 Boe Technology Group Co., Ltd. Pixel driving circuit, pixel structure, and display panel
CN114220379A (zh) * 2021-09-07 2022-03-22 友达光电股份有限公司 控制电路、显示面板及像素电路驱动方法
CN114220379B (zh) * 2021-09-07 2023-06-02 友达光电股份有限公司 控制电路、显示面板及像素电路驱动方法
CN114399974A (zh) * 2021-09-28 2022-04-26 友达光电股份有限公司 显示面板及其操作方法
CN114399974B (zh) * 2021-09-28 2023-12-12 友达光电股份有限公司 显示面板及其操作方法

Also Published As

Publication number Publication date
CN108520716A (zh) 2018-09-11
US10984719B2 (en) 2021-04-20
CN108520716B (zh) 2019-10-01
US20200388220A1 (en) 2020-12-10

Similar Documents

Publication Publication Date Title
WO2019196925A1 (zh) 像素电路单元及驱动方法、显示面板、显示装置
US11881164B2 (en) Pixel circuit and driving method thereof, and display panel
CN109523956B (zh) 像素电路及其驱动方法、显示装置
US11468835B2 (en) Pixel circuit and driving method thereof, and display device
US10943544B2 (en) Organic light emitting display device and driving method thereof
US11056065B2 (en) Light-emitting display for compensating degradation of organic light-emitting diode and method of driving the same
EP3125226A1 (en) Touch sensor integrated display device and method for driving the same
CN110235193B (zh) 像素电路及其驱动方法、显示装置及其驱动方法
WO2019134459A1 (zh) 像素电路及其驱动方法、显示装置
CN109859692B (zh) 显示驱动电路及其驱动方法、显示面板及显示装置
CN110021273B (zh) 像素电路及其驱动方法、显示面板
US10909927B2 (en) Pixel compensation circuit and compensation method, pixel circuit, and display panel
US11049459B2 (en) Light-emitting display and method of driving the same
US20210335258A1 (en) Method for driving display panel and display device
WO2019174228A1 (zh) 像素电路及其驱动方法、显示面板
US10354591B2 (en) Pixel driving circuit, repair method thereof and display device
KR20210012093A (ko) 표시장치의 열화 보상 방법
US11386849B2 (en) Light emitting display device and method of driving same
CN111179853B (zh) 一种像素电路及其驱动方法、显示装置
WO2019114348A1 (zh) 像素电路及其驱动方法、显示面板及电子设备
US11579717B2 (en) Touch display device and method for driving the same
US11847959B2 (en) Display device having sensing mode for sensing electrical characteristics of pixels
WO2019090896A1 (zh) Oled显示装置
US11670228B2 (en) Display device and method of driving the same
WO2021035554A1 (zh) 检测电路及其驱动方法、驱动电路、装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19784253

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.01.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19784253

Country of ref document: EP

Kind code of ref document: A1