WO2022001838A1 - 基于spi的数据传输系统 - Google Patents

基于spi的数据传输系统 Download PDF

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Publication number
WO2022001838A1
WO2022001838A1 PCT/CN2021/102207 CN2021102207W WO2022001838A1 WO 2022001838 A1 WO2022001838 A1 WO 2022001838A1 CN 2021102207 W CN2021102207 W CN 2021102207W WO 2022001838 A1 WO2022001838 A1 WO 2022001838A1
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WO
WIPO (PCT)
Prior art keywords
data
spi
camera
select signal
chip select
Prior art date
Application number
PCT/CN2021/102207
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English (en)
French (fr)
Inventor
方庆银
胡佳
Original Assignee
华为技术有限公司
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Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21831877.2A priority Critical patent/EP4161059A4/en
Priority to JP2022580738A priority patent/JP2023532689A/ja
Publication of WO2022001838A1 publication Critical patent/WO2022001838A1/zh
Priority to US18/069,552 priority patent/US11979695B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/45—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/65—Control of camera operation in relation to power supply
    • H04N23/651—Control of camera operation in relation to power supply for reducing power consumption by affecting camera operations, e.g. sleep mode, hibernation mode or power off of selective parts of the camera
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/66—Remote control of cameras or camera parts, e.g. by remote control devices
    • H04N23/661—Transmitting camera control signals through networks, e.g. control via the Internet
    • H04N23/662—Transmitting camera control signals through networks, e.g. control via the Internet by using master/slave camera arrangements for affecting the control of camera image capture, e.g. placing the camera in a desirable condition to capture a desired image
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/665—Control of cameras or camera modules involving internal camera communication with the image sensor, e.g. synchronising or multiplexing SSIS control signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/667—Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/68—Control of cameras or camera modules for stable pick-up of the scene, e.g. compensating for camera body vibrations
    • H04N23/681—Motion detection
    • H04N23/6812—Motion detection based on additional sensors, e.g. acceleration sensors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of data transmission, and in particular, to an SPI-based data transmission system.
  • camera modules supporting optical image stabilization include motor drivers, and each motor driver controls the motor of the camera module according to the gyroscope information collected by the gyroscope sensor (GYRO) to realize shake compensation.
  • the gyroscope sensor is generally installed on the main board of the smartphone, and the gyroscope sensor and the camera module are connected through a serial peripheral interface (SPI) to realize the gyroscope sensor and the camera.
  • SPI serial peripheral interface
  • the smartphone When the smartphone includes multiple camera modules that support optical image stabilization, one of the multiple camera modules is used as the master (master) SPI device, and the gyroscope sensor and other camera modules are used as the slave (slave) SPI device device. Since the master SPI device can only transmit data with one slave SPI device at the same time, when one camera module obtains the gyro information from the gyro sensor, other camera modules will be delayed in obtaining the gyro information from the gyro sensor, resulting in a delay. OIS effect is not ideal.
  • the present application provides an SPI-based data transmission system to improve the data transmission efficiency of the SPI system including a plurality of slave SPI devices.
  • the present application provides a data transmission system, which may include a master SPI device, a first slave SPI device, and a second slave SPI device.
  • the master SPI device can be used to output the first chip select signal to the first slave SPI device and the second slave SPI device, and output the second chip select signal to the first slave SPI device, the first chip select signal
  • the combination of the select signal and the second chip select signal is used to enable the first slave SPI device, the first chip select signal is used to enable the second slave SPI device, the master SPI device, all The first slave SPI device and the second slave SPI device are also connected through a data line.
  • the master SPI device can also be used to, when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, to control the second slave SPI device to pass The data line transmits data, and the second slave SPI device receives data through the data line.
  • the second SPI device can be used for, when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, according to the control of the master SPI device to pass The data line transmits data.
  • the first slave SPI device may be configured to receive the data through the data line when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state. Second data sent from the SPI device.
  • the master SPI device enables the first slave SPI device through the combination of the first chip select signal and the second chip select signal.
  • the master SPI device drives the first chip select signal to an active state and drives the second chip select signal In the inactive state
  • the master SPI device controls the second slave SPI device to send data through the data line
  • the master SPI device can also receive data through the data line
  • the first slave SPI device can receive data through the data line. Therefore, when the first chip select signal is in an active state and the second chip select signal is in an inactive state, the master SPI device and the first slave SPI device can simultaneously receive the data transmitted by the second slave SPI device, which improves the data of the SPI system transmission efficiency.
  • the sending port of the first slave SPI device and the receiving port of the master SPI device are connected through a first data line
  • the receiving port of the first slave SPI device is connected to the master SPI device
  • the transmission ports of the devices are connected by a second data line, and the data lines include the first data line and the second data line, and the transmission ports of the first slave SPI device and the master SPI device are used for For data transmission, the receiving port of the first slave SPI device and the receiving port of the master SPI device are used for data reception, then the first slave SPI device can also be used for, when the master SPI device drives the When the first chip selection signal is in an active state and the second chip selection signal is driven into an inactive state, switching the transmit port of the first slave SPI device to a receive port, and switching the first slave SPI device The receive port is switched to the transmit port.
  • the first slave SPI device when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, the first slave SPI device can switch the transmit port It is the receiving port to receive the data sent by the second slave SPI device through the data line.
  • the first slave SPI device can also switch the receiving port to the sending port, so that it does not receive data from the master SPI device, and does not need to respond to the write indication bit sent by the master SPI device, avoiding the same pass as the second slave SPI device. data line to send data to avoid data conflict.
  • the first slave SPI device is further configured to configure a data port of the first slave SPI device as a bidirectional data port, and the bidirectional data port supports data reception and transmission.
  • the first slave SPI device sets the data port as a bidirectional data port to receive data sent by the second slave SPI device through the data port.
  • the first slave SPI device can also send data sent by the master SPI device through the data port, thereby further improving data transmission efficiency.
  • the master SPI device may be specifically configured to, when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, send the data through the data line A first indication, where the first indication is used to control the sending of data. Then the first slave SPI device can also be used to not respond to the first chip select signal when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state. An instruction to send data.
  • the first slave SPI device does not respond to the first instruction from the master SPI device, which can avoid sending data simultaneously with the second slave SPI device through the data line according to the first instruction to avoid data conflict.
  • the master SPI device can also be used to send a second indication through the data line when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state and data, the second indication is used to control the reception of the data.
  • the first slave SPI device can also be used to receive through the data line when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state the second indication, and receiving data over the data line in response to the second indication.
  • the first slave SPI device can receive data from the master SPI device according to the second instruction device data.
  • the master SPI device can also be used to send a first indication through the data line when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state and receiving data from the first slave SPI device through the data line, and the first indication is used to control the transmission of the data.
  • the first slave SPI device can also be used to receive through the data line when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state the first indication, and sending data over the data line in response to the first indication.
  • the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state
  • the first slave SPI device can report to the master SPI device according to the first instruction Send data.
  • the first slave SPI device can also be used to not pass the Data lines transmit data, and data are not received over the data lines.
  • the first slave SPI device may not respond to the data sent by the master SPI device.
  • the read indicator bit reads data.
  • the first slave SPI device does not send data in response to the write indication bit sent by the master SPI device, so as to avoid collision of data transmission on the data line.
  • the present application provides a chip, which can be used in the first slave SPI device described in the first aspect.
  • the chip may include an SPI controller, an SPI control logic unit (or SPI control logic circuit), an SPI data transceiver switching unit (or SPI data transceiver switching circuit), and an SPI data port (or data port), etc. components.
  • the SPI control logic circuit can be used to receive a first chip select signal and a second chip select signal from the master SPI device, and the combination of the first chip select signal and the second chip select signal is used to enable the chip.
  • the SPI data port can be connected to the master SPI device and the second slave SPI device through data lines.
  • the SPI control logic circuit can be used to control the SPI controller to pass the The SPI data port receives the data sent by the second slave SPI device in the data line.
  • the SPI data port may include a sending port and a receiving port, the sending port is connected to the receiving port of the main SPI device through a data line, and the receiving port is connected to the receiving port of the main SPI device through a data line.
  • a sending port is connected, the sending port is used for the chip to send data to the data line, and the receiving port is used for the chip to receive the data transmitted in the data line.
  • the SPI control logic circuit can also be used to configure the transmit port to use when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state. for receiving the data transmitted in the data line.
  • the chip may further include an SPI data transceiver switching circuit
  • the SPI controller may include a sending module and a receiving module, the sending module is used for data transmission, and the receiving module is used for data reception.
  • the SPI control logic circuit can also be used for, when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, to control the SPI data transceiver switching circuit to switch all the The sending port is connected to the receiving module.
  • the SPI control logic circuit can also be used to configure the SPI data port as a bidirectional data port, and the bidirectional data port supports data reception and transmission.
  • the SPI control logic circuit can also be used to control the SPI controller not to respond when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the data is sent according to the first instruction transmitted by the data line, and the first instruction is used to control the sending of the data.
  • the SPI control logic circuit can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to control the SPI controller to pass the The SPI data port receives the data transmitted in the data line.
  • the SPI controller can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to receive the first chip transmitted in the data line.
  • Two indications the second indication is used to control the reception of data, and in response to the second indication, the data transmitted in the data line is received through the SPI data port.
  • the SPI control logic circuit can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to control the SPI controller to pass the The SPI data port receives the data transmitted in the data line.
  • the SPI controller can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to receive the first chip transmitted in the data line.
  • an instruction the first instruction is used to control the sending of data; in response to the first instruction, data is sent to the data line through the SPI data port.
  • the SPI control logic circuit can also be used to control the SPI controller not to be active when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an inactive state. Data is sent through the data line, and the SPI controller is controlled not to receive data through the data line.
  • SPI controller SPI control logic circuit
  • SPI data transceiver switching circuit SPI data port
  • the present application provides a camera module
  • the camera module may include the chip described in the second aspect or any design of the second aspect, and the camera module may have any design of the second aspect or the second aspect the function of the chip.
  • the camera module may further include a motor and a camera.
  • the motor may be used to obtain data from the gyro sensor from the chip to perform shake control and/or auto focus (AF) of the camera.
  • the present application provides a terminal device.
  • the terminal device may include the data transmission system described in the first aspect or any design of the first aspect, so the terminal device may have the first aspect or any one of the first aspect. Design the functions described.
  • the terminal device may include the chip described in the second aspect or any design of the first aspect, so the terminal device may have the functions of the chip described in the first aspect or any design of the first aspect.
  • the terminal device may include the camera module described in the third aspect, and therefore, the terminal device may have the function of the chip designed in the second aspect or any one of the second aspect.
  • the terminal device may be a device capable of taking pictures.
  • the terminal device may also include an image processing chip (image signal processing, ISP) for acquiring image signals from the camera module and processing the image signals, for example, performing high-definition processing on the image signals output by the camera module etc.
  • ISP image signal processing
  • the present application provides a data transmission system, which may include a first camera, a second camera and a first sensor.
  • the first camera, the second camera and the first sensor communicate through the SPI protocol.
  • the first camera is a master SPI device, and the second camera and the first sensor are slave SPI devices, wherein, when the first camera and the second camera are running at the same time, the first camera obtains the first sensor data through the SPI protocol, and The second camera simultaneously acquires the first sensor data through the SPI protocol.
  • the first camera and the second camera can simultaneously acquire the first sensor data, thereby reducing the delay in acquiring the sensor data by the cameras, and improving the OIS effect of the camera module.
  • the first camera can output the first chip select signal to the second camera and the first sensor, and output the second chip select signal to the second camera and the first sensor, the first chip select signal And the state combination of the second chip select signal is used to control whether to enable the second camera and to control whether to enable the first sensor.
  • the first camera, the second camera and the first sensor SPI device are also connected through a data line.
  • the first camera can control the second camera to send data through the data line, and receive the second camera through the data line
  • the first sensor can send data through the data line according to the control of the first camera
  • the second camera can receive the data sent by the first sensor to the first camera through the data line.
  • the first camera can flexibly control the working states of the second camera and the first sensor through the first chip selection signal and the second chip selection signal.
  • the first camera and the second camera can simultaneously acquire the data of the first sensor, thereby improving the data transmission efficiency.
  • the first camera can output the first chip select signal to the second camera and the first sensor, and output the second chip select signal to the second camera and the first sensor, the first chip select signal And the state combination of the second chip select signal is used to control whether to enable the second camera and to control whether to enable the first sensor.
  • the first camera, the second camera and the first sensor SPI device are also connected through a data line.
  • the first The camera can control the second camera to send data through the data line, and receive data sent by the second camera through the data line, the first sensor can send data through the data line according to the control of the first camera, and the second camera can send data through the data line.
  • the camera can receive data sent by the first sensor to the first camera through the data line.
  • the first camera can flexibly control the working states of the second camera and the first sensor through the first chip selection signal and the second chip selection signal.
  • the first camera and the second camera can simultaneously acquire the data of the first sensor, thereby improving the data transmission efficiency.
  • the first camera can send data to the second camera through the data line
  • the first sensor can receive the data sent by the first camera through the data line
  • the second camera can receive the data sent by the first camera through the data line Data from the first sensor.
  • the first camera can flexibly control the working states of the second camera and the first sensor through the first chip selection signal and the second chip selection signal.
  • the second camera and the first sensor can simultaneously acquire data from the first camera, thereby improving data transmission efficiency.
  • the sending port of the second camera is connected to the receiving port of the first camera through a first data line
  • the receiving port of the second camera is connected to the sending port of the first camera through a second data line
  • the data The line includes a first data line and the second data line, the sending port of the second camera and the sending port of the first camera are used for data transmission, and the receiving port of the second camera and the receiving port of the first camera are used for data transmission.
  • the second camera can also Switch the sending port of the second camera to the receiving port, and switch the receiving port of the second camera to the sending port.
  • the second camera can receive the data sent by the first camera by switching between the sending port and the receiving port, and the second camera no longer receives data and instructions from the first camera. No data is sent through the data line to avoid data transmission conflicts.
  • the data port of the second camera can also be configured as a bidirectional data port, the bidirectional data port supports data reception and transmission.
  • the data port of the second camera can be set as a bidirectional data port to receive data sent by the first sensor through the data port.
  • the second camera can also receive the data sent by the first camera through the data port, so as to further improve the data transmission efficiency.
  • the first camera can send a first instruction through the data line, the first instruction is used to control the sending of data, and the second camera does not send data in response to the first instruction.
  • the second camera may not respond to the received first instruction, so data will not be sent through the data line, thereby avoiding data transmission conflicts.
  • the first camera when the first chip select signal is in an inactive state and the second chip select signal is in an active state, or when the first chip select signal and the second chip select signal are in a preset state combination , the first camera can send the second instruction and data through the data line, the second instruction can be used to control data reception, the second camera can receive the second instruction through the data line, and receive data through the data line in response to the second instruction.
  • the first camera can flexibly control the working state of the second camera, so that the second camera can receive the data transmitted in the data line according to the second instruction from the first camera, so as to improve the transmission efficiency.
  • the first camera when the first chip select signal is in an inactive state and the second chip select signal is in an active state, or when the first chip select signal and the second chip select signal are in a preset state combination , the first camera can send the first instruction through the data line, the first instruction is used to control the sending of data, the second camera can receive the first instruction, and send the data through the data line according to the first instruction, the first camera can also Receive data from the second camera through the data line.
  • the second camera can send data to the first camera according to the first instruction, so as to improve transmission efficiency.
  • the second camera when the first chip selection signal is in an inactive state and the second chip selection signal is in an inactive state, or, when the first chip selection signal and the second chip selection signal are in a preset state combination (For example, when the first chip selection signal is in an inactive state and the second chip selection signal is in an inactive state, or other state combinations), the second camera does not send data through the data line, and does not receive data through the data line, so as to The flexible switching of the working mode of the second camera is realized.
  • the first sensor is a gyroscope sensor.
  • the first sensor information comes from the first sensor, and the first sensor information is gyroscope information.
  • the present application provides a circuit.
  • the circuit can be connected to the second camera of the fifth aspect.
  • the circuit may include an SPI controller, an SPI control logic unit (or SPI control logic circuit), an SPI data transceiver switching unit (or SPI data transceiver switching circuit), or an SPI data port (or a data port). some or all of the components.
  • the SPI controller may be configured to control the SPI data port to obtain the first sensor data when the first camera obtains the first sensor data through the SPI protocol.
  • the SPI data port is used for the SPI protocol communication between the second camera and the first camera and/or the first sensor, the first camera is a master SPI device, and the second camera and the first sensor are slave SPI devices.
  • the SPI data port may send the acquired first sensor data to the second camera.
  • the SPI data port is connected to the first camera and the first sensor through a data line.
  • the circuit further includes an SPI control logic unit for receiving the first chip select signal and the second chip select signal from the first camera, and the combination of the first chip select signal and the second chip select signal is used for Controls whether to enable the second camera.
  • the SPI control logic circuit can control the SPI controller to control the SPI data port to receive data sent by the first sensor in the data line to the first camera.
  • the circuit further includes an SPI control logic unit for receiving the first chip select signal and the second chip select signal from the first camera, and the combination of the first chip select signal and the second chip select signal is used for Controls whether to enable the second camera.
  • the SPI control logic circuit can control the SPI controller to control the SPI data port to receive data sent by the first sensor in the data line to the first camera.
  • the SPI control logic unit may further control the SPI controller to control the SPI data port to receive data sent from the first camera in the data line to the first sensor.
  • the sending port of the second camera is connected to the receiving port of the first camera through a first data line
  • the receiving port of the second camera is connected to the sending port of the first camera through a second data line
  • the data The line includes a first data line and the second data line
  • the sending port of the second camera and the sending port of the first camera are used for data transmission
  • the receiving port of the second camera and the receiving port of the first camera are used for data transmission.
  • the SPI control logic unit also
  • the transmit port can be configured to receive data transmitted on the data line.
  • the circuit further includes an SPI data transceiver switching circuit
  • the SPI controller includes a sending module and a receiving module, the sending module is used for data transmission, and the receiving module is used for data reception; when the first chip select signal When it is in an active state and the second chip select signal is in an inactive state, or, when the first chip select signal and the second chip select signal are a preset state combination, the SPI control logic unit can also control the SPI data transmission and reception switching Circuitry connects the transmit port to the receive module.
  • the SPI control logic unit may further configure the SPI data port as a bidirectional data port, the bidirectional data port supports data reception and transmission.
  • the SPI control logic unit may further control the SPI controller not to send data in response to a first instruction transmitted by the data line, where the first instruction is used to control the sending of data.
  • the SPI control logic unit can control the SPI controller to receive the second indication transmitted in the data line through the SPI data port.
  • the SPI controller can control the SPI data port to receive the data transmitted in the data line in response to the second indication, and the second indication is used to control the reception of the data.
  • the SPI control logic unit can control the SPI controller to receive the first indication transmitted in the data line through the SPI data port.
  • the SPI controller may control the SPI data port to send data to the data line in response to the first instruction, and the first instruction is used to control the sending of the data.
  • the SPI control logic unit can control the SPI controller not to send data through the data line, and control the SPI controller not to receive data through the data line.
  • the present application provides a circuit.
  • the circuit can be connected to the first camera of the fifth aspect.
  • the circuit may include a control unit (or called a control circuit) and an SPI data port.
  • a control unit or called a control circuit
  • SPI data port an SPI data port
  • the SPI data port can be used for the first camera to obtain the first sensor data through the SPI protocol.
  • the control circuit can be used to control the second camera to simultaneously obtain the first sensor data through the SPI protocol, the first camera is the main SPI device, and the second camera and the first sensor are from the SPI device.
  • the first sensor data comes from the first sensor.
  • the SPI data port is connected to the second camera and the first sensor through a data line.
  • control circuit may output a first chip select signal to the second camera and the first sensor, and output a second chip select signal to the second camera and the first sensor A sensor, the state combination of the first chip selection signal and the second chip selection signal is used to control whether to enable the second camera and to control whether to enable the first sensor.
  • the control circuit can control the first sensor to send data through the data line, and control the SPI data port to send data through the data line.
  • the data line receives data sent by the first sensor, and controls the second camera to receive data sent by the first sensor to the first camera through the data line.
  • the control circuit can control the first sensor to send data through the data line, and control the SPI data port to send data through the The data line receives data sent by the first sensor, and controls the second camera to receive data sent by the first sensor to the first camera through the data line.
  • control circuit may further control the SPI data port to send data to the first sensor through the data line, and control the second camera to receive the data sent from the first camera to the first sensor through the data line.
  • the control circuit can control the SPI data port to send the first indication through the data line, and the first indication is used to control the sending of the data.
  • the control circuit can control the SPI data port to send the first indication through the data line, and the first indication is used to control the sending of the data.
  • the present application provides a camera module
  • the camera module can include the circuit described in the sixth aspect or any design of the sixth aspect, so as to realize the circuit described in the sixth aspect or any design of the sixth aspect function.
  • the camera module may further include a motor and a second camera.
  • the motor can be used to obtain first sensor data (ie, gyroscope data) through the circuit, and use and perform shake control and/or auto focus of the camera according to the first sensor data , AF).
  • the present application provides a camera module.
  • the camera module may include the circuit described in the seventh aspect or any design of the seventh aspect, so as to realize the circuit described in the seventh aspect or any design of the seventh aspect. function.
  • the camera module may further include a motor and a first camera.
  • the motor can be used to obtain first sensor data (ie, gyroscope data) through the circuit, and perform shake control and/or auto focus of the camera according to the first sensor data.
  • the present application provides a terminal device.
  • the terminal device may include the data transmission system described in the fifth aspect or any design of the fifth aspect. Therefore, the terminal device may have the fifth aspect or any one of the fifth aspect. Design the functions described.
  • the terminal device may include the circuit described in the sixth aspect or any design of the sixth aspect, so the terminal device may have the function of the circuit described in the sixth aspect or any design of the sixth aspect.
  • the terminal device may include the circuit described in the seventh aspect or any design of the seventh aspect, so the terminal device may have the function of the circuit described in the seventh aspect or any design of the seventh aspect.
  • the terminal device may include the camera module described in the eighth aspect or any design of the eighth aspect, therefore, the terminal device may have the function of the camera module described in the eighth aspect or any design of the eighth aspect .
  • the terminal device may include the camera module described in the ninth aspect or any design of the ninth aspect, therefore, the terminal device may have the function of the camera module described in the ninth aspect or any design of the ninth aspect .
  • the terminal device may be a camera-capable device.
  • the terminal device may also include an image processing chip (image signal processing, ISP) for acquiring image signals from the camera module and processing the image signals, for example, performing high-definition processing on the image signals output by the camera module etc.
  • ISP image signal processing
  • the present application provides a terminal device, including a first camera module, a second camera module, and a gyroscope sensor for outputting gyroscope information.
  • the first camera module, the second camera module and the gyro sensor are connected through a serial peripheral interface SPI.
  • the first camera module is used as the master SPI device
  • the gyroscope sensor and the second camera module are both used as slave SPI devices
  • the first camera module and the second camera module are sent by the first camera module.
  • the gyroscope information is obtained from the gyroscope sensor at the same time.
  • the image processing unit is used for acquiring image signals from the first camera module and the second camera module.
  • both the first camera module and the second camera module are connected to the gyro sensor through a data cable; the SPI chip selection signal sent by the first camera module is a preset state combination At the same time, the first camera module and the second camera module obtain the gyroscope information from the gyroscope sensor at the same time.
  • both the first camera module and the second camera module are connected to the gyro sensor through a data cable; the SPI chip select signal sent by the first camera module enables the second camera module and the gyro sensor, the first camera module and the second camera module simultaneously obtain the gyro information from the gyro sensor.
  • the second camera module and the gyro sensor receive data from the first camera module at the same time.
  • FIG. 1 is a schematic structural diagram of a data transmission system according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a logic judgment result of a dual chip select provided by an embodiment of the present application
  • FIG. 3 is a schematic sequence diagram of data transmission according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a connection relationship of a data transmission system according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a connection relationship of another data transmission system provided by an embodiment of the present application.
  • FIG. 6 is a schematic sequence diagram of another data transmission provided by an embodiment of the present application.
  • FIG. 7 is a schematic sequence diagram of another data transmission provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a connection relationship of another data transmission system provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a slave SPI device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a data transmission system according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a connection relationship of another data transmission system provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a connection relationship of another data transmission system provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a connection relationship of another data transmission system provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a circuit provided by an embodiment of the present application.
  • At least one means one, or more than one, that is, including one, two, three and more.
  • Plural means two, or more than two, that is, including two, three and more.
  • Carrying may mean that a certain message is used to carry certain information or data, or it may mean that a certain message is composed of certain information.
  • Coupling refers to indirect coupling or communication connection between devices, units or modules, which can be in electrical, mechanical or other forms, for information exchange between devices, units or modules.
  • the SPI structure may include a master SPI device (or a master device, a master device) and a slave SPI device (or a slave device, a slave device), and an SPI connection line between the master SPI device and the slave SPI device.
  • the SPI connection line between the master SPI device and the slave SPI device may include a chip select signal line, a serial clock (serial clock, SCK) (hereinafter may be referred to as a clock line), a data line, and the like.
  • the master SPI device can enable (or gate) a slave SPI device through a chip select signal, and pass an indication bit of the data line (hereinafter referred to as In order to write the indication bit) and the clock line instructing the enabled slave SPI device to send data through the data line, the master SPI device can read the data sent from the slave SPI device through the data line.
  • the master SPI device can read data through the data line through an indication bit of the data line (hereinafter referred to as the read indication bit) and the clock line instructs the enabled slave SPI device to read data through the data line, and the master SPI device can also send data through the data line, thereby Causes the slave SPI device to receive data over the data line.
  • the read indication bit an indication bit of the data line
  • the clock line instructs the enabled slave SPI device to read data through the data line
  • the master SPI device can also send data through the data line, thereby Causes the slave SPI device to receive data over the data line.
  • the chip selection signal line refers to a signal line for transmitting a chip selection signal (chip selection, CS).
  • the chip select signal may include an active state and an inactive state.
  • the chip select signal can be used to enable the slave SPI device.
  • the master SPI device 101 may drive the chip select signal in an inactive state, thereby making the slave SPI device in an inactive state.
  • the chip select signal is at a low level (eg, the potential is 0)
  • the chip select signal is in an active state
  • the chip select signal is at a high level (eg, the potential is 1)
  • the chip select signal is at a Invalid state.
  • Clock line which can be generated by the master SPI device.
  • the clock line can be used for clock synchronization to the master SPI device as well as the slave SPI device.
  • the data line may include a serial data line (SDA) in a three-wire mode.
  • SDA serial data line
  • the data lines may also include a four-wire mode output data line (serial data output, SDO) and an input data line (serial data input, SDI).
  • SDO and SDI are unidirectional data lines.
  • SDO can be used for SPI devices to send data
  • SDI can be used for SPI devices to receive data.
  • the data line that sends data from the master SPI device to the slave SPI device can also be called the master output/slave input data line (MOSI), that is, the MOSI can be used to transmit the data sent by the master SPI device through SDO.
  • MOSI master output/slave input data line
  • the data from the SPI device can receive data from MOSI via SDI.
  • the data line that sends data from the SPI device to the master SPI device can also be called the master input/slave output data line (master input/slave output, MISO), that is, MISO can be used to transmit data sent from the SPI device through SDO, the master SPI A device can receive data from MOSI via SDI.
  • MISO master input/slave output
  • the SPI device can send data to the data line through the data port, or receive data in the data line through the data port.
  • the SPI device has at least one data port, which is a bidirectional data port that supports data reception and transmission. In three-wire mode, this data port can be connected to SDA.
  • the SPI device can include at least two data ports, wherein one data port can be used as a transmit port to support data transmission, and the transmit port is connected to SDO; one data port can be used as a receive port to support Event reception, the send port is connected to SDI.
  • Read and write indicator bits which can include read indicator bits and write indicator bits.
  • the read indication bit can be used to control the slave SPI device receiving the read indication to receive data through the data line.
  • the read/write indication bit may be the first data bit output by the master SPI device after the clock line starts.
  • the read/write indicator bit may be the first data bit output by the master SPI device through SDA after the clock line starts; in four-wire mode, the read/write indicator bit may be output by the master SPI device through SDO after the clock line starts the first data bit. If the first data bit after the start of the clock line is set to 1, this data bit may be referred to as a read indicator bit.
  • the write indicator bit can be used to control the slave SPI device that receives the read indicator to send data over the data line.
  • the data bit may be referred to as a write indication bit.
  • the write indication bit may also be referred to as the first indication.
  • the read indicator bit may also be referred to as a second indicator.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c Can be single or multiple.
  • the data transmission method provided in the embodiment of the present application can be applied to an SPI bus system (or SPI structure), wherein the system may include a master SPI device and at least two slave SPI devices, the master SPI device and the at least The two slave SPI devices are connected by a data line.
  • SPI bus system or SPI structure
  • the system may include a master SPI device and at least two slave SPI devices, the master SPI device and the at least The two slave SPI devices are connected by a data line.
  • a data transmission system 100 may include a master SPI device 101 , a first slave SPI device 102 , and a second slave SPI device 103 .
  • the data transmission system 100 provided in this embodiment of the present application can be applied to a terminal device or other electronic device having an SPI structure, for example, a mobile terminal or a computer and other devices.
  • a possible application scenario of the data transmission system 100 provided in this embodiment of the present application is a camera-capable device including multiple camera modules.
  • the camera-capable device may be a smartphone with a camera function, a mobile smart device, Functional home equipment or tablet computers, etc., can also be portable, pocket-sized, hand-held, computer built-in or vehicle-mounted mobile devices.
  • the master SPI device 101 may include one camera module among the multiple camera modules of the photographic device (in this application, the camera module serving as the master SPI device may be referred to as camera module A), the first slave The SPI device 102 may include another camera module of the photographic device (in this application, the camera module as the slave SPI device may be referred to as camera module B), and the second slave SPI device 103 may include the gyroscope of the photographic device. instrument sensor. Among them, the gyroscope sensor can be deployed on the main board of the camera device.
  • each camera module may include a motor driver chip, or a motor driver integrated circuit (IC).
  • the motor driver IC can be used to output current or pulse width modulation (PWM) signal to control the motor of the camera module to move as required to achieve jitter compensation.
  • PWM pulse width modulation
  • the master SPI device 101, the first slave SPI device 102, and the second slave SPI device 103 are connected through a data line.
  • the data line may include SDA.
  • the data lines may include SDO and SDI.
  • the master SPI device 101 , the first slave SPI device 102 and the second slave SPI device 103 are also connected through a clock line.
  • the master SPI device 101 outputs a first chip select signal (CS1) to the first slave SPI device 102 and a second chip select signal (CS2) to the first slave SPI device 102. Therefore, the master SPI device 101 can make the first slave SPI device 102 in various working modes through the combination of the active state or inactive state of the first chip select signal and the active state or inactive state of the second chip select signal.
  • CS1 chip select signal
  • CS2 second chip select signal
  • the master SPI device 101 can also output the first chip select signal to the second slave SPI device 103, so that the second slave SPI device 103 can be enabled by the first chip select signal.
  • the first chip select signal when the first chip select signal is in an active state, the first chip select signal enables the second slave SPI device 103 , and the second slave SPI device 103 can send the data line according to the write indication bit output by the master SPI device 101 .
  • the second slave SPI device 103 may read data through the data line according to the read indication bit output by the master SPI device 101 .
  • the logical judgment result of the dual chip selection of the first slave SPI device 102 can be represented by FIG. 2 .
  • the judgment result of the dual chip select logic is the working mode of the first slave SPI device 102 .
  • the chip select signal is inactive.
  • "a&b" means a and b.
  • the result of the dual chip select logic judgment is the data listening mode, and the first slave SPI device 102 can enter the data listening mode (or, the first slave SPI device 102) according to the judgment result. 102 is in data listening mode).
  • the first slave SPI device 102 can receive data through the data line, but not send data through the data line.
  • the first slave SPI device 102 regardless of whether the master SPI device 101 outputs the write indication bit or the read indication bit, the first slave SPI device 102 only listens to the data line and receives the data transmitted by the data line.
  • the judgment result of the dual chip select logic is the standard slave SPI device mode (or called the standard slave mode), and the first slave SPI device 102 can enter the standard slave SPI device mode (or called as the standard slave mode) according to the judgment result.
  • the first slave SPI device 102 is in standard slave SPI device mode). In the standard slave mode, the first slave SPI device 102 can receive data through the data line according to the read indication bit output by the master SPI device 101 , and can also transmit data through the data line according to the write indication bit output by the master SPI device 101 .
  • the result of the dual chip select logic judgment is the non-gated mode, and the first slave SPI device 102 can enter the non-gated mode according to the judgment result (or, the first slave SPI device 102 is in the non-gated mode). un-gated mode).
  • the first slave SPI device 102 does not receive data through the data line, nor does it send data through the data line.
  • the first slave SPI device 102 does not respond to the instruction of the master SPI device 101 .
  • FIG. 3 the bus access mode of the first slave SPI device 102 in the data listening mode will be described.
  • the master SPI device 101 sets the first data bit (ie read/write indication bit) after the start of SCK to 0 (indicates write) or 1 (indicates read)
  • the first slave SPI device 102 only supports data input because it is in the data listening mode, and will not output data to the data lines (including SDA in three-wire mode or SDO in four-wire mode).
  • the connection relationship among the master SPI device 101 , the first slave SPI device 102 and the second slave SPI device 103 is shown in FIG. 4 . It can be seen that the respective data ports of the first slave SPI device 102 and the second slave SPI device 103 of the master SPI device 101 (the data ports are connected to the SDA) both support bidirectional data transmission. Illustratively, when in three-wire mode, the first slave SPI device 102 may configure its data port as a bidirectional port.
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the master SPI device 101 sends a write indication bit through SDA
  • the master SPI device 101 can receive data sent by the second slave SPI device 103 through SDA
  • the first slave SPI device 102 is in the data
  • the first slave SPI device 102 can receive the data sent by the second slave SPI device 103 through the SDA.
  • the first slave SPI device 102 does not send data on the SDA in response to the write indication bit transmitted by the SDA (or, the first slave SPI device 102 ignores the data transmission in response to the write indication bit) to avoid causing SDA Data conflict on.
  • the expression “the SPI device sends data through the SDA/SDO” in this application means that the SPI device sends data to the SDA/SDO through the sending port connected to the SDO, and the SDA/SDO sends the data to other SPI devices. send. It should also be understood that the expression “the SPI device receives data through SDA/SDI” in this application means that the SPI device receives data from the SDA/SDI through the receiving port connected to the SDA/SDI from other SPI devices through the SDA/SDA of other SPI devices. Data sent by SDO.
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the master SPI device 101 sends a read indication bit through the SDA
  • the master SPI device 101 The device 101 can also send data through SDA.
  • the second slave SPI device 103 can receive the data sent by the master SPI device 101 through SDA in response to the read indication bit, and the first slave SPI device 102 is in the data listening mode. Therefore, The first slave SPI device 102 can receive data sent by the master SPI device 101 through SDA. Therefore, multiple slave SPI devices can simultaneously receive data sent by the master SPI device, thus improving the efficiency when multiple slave SPI devices receive data from the master SPI device.
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the master SPI device 101 , the first slave SPI device 102 and the second slave SPI device 103 The connection relationship between them is shown in Figure 5. It can be seen that the master SPI device 101, the first slave SPI device 102 and the second slave SPI device 103 can transmit data through their respective transmit ports (the transmit ports are connected to the SDO), and can transmit data through their respective receive ports (the receive ports are connected to the SDO). SDI connection) to receive data.
  • the second slave SPI device 103 can send data through SDO in response to the write indication bit, and the master SPI device 101 can receive the second through SDI.
  • the data sent by the slave SPI device 103 through SDO, and the first slave SPI device 102 is in data listening mode, so the first slave SPI device 102 can receive data sent by the second slave SPI device 103 through SDO through SDI.
  • the SDO of the first slave SPI device 102 will not receive the write indication bit sent by the master SPI device 101 through the SDO. Therefore, the first slave SPI device 102 does not transmit data in response to the write indication bit sent by the master SPI device 101 ( In other words, the first slave SPI device 102 ignores the data transmission in response to the write indication bit), so as to avoid data transmission conflicts.
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, if the master SPI device 101 sends a read indication bit through SDO , and send data through SDO, at this time, the second slave SPI device 103 can receive data through SDI in response to the read indication bit.
  • the bus access mode of the first slave SPI device 102 in the standard slave SPI device mode will be described by taking FIG. 6 and FIG. 7 as examples.
  • the first slave SPI device 102 works in the standard slave SPI device mode. If the master SPI device 101 sets the first bit of data after SCK to 0, the first slave SPI device 102 can read data transmitted on the data lines (SDA or SDI) under the control of the master SPI device 101 . As shown in FIG.
  • the first slave SPI device 102 in the standard slave SPI device mode, if the master SPI device 101 sets the first bit of data after SCK to 1, the first slave SPI device 102 can pass the data line under the control of the master SPI device 101 (SDA or SDO) to send data. Therefore, when in the standard slave SPI device mode, the first slave SPI device 102 can implement data transmission between the first slave SPI device 102 and the master SPI device 101 under the control of the master SPI device 101 .
  • the connection relationship among the master SPI device 101 , the first slave SPI device 102 and the second slave SPI device 103 is shown in FIG. 4 .
  • the master SPI device 101 drives the first chip select signal to an inactive state and drives the second chip select signal to an active state
  • the master SPI device 101 sends a write indication bit through SDA
  • the first slave SPI device 102 is in the standard slave mode at this time
  • the second slave SPI device 103 can send data through SDA in response to the write indication bit
  • the master SPI device 101 can receive data sent by the first slave SPI device 102 through SDA.
  • the second slave SPI device 103 is in a non-gated state, and does not respond to the write indication bit transmitted by the SDA.
  • the master SPI device 101 drives the first chip select signal to an inactive state and drives the second chip select signal to an active state
  • the master SPI device 101 sends a read indication bit through SDA and transmits data through SDA
  • the first slave SPI device 102 can receive data through the SDA in response to the read indication bit transmitted by the SDA.
  • the second slave SPI device 103 is in a non-gated state, and does not respond to the read indication bit transmitted by the SDA.
  • the connection relationship among the master SPI device 101 , the first slave SPI device 102 and the second slave SPI device 103 is shown in FIG. 8 .
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the master SPI device 101 sends a write indication bit through SDO
  • the first slave SPI device 102 is in the standard slave mode at this time
  • the first slave SPI device 102 can receive the write indication bit through SDI
  • the master SPI device 101 can receive through SDI the data sent by the first slave SPI device 102 through SDO.
  • the second slave SPI device 103 is in a non-gated state, and does not respond to the write indication bit sent by the master SPI device 101 through SDO.
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the master SPI device 101 sends the read indication bit through SDO and sends data through SDO
  • the first slave SPI device 102 is in the standard slave mode
  • the first slave SPI device 102 can receive the read indication bit through SDI, and read data through SDI in response to the read indication bit.
  • the second slave SPI device 103 is in a non-gated state, and does not respond to the read indication bit sent by the master SPI device 101 through SDO.
  • the connection relationship among the master SPI device 101 , the first slave SPI device 102 and the second slave SPI device 103 is as shown in FIG. 4 .
  • the connection relationship among the master SPI device 101 , the first slave SPI device 102 , and the second slave SPI device 103 is as shown in FIG. 8 .
  • the judgment result of the above dual chip select logic can also be represented by Table 1.
  • the first chip select signal Second chip select signal The operating mode of the first slave SPI device valid state Inactive state data listening mode Inactive state valid state Callout Slave SPI Device Mode Inactive state Inactive state Ungated mode
  • the first slave SPI device 102 when the state of the first chip select signal is an active state and the state of the second chip select signal is an inactive state, the first slave SPI device 102 can be made to enter the data listening mode. When the state of the first chip select signal is an inactive state and the state of the second chip select signal is an active state, the first slave SPI device 102 can be made to enter the standard slave SPI device mode. When the state of the first chip select signal is an inactive state and the state of the second chip select signal is an inactive state, the first slave SPI device 102 can be made to enter the non-gating mode.
  • the master SPI device 101 when the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state , the master SPI device 101 can control the second slave SPI device 103 to send data through the data line, and receive data sent by the second slave SPI device 103 through the data line. At this time, since the first slave SPI device 102 is in the data listening mode, the first slave SPI device 102 can receive data through the data line.
  • the master SPI device 101 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the master SPI device 101 and the first slave SPI device can simultaneously receive the data sent by the second slave SPI device 103 , which improves the data transmission efficiency between the master SPI device and multiple slave SPI devices.
  • the master SPI device 101 includes one camera module among the plurality of camera modules of the camera-capable device
  • the first slave SPI device 102 includes the other camera module of the camera-capable device
  • the second slave SPI device 103 includes the camera-capable device
  • the gyroscope sensor is used, multiple camera modules including the master SPI device 101 and the first slave SPI device 102 can simultaneously receive gyroscope information (or data from the gyroscope sensor) sent by the gyroscope sensor.
  • the gyroscope information here may include data such as the X/Y/Z triaxial angular velocity information of the gyroscope, and the camera module that supports optical image stabilization can calculate the angular velocity information of the human hand when taking pictures according to the X/Y/Z triaxial angular velocity information of the gyroscope. shake, and control the lens through a motor (such as a motor integrated inside the camera module) to achieve shake compensation.
  • a motor such as a motor integrated inside the camera module
  • the master SPI device 101 should avoid driving the first chip select signal to an active state and driving the second chip select signal to an active state at the same time. If the master SPI device 101 erroneously drives the first chip select signal and the second chip select signal to be active at the same time, the first slave SPI device 102 can determine that the drive state is wrong and does not respond to the bus operation.
  • the first slave SPI device 102 can switch its data port, so as to realize the connection relationship shown in FIG. 5 and FIG. 8 without changing the connection lines between chips switch.
  • the switching of the data port includes, but is not limited to, switching the data port from a unidirectional data port to a bidirectional data port, or switching a sending port to a receiving port, or switching a receiving port to a sending port, and so on.
  • the first slave SPI device 102 can respond to CS1 and CS2 to switch the transmit port of the first slave SPI device 102 to the receive port (in other words, the first slave SPI device 102 The SPI device 102 switches the SDO of the first slave SPI device 102 to SDI), and switches the receive port of the first slave SPI device 102 to the transmit port (in other words, the first slave SPI device 102 switches the first slave SPI device 102 The SDI is switched to SDO), and the connection relationship shown in Figure 5 is obtained. At this time, the receive port of the first slave SPI device 102 is connected to the receive port of the master SPI device 101 , and the transmit port of the first slave SPI device 102 is connected to the transmit port of the master SPI device 101 .
  • the first slave SPI device 102 can switch the receiving port of the first slave SPI device 102 to the sending port in response to CS1 and CS2 (in other words, the first slave SPI device 102 switches the SDI of the first slave SPI device 102 switch to SDO), and switch the transmit port of the first slave SPI device 102 to the receive port (in other words, the first slave SPI device 102 switches the SDO of the first slave SPI device 102 to SDI), thereby obtaining Figure 8 connection shown.
  • the following describes the manner in which the first slave SPI device 102 performs data port switching with reference to FIG. 9 .
  • the first slave SPI device 102 can be composed of an SPI controller, an SPI control logic unit (or SPI control logic circuit), an SPI data transceiving switching unit (or SPI data transceiving switching circuit), and an SPI data port (or SPI data transceiving switching circuit). called data port) and so on.
  • the SPI controller can be used for the first slave SPI device 102 to process data to be sent, or for the first slave SPI device 102 to process data received through the data line.
  • the SPI controller may include a sending module and a receiving module, the sending module may be used for processing and sending data to be sent to the sending port, and the receiving module may be used for receiving and processing data from the receiving port.
  • the SPI controller may also control the reception and/or transmission of data according to the operating mode the first slave SPI device 102 is in. For example, when the first slave SPI device 102 is in the listening mode, the SPI controller may not transmit the data to be sent to the sending port. For another example, when the first slave SPI device 102 is in the non-gating mode, the SPI controller may not transmit data to be sent to the transmit port, and the SPI controller may not process the data from the receive port through the receive module.
  • the SPI control logic unit can receive the first chip select signal and the second chip select signal, and according to the first chip select signal and the second chip select signal, it can judge the logic result of the dual chip select judgment.
  • the judgment result can be shown in Figure 2 or Table 1. shown.
  • the SPI control logic unit can also be used to output the logic judgment result to the SPI controller to indicate the working mode of the first slave SPI device 102 .
  • the SPI control logic unit can also be used to configure the transmission direction of the SPI data port according to the result of the logic judgment.
  • the SPI control logic unit can also control the SPI data transceiver switching unit to connect the SPI data port with the sending module and/or the receiving module in the SPI controller.
  • the SPI data transceiver switching unit can be used to connect the SPI data port and the transmission module in the SPI controller according to the control of the SPI control logic unit to form a transmission path.
  • the transmit path may be used for the first slave SPI device 102 to transmit data to the SDO.
  • the SPI data transceiver switching unit can also be used to connect the SPI data port and the receiving module in the SPI controller according to the control of the SPI control logic unit to form a receiving path.
  • the receive path is available for the first slave SPI device 102 to receive data from SDI.
  • the first slave SPI device 102 may include at least one SPI data port.
  • the first slave SPI device 102 only supports the three-wire mode.
  • the first slave SPI device 102 can support a three-wire mode, that is, a four-wire mode.
  • the SPI control logic unit can switch the SPI data port 1 (or data port 2) to a bidirectional data port. Specifically, the SPI control logic unit can configure the transmission direction of the SPI data port 1 (or data port 2) to be bidirectional transmission through the configuration interface 1, and control the SPI data port 1 (or data port 2) to communicate with the SPI through the configuration interface 2
  • the sending module and the receiving module of the controller can switch the SPI data port 1 (or data port 2) to a bidirectional data port.
  • the SPI control logic unit can configure the SPI data port 1 through the configuration interface 1 and the transmission direction of data port 2.
  • the SPI control logic unit can configure the transmission direction of the SPI data port 1 as the receive direction through the configuration interface 1, and configure the transmission direction of the SPI data port 2 as the send direction through the configuration interface 1, that is, the SPI control logic unit configures the SPI through the configuration interface 1.
  • Data port 1 is the receiving port (the data line connected to the SPI data port 1 is SDI at this time), and the SPI data port 2 is configured as the sending port through the configuration interface 1 (the data line connected to the SPI data port 2 is SDO at this time) .
  • the SPI control logic unit also controls the SPI data transceiver switching unit through the configuration interface 2 to connect the SPI data interface 1 to the receiving module of the SPI controller to form a receiving path, and the SPI control logic unit also controls the SPI data through the configuration interface 2.
  • the transceiver switching unit connects the SPI data interface 2 to the sending module of the SPI controller to form a sending path. At this point, the switching of the sending port and the receiving port is completed.
  • the SPI control logic unit can configure the transmission direction of the SPI data port 1 to be the sending direction through the configuration interface 1 (at this time, the data line connected to the SPI data port 1 is SDO) , and configure the transmission direction of the SPI data port 2 as the receive direction through the configuration interface 1 (at this time, the data line connected to the SPI data port 2 is SDI).
  • the SPI control logic unit also controls the SPI data transceiver switching unit through the configuration interface 2 to connect the SPI data interface 1 to the transmission module of the SPI controller to form a transmission path, and the SPI control logic unit also controls the SPI data through the configuration interface 2.
  • the transceiver switching unit connects the SPI data interface 2 to the receiving module of the SPI controller to form a receiving path. At this point, the switching of the sending port and the receiving port is completed.
  • the functions of some or all of the components in the SPI control logic unit SPI controller, the SPI data transceiver switching unit or the SPI data port shown in FIG. 9 may be implemented by an integrated circuit or a logic circuit.
  • FIG. 1 shows a data transmission system including one master SPI device and two slave SPI devices only by way of example, and the present application is not limited to be applied in a data transmission system including more slave SPI devices.
  • the present application also provides a chip, which can have the function of the above first slave SPI device 102 .
  • the first slave SPI device shown in FIG. 1 can be replaced with this chip.
  • the chip may have the structure shown in FIG. 9 .
  • the chip may include an SPI controller, an SPI control logic unit (or SPI control logic circuit), an SPI data transceiver switching unit (or SPI data transceiver switching circuit), and an SPI data port (or data port). ) and other components.
  • the SPI control logic unit may be configured to receive a first chip select signal and a second chip select signal from the master SPI device, and the combination of the first chip select signal and the second chip select signal is used to enable the chip.
  • the SPI data port can be connected to the master SPI device and the second slave SPI device through data lines.
  • the SPI control logic unit can be used to control the SPI controller to pass the The SPI data port receives the data sent by the second slave SPI device in the data line.
  • the SPI data port may include a sending port and a receiving port, the sending port is connected to the receiving port of the main SPI device through a data line, and the receiving port is connected to the receiving port of the main SPI device through a data line.
  • a sending port is connected, the sending port is used for the chip to send data to the data line, and the receiving port is used for the chip to receive the data transmitted in the data line.
  • the SPI control logic unit can also be used to configure the transmit port to use when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state. for receiving the data transmitted in the data line.
  • the chip may further include an SPI data transceiver switching unit, and the SPI controller may include a sending module and a receiving module, where the sending module is used for data transmission, and the receiving module is used for data reception.
  • the SPI control logic unit can also be used for, when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state, to control the SPI data transceiver switching unit to switch all the The sending port is connected to the receiving module.
  • the SPI control logic unit can also be used to configure the SPI data port as a bidirectional data port, and the bidirectional data port supports data reception and transmission.
  • the SPI control logic unit can also be used to control the SPI controller not to respond when the master SPI device drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the data is sent according to the first instruction transmitted by the data line, and the first instruction is used to control the sending of the data.
  • the SPI control logic unit can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to control the SPI controller to pass the
  • the SPI data port receives the data transmitted in the data line.
  • the SPI controller can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to receive the first chip transmitted in the data line.
  • Two indications the second indication is used to control the reception of data, and in response to the second indication, the data transmitted in the data line is received through the SPI data port.
  • the SPI control logic unit can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to control the SPI controller to pass the The SPI data port receives the data transmitted in the data line.
  • the SPI controller can also be used for, when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an active state, to receive the first chip transmitted in the data line.
  • an instruction the first instruction is used to control the sending of data; in response to the first instruction, data is sent to the data line through the SPI data port.
  • the SPI control logic unit can also be used to control the SPI controller not to operate when the master SPI device drives the first chip select signal to an inactive state and drives the second chip select signal to an inactive state. Data is sent through the data line, and the SPI controller is controlled not to receive data through the data line.
  • the present application also provides a camera module.
  • the camera module may include the above-mentioned chip, or include the above-mentioned first slave SPI device 102 .
  • the first slave SPI device 102 is a motor driver IC in the camera module, or a component of the motor driver IC in the camera module.
  • the camera module can support shake compensation.
  • the camera module may further include a motor and a camera.
  • the motor may be used to obtain data from the gyroscope sensor from the chip, and perform shake control and/or auto focus on the camera according to the data from the gyroscope sensor.
  • the camera module 1 can receive the gyroscope information from the gyroscope sensor through the data line when the main SPI device drives the first chip selection signal to an active state and drives the second chip selection signal to an inactive state.
  • the camera The module 2 can also receive the gyroscope information from the gyroscope sensor through the data line, and it is no longer necessary to first receive the gyroscope data from the gyroscope sensor by the camera module 2 according to the prior art, and then use the camera module 2 to receive the gyroscope data.
  • the data is sent to camera module 1. Therefore, the embodiments of the present application can improve the efficiency of the camera module 1 and the camera module 2 in receiving gyroscope information, and improve the shake compensation effect of the camera module.
  • the main SPI device 101 can be used as the motor driver IC of the camera module 2 or as a component of the motor driver IC of the camera module 2 .
  • the present application also provides a terminal device.
  • the terminal device can be a smart phone, a mobile smart device, a functional household device or a tablet computer, etc., or it can be a portable, pocket-sized, hand-held, computer-built or vehicle-mounted mobile device.
  • the terminal device may include the data transmission system described above.
  • the terminal device may include the above-mentioned chip.
  • the terminal device may include the above-mentioned camera module.
  • the terminal device may be a camera-capable device, and the camera-capable device may take pictures through the camera module, and realize shake compensation and automatic shooting during the shooting process. Focus.
  • the terminal device may further include an image processing chip for acquiring image signals from the camera module and processing the image signals.
  • the present application also provides another data transmission system.
  • the data transmission system 1000 may include a first camera module 1001 , a second camera module 1002 and a first sensor 1003 , wherein, The first camera module 1001 serves as a master SPI device, and the second camera module 1002 and the first sensor 1003 serve as slave SPI devices.
  • the first camera module 1001 , the second camera module 1002 and the first sensor 1003 communicate through the SPI protocol.
  • the first camera and the second camera run at the same time, the first camera obtains the first sensor data through the SPI protocol, and the second camera simultaneously obtains the first sensor data through the SPI protocol, so as to improve the efficiency of multiple cameras in the SPI system to obtain sensor data. efficient.
  • the data transmission system 1000 can be applied to a terminal device with an SPI structure or other electronic devices, for example, can be applied to a mobile terminal or a computer and other devices.
  • a possible application scenario of the data transmission system 1000 provided by the embodiment of the present application is a camera device including multiple camera modules, and the camera device may be a smartphone with a camera function, a mobile smart device, Functional home equipment or tablet computers, etc., can also be portable, pocket-sized, hand-held, computer built-in or vehicle-mounted mobile devices.
  • the first camera module 1001 may include one camera module or a camera among multiple camera modules of the camera-capable device
  • the second camera module 1002 may include another camera module or camera of the camera-capable device
  • the first sensor 1003 may include a gyro sensor of the camera device.
  • the gyroscope sensor can be deployed on the main board of the camera device.
  • the first camera module 1001 and the second camera module 1002 may each include at least one motor driver chip, or a motor driver integrated circuit (IC).
  • the motor driver IC can be used to output current or pulse width modulation (PWM) signal to control the motor of the camera module to move as required to achieve jitter compensation.
  • PWM pulse width modulation
  • connection mode and working mode of each component of the data transmission system 1000 will be described below. It should be understood that, in the following description, the first camera module 1001 can also be replaced with a first camera, and the second camera module 1002 can be replaced with a second camera.
  • the first camera module 1001, the second camera module 1002 and the first sensor 1003 are connected by a data cable, for example, the first camera module 1001, the second camera module 1002 and the first sensor 1003 are three Among them, any two are connected by a data line, or, the first camera module 1001 , the second camera module 1002 and the first sensor 1003 are connected by the same data line.
  • the data line may include SDA.
  • the data wires may include SDO and SDI.
  • first camera module 1001, the second camera module 1002 and the first sensor 1003 are also connected through a clock line.
  • the first camera module 1001 outputs the first chip select signal ( CS1 ) to the second camera module 1002 and outputs the second chip select signal ( CS2 ) to the second camera module 1002 . Therefore, the first camera module 1001 can make the second camera module 1002 in a variety of working modes through the combination of the active state or the inactive state of the first chip selection signal and the active state or the inactive state of the second chip selection signal. a working mode.
  • Various operating modes may include: data listening mode, standard slave SPI device mode, and unstrobe mode. in,
  • the second camera module 1002 can receive the data sent by the first sensor 1003 to the first camera module 1001 through the data line, and/or receive the data sent by the first camera module 1001 to the first sensor 1003. data.
  • the second camera module 1002 does not send data through the data line, so even if the second camera module 1002 receives the write instruction bit from the first camera module 1001, it will not respond to the write instruction bit for data transmission.
  • the second camera module 1002 can send data through the data line according to the write indication bit from the first camera module 1001, and/or, according to the read indication bit from the first camera module 1001 Receive data through the data line. Therefore, when the second camera module 1002 receives the write indication bit from the first camera module 1001, it will send data in response to the write indication bit; or, when the second camera module 1002 receives the write indication bit from the first camera When the module 1001 has a read indication bit, it will receive data in response to the read indication bit.
  • the data listening mode may correspond to a preset state combination of the first chip select signal and the second chip select signal.
  • the first chip selection signal is in an active state and the second chip selection signal is in an inactive state, the second camera module 1002 is in the data listening mode.
  • the standard slave SPI device mode may correspond to another preset state combination of the first chip select signal and the second chip select signal. For example, when the first chip selection signal is in an inactive state and the second chip selection signal is in an active state, the second camera module 1002 is in the standard slave SPI device mode.
  • the non-gated mode may correspond to another preset state combination of the first chip select signal and the second chip select signal. For example, when the first chip selection signal is in an inactive state and the second chip selection signal is in an inactive state, the second camera module 1002 is in a non-gating mode.
  • the correspondence between the above multiple operating modes and the state combination of the first chip select signal and the second chip select signal is only an example, and the corresponding relationship between the working mode and the state combination of the chip select signal can be based on application requirements. Flexible adjustment. For example, the following configuration may also be adopted: when the first chip selection signal is in an active state and the second chip selection signal is in an active state, the second camera module 1002 is in a data listening mode.
  • the first camera module 1001 which is the main SPI device, can also configure the corresponding relationship between the multiple operating modes of the second camera module 1002 and the state combinations of the first chip select signal and the second chip select signal.
  • the logical judgment result of the dual chip selection of the second camera module 1002 can be represented by FIG. 2 .
  • the logical judgment result of the dual chip selection is the working mode of the second camera module 1002 .
  • the chip select signal is inactive.
  • "a&b" means "a and b".
  • the dual chip select logic is the data listening mode, and the second camera module 1002 can enter the data listening mode according to the judgment result (or, the second camera module 1002 is in the data listening mode).
  • the second camera module 1002 can receive data through the data line, but not send data through the data line.
  • the second camera module 1002 regardless of whether the first camera module 1001 outputs a write indication bit or a read indication bit, the second camera module 1002 only listens to the data line and receives the data transmitted by the data line.
  • the result of the dual chip selection logic judgment is:
  • the second camera module 1002 can enter the standard slave SPI device mode (or the second camera module 1002 is in the standard slave SPI device mode) according to the judgment result.
  • the second camera module 1002 can receive data through the data line according to the read indication bit output by the first camera module 1001, or can perform data reception through the data line according to the write indication bit output by the first camera module 1001. sending of data.
  • the dual-chip selection logic determines the result For the un-gated mode, the second camera module 1002 can enter the un-gated mode according to the judgment result (or, the second camera module 1002 is in the un-gated mode).
  • the second camera module 1002 does not receive data through the data line, nor does it send data through the data line.
  • the second camera module 1002 does not respond to the instruction of the first camera module 1001 .
  • the bus access mode of the second camera module 1002 in the data listening mode will be described.
  • the first camera module 1001 sets the first data bit (ie read/write indication bit) after the start of SCK to 0 (indicating writing) or 1 (indicating writing) read)
  • the second camera module 1002 only supports data input because it is in the data listening mode, and will not output data to the data lines (including SDA in three-wire mode or SDO in four-wire mode).
  • the connection relationship among the first camera module 1001 , the second camera module 1002 and the first sensor 1003 is shown in FIG. 11 . It can be seen that the respective data ports of the first camera module 1001, the second camera module 1002 and the first sensor 1003 (the data ports are connected to the SDA) all support bidirectional data transmission. Exemplarily, when in the three-wire mode, the second camera module 1002 can configure its data port as a bidirectional port.
  • the first camera module 1001 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the first camera module 1001 sends a write through SDA Indication bit
  • the first sensor 1003 receives the write indication bit through SDA
  • it can send data through SDA in response to the write indication bit
  • the first camera module 1001 can receive the data sent by the first sensor 1003 through SDA
  • the second camera module 1002 is in the data listening mode, so the second camera module 1002
  • the second camera module 1002 can receive the data sent by the first sensor 1003 through the SDA.
  • the second camera module 1002 does not send data on the SDA in response to the write indication bit transmitted by the SDA (or, the second camera module 1002 ignores the data transmission in response to the write indication bit) to avoid causing the SDA Data conflict on.
  • the expression “the SPI device sends data through the SDA/SDO” in this application means that the SPI device sends data to the SDA/SDO through the sending port connected to the SDO, and the SDA/SDO sends the data to other SPI devices. send. It should also be understood that the expression “the SPI device receives data through SDA/SDI” in this application means that the SPI device receives data from the SDA/SDI through the receiving port connected to the SDA/SDI from other SPI devices through the SDA/SDA of other SPI devices. Data sent by SDO.
  • the first camera module 1001 drives the first chip selection signal to an active state and drives the second chip selection signal to an inactive state
  • the first camera module 1001 can also send data through SDA.
  • the first sensor 1003 can respond to the read indicator bit and receive the data sent by the first camera module 1001 through SDA
  • the second camera module 1002 In the data listening mode, the second camera module 1002 can receive the data sent by the first camera module 1001 through the SDA. Therefore, multiple slave SPI devices can simultaneously receive data sent by the master SPI device, thus improving the efficiency when multiple slave SPI devices receive data from the master SPI device.
  • the first camera module 1001 drives the first chip select signal to an active state and drives the second chip select signal to an inactive state
  • the first camera module 1001 , the second camera module 1002 and the first The connection relationship between the sensors 1003 is shown in FIG. 12 . It can be seen that the first camera module 1001, the second camera module 1002 and the second slave SPI device 10 can send data through their respective sending ports (the sending ports are connected to the SDO), and can send data through their respective receiving ports (receiving The port is connected with SDI) to receive data.
  • the first sensor 1003 can send data through SDO in response to the write indication bit, and the first camera module 1001 can send data through SDI
  • the data sent by the first sensor 1003 through SDO is received, and the second camera module 1002 is in the data listening mode, so the second camera module 1002 can receive the data sent by the first sensor 1003 through SDO through SDI.
  • the SDO of the second camera module 1002 will not receive the write indication bit sent by the first camera module 1001 through the SDO. Therefore, the second camera module 1002 does not respond to the write indication bit sent by the first camera module 1001. Data transmission (or, in other words, the second camera module 1002 ignores the data transmission in response to the write indication bit) to avoid data transmission conflicts.
  • the first sensor 1003 can receive data through the SDI in response to the read indication bit.
  • the bus access mode of the second camera module 1002 in the standard slave SPI device mode will be described by taking FIG. 6 and FIG. 7 as examples.
  • the second camera module 1002 works in the standard slave SPI device mode. If the first camera module 1001 sets the first data position after SCK to 0, the second camera The module 1002 can read the data transmitted on the data line (SDA or SDI) under the control of the first camera module 1001 .
  • the second camera module 1002 can be controlled by the first camera module 1001 , send data through the data line (SDA or SDO). Therefore, when in the standard slave SPI device mode, the second camera module 1002 can realize data transmission between the second camera module 1002 and the first camera module 1001 under the control of the first camera module 1001 .
  • the connection relationship among the first camera module 1001 , the second camera module 1002 and the first sensor 1003 is shown in FIG. 11 .
  • the first camera module 1001 drives the first chip selection signal to an inactive state and drives the second chip selection signal to an active state
  • the first camera module 1001 sends a write indication bit through SDA
  • the second camera module 1002 is in standard slave mode
  • the first sensor 1003 can send data through SDA in response to the write indication bit
  • the first camera module 1001 can receive data sent by the second camera module 1002 through SDA .
  • the first sensor 1003 is in a non-gated state, and does not respond to the write indication bit transmitted by the SDA.
  • the first camera module 1001 drives the first chip selection signal to an inactive state and drives the second chip selection signal to an active state
  • the first camera module 1001 sends a read indication bit through SDA and passes SDA transmits data.
  • the second camera module 1002 is in the standard slave mode, and the second camera module 1002 can receive data through the SDA in response to the read indication bit transmitted by the SDA.
  • the first sensor 1003 is in a non-gated state, and does not respond to the read indication bit transmitted by the SDA.
  • the connection relationship among the first camera module 1001 , the second camera module 1002 and the first sensor 1003 is shown in FIG. 13 .
  • the first camera module 1001 drives the first chip selection signal to an active state and drives the second chip selection signal to an inactive state
  • the second camera module 1002 is in the standard slave mode
  • the second camera module 1002 can receive the write indication bit through SDI, and send data through SDO in response to the write indication bit
  • the first camera module 1001 can receive the second camera module 1002 through SDI and send data through SDO The data.
  • the first sensor 1003 is in a non-gated state, and does not respond to the write indication bit sent by the first camera module 1001 through the SDO.
  • the first camera module 1001 drives the first chip selection signal to an active state and drives the second chip selection signal to an inactive state
  • the first camera module 1001 sends a read indication bit through SDO And sending data through SDO
  • the second camera module 1002 can receive the read indication bit through SDI, and read data through SDI in response to the read indication bit.
  • the first sensor 1003 is in a non-gated state, and does not respond to the read indication bit sent by the first camera module 1001 through the SDO.
  • connection relationship among the first camera module 1001 , the second camera module 1002 and the first sensor 1003 is as shown in FIG. 11 .
  • connection relationship among the first camera module 1001 , the second camera module 1002 and the first sensor 1003 is shown in FIG. 13 .
  • the judgment result of the above dual chip select logic can be represented by Table 1.
  • the second camera module 1002 when the state of the first chip select signal is an active state and the state of the second chip select signal is an inactive state, the second camera module 1002 can be made to enter the data listening mode. When the state of the first chip select signal is an inactive state and the state of the second chip select signal is an active state, the second camera module 1002 can be made to enter the standard slave SPI device mode. When the state of the first chip selection signal is an inactive state and the state of the second chip selection signal is an inactive state, the second camera module 1002 can be made to enter the non-gating mode.
  • the first camera module 1001 can also output the first chip selection signal and the second chip selection signal to the first sensor 1003, so that whether to enable the first sensor can be controlled by the first chip selection signal and the second chip selection signal 1003. Therefore, the first camera module 1001 can make the first sensor 1003 in various working modes through the combination of the active state or inactive state of the first chip selection signal and the active state or inactive state of the second chip selection signal.
  • the various operating modes of the first sensor 1003 may include a data listening mode, a standard slave SPI device mode, and an un-gated mode.
  • the various operating modes of the first sensor 1003 may include a standard slave SPI device mode and an un-gated mode.
  • the first sensor 1003 when the second camera module 1002 is in the listening mode, the first sensor 1003 is in the standard slave SPI device mode or the un-gated mode, and/or, when the first sensor 1003 is in the listening mode, the second sensor 1003 is in the listening mode.
  • the camera module 1002 is in standard slave SPI device mode or unstrobe mode.
  • the working mode of the first sensor 1003 may refer to the description of the working mode of the second camera module 1002 in this application.
  • the first camera module 1001 when the first camera module 1001 drives the first chip selection signal to be in an active state and drives the second chip selection signal to an inactive state , the first camera module 1001 can control the first sensor 1003 to send data through the data line, and receive the data sent by the first sensor 1003 through the data line. At this time, since the second camera module 1002 is in the data listening mode, the second camera module 1002 can receive data through the data line. Therefore, when the first camera module 1001 drives the first chip selection signal to an active state and drives the second chip selection signal to an inactive state, the first camera module 1001 and the first slave SPI device can simultaneously receive the transmission from the first sensor 1003. data, which improves the data transmission efficiency between the master SPI device and multiple slave SPI devices.
  • the first camera module 1001 includes one camera module among a plurality of camera modules of the camera-capable device
  • the second camera module 1002 includes another camera module of the camera-capable device
  • the first sensor 1003 includes a camera-capable device
  • the device is a gyroscope sensor
  • multiple camera modules including the first camera module 1001 and the second camera module 1002 can simultaneously receive gyroscope information (or data from the gyroscope sensor) sent by the gyroscope sensor.
  • the gyroscope information here may include data such as the X/Y/Z triaxial angular velocity information of the gyroscope, and the camera module that supports optical image stabilization can calculate the angular velocity information of the human hand when taking pictures according to the X/Y/Z triaxial angular velocity information of the gyroscope. shake, and control the lens through a motor (such as a motor integrated inside the camera module) to achieve shake compensation.
  • a motor such as a motor integrated inside the camera module
  • the first camera module 1001 should avoid simultaneously driving the first chip selection signal to an active state and driving the second chip selection signal to an active state. If the first camera module 1001 incorrectly drives the first chip select signal and the second chip select signal to be active at the same time, the second camera module 1002 can determine that the driving state is incorrect and does not respond to the bus operation.
  • the second camera module 1002 can switch its data ports, so as to realize the connection relationship shown in FIG. 12 and FIG. 13 without changing the connection lines between the chips switch.
  • the switching of the data port includes, but is not limited to, switching the data port from a unidirectional data port to a bidirectional data port, or switching a sending port to a receiving port, or switching a receiving port to a sending port, and so on.
  • the sending port of the module 1001 and the receiving port of the first sensor 1003 are connected by a second data cable), the second camera module 1002 can respond to CS1 and CS2 to switch the sending port of the second camera module 1002 to the receiving port (In other words, the second camera module 100
  • the second camera module 1002 may, in response to CS1 and CS2, switch the receiving port of the second camera module 1002 to the transmitting port (in other words, the second camera module 1002 switches the SDI of the second camera module 1002 to SDO), and switch the first camera module 1002 to SDO.
  • the sending port of the two camera modules 1002 is switched to the receiving port (in other words, the second camera module 1002 switches the SDO of the second camera module 1002 to SDI), thereby obtaining the connection relationship shown in FIG. 13 .
  • the second camera module 1002 may include components such as a circuit, a camera, and a motor.
  • the circuit can be used to receive and/or transmit data through the SPI protocol according to the chip select signal.
  • Cameras can be used to capture images or video.
  • Motors can be used for camera shake control and/or autofocus.
  • the circuit may include an SPI controller, an SPI control logic unit (or SPI control logic circuit), an SPI data transceiver switching unit (or SPI data transceiver switching circuit), and an SPI data port (or a data port). ) and other components.
  • the SPI controller may be configured to control the SPI data port to obtain the first sensor data when the first camera module 1001 obtains the first sensor data through the SPI protocol.
  • the SPI data port is used for the SPI protocol communication between the second camera module 1002 and the first camera module 1001 and/or the first sensor 1003, the first camera module 1001 is the main SPI device, and the second camera module Group 1002 and first sensor 1003 are slave SPI devices.
  • the SPI controller can be used to process data that needs to be sent, or to process data received over a data line.
  • the SPI controller may include a sending module and a receiving module, the sending module may be used for processing and sending data to be sent to the sending port, and the receiving module may be used for receiving and processing data from the receiving port.
  • the SPI controller can also control the reception and/or transmission of data according to the working mode of the second camera module 1002 . For example, when the second camera module 1002 is in the data listening mode, the SPI controller can control the SPI data port not to transmit the data to be sent to the sending port.
  • the SPI controller can control the SPI data port not to send the data to be sent to the data line, and control the SPI data port not to process the data from the receiving data line through the receiving module.
  • the SPI control logic unit can receive the first chip select signal and the second chip select signal, and according to the first chip select signal and the second chip select signal, it can judge the logic result of the dual chip select judgment.
  • the judgment result can be shown in Figure 2 or Table 1. shown.
  • the SPI control logic unit can also be used to output the logic judgment result to the SPI controller to indicate the working mode of the second camera module 1002 .
  • the SPI control logic unit can also be used to configure the transmission direction of the SPI data port according to the result of the logic judgment.
  • the SPI control logic unit can also control the SPI data transceiver switching unit to connect the SPI data port with the sending module and/or the receiving module in the SPI controller.
  • the SPI data transceiver switching unit can be used to connect the SPI data port and the transmission module in the SPI controller according to the control of the SPI control logic unit to form a transmission path.
  • the transmit path can be used to send data to the SDO.
  • the SPI data transceiver switching unit can also be used to connect the SPI data port and the receiving module in the SPI controller according to the control of the SPI control logic unit to form a receiving path.
  • the receive path can be used to receive data from SDI.
  • the circuit may include at least one SPI data port.
  • the second camera module 1002 When the number of SPI data ports is one, the second camera module 1002 only supports the three-wire mode. When the number of SPI data ports is two or more, the second camera module 1002 can support the three-wire mode and the four-wire mode.
  • the SPI control logic unit can switch the SPI data port 1 (or data port 2) to a bidirectional data port. Specifically, the SPI control logic unit can configure the transmission direction of the SPI data port 1 (or data port 2) to be bidirectional transmission through the configuration interface 1, and control the SPI data port 1 (or data port 2) to communicate with the SPI through the configuration interface 2
  • the sending module and the receiving module of the controller can switch the SPI data port 1 (or data port 2) to a bidirectional data port.
  • the SPI control logic unit can configure the transmission direction of the SPI data port 1 and the data port 2 through the configuration interface 1 .
  • the SPI control logic unit can configure the transmission direction of the SPI data port 1 as the receiving direction through the configuration interface 1, and configure the SPI through the configuration interface 1.
  • the transmission direction of the data port 2 is the sending direction, that is, the SPI control logic unit configures the SPI data port 1 as the receiving port through the configuration interface 1 (the data line connected to the SPI data port 1 is SDI at this time), and configures the SPI data port 1 through the configuration interface 1.
  • the SPI data port 2 is the sending port (the data line connected to the SPI data port 2 is SDO at this time).
  • the SPI control logic unit also controls the SPI data transceiver switching unit through the configuration interface 2 to connect the SPI data interface 1 to the receiving module of the SPI controller to form a receiving path, and the SPI control logic unit also controls the SPI data through the configuration interface 2.
  • the transceiver switching unit connects the SPI data interface 2 to the sending module of the SPI controller to form a sending path. At this point, the switching of the sending port and the receiving port is completed.
  • the SPI control logic unit can configure the transmission direction of SPI data port 1 through configuration interface 1 as The sending direction (the data line connected to the SPI data port 1 is SDO at this time), and the transmission direction of the SPI data port 2 configured through the configuration interface 1 is the receiving direction (the data line connected to the SPI data port 2 at this time is SDI).
  • the SPI control logic unit also controls the SPI data transceiver switching unit through the configuration interface 2 to connect the SPI data interface 1 to the transmission module of the SPI controller to form a transmission path, and the SPI control logic unit also controls the SPI data through the configuration interface 2.
  • the transceiver switching unit connects the SPI data interface 2 to the receiving module of the SPI controller to form a receiving path. At this point, the switching of the sending port and the receiving port is completed.
  • the functions of some or all of the components in the SPI control logic unit SPI controller, the SPI data transceiver switching unit or the SPI data port shown in FIG. 9 may be implemented by a chip, an integrated circuit or a logic circuit.
  • Each component of the circuit shown in FIG. 9 can be implemented in an integrated manner, a discrete manner, or through a chip or a chip system composed of multiple chips.
  • the present application also provides a circuit, which can be connected to the second camera, so as to realize the functions shown in the second camera module 1002 above.
  • the circuit may have the structure shown in FIG. 9 .
  • the circuit may include an SPI controller, an SPI control logic unit (or SPI control logic circuit), an SPI data transceiver switching unit (or SPI data transceiver switching circuit), and an SPI data port (or a data port). ) and other components.
  • the SPI controller may be configured to control the SPI data port to obtain the first sensor data when the first camera obtains the first sensor data through the SPI protocol.
  • the SPI data port is used for the SPI protocol communication between the second camera and the first camera and/or the first sensor, the first camera is a master SPI device, and the second camera and the first sensor are slave SPI devices.
  • the SPI data port may send the acquired first sensor data to the second camera.
  • the SPI data port is connected to the first camera and the first sensor through a data line.
  • the circuit further includes an SPI control logic unit for receiving the first chip select signal and the second chip select signal from the first camera, and the combination of the first chip select signal and the second chip select signal is used for Controls whether to enable the second camera.
  • the SPI control logic circuit can control the SPI controller to control the SPI data port to receive data sent by the first sensor in the data line to the first camera.
  • the circuit further includes an SPI control logic unit for receiving the first chip select signal and the second chip select signal from the first camera, and the combination of the first chip select signal and the second chip select signal is used for Controls whether to enable the second camera.
  • the SPI control logic circuit can control the SPI controller to control the SPI data port to receive data sent by the first sensor in the data line to the first camera.
  • the SPI control logic unit may further control the SPI controller to control the SPI data port to receive data sent from the first camera in the data line to the first sensor.
  • the sending port of the second camera is connected to the receiving port of the first camera through a first data line
  • the receiving port of the second camera is connected to the sending port of the first camera through a second data line
  • the data The line includes a first data line and the second data line
  • the sending port of the second camera and the sending port of the first camera are used for data transmission
  • the receiving port of the second camera and the receiving port of the first camera are used for data transmission.
  • the SPI control logic unit also
  • the transmit port can be configured to receive data transmitted on the data line.
  • the circuit further includes an SPI data transceiver switching circuit
  • the SPI controller includes a sending module and a receiving module, the sending module is used for data transmission, and the receiving module is used for data reception; when the first chip select signal When it is in an active state and the second chip select signal is in an inactive state, or, when the first chip select signal and the second chip select signal are a preset state combination, the SPI control logic unit can also control the SPI data transmission and reception switching Circuitry connects the transmit port to the receive module.
  • the SPI control logic unit may further configure the SPI data port as a bidirectional data port, and the bidirectional data port supports data reception and transmission.
  • the SPI control logic unit may further control the SPI controller not to send data in response to a first instruction transmitted by the data line, where the first instruction is used to control the sending of data.
  • the SPI control logic unit can control the SPI controller to receive the second indication transmitted in the data line through the SPI data port.
  • the SPI controller can control the SPI data port to receive the data transmitted in the data line in response to the second indication, and the second indication is used to control the reception of the data.
  • the SPI control logic unit can control the SPI controller to receive the first indication transmitted in the data line through the SPI data port.
  • the SPI controller may control the SPI data port to send data to the data line in response to the first instruction, and the first instruction is used to control the sending of the data.
  • the SPI control logic unit can control the SPI controller not to send data through the data line, and control the SPI controller not to receive data through the data line.
  • the present application also provides a circuit, which can be connected to the first camera to realize the functions shown in the first camera module 1001 above.
  • the circuit may have the structure shown in FIG. 14 .
  • the circuit may include components such as a control unit (or control circuit) and an SPI data port (or data port).
  • the SPI data port can be used for the first camera module 1001 to obtain the first sensor data through the SPI protocol.
  • the control circuit can be used to control the second camera module 1002 to simultaneously obtain the first sensor data through the SPI protocol.
  • the first camera module 1001 is the master SPI device, and the second camera module 1002 and the first sensor 1003 are slave SPI devices.
  • the first sensor data comes from the first sensor 1003 .
  • the SPI data port is connected to the second camera module 1002 and the first sensor 1003 through a data line.
  • control circuit can output the first chip select signal to the second camera module 1002 and the first sensor 1003, and output the second chip select signal to the second camera module 1002 and the first sensor 1003 , the state combination of the first chip selection signal and the second chip selection signal is used to control whether to enable the second camera module 1002 and to control whether to enable the first sensor 1003 .
  • the control circuit can control the first sensor 1003 to send data through the data line, and control the SPI data port The data sent by the first sensor 1003 is received through the data line, and the second camera module 1002 is controlled to receive the data sent by the first sensor 1003 to the first camera module 1001 through the data line.
  • the control circuit can control the first sensor 1003 to send data through the data line, control the SPI data port to receive the data sent by the first sensor 1003 through the data line, and control the second camera module 1002 to receive the data through the data line. Data sent by a sensor 1003 to the first camera module 1001 .
  • control circuit can also control the SPI data port to send data to the first sensor 1003 through the data line, and control the second camera module 1002 to receive the data sent from the first camera module 1001 to the first sensor through the data line 1003 data.
  • the control circuit can control the SPI data port to send the first indication through the data line, and the first indication is used to control the sending of the data.
  • the control circuit can control the SPI data port to send the first indication through the data line, and the first indication is used to control the sending of the data.
  • the present application also provides a camera module.
  • the camera module may include the first camera module 1001 or the second camera module 1002 above.
  • the first camera module 1001 may include the circuit shown in FIG. 14 , a motor, and a first camera.
  • the circuit shown in FIG. 14 can be implemented by a motor driver IC, or as a component of a motor driver IC in a camera module.
  • the second camera module 1002 may include the circuit shown in FIG. 9 , a motor and a second camera.
  • the circuit shown in FIG. 9 can be specifically implemented by a motor driver IC, or as a component of a motor driver IC in a camera module.
  • the motors in the first camera module 1001 and the second camera module 1002 can be used to obtain data from the gyroscope sensor through a circuit, and perform shaking on the camera according to the data from the gyroscope sensor. control and/or autofocus.
  • the first camera module 1001 can drive the first chip selection signal to an active state and drive the second chip
  • the selection signal is in an inactive state
  • the gyroscope information is received from the gyroscope sensor through the data line.
  • the second camera module 1002 can also receive the gyroscope information through the data line, and no longer needs to be according to the prior art.
  • the first camera module 1001 receives the gyroscope data from the gyroscope sensor, and then the first camera module 1001 sends the gyroscope data to the first camera module 102 . Therefore, the embodiment of the present application can improve the efficiency of the camera module in receiving the gyroscope information, and improve the shake compensation effect of the camera module.
  • the present application also provides a terminal device.
  • the terminal device may be a smart phone, a mobile smart device, a functional household device or a tablet computer, etc., or a portable, pocket-sized, hand-held, computer-built-in or vehicle-mounted terminal device.
  • the terminal device may be a device capable of taking pictures, and the device capable of taking pictures can be photographed by the first camera module and/or the second camera module, and realize shake compensation and automatic focusing during the photographing process.
  • the terminal device may further include an image processing chip for acquiring image signals from the camera module and processing the image signals.
  • the terminal device may include the circuit shown in FIG. 9 , the circuit shown in FIG. 14 , some or all of the components of the first camera (or the first camera module 1001 ) and the second camera (or the second camera module 1002 ).
  • the terminal device may further include a first sensor, and the first sensor includes a gyroscope sensor.
  • the terminal device may include a first camera module, a second camera module, and a gyroscope sensor for outputting gyroscope information.
  • the first camera module, the second camera module and the gyro sensor are connected through a serial peripheral interface SPI.
  • the first camera module is used as the master SPI device
  • the gyroscope sensor and the second camera module are both used as slave SPI devices
  • the first camera module and the second camera module are sent by the first camera module.
  • the gyroscope information is obtained from the gyroscope sensor at the same time.
  • the image processing unit is used for acquiring image signals from the first camera module and the second camera module.
  • both the first camera module and the second camera module are connected to the gyro sensor through a data cable; the SPI chip selection signal sent by the first camera module is a preset state combination At the same time, the first camera module and the second camera module obtain the gyroscope information from the gyroscope sensor at the same time.
  • both the first camera module and the second camera module are connected to the gyro sensor through a data cable; the SPI chip select signal sent by the first camera module enables the second camera module and the gyro sensor, the first camera module and the second camera module simultaneously obtain the gyro information from the gyro sensor.
  • the second camera module and the gyro sensor receive data from the first camera module at the same time.

Abstract

本申请提供一种基于SPI的数据传输系统。该系统中，主SPI装置通过第一片选信号以及第二片选信号的组合使能第一从SPI装置，当主SPI装置驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，主SPI装置控制第二从SPI装置通过数据线发送数据，主SPI装置还可通过数据线接收数据，以及第一从SPI装置可通过数据线接收数据。因此，在第一片选信号为有效状态且第二片选信号为非有效状态时，主SPI装置与第一从SPI装置可同时接收第二从SPI装置传输的数据，提高了SPI系统的数据传输效率。

Description

基于SPI的数据传输系统
相关申请的交叉引用
本申请要求在2020年06月28日提交中国专利局、申请号为202010600781.3、申请名称为“基于SPI的数据传输系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据传输技术领域，尤其涉及一种基于SPI的数据传输系统。
背景技术
目前，支持光学防抖(optical image stabilization，OIS)的摄像头模组包含马达驱动，每个马达驱动根据陀螺仪传感器(GYRO)采集的陀螺仪信息对摄像头模组的马达进行控制，实现抖动补偿。其中，以智能手机为例，陀螺仪传感器一般安装于智能手机的主板，陀螺仪传感器与摄像头模组之间通过串行外设接口(serial peripheral interface，SPI)连接，以实现陀螺仪传感器与摄像头模组之间的陀螺仪信息传输。
当智能手机包括多个支持光学防抖摄像头模组时，多个摄像头模组中的一个摄像头模组作为主(master)SPI装置，陀螺仪传感器以及其他的摄像头模组均作为从(slave)SPI装置。由于主SPI装置同时只能与一个从SPI装置进行数据传输，因此，当一个摄像头模组从陀螺仪传感器获取陀螺仪信息时，其他摄像头模组从陀螺仪传感器获取陀螺仪信息将出现延迟，导致OIS效果不理想。
综上，由于包括多个从SPI装置的SPI系统中的SPI装置之间的数据传输效率不高，导致作为从SPI装置的摄像头模组的OIS效果不理想。
发明内容
本申请提供一种基于SPI的数据传输系统，用以提高包括多个从SPI装置的SPI系统的数据传输效率。
第一方面，本申请提供一种数据传输系统，该系统可包括主SPI装置、第一从SPI装置以及第二从SPI装置。其中，主SPI装置可用于，将第一片选信号输出至第一从SPI装置和第二从SPI装置，以及将第二片选信号输出至所述第一从SPI装置，所述第一片选信号以及所述第二片选信号的组合用于使能所述第一从SPI装置，所述第一片选信号用于使能所述第二从SPI装置，所述主SPI装置、所述第一从SPI装置以及所述第二从SPI装置还通过数据线相连。所述主SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述第二从SPI装置通过所述数据线发送数据，以及通过所述数据线接收所述第二从SPI装置发送的数据。所述第二SPI装置可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，根据所述主SPI装置的控制通过所述数据线发送数据。所述第一从SPI装置可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信 号为非有效状态时，通过所述数据线接收所述第二从SPI装置发送的数据。
采用以上数据传输系统，主SPI装置通过第一片选信号以及第二片选信号的组合使能第一从SPI装置，当主SPI装置驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，主SPI装置控制第二从SPI装置通过数据线发送数据，主SPI装置还可通过数据线接收数据，以及第一从SPI装置可通过数据线接收数据。因此，在第一片选信号为有效状态且第二片选信号为非有效状态时，主SPI装置与第一从SPI装置可同时接收第二从SPI装置传输的数据，提高了SPI系统的数据传输效率。
在一种可能的示例中，若所述第一从SPI装置的发送端口与所述主SPI装置的接收端口通过第一数据线相连，所述第一从SPI装置的接收端口与所述主SPI装置的发送端口通过第二数据线相连，所述数据线包括所述第一数据线以及所述第二数据线，所述第一从SPI装置的发送端口以及所述主SPI装置的发送端口用于数据的发送，所述第一从SPI装置的接收端口以及所述主SPI装置的接收端口用于数据的接收，则所述第一从SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，将所述第一从SPI装置的发送端口切换为接收端口，以及，将所述第一从SPI装置的接收端口切换为发送端口。
采用该设计，在四线模式下，当所述主SPI装置驱动第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，第一从SPI装置可将发送端口切换为接收端口，以通过数据线接收第二从SPI装置发送的数据。第一从SPI装置还可将接收端口切换为发送端口，从而不接收来自主SPI装置的数据，也就不需要对主SPI装置发送的写指示位进行响应，避免与第二从SPI装置通过相同的数据线发送数据，以免造成数据冲突。
在另一种可能的示例中，所述第一从SPI装置还可用于，将所述第一从SPI装置的数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
采用该设计，在三线模式下，第一从SPI装置将数据端口设置为双向数据端口，以通过数据端口接收第二从SPI装置发送的数据。另外，第一从SPI装置还可通过该数据端口发送主SPI装置发送的数据，进一步提高数据传输效率。
另外，所述主SPI装置可具体用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，通过所述数据线发送第一指示，所述第一指示用于控制数据的发送。则所述第一从SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，不响应于所述第一指示进行数据的发送。
采用该设计，第一从SPI装置不对来自主SPI装置的第一指示进行响应，可避免与第二从SPI装置同时根据第一指示通过数据线发送数据，以免造成数据冲突。
所述主SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，通过所述数据线发送第二指示以及数据，所述第二指示用于控制数据的接收。则所述第一从SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，通过所述数据线接收所述第二指示，并响应于所述第二指示通过所述数据线接收数据。
采用该设计，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，第一从SPI装置可根据第二指示接收来自主SPI装置的数据。
所述主SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且 驱动所述第二片选信号为有效状态时，通过所述数据线发送第一指示以及通过所述数据线接收来自所述第一从SPI装置的数据，所述第一指示用于控制数据的发送。则所述第一从SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，通过所述数据线接收所述第一指示，并响应于所述第一指示通过所述数据线发送数据。
采用该设计，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，第一从SPI装置可根据第一指示向主SPI装置进行数据的发送。
另外，所述第一从SPI装置还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为非有效状态时，不通过所述数据线发送数据，以及不通过所述数据线接收数据。
采用该设计，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为非有效状态时，第一从SPI装置可不响应于主SPI装置发送的读指示位进行数据的读取。以及，第一从SPI装置不响应于主SPI装置发送的写指示位进行数据的发送，避免数据线上数据的传输发生冲突。
第二方面，本申请提供一种芯片，该芯片可以用于第一方面所述的第一从SPI装置。
示例性的，该芯片可包括SPI控制器、SPI控制逻辑单元(或称SPI控制逻辑电路)、SPI数据收发切换单元(或称SPI数据收发切换电路)以及SPI数据端口(或称数据端口)等组件。
其中，SPI控制逻辑电路可用于从主SPI装置接收第一片选信号以及第二片选信号，所述第一片选信号以及所述第二片选信号的组合用于使能所述芯片。SPI数据端口可通过数据线与所述主SPI装置以及第二从SPI装置连接。所述SPI控制逻辑电路可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中所述第二从SPI装置发送的数据。
可选地，所述SPI数据端口可包括发送端口以及接收端口，所述发送端口通过数据线与所述主SPI装置的接收端口连接，以及所述接收端口通过数据线与所述主SPI装置的发送端口连接，所述发送端口用于所述芯片向所述数据线发送数据，所述接收端口用于所述芯片接收所述数据线中传输的数据。所述SPI控制逻辑电路还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，将所述发送端口配置为用于接收所述数据线中传输的数据。
所述芯片还可包括SPI数据收发切换电路，所述SPI控制器可包括发送模块以及接收模块，所述发送模块用于数据的发送，所述接收模块用于数据的接收。所述SPI控制逻辑电路还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制SPI数据收发切换电路将所述发送端口连接至所述接收模块。
所述SPI控制逻辑电路还可用于，将所述SPI数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
所述SPI控制逻辑电路还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器不响应于所述数据线传输的第一指示进行数据的发送，所述第一指示用于控制数据的发送。
所述SPI控制逻辑电路还可用于，当所述主SPI装置驱动所述第一片选信号为非有效 状态且驱动所述第二片选信号为有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中传输的数据。所述SPI控制器还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，接收所述数据线中传输的第二指示，所述第二指示用于控制数据的接收，并响应于所述第二指示通过所述SPI数据端口接收所述数据线中传输的数据。
所述SPI控制逻辑电路还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中传输的数据。所述SPI控制器还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，接收所述数据线中传输的第一指示，所述第一指示用于控制数据的发送；响应于所述第一指示通过所述SPI数据端口向所述数据线发送数据。
所述SPI控制逻辑电路还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器不通过所述数据线发送数据，以及控制所述SPI控制器不通过所述数据线接收数据。
以上SPI控制器、SPI控制逻辑电路、SPI数据收发切换电路以及SPI数据端口可由集成电路实现。
第三方面，本申请提供一种摄像头模组，该摄像头模组可包括第二方面或第二方面任一设计所述的芯片，该摄像头模组可具备第二方面或第二方面任一设计所述的芯片的功能。该摄像头模组还可包括马达以及摄像头。当第二从SPI装置包括陀螺仪传感器时，所述马达可用于从所述芯片获取陀螺仪传感器的数据以执行所述摄像头的抖动控制和/或自动对焦(auto focus，AF)。
第四方面，本申请提供了一种终端设备，该终端设备可包括第一方面或第一方面任一设计所述的数据传输系统，因此该终端设备可具备第一方面或第一方面任一设计所述的功能。
或者，该终端设备可包括第二方面或第一方面任一设计所述的芯片，因此该终端设备可具备第一方面或第一方面任一设计所述芯片的功能。
或者，该终端设备可包括第三方面所述的摄像头模组，因此，该终端设备可具备第二方面或第二方面任一设计所述芯片的功能。此时，该终端设备可以是可拍照设备。终端设备还可包括图像处理芯片(image signal processing，ISP)，用于从所述摄像头模组获取图像信号，并对所述图像信号进行处理，例如，对摄像头模组输出的图像信号进行高清处理等等。
第五方面，本申请提供一种数据传输系统，该系统可包括第一摄像头、第二摄像头和第一传感器。该第一摄像头、该第二摄像头和该第一传感器之间通过SPI协议进行通信。该第一摄像头为主SPI设备，该第二摄像头和该第一传感器为从SPI设备，其中，当第一摄像头和第二摄像头同时运行时，第一摄像头通过SPI协议获取第一传感器数据，且所述第二摄像头通过SPI协议同时获取所述第一传感器数据。
采用以上数据传输系统，第一摄像头和第二摄像头能够同时获取第一传感器数据，降低摄像头获取传感器数据的延迟，提高摄像头模组的OIS效果。
在一种可能的设计中，第一摄像头可将第一片选信号输出至第二摄像头和第一传感器，以及将第二片选信号输出至第二摄像头和第一传感器，第一片选信号以及第二片选信号的 状态组合用于控制是否使能第二摄像头以及用于控制是否使能第一传感器。第一摄像头、第二摄像头和第一传感器SPI装置还通过数据线相连。当第一片选信号为有效状态且第二片选信号为非有效状态时，第一摄像头可控制所述第二摄像头通过所述数据线发送数据，以及通过所述数据线接收所述第二摄像头发送的数据，第一传感器可根据第一摄像头的控制通过数据线发送数据，第二摄像头可通过数据线接收第一传感器发送给第一摄像头的数据。
采用该设计，第一摄像头可通过第一片选信号以及第二片选信号实现第二摄像头和第一传感器工作状态的灵活控制。在第二摄像头和第一传感器处于工作状态(或称使能状态)时，第一摄像头和第二摄像头可同时获取第一传感器的数据，提高数据传输效率。
在一种可能的设计中，第一摄像头可将第一片选信号输出至第二摄像头和第一传感器，以及将第二片选信号输出至第二摄像头和第一传感器，第一片选信号以及第二片选信号的状态组合用于控制是否使能第二摄像头以及用于控制是否使能第一传感器。第一摄像头、第二摄像头和第一传感器SPI装置还通过数据线相连。当第一片选信号以及第二片选信号为预设的状态组合(比如，第一片选信号为有效状态且第二片选信号为非有效状态，或者其他的状态组合)时，第一摄像头可控制所述第二摄像头通过所述数据线发送数据，以及通过所述数据线接收所述第二摄像头发送的数据，第一传感器可根据第一摄像头的控制通过数据线发送数据，第二摄像头可通过数据线接收第一传感器发送给第一摄像头的数据。
采用该设计，第一摄像头可通过第一片选信号以及第二片选信号实现第二摄像头和第一传感器工作状态的灵活控制。在第二摄像头和第一传感器处于工作状态(或称使能状态)时，第一摄像头和第二摄像头可同时获取第一传感器的数据，提高数据传输效率。
在一种可能的设计中，第一摄像头可通过数据线向第二摄像头发送数据，第一传感器可通过数据线接收第一摄像头发送的数据，第二摄像头可通过数据线接收第一摄像头发送给第一传感器的数据。
采用该设计，第一摄像头可通过第一片选信号以及第二片选信号实现第二摄像头和第一传感器工作状态的灵活控制。在第二摄像头和第一传感器处于工作状态(或称使能状态)时，第二摄像头和第一传感器可同时获取第一摄像头的数据，提高数据传输效率。
在一种可能的设计中，若第二摄像头的发送端口与第一摄像头的接收端口通过第一数据线相连，第二摄像头的接收端口与第一摄像头的发送端口通过第二数据线相连，数据线包括第一数据线以及所述第二数据线，第二摄像头的发送端口以及第一摄像头的发送端口用于数据的发送，第二摄像头的接收端口以及第一摄像头的接收端口用于数据的接收，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，第二摄像头还可将第二摄像头的发送端口切换为接收端口，以及，将第二摄像头的接收端口切换为发送端口。
采用该设计，在四线模式下，第二摄像头可通过发送端口和接收端口的切换，接收第一摄像头发送的数据，同时第二摄像头不再接收来自于第一摄像头的数据和指令，也就不会通过数据线发送数据，避免数据传输冲突。
在一种可能的设计中，第二摄像头还可将数据端口配置为双向数据端口，该双向数据端口支持数据的接收以及发送。
采用该设计，在三线模式下，第二摄像头可将数据端口设置为双向数据端口，以通过数据端口接收第一传感器发送的数据。另外，第二摄像头可还可通过该数据端口接收第一 摄像头发送的数据，进一步提高数据传输效率。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，第一摄像头可通过数据线发送第一指示，第一指示用于控制数据的发送，第二摄像头不响应于所述第一指示进行数据的发送。
采用该设计，第二摄像头可不对接收的第一指示进行响应，因此不会通过数据线发送数据，避免数据传输冲突。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，第一摄像头可通过数据线发送第二指示以及数据，第二指示可用于控制数据的接收，第二摄像头可通过数据线接收第二指示，并响应于第二指示通过数据线接收数据。
采用该设计，第一摄像头可灵活控制第二摄像头的工作状态，令第二摄像头根据来自于第一摄像头的第二指示接收数据线中传输的数据，以提高传输效率。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，第一摄像头可通过数据线发送第一指示，第一指示用于控制数据的发送，第二摄像头可接收第一指示，并根据第一指示通过数据线进行数据的发送，第一摄像头还可通过数据线接收来自于第二摄像头的数据。
采用该设计，第二摄像头可根据第一指示向第一摄像头发送数据，以提高传输效率。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合(比如，第一片选信号为非有效状态且第二片选信号为非有效状态，或者其他的状态组合)时，第二摄像头不通过数据线发送数据，以及不通过数据线接收数据，以实现第二摄像头工作模式的灵活切换。
在一种可能的设计中，第一传感器为陀螺仪传感器。第一传感器信息来自于第一传感器，第一传感器信息为陀螺仪信息。
第六方面，本申请提供一种电路。该电路可连接至第五方面所述的第二摄像头。
示例性的，该电路可包括SPI控制器、SPI控制逻辑单元(或称SPI控制逻辑电路)、SPI数据收发切换单元(或称SPI数据收发切换电路)或者SPI数据端口(或称数据端口)中的部分或全部组件。
SPI控制器可用于在第一摄像头通过SPI协议获取第一传感器数据时，控制SPI数据端口获取第一传感器数据。其中，SPI数据端口用于第二摄像头进行与第一摄像头和/或第一传感器之间的SPI协议通信，第一摄像头为主SPI设备，第二摄像头和第一传感器为从SPI设备。
在一种可能的设计中，SPI数据端口可将获取的第一传感器数据发送至所述第二摄像头。
在一种可能的设计中，SPI数据端口通过数据线与第一摄像头以及第一传感器连接。
在一种可能的设计中，电路还包括SPI控制逻辑单元，用于从第一摄像头接收第一片选信号以及第二片选信号，第一片选信号以及第二片选信号的组合用于控制是否使能第二摄像头。当第一片选信号为有效状态且第二片选信号为非有效状态时，SPI控制逻辑电路可控制SPI控制器控制SPI数据端口接收数据线中第一传感器发送给第一摄像头的数据。
在一种可能的设计中，电路还包括SPI控制逻辑单元，用于从第一摄像头接收第一片选信号以及第二片选信号，第一片选信号以及第二片选信号的组合用于控制是否使能第二摄像头。当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑电路可控制SPI控制器控制SPI数据端口接收数据线中第一传感器发送给第一摄像头的数据。
在一种可能的设计中，SPI控制逻辑单元还可控制所述SPI控制器控制SPI数据端口接收所述数据线中所述第一摄像头发送给第一传感器的数据。
在一种可能的设计中，若第二摄像头的发送端口与第一摄像头的接收端口通过第一数据线相连，第二摄像头的接收端口与第一摄像头的发送端口通过第二数据线相连，数据线包括第一数据线以及所述第二数据线，第二摄像头的发送端口以及第一摄像头的发送端口用于数据的发送，第二摄像头的接收端口以及第一摄像头的接收端口用于数据的接收，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元还可将发送端口配置为用于接收数据线中传输的数据。
在一种可能的设计中，该电路还包括SPI数据收发切换电路，SPI控制器包括发送模块以及接收模块，发送模块用于数据的发送，接收模块用于数据的接收；当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元还可控制所述SPI数据收发切换电路将所述发送端口连接至所述接收模块。
在一种可能的设计中，SPI控制逻辑单元还可将SPI数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元还可控制所述SPI控制器不响应于所述数据线传输的第一指示进行数据的发送，所述第一指示用于控制数据的发送。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元可控制SPI控制器通过SPI数据端口接收数据线中传输的第二指示。SPI控制器可响应于该第二指示，控制SPI数据端口接收数据线中传输的数据，第二指示用于控制数据的接收。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元可控制SPI控制器通过SPI数据端口接收数据线中传输的第一指示。SPI控制器可响应于该第一指示，控制SPI数据端口向数据线发送数据，第一指示用于控制数据的发送。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元可控制SPI控制器不通过数据线发送数据，以及控制SPI控制器不通过数据线接收数据。
第七方面，本申请提供一种电路。该电路可连接至第五方面所述的第一摄像头。
示例性的，该电路可包括控制单元(或称控制电路)以及SPI数据端口。
SPI数据端口可用于第一摄像头通过SPI协议获取第一传感器数据。控制电路可用于控制第二摄像头通过SPI协议同时获取第一传感器数据，第一摄像头为主SPI设备，第二 摄像头和第一传感器为从SPI设备。第一传感器数据来自于该第一传感器。
在一种可能的设计中，SPI数据端口通过数据线与第二摄像头以及第一传感器连接。
在一种可能的设计中，控制电路可将第一片选信号输出至所述第二摄像头和所述第一传感器，以及将第二片选信号输出至所述第二摄像头和所述第一传感器，所述第一片选信号以及所述第二片选信号的状态组合用于控制是否使能所述第二摄像头以及用于控制是否使能所述第一传感器。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，控制电路可控制第一传感器通过所述数据线发送数据，并控制SPI数据端口通过所述数据线接收所述第一传感器发送的数据，以及控制第二摄像头通过数据线接收第一传感器发送给第一摄像头的数据。
在一种可能的设计中，当第一片选信号以及第二片选信号为预设的状态组合时，控制电路可控制第一传感器通过所述数据线发送数据，并控制SPI数据端口通过所述数据线接收所述第一传感器发送的数据，以及控制第二摄像头通过数据线接收第一传感器发送给第一摄像头的数据。
在一种可能的设计中，控制电路还可控制SPI数据端口通过数据线向第一传感器发送数据，并控制第二摄像头通过数据线接收第一摄像头发送给第一传感器的数据。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，控制电路可控制SPI数据端口通过数据线发送第一指示，第一指示用于控制数据的发送。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，控制电路可控制SPI数据端口通过数据线发送第一指示，第一指示用于控制数据的发送。
第八方面，本申请提供一种摄像头模组，该摄像头模组可包括第六方面或第六方面任一设计所述的电路，以实现第六方面或第六方面任一设计所述的电路的功能。该摄像头模组还可包括马达以及第二摄像头。当第一传感器为陀螺仪传感器时，马达可用于通过该电路获取第一传感器数据(即陀螺仪数据)，用并根据第一传感器数据执行所述摄像头的抖动控制和/或自动对焦(auto focus，AF)。
第九方面，本申请提供一种摄像头模组，该摄像头模组可包括第七方面或第七方面任一设计所述的电路，以实现第七方面或第七方面任一设计所述的电路的功能。该摄像头模组还可包括马达以及第一摄像头。当第一传感器为陀螺仪传感器时，马达可用于通过该电路获取第一传感器数据(即陀螺仪数据)，用并根据第一传感器数据执行所述摄像头的抖动控制和/或自动对焦。
第十方面，本申请提供了一种终端设备，该终端设备可包括第五方面或第五方面任一设计所述的数据传输系统，因此该终端设备可具备第五方面或第五方面任一设计所述的功能。
和/或，该终端设备可包括第六方面或第六方面任一设计所述的电路，因此该终端设备可具备第六方面或第六方面任一设计所述电路的功能。
和/或，该终端设备可包括第七方面或第七方面任一设计所述的电路，因此该终端设备可具备第七方面或第七方面任一设计所述电路的功能。
和/或，该终端设备可包括第八方面或第八方面任一设计所述的摄像头模组，因此，该 终端设备可具备第八方面或第八方面任一设计所述摄像头模组的功能。
和/或，该终端设备可包括第九方面或第九方面任一设计所述的摄像头模组，因此，该终端设备可具备第九方面或第九方面任一设计所述摄像头模组的功能。
和/或，该终端设备可以是可拍照设备。终端设备还可包括图像处理芯片(image signal processing，ISP)，用于从所述摄像头模组获取图像信号，并对所述图像信号进行处理，例如，对摄像头模组输出的图像信号进行高清处理等等。
第十一方面，本申请提供了一种终端设备，包括第一摄像头模组、第二摄像头模组，以及用于输出陀螺仪信息的陀螺仪传感器。其中，该第一摄像头模组、该第二摄像头模组与该陀螺仪传感器通过串行外设接口SPI连接。该第一摄像头模组作为主SPI装置，该陀螺仪传感器以及该第二摄像头模组均作为从SPI装置，该第一摄像头模组与该第二摄像头模组在该第一摄像头模组发送的SPI片选信号的控制下，同时从所述陀螺仪传感器获得所述陀螺仪信息。该图像处理单元，用于从该第一摄像头模组以及该第二摄像头模组获取图像信号。
在一种可能的设计中，该第一摄像头模组与该第二摄像头模组均通过数据线与该陀螺仪传感器连接；该第一摄像头模组发送的SPI片选信号为预设的状态组合时，该第一摄像头模组与该第二摄像头模组同时从该陀螺仪传感器获得该陀螺仪信息。
在一种可能的设计中，该第一摄像头模组与该第二摄像头模组均通过数据线与该陀螺仪传感器连接；该第一摄像头模组发送的SPI片选信号使能该第二摄像头模块以及该陀螺仪传感器时，该第一摄像头模组与该第二摄像头模组同时从该陀螺仪传感器获得该陀螺仪信息。
在一种可能的设计中，该第二摄像头模组与该陀螺仪传感器同时从该第一摄像头模组接收数据。
应理解，以上第二方面及其可能的设计至第十一方面及其可能的设计的有益效果，可参照在上述第一方面及其可能的设计中对有益效果的描述。
附图说明
图1为本申请实施例提供的一种数据传输系统的结构示意图；
图2为本申请实施例提供的一种双片选逻辑判断结果示意图；
图3为本申请实施例提供的一种数据传输时的时序示意图；
图4为本申请实施例提供的一种数据传输系统的连接关系示意图；
图5为本申请实施例提供的另一种数据传输系统的连接关系示意图；
图6为本申请实施例提供的另一种数据传输时的时序示意图；
图7为本申请实施例提供的另一种数据传输时的时序示意图；
图8为本申请实施例提供的另一种数据传输系统的连接关系示意图；
图9为本申请实施例提供的一种从SPI装置的结构示意图；
图10为本申请实施例提供的一种数据传输系统的结构示意图；
图11为本申请实施例提供的另一种数据传输系统的连接关系示意图；
图12为本申请实施例提供的另一种数据传输系统的连接关系示意图；
图13为本申请实施例提供的另一种数据传输系统的连接关系示意图；
图14为本申请实施例提供的一种电路的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。方法实施例中的具体操作方法也可以应用于装置实施例或系统实施例中。
下面对本申请涉及术语进行解释：
至少一个，是指一个，或一个以上，即包括一个、两个、三个及以上。
多个，是指两个，或两个以上，即包括两个、三个及以上。
携带，可以是指某消息用于承载某信息或数据，也可以是指某消息由某信息构成。
耦合是指装置、单元或模块之间的间接耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。
SPI结构，可包括主SPI装置(或称主设备、主装置)以及从SPI装置(或称从设备、从装置)，以及主SPI装置以及从SPI装置之间的SPI连接线。其中，主SPI装置以及从SPI装置之间的SPI连接线可包括片选信号线、串行同步时钟信号线(serial clock，SCK)(以下可称为时钟线)以及数据线等等。当主SPI装置与多个从SPI装置通过时钟线以及数据线连接时，主SPI装置可通过片选信号使能(或称选通)一个从SPI装置，并通过数据线的一个指示位(以下称为写指示位)以及时钟线指示使能的从SPI装置通过数据线发送数据，主SPI装置可通过数据线读取从SPI装置发送的数据。或者，主SPI装置可通过数据线的一个指示位(以下称为读指示位)以及时钟线指示使能的从SPI装置通过数据线读取数据，主SPI装置还可通过数据线发送数据，从而令从SPI装置通过数据线接收数据。
片选信号线，在本申请中是指用于传输片选信号(chip selection，CS)的信号线。其中，片选信号可包括有效状态和非有效状态。当主SPI装置驱动片选信号处于有效状态时，该片选信号可用于使能从SPI装置。或者，主SPI装置101可驱动片选信号处于非有效状态，从而令从SPI装置处于非选通状态。示例性的，当片选信号处于低电平(例如，电位为0)时，片选信号处于有效状态，以及当片选信号处于高电平(例如，电位为1)时，片选信号处于非有效状态。
时钟线，可由主SPI装置产生。时钟线可用于向主SPI装置以及从SPI装置进行时钟同步。
数据线，可包括三线模式的串行数据线(serial data，SDA)。其中，SDA为双向数据线。数据线也可包括四线模式的输出数据线(serial data output，SDO)以及输入数据线(serial data input，SDI)。其中，SDO以及SDI均为单向数据线。SDO可用于SPI装置发送数据，SDI可用于SPI装置接收数据。四线模式中，由主SPI装置向从SPI装置发送数据的数据线也可被称为主输出从输入数据线(master output/slave input，MOSI)，即MOSI可用于传输主SPI装置通过SDO发送的数据，从SPI装置可通过SDI从MOSI接收数据。由从SPI装置向主SPI装置发送数据的数据线也可被称为主输入从输出数据线(master input/slave output，MISO)，即MISO可用于传输从SPI装置通过SDO发送的数据，主SPI装置可通过SDI从MOSI接收数据。
数据端口，SPI装置可通过数据端口向数据线发送数据，或通过数据端口接收数据线中的数据。对于三线模式，SPI装置至少可一个数据端口，该数据端口为双向数据端口，可支持数据的接收及发送。三线模式下，该数据端口可与SDA连接。对于四线模式，SPI装置至少可包括两个数据端口，其中，一个数据端口可作为发送端口，用于支持数据的发送，该发送端口与SDO连接；一个数据端口可作为接收端口，用于支持事件的接收，该 发送端口与SDI连接。
读写指示位，可包括读指示位以及写指示位。其中，读指示位可用于控制接收读指示的从SPI装置通过数据线接收数据。示例性的，读写指示位可以是时钟线开始后主SPI装置输出的第一个数据位。例如，三线模式下，读写指示位可以是时钟线开始后主SPI装置通过SDA输出的第一个数据位；四线模式下，读写指示位可以是时钟线开始后主SPI装置通过SDO输出的第一个数据位。若时钟线开始后的第一位数据位被置为1，则该数据位可被称为读指示位。写指示位可用于控制接收读指示的从SPI装置通过数据线发送数据。示例性的，若时钟线开始后的第一位数据位被置为0，则该数据位可被称为写指示位。应理解，在本申请中，写指示位也可被称为第一指示。读指示位也可被称为第二指示。
另外应理解，本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一(项)个”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a、b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c，或a、b和c，其中a、b、c可以是单个，也可以是多个。
下面，结合附图对本申请实施例进行详细说明。
本申请实施例提供的数据传输方法，可应用于SPI总线系统(或称SPI结构)，其中，该系统可包括一个主SPI装置以及至少两个从SPI装置，所述主SPI装置与所述至少两个从SPI装置通过数据线连接。
如图1所示，本申请实施例提供的一种数据传输系统100可包括主SPI装置101、第一从SPI装置102以及第二从SPI装置103。
应理解，本申请实施例提供的数据传输系统100，可应用于具备SPI结构的终端设备或其他电子设备中，例如，可应用于移动终端或计算机等设备中。示例性，本申请实施例提供的数据传输系统100的一种可能的应用场景为包含多个摄像头模组的可拍照设备，该可拍照设备可以是具备拍照功能的智能手机、可移动智能设备、职能家居设备或者平板电脑等等，也可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置。
该场景下，主SPI装置101可包括可拍照设备的多个摄像头模组中的一个摄像头模组(本申请中，作为主SPI装置的摄像头模组可称为摄像头模组A)，第一从SPI装置102可包括可拍照设备的其他的一个摄像头模组(本申请中，作为从SPI装置的摄像头模组可称为摄像头模组B)，第二从SPI装置103可包括可拍照设备的陀螺仪传感器。其中，陀螺仪传感器可部署于可拍照设备的主板。示例性的，每个摄像头模组可包含一个马达驱动芯片，或称马达驱动集成电路(integrated circuit，IC)。马达驱动IC可用于输出电流或脉宽调制(pulse width modulation，PWM)信号以控制摄像头模组的马达按照要求进行移动操作，实现抖动补偿。
数据传输系统100中，主SPI装置101、第一从SPI装置102以及第二从SPI装置103通过数据线连接。示例性的，若主SPI装置101、第一从SPI装置102以及第二从SPI装置103通过三线模式连接，则数据线可包括SDA。或者，若主SPI装置101、第一从SPI装置102以及第二从SPI装置103通过四线模式连接，则数据线可包括SDO以及SDI。
另外，主SPI装置101、第一从SPI装置102以及第二从SPI装置103还通过时钟线连接。
如图1所示，主SPI装置101将第一片选信号(CS1)输出至第一从SPI装置102以 及将第二片选信号(CS2)输出至第一从SPI装置102。从而主SPI装置101可通过第一片选信号的有效状态或非有效状态以及第二片选信号的有效状态或非有效状态的组合，令第一从SPI装置102处于多种工作模式。
主SPI装置101还可将第一片选信号输出至第二从SPI装置103，从而可通过第一片选信号使能第二从SPI装置103。具体的，当第一片选信号为有效状态时，第一片选信号使能第二从SPI装置103，第二从SPI装置103可根据主SPI装置101输出的写指示位，通过数据线发送数据。或者，第二从SPI装置103可根据主SPI装置101输出的读指示位，通过数据线读取数据。
示例性的，第一从SPI装置102的双片选逻辑判断结果可由图2表示。其中，双片选逻辑判断结果即为第一从SPI装置102所处的工作模式。图2中，CS1＝0表示第一片选信号处于有效状态，CS2＝0表示第二片选信号处于有效状态，CS1＝1表示第一片选信号处于非有效状态，CS2＝1表示第二片选信号处于非有效状态。“a&b”表示a且b。
根据图2，当CS1＝0&CS2＝1时，双片选逻辑判断结果为数据侦听模式，第一从SPI装置102可根据该判断结果进入该数据侦听模式(或称，第一从SPI装置102处于数据侦听模式)。数据侦听模式下，第一从SPI装置102可通过数据线进行数据的接收，而不通过数据线进行数据的发送。换句话说，数据侦听模式下，无论主SPI装置101输出写指示位还是读指示位，第一从SPI装置102都只侦听数据线，并对数据线传输的数据进行接收。
当CS1＝1&CS2＝0时，双片选逻辑判断结果为标准从SPI装置模式(或称标准slave模式)，第一从SPI装置102可根据该判断结果进入该标准从SPI装置模式(或称，第一从SPI装置102处于标准从SPI装置模式)。标准slave模式下，第一从SPI装置102可根据主SPI装置101输出的读指示位通过数据线进行数据的接收，也可根据主SPI装置101输出的写指示位通过数据线进行数据的发送。
另外，当CS1＝1&CS2＝1时，双片选逻辑判断结果为未选通模式，第一从SPI装置102可根据该判断结果进入该未选通模式(或称，第一从SPI装置102处于未选通模式)。未选通模式下，第一从SPI装置102不通过数据线进行数据的接收，也不通过数据线进行数据的发送。换句话说，未选通模式下，无论主SPI装置101输出写指示位还是读指示位，第一从SPI装置102都不对主SPI装置101的指示进行响应。
以图3为例，对数据侦听模式下第一从SPI装置102的总线访问模式进行说明。如图3所示，当CS1＝0&CS2＝1时，无论主SPI装置101将SCK开始后的第一位数据位(即读写指示位)置为0(表示写)，还是1(表示读)，第一从SPI装置102由于处于数据侦听模式而只支持数据输入，不会往数据线(包括三线模式的SDA或四线模式的SDO)上输出数据。
具体来说，对于三线模式，主SPI装置101、第一从SPI装置102以及第二从SPI装置103之间的连接关系如图4所示。可见，主SPI装置101第一从SPI装置102以及第二从SPI装置103各自的数据端口(数据端口与SDA连接)均支持双向数据传输。示例性的，当处于三线模式时，第一从SPI装置102可将其数据端口配置为双向端口。
如图4所示，三线模式下，当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若主SPI装置101通过SDA发送写指示位，第二从SPI装置103在通过SDA接收写指示位后，可响应于写指示位通过SDA发送数据，主SPI装置101可通过SDA接收第二从SPI装置103发送的数据，第一从SPI装置102处于数据侦听模式， 因此第一从SPI装置102第一从SPI装置102可通过SDA接收第二从SPI装置103发送的数据。另外，第一从SPI装置102不响应于SDA传输的写指示位在SDA上进行数据的发送(或称，第一从SPI装置102忽略响应于写指示位进行数据的发送)，以避免造成SDA上的数据冲突。
应理解，在本申请中的表述“SPI装置通过SDA/SDO发送数据”，是指SPI装置通过与SDO连接的发送端口将数据发送至SDA/SDO，并由SDA/SDO将数据向其他SPI装置发送。还应理解，在本申请中的表述“SPI装置通过SDA/SDI接收数据”，是指SPI装置通过与SDA/SDI连接的接收端口，从SDA/SDI接收其他SPI装置通过其他SPI装置的SDA/SDO发送的数据。
另外，根据图4，三线模式下，当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若主SPI装置101通过SDA发送读指示位，主SPI装置101还可通过SDA发送数据，此时第二从SPI装置103可响应于读指示位，通过SDA接收主SPI装置101发送的数据，以及，第一从SPI装置102处于数据侦听模式，因此第一从SPI装置102可通过SDA接收主SPI装置101发送的数据。从而多个从SPI装置可同时接收主SPI装置发送的数据，因此提高多个从SPI装置从主SPI装置接收数据时的效率。
对于四线模式，当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，主SPI装置101、第一从SPI装置102以及第二从SPI装置103之间的连接关系如图5所示。可见，主SPI装置101、第一从SPI装置102以及第二从SPI装置103可通过各自的发送端口(发送端口与SDO连接)进行数据的发送，以及，可通过各自的接收端口(接收端口与SDI连接)进行数据的接收。
如图5所示，四线模式下，当主SPI装置101通过SDO发送写指示位时，第二从SPI装置103可响应于写指示位通过SDO发送数据，主SPI装置101可通过SDI接收第二从SPI装置103通过SDO发送的数据，以及，第一从SPI装置102处于数据侦听模式，因此第一从SPI装置102可通过SDI接收第二从SPI装置103通过SDO发送的数据。另外，第一从SPI装置102的SDO不会接收主SPI装置101通过SDO发送的写指示位，因此，第一从SPI装置102不响应于主SPI装置101发送的写指示位进行数据的发送(或称，第一从SPI装置102忽略响应于写指示位进行数据的发送)，以避免造成数据传输的冲突。
另外，如图5所示，对于四线模式，当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若主SPI装置101通过SDO发送读指示位，并通过SDO发送数据，此时第二从SPI装置103可响应于读指示位通过SDI接收数据。
下面，以图6以及图7为例对标准从SPI装置模式下第一从SPI装置102的总线访问模式进行说明。如图6所示，标准从SPI装置模式下，第一从SPI装置102工作在标准从SPI装置模式，若主SPI装置101将SCK开始后的第一位数据位置为0，第一从SPI装置102可在主SPI装置101的控制下读取数据线(SDA或SDI)上传输的数据。如图7所示，标准从SPI装置模式下，若主SPI装置101将SCK开始后的第一位数据位置为1，第一从SPI装置102可在主SPI装置101的控制下，通过数据线(SDA或SDO)发送数据。从而在处于标准从SPI装置模式时，第一从SPI装置102可以在主SPI装置101的控制下实现第一从SPI装置102与主SPI装置101之间的数据传输。
具体来说，对于三线模式，主SPI装置101、第一从SPI装置102以及第二从SPI装置103之间的连接关系如图4所示。当主SPI装置101驱动第一片选信号为非有效状态且 驱动第二片选信号为有效状态时，若主SPI装置101通过SDA发送写指示位，此时第一从SPI装置102处于标准slave模式，第二从SPI装置103在通过SDA接收写指示位后，可响应于该写指示位通过SDA发送数据，主SPI装置101可通过SDA接收第一从SPI装置102发送的数据。此时第二从SPI装置103处于未选通状态，不对SDA传输的写指示位进行响应。
另外，对于三线模式，当主SPI装置101驱动第一片选信号为非有效状态且驱动第二片选信号为有效状态时，若主SPI装置101通过SDA发送读指示位并通过SDA传输数据，此时第一从SPI装置102处于标准slave模式，第一从SPI装置102可响应于SDA传输的读指示位通过SDA接收数据。以及，此时第二从SPI装置103处于未选通状态，不对SDA传输的读指示位进行响应。
对于四线模式，主SPI装置101、第一从SPI装置102以及第二从SPI装置103之间的连接关系如图8所示。当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若主SPI装置101通过SDO发送写指示位，此时第一从SPI装置102处于标准slave模式，第一从SPI装置102可通过SDI接收写指示位，并响应于写指示位通过SDO发送数据，主SPI装置101可通过SDI接收第一从SPI装置102通过SDO发送的数据。以及，此时第二从SPI装置103处于未选通状态，不对主SPI装置101通过SDO发送的写指示位进行响应。
另外，如图8所示，当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若主SPI装置101通过SDO发送读指示位以及通过SDO发送数据，此时第一从SPI装置102处于标准slave模式，第一从SPI装置102可通过SDI接收读指示位，并响应于读指示位通过SDI读取数据。以及，此时第二从SPI装置103处于未选通状态，不对主SPI装置101通过SDO发送的读指示位进行响应。
应理解，未选通模式下，对于三线模式，主SPI装置101、第一从SPI装置102以及第二从SPI装置103之间的连接关系如图4所示。另外，未选通模式下，对于四线模式，主SPI装置101、第一从SPI装置102以及第二从SPI装置103之间的连接关系如图8所示。
可选地，以上双片选逻辑判断结果也可由表1表示。
第一片选信号 第二片选信号 第一从SPI装置的工作模式
有效状态 非有效状态 数据侦听模式
非有效状态 有效状态 标注从SPI装置模式
非有效状态 非有效状态 未选通模式
表1
根据图2或表1所示，当第一片选信号的状态为有效状态、第二片选信号的状态为非有效状态时，可令第一从SPI装置102进入数据侦听模式。当第一片选信号的状态为非有效状态、第二片选信号的状态为有效状态时，可令第一从SPI装置102进入标准从SPI装置模式。当第一片选信号的状态为非有效状态、第二片选信号的状态为非有效状态时，可令第一从SPI装置102进入未选通模式。
结合以上表1所示第一从SPI装置102的工作模式以及第二从SPI装置103的工作模 式，当主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，主SPI装置101可控制第二从SPI装置103通过数据线发送数据，并通过数据线接收第二从SPI装置103发送的数据。此时，由于第一从SPI装置102处于数据侦听模式，第一从SPI装置102可通过数据线接收数据。从而在主SPI装置101驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，主SPI装置101以及第一从SPI装置可同时接收第二从SPI装置103发送的数据，提高了主SPI装置以及多个从SPI装置之间的数据传输效率。
当主SPI装置101包括可拍照设备的多个摄像头模组中的一个摄像头模组，第一从SPI装置102包括可拍照设备的其他的一个摄像头模组，以及第二从SPI装置103包括可拍照设备的陀螺仪传感器时，包括主SPI装置101以及第一从SPI装置102在内的多个摄像头模组可同时接收陀螺仪传感器发送的陀螺仪信息(或称陀螺仪传感器的数据)。这里的陀螺仪信息可包括陀螺仪的X/Y/Z三轴角速度信息等数据，支持光学防抖的摄像头模组可根据陀螺仪的X/Y/Z三轴角速度信息计算出拍照时人手的抖动，并通过马达(如集成于摄像头模组内部的马达)控制镜头实现抖动补偿。采用以上数据传输方法，可提高了多个摄像头模组接收陀螺仪信息的效率，从而优化光学防抖效果。
另外，主SPI装置101应避免同时驱动第一片选信号为有效状态以及驱动第二片选信号为有效状态。若主SPI装置101错误驱动第一片选信号以及第二片选信号同时处于有效状态，则第一从SPI装置102可判断驱动状态错误，不响应总线操作。
在一种可能的示例中，第一从SPI装置102可对其数据端口进行切换，从而在不改变芯片之间连接线路的条件下以实现如图5及如图8所示的连接关系之间的切换。其中，数据端口的切换，包括但不限于将数据端口从单向数据端口切换至双向数据端口，或者，将发送端口切换为接收端口，或者，将接收端口切换为发送端口等等。
当CS1＝1&CS2＝0时，若第一从SPI装置102的发送端口与主SPI装置101的接收端口相连(或者说，第一从SPI装置102的发送端口与主SPI装置101的接收端口以及第二从SPI装置103的发送端口连接)，以及第一从SPI装置102的接收端口与主SPI装置101的发送端口相连(或者说，第一从SPI装置102的接收端口与主SPI装置101的发送端口以及第二从SPI装置103的接收端口连接)，则第一从SPI装置102可响应于CS1以及CS2，将第一从SPI装置102的发送端口切换为接收端口(换句话说，第一从SPI装置102将第一从SPI装置102的SDO切换为SDI)，以及将第一从SPI装置102的接收端口切换为发送端口(换句话说，第一从SPI装置102将第一从SPI装置102的SDI切换为SDO)，得到如图5所示的连接关系。此时，第一从SPI装置102的接收端口与主SPI装置101的接收端口相连，以及第一从SPI装置102的发送端口与主SPI装置101的发送端口相连。
另外，若CS1≠1或CS2≠0时，若第一从SPI装置102的接收端口与主SPI装置101的接收端口相连，以及第一从SPI装置102的发送端口与主SPI装置101的发送端口相连，则第一从SPI装置102可响应于CS1以及CS2，将第一从SPI装置102的接收端口切换为发送端口(换句话说，第一从SPI装置102将第一从SPI装置102的SDI切换为SDO)，以及将第一从SPI装置102的发送端口切换为接收端口(换句话说，第一从SPI装置102将第一从SPI装置102的SDO切换为SDI)，从而得到如图8所示的连接关系。
下面结合图9，说明第一从SPI装置102进行数据端口切换的方式。
如图9所示，第一从SPI装置102可由SPI控制器、SPI控制逻辑单元(或称SPI控 制逻辑电路)、SPI数据收发切换单元(或称SPI数据收发切换电路)以及SPI数据端口(或称数据端口)等组成。
示例性的，SPI控制器可用于第一从SPI装置102处理需要发送的数据，或用于第一从SPI装置102处理通过数据线接收的数据。例如，SPI控制器可包括发送模块及接收模块，发送模块可用于处理并向发送端口发送需要发送的数据，接收模块可用于接收并处理来自接收端口的数据。SPI控制器还可根据第一从SPI装置102所处的工作模式控制数据的接收和/或发送。比如，当第一从SPI装置102处于侦听模式，SPI控制器可不向发送端口传输需要发送的数据。又比如，当第一从SPI装置102处于未选通模式，SPI控制器可不向发送端口传输需要发送的数据，以及SPI控制器可不通过接收模块处理来自接收端口的数据。
SPI控制逻辑单元可接收第一片选信号以及第二片选信号，并根据第一片选信号以及第二片选信号进行双片选判断逻辑结果判断，其判断结果可如图2或表1所示。SPI控制逻辑单元还可用于向SPI控制器输出该逻辑判断结果，以指示第一从SPI装置102所处的工作模式。SPI控制逻辑单元还可用于根据该逻辑判断结果配置SPI数据端口的传输方向。SPI控制逻辑单元还可用控制SPI数据收发切换单元连通SPI数据端口与SPI控制器中的发送模块和/或接收模块。
SPI数据收发切换单元可用于根据SPI控制逻辑单元的控制，连通SPI数据端口与SPI控制器中的发送模块，形成发送通路。发送通路可用于第一从SPI装置102向SDO发送数据。SPI数据收发切换单元还可用于根据SPI控制逻辑单元的控制，连通SPI数据端口与SPI控制器中的接收模块，形成接收通路。接收通路可用于第一从SPI装置102从SDI接收数据。
示例性的，第一从SPI装置102可包括至少一个SPI数据端口。当SPI数据端口数量为一个时，第一从SPI装置102仅支持三线模式。当SPI数据端口数量为两个或两个以上时，第一从SPI装置102可支持三线模式即四线模式。
以SPI数据端口包括SPI数据端口1以及SPI数据端口2为例，在进行端口切换时，对于三线模式，SPI控制逻辑单元可将SPI数据端口1(或数据端口2)切换为双向数据端口。具体的，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1(或数据端口2)的传输方向为双向传输，以及，通过配置接口2控制SPI数据端口1(或数据端口2)连通至SPI控制器的发送模块以及接收模块。
以SPI数据端口包括SPI数据端口1以及SPI数据端口2为例，在进行端口切换时，对于四线模式，当CS1＝0&CS2＝1时，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1以及数据端口2的传输方向。
示例性的，四线模式下，当CS1≠0或CS2≠1时，若SPI数据端口1的传输方向为发送方向，以及SPI数据端口2的传输方向为接收方向，即，SPI数据端口1为发送端口(此时与SPI数据端口1连通的数据线为SDO)，SPI数据端口2为接收端口(此时与SPI数据端口2连通的数据线为SDI)，则当CS1＝0&CS2＝1时，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1的传输方向为接收方向，以及通过配置接口1配置SPI数据端口2的传输方向为发送方向，即，SPI控制逻辑单元通过配置接口1配置SPI数据端口1为接收端口(此时与SPI数据端口1连通的数据线为SDI)，以及通过配置接口1配置SPI数据端口2为发送端口(此时与SPI数据端口2连通的数据线为SDO)。此外，SPI控制逻辑单 元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口1连接至SPI控制器的接收模块，以形成接收通路，以及，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口2连接至SPI控制器的发送模块，形成发送通路。至此完成发送端口以及接收端口的切换。
另外，四线模式下，当CS1以及CS2的状态从CS1＝0&CS2＝1变为CS1≠0或CS2≠1(例如，CS1＝1或CS2＝0)时，若SPI数据端口1的传输方向为接收方向，且SPI数据端口2的传输方向为发送方向，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1的传输方向为发送方向(此时与SPI数据端口1连通的数据线为SDO)，以及通过配置接口1配置SPI数据端口2的传输方向为接收方向(此时与SPI数据端口2连通的数据线为SDI)。此外，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口1连接至SPI控制器的发送模块，以形成发送通路，以及，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口2连接至SPI控制器的接收模块，形成接收通路。至此完成发送端口以及接收端口的切换。
示例性的，以上图9所示SPI控制逻辑单元SPI控制器、SPI数据收发切换单元或SPI数据端口中的部分或全部组件的功能可由集成电路或逻辑电路实现。
应理解，以上图1仅通过示例的方式示出了包含一个主SPI装置以及两个从SPI装置的数据传输系统，本申请并不限制在包含更多从SPI装置的数据传输系统中得到应用。例如，该数据传输系统可包括至少一个主SPI装置和两个或两个以上的从SPI装置(包括从SPI装置A以及从SPI装置B或包括从SPI装置A以及从SPI装置B以及更多的从SPI装置)，主SPI装置至少输出两个SPI片选信号，其中片选信号CS1同时连接全部的从SPI装置，另外一个片选信号CS2只连接其中一个从SPI装置B，当CS1＝0&CS＝1时，可实现主SPI装置选通1个从SPI装置A并对该从SPI装置A进行数据读写操作，以及实现从SPI装置B工作在数据侦听模式。当CS1＝1&CS＝0时，可实现SPI主设备对SPI从设备B进行读写操作。
基于相同的构思，本申请还提供一种芯片，该芯片可具备以上第一从SPI装置102的功能。换句话说，可将该如图1所示第一从SPI装置替换为该芯片。
示例性的，该芯片可具有如图9所示结构。如图9所示，该芯片可包括SPI控制器、SPI控制逻辑单元(或称SPI控制逻辑电路)、SPI数据收发切换单元(或称SPI数据收发切换电路)以及SPI数据端口(或称数据端口)等组件。
其中，SPI控制逻辑单元可用于从主SPI装置接收第一片选信号以及第二片选信号，所述第一片选信号以及所述第二片选信号的组合用于使能所述芯片。SPI数据端口可通过数据线与所述主SPI装置以及第二从SPI装置连接。所述SPI控制逻辑单元可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中所述第二从SPI装置发送的数据。
可选地，所述SPI数据端口可包括发送端口以及接收端口，所述发送端口通过数据线与所述主SPI装置的接收端口连接，以及所述接收端口通过数据线与所述主SPI装置的发送端口连接，所述发送端口用于所述芯片向所述数据线发送数据，所述接收端口用于所述芯片接收所述数据线中传输的数据。所述SPI控制逻辑单元还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，将所述发送 端口配置为用于接收所述数据线中传输的数据。
所述芯片还可包括SPI数据收发切换单元，所述SPI控制器可包括发送模块以及接收模块，所述发送模块用于数据的发送，所述接收模块用于数据的接收。所述SPI控制逻辑单元还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制SPI数据收发切换单元将所述发送端口连接至所述接收模块。
所述SPI控制逻辑单元还可用于，将所述SPI数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
所述SPI控制逻辑单元还可用于，当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器不响应于所述数据线传输的第一指示进行数据的发送，所述第一指示用于控制数据的发送。
所述SPI控制逻辑单元还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中传输的数据。所述SPI控制器还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，接收所述数据线中传输的第二指示，所述第二指示用于控制数据的接收，并响应于所述第二指示通过所述SPI数据端口接收所述数据线中传输的数据。
所述SPI控制逻辑单元还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中传输的数据。所述SPI控制器还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，接收所述数据线中传输的第一指示，所述第一指示用于控制数据的发送；响应于所述第一指示通过所述SPI数据端口向所述数据线发送数据。
所述SPI控制逻辑单元还可用于，当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器不通过所述数据线发送数据，以及控制所述SPI控制器不通过所述数据线接收数据。
基于相同的构思，本申请还提供一种摄像头模组。摄像头模组可包括以上所述的芯片，或包括以上所述的第一从SPI装置102。示例性的，第一从SPI装置102为摄像头模组中的马达驱动IC，或作为摄像头模组中的马达驱动IC的组件。示例性的，该摄像头模组可支持抖动补偿。
该摄像头模组还可包括马达以及摄像头。当第二从SPI装置包括陀螺仪传感器时，所述马达可用于从所述芯片获取陀螺仪传感器的数据，根据陀螺仪传感器的数据对所述摄像头执行抖动控制和/或自动对焦。
当该摄像头模组(以下称摄像头模组1)作为第一从SPI装置102、另一摄像头模组(以下称摄像头模组2)作为主SPI装置101以及陀螺仪传感器作为第二从SPI装置103时，该摄像头模组1可在主SPI装置驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，通过数据线从陀螺仪传感器接收陀螺仪信息，此时，摄像头模组2也可通过数据线从陀螺仪传感器接收陀螺仪信息，而不再需要按照现有技术，先由摄像头模组2从陀螺仪传感器接收陀螺仪数据，再由摄像头模组2将陀螺仪数据发送至摄像头模组1。因此，本申请实施例可提高摄像头模组1以及提高摄像头模组2接收陀螺仪信息的效率，提高摄像头模组的抖动补偿效果。
示例性的，上例中，主SPI装置101可作为摄像头模组2的马达驱动IC，或作为摄像头模组2的马达驱动IC的组件。
基于相同的构思，本申请还提供一种终端设备。该终端设备可以是智能手机、可移动智能设备、职能家居设备或者平板电脑等等，也可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置该终端设备。
示例性的，该终端设备可包括以上所述的数据传输系统。或者，该终端设备可包括以上所述的芯片。
或者，该终端设备可包括以上所述的摄像头模组，此时，该终端设备可以是可拍照设备，该可拍照设备可通过该摄像头模组进行拍摄，并实现拍摄过程中的抖动补偿和自动对焦。该终端设备还可包括图像处理芯片，用于从所述摄像头模组获取图像信号，并对所述图像信号进行处理。
基于相同的构思，本申请还提供另一种数据传输系统，如图10所示，该数据传输系统1000可包括第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003，其中，第一摄像头模组1001作为主SPI装置，第二摄像头模组1002以及第一传感器1003作为从SPI装置。以上第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间通过SPI协议进行通信。当第一摄像头和第二摄像头同时运行时，第一摄像头通过SPI协议获取第一传感器数据，且第二摄像头通过SPI协议同时获取第一传感器数据，以提高SPI系统中多个摄像头获取传感器数据的效率。
应理解，该数据传输系统1000，可应用于具备SPI结构的终端设备或其他电子设备中，例如，可应用于移动终端或计算机等设备中。示例性，本申请实施例提供的数据传输系统1000的一种可能的应用场景为包含多个摄像头模组的可拍照设备，该可拍照设备可以是具备拍照功能的智能手机、可移动智能设备、职能家居设备或者平板电脑等等，也可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置。
该场景下，第一摄像头模组1001可包括可拍照设备的多个摄像头模组中的一个摄像头模组或摄像头，第二摄像头模组1002可包括可拍照设备的其他的一个摄像头模组或摄像头，第一传感器1003可包括该可拍照设备的陀螺仪传感器。其中，陀螺仪传感器可部署于可拍照设备的主板。示例性的，第一摄像头模组1001以及第二摄像头模组1002可分别包含至少一个马达驱动芯片，或称马达驱动集成电路(integrated circuit，IC)。马达驱动IC可用于输出电流或脉宽调制(pulse width modulation，PWM)信号以控制摄像头模组的马达按照要求进行移动操作，实现抖动补偿。
下面对数据传输系统1000各个组件的连接方式和工作方式进行说明。应理解，以下说明中，也可将第一摄像头模组1001替换为第一摄像头，将第二摄像头模组1002替换为第二摄像头。
数据传输系统1000中，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003通过数据线连接，比如，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003三者中，任意两者之间通过数据线连接，或者，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003三者通过相同的数据线连接。示例性的，若第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003通过三线模式连接，则数据线可包括SDA。或者，若第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003通过四线模式连接，则数据线可包括SDO以及SDI。
另外，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003还通过时钟线连接。
如图10所示，第一摄像头模组1001将第一片选信号(CS1)输出至第二摄像头模组1002以及将第二片选信号(CS2)输出至第二摄像头模组1002。从而第一摄像头模组1001可通过第一片选信号的有效状态或非有效状态以及第二片选信号的有效状态或非有效状态的组合，令第二摄像头模组1002处于多种工作模式中的一种工作模式。
多种工作模式可以包括：数据侦听模式、标准从SPI装置模式以及未选通模式。其中，
数据侦听模式下，第二摄像头模组1002可通过数据线接收第一传感器1003发送给第一摄像头模组1001的数据，和/或，接收第一摄像头模组1001发送给第一传感器1003的数据。并且，数据侦听模式下，第二摄像头模组1002不通过数据线发送数据，因此即便第二摄像头模组1002接收来自于第一摄像头模组1001的写指示位，也不会响应于写指示位进行数据的发送。
标准从SPI装置模式下，第二摄像头模组1002可根据来自于第一摄像头模组1001的写指示位通过数据线发送数据，和/或，根据自于第一摄像头模组1001的读指示位通过数据线接收数据。因此，当第二摄像头模组1002接收来自于第一摄像头模组1001的写指示位时，会响应于写指示位进行数据的发送；或者，当第二摄像头模组1002接收来自于第一摄像头模组1001的读指示位时，会响应于读指示位进行数据的接收。
示例性的，数据侦听模式可对应于第一片选信号和第二片选信号的一种预设的状态组合。比如，当第一片选信号为有效状态且第二片选信号为非有效状态时，第二摄像头模组1002处于数据侦听模式。
标准从SPI装置模式可对应于第一片选信号和第二片选信号的另一种预设的状态组合。比如，当第一片选信号为非有效状态且第二片选信号为有效状态时，第二摄像头模组1002处于标准从SPI装置模式。
未选通模式可对应于第一片选信号和第二片选信号的另一种预设的状态组合。比如，当第一片选信号为非有效状态且第二片选信号为非有效状态时，第二摄像头模组1002处于未选通模式。
应理解，以上多个工作模式与第一片选信号和第二片选信号的状态组合之间的对应关系仅仅是举例说明，工作模式与片选信号状态组合之间的对应关系可以根据应用需要灵活调整。比如，也可采用以下配置：当第一片选信号为有效状态且第二片选信号为有效状态时，第二摄像头模组1002处于数据侦听模式。此外，也可由主SPI装置即第一摄像头模组1001配置第二摄像头模组1002的多个工作模式与第一片选信号和第二片选信号的状态组合之间的对应关系。
示例性的，第二摄像头模组1002的双片选逻辑判断结果可由图2表示。其中，双片选逻辑判断结果即为第二摄像头模组1002所处的工作模式。图2中，CS1＝0表示第一片选信号处于有效状态，CS2＝0表示第二片选信号处于有效状态，CS1＝1表示第一片选信号处于非有效状态，CS2＝1表示第二片选信号处于非有效状态。“a&b”表示“a与b”。
根据图2，当CS1＝0&CS2＝1时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合)时，双片选逻辑判断结果为数据侦听模式，第二摄像头模组1002可根据该判断结果进入该数据侦听模式(或称，第二摄像头模组1002处于数据侦听模式)。数据侦听模式下，第二摄像头模组1002可通过数据 线进行数据的接收，而不通过数据线进行数据的发送。换句话说，数据侦听模式下，无论第一摄像头模组1001输出写指示位还是读指示位，第二摄像头模组1002都只侦听数据线，并对数据线传输的数据进行接收。
当CS1＝1&CS2＝0时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的标准从SPI装置模式对应的状态组合)时，双片选逻辑判断结果为标准从SPI装置模式(或称标准slave模式)，第二摄像头模组1002可根据该判断结果进入该标准从SPI装置模式(或称，第二摄像头模组1002处于标准从SPI装置模式)。标准slave模式下，第二摄像头模组1002可根据第一摄像头模组1001输出的读指示位通过数据线进行数据的接收，也可根据第一摄像头模组1001输出的写指示位通过数据线进行数据的发送。
另外，当CS1＝1&CS2＝1时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的未选通模式对应的状态组合)时，双片选逻辑判断结果为未选通模式，第二摄像头模组1002可根据该判断结果进入该未选通模式(或称，第二摄像头模组1002处于未选通模式)。未选通模式下，第二摄像头模组1002不通过数据线进行数据的接收，也不通过数据线进行数据的发送。换句话说，未选通模式下，无论第一摄像头模组1001输出写指示位还是读指示位，第二摄像头模组1002都不对第一摄像头模组1001的指示进行响应。
以图3为例，对数据侦听模式下第二摄像头模组1002的总线访问模式进行说明。如图3所示，当CS1＝0&CS2＝1时，无论第一摄像头模组1001将SCK开始后的第一位数据位(即读写指示位)置为0(表示写)，还是1(表示读)，第二摄像头模组1002由于处于数据侦听模式而只支持数据输入，不会往数据线(包括三线模式的SDA或四线模式的SDO)上输出数据。
具体来说，对于三线模式，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间的连接关系如图11所示。可见，第一摄像头模组1001第二摄像头模组1002以及第一传感器1003各自的数据端口(数据端口与SDA连接)均支持双向数据传输。示例性的，当处于三线模式时，第二摄像头模组1002可将其数据端口配置为双向端口。
如图11所示，三线模式下，当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若第一摄像头模组1001通过SDA发送写指示位，第一传感器1003在通过SDA接收写指示位后，可响应于写指示位通过SDA发送数据，第一摄像头模组1001可通过SDA接收第一传感器1003发送的数据，第二摄像头模组1002处于数据侦听模式，因此第二摄像头模组1002第二摄像头模组1002可通过SDA接收第一传感器1003发送的数据。另外，第二摄像头模组1002不响应于SDA传输的写指示位在SDA上进行数据的发送(或称，第二摄像头模组1002忽略响应于写指示位进行数据的发送)，以避免造成SDA上的数据冲突。
应理解，在本申请中的表述“SPI装置通过SDA/SDO发送数据”，是指SPI装置通过与SDO连接的发送端口将数据发送至SDA/SDO，并由SDA/SDO将数据向其他SPI装置发送。还应理解，在本申请中的表述“SPI装置通过SDA/SDI接收数据”，是指SPI装置通过与SDA/SDI连接的接收端口，从SDA/SDI接收其他SPI装置通过其他SPI装置的SDA/SDO发送的数据。
另外，根据图11，三线模式下，当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若第一摄像头模组1001通过SDA发送读指示位， 第一摄像头模组1001还可通过SDA发送数据，此时第一传感器1003可响应于读指示位，通过SDA接收第一摄像头模组1001发送的数据，以及，第二摄像头模组1002处于数据侦听模式，因此第二摄像头模组1002可通过SDA接收第一摄像头模组1001发送的数据。从而多个从SPI装置可同时接收主SPI装置发送的数据，因此提高多个从SPI装置从主SPI装置接收数据时的效率。
对于四线模式，当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间的连接关系如图12所示。可见，第一摄像头模组1001、第二摄像头模组1002以及第二从SPI装置10可通过各自的发送端口(发送端口与SDO连接)进行数据的发送，以及，可通过各自的接收端口(接收端口与SDI连接)进行数据的接收。
如图12所示，四线模式下，当第一摄像头模组1001通过SDO发送写指示位时，第一传感器1003可响应于写指示位通过SDO发送数据，第一摄像头模组1001可通过SDI接收第一传感器1003通过SDO发送的数据，以及，第二摄像头模组1002处于数据侦听模式，因此第二摄像头模组1002可通过SDI接收第一传感器1003通过SDO发送的数据。另外，第二摄像头模组1002的SDO不会接收第一摄像头模组1001通过SDO发送的写指示位，因此，第二摄像头模组1002不响应于第一摄像头模组1001发送的写指示位进行数据的发送(或称，第二摄像头模组1002忽略响应于写指示位进行数据的发送)，以避免造成数据传输的冲突。
另外，如图12所示，对于四线模式，当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若第一摄像头模组1001通过SDO发送读指示位，并通过SDO发送数据，此时第一传感器1003可响应于读指示位通过SDI接收数据。
下面，以图6以及图7为例对标准从SPI装置模式下第二摄像头模组1002的总线访问模式进行说明。如图6所示，标准从SPI装置模式下，第二摄像头模组1002工作在标准从SPI装置模式，若第一摄像头模组1001将SCK开始后的第一位数据位置为0，第二摄像头模组1002可在第一摄像头模组1001的控制下读取数据线(SDA或SDI)上传输的数据。如图7所示，标准从SPI装置模式下，若第一摄像头模组1001将SCK开始后的第一位数据位置为1，第二摄像头模组1002可在第一摄像头模组1001的控制下，通过数据线(SDA或SDO)发送数据。从而在处于标准从SPI装置模式时，第二摄像头模组1002可以在第一摄像头模组1001的控制下实现第二摄像头模组1002与第一摄像头模组1001之间的数据传输。
具体来说，对于三线模式，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间的连接关系如图11所示。当第一摄像头模组1001驱动第一片选信号为非有效状态且驱动第二片选信号为有效状态时，若第一摄像头模组1001通过SDA发送写指示位，此时第二摄像头模组1002处于标准slave模式，第一传感器1003在通过SDA接收写指示位后，可响应于该写指示位通过SDA发送数据，第一摄像头模组1001可通过SDA接收第二摄像头模组1002发送的数据。此时第一传感器1003处于未选通状态，不对SDA传输的写指示位进行响应。
另外，对于三线模式，当第一摄像头模组1001驱动第一片选信号为非有效状态且驱动第二片选信号为有效状态时，若第一摄像头模组1001通过SDA发送读指示位并通过SDA传输数据，此时第二摄像头模组1002处于标准slave模式，第二摄像头模组1002可 响应于SDA传输的读指示位通过SDA接收数据。以及，此时第一传感器1003处于未选通状态，不对SDA传输的读指示位进行响应。
对于四线模式，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间的连接关系如图13所示。当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若第一摄像头模组1001通过SDO发送写指示位，此时第二摄像头模组1002处于标准slave模式，第二摄像头模组1002可通过SDI接收写指示位，并响应于写指示位通过SDO发送数据，第一摄像头模组1001可通过SDI接收第二摄像头模组1002通过SDO发送的数据。以及，此时第一传感器1003处于未选通状态，不对第一摄像头模组1001通过SDO发送的写指示位进行响应。
另外，如图13所示，当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，若第一摄像头模组1001通过SDO发送读指示位以及通过SDO发送数据，此时第二摄像头模组1002处于标准slave模式，第二摄像头模组1002可通过SDI接收读指示位，并响应于读指示位通过SDI读取数据。以及，此时第一传感器1003处于未选通状态，不对第一摄像头模组1001通过SDO发送的读指示位进行响应。
应理解，未选通模式下，对于三线模式，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间的连接关系如图11所示。另外，未选通模式下，对于四线模式，第一摄像头模组1001、第二摄像头模组1002以及第一传感器1003之间的连接关系如图13所示。
可选地，以上双片选逻辑判断结果可由表1表示。
根据图2或表1所示，当第一片选信号的状态为有效状态、第二片选信号的状态为非有效状态时，可令第二摄像头模组1002进入数据侦听模式。当第一片选信号的状态为非有效状态、第二片选信号的状态为有效状态时，可令第二摄像头模组1002进入标准从SPI装置模式。当第一片选信号的状态为非有效状态、第二片选信号的状态为非有效状态时，可令第二摄像头模组1002进入未选通模式。
此外，第一摄像头模组1001还可将第一片选信号以及第二片选信号输出至第一传感器1003，从而可通过第一片选信号以及第二片选信号控制是否使能第一传感器1003。从而第一摄像头模组1001可通过第一片选信号的有效状态或非有效状态以及第二片选信号的有效状态或非有效状态的组合，令第一传感器1003处于多种工作模式。例如，第一传感器1003的多种工作模式可包括数据侦听模式、标准从SPI装置模式和未选通模式。或者，第一传感器1003的多种工作模式可包括标准从SPI装置模式和未选通模式。
示例性的，当第二摄像头模组1002处于侦听模式时，第一传感器1003处于标准从SPI装置模式或未选通模式，和/或，当第一传感器1003处于侦听模式时，第二摄像头模组1002处于标准从SPI装置模式或未选通模式。第一传感器1003的工作模式可参照本申请中对于第二摄像头模组1002的工作模式的说明。
结合以上对于第二摄像头模组1002的工作模式以及第一传感器1003的工作模式的说明，当第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，第一摄像头模组1001可控制第一传感器1003通过数据线发送数据，并通过数据线接收第一传感器1003发送的数据。此时，由于第二摄像头模组1002处于数据侦听模式，第二摄像头模组1002可通过数据线接收数据。从而在第一摄像头模组1001驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，第一摄像头模组1001以及第一从 SPI装置可同时接收第一传感器1003发送的数据，提高了主SPI装置以及多个从SPI装置之间的数据传输效率。
当第一摄像头模组1001包括可拍照设备的多个摄像头模组中的一个摄像头模组，第二摄像头模组1002包括可拍照设备的其他的一个摄像头模组，以及第一传感器1003包括可拍照设备的陀螺仪传感器时，包括第一摄像头模组1001以及第二摄像头模组1002在内的多个摄像头模组可同时接收陀螺仪传感器发送的陀螺仪信息(或称陀螺仪传感器的数据)。这里的陀螺仪信息可包括陀螺仪的X/Y/Z三轴角速度信息等数据，支持光学防抖的摄像头模组可根据陀螺仪的X/Y/Z三轴角速度信息计算出拍照时人手的抖动，并通过马达(如集成于摄像头模组内部的马达)控制镜头实现抖动补偿。采用以上数据传输方法，可提高了多个摄像头模组接收陀螺仪信息的效率，从而优化光学防抖效果。
另外，第一摄像头模组1001应避免同时驱动第一片选信号为有效状态以及驱动第二片选信号为有效状态。若第一摄像头模组1001错误驱动第一片选信号以及第二片选信号同时处于有效状态，则第二摄像头模组1002可判断驱动状态错误，不响应总线操作。
在一种可能的示例中，第二摄像头模组1002可对其数据端口进行切换，从而在不改变芯片之间连接线路的条件下以实现如图12及如图13所示的连接关系之间的切换。其中，数据端口的切换，包括但不限于将数据端口从单向数据端口切换至双向数据端口，或者，将发送端口切换为接收端口，或者，将接收端口切换为发送端口等等。
当CS1＝0&CS2＝1时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合)时，若第二摄像头模组1002的发送端口与第一摄像头模组1001的接收端口通过第一数据线相连(或者说，第二摄像头模组1002的发送端口与第一摄像头模组1001的接收端口以及第一传感器1003的发送端口通过第一数据线连接)，以及第二摄像头模组1002的接收端口与第一摄像头模组1001的发送端口通过第二数据线相连(或者说，第二摄像头模组1002的接收端口与第一摄像头模组1001的发送端口以及第一传感器1003的接收端口通过第二数据线连接)，则第二摄像头模组1002可响应于CS1以及CS2，将第二摄像头模组1002的发送端口切换为接收端口(换句话说，第二摄像头模组1002将第二摄像头模组1002的SDO切换为SDI)，以及将第二摄像头模组1002的接收端口切换为发送端口(换句话说，第二摄像头模组1002将第二摄像头模组1002的SDI切换为SDO)，得到如图12所示的连接关系。此时，第二摄像头模组1002的接收端口与第一摄像头模组1001的接收端口相连，以及第二摄像头模组1002的发送端口与第一摄像头模组1001的发送端口相连。
另外，当CS1≠0或CS2≠1时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合以外的任意组合)时，若第二摄像头模组1002的接收端口与第一摄像头模组1001的接收端口相连，以及第二摄像头模组1002的发送端口与第一摄像头模组1001的发送端口相连，则第二摄像头模组1002可响应于CS1以及CS2，将第二摄像头模组1002的接收端口切换为发送端口(换句话说，第二摄像头模组1002将第二摄像头模组1002的SDI切换为SDO)，以及将第二摄像头模组1002的发送端口切换为接收端口(换句话说，第二摄像头模组1002将第二摄像头模组1002的SDO切换为SDI)，从而得到如图13所示的连接关系。
下面结合图9，说明第二摄像头模组1002进行数据端口切换的方式。应理解，第二摄像头模组1002可包括电路、摄像头以及马达等组件。其中，电路可用于根据片选信号通 过SPI协议进行数据的接收和/或发送。摄像头可用于采集图像或视频。马达可用于对摄像头进行抖动控制和/或自动对焦。
如图9所示，该电路可包括SPI控制器、SPI控制逻辑单元(或称SPI控制逻辑电路)、SPI数据收发切换单元(或称SPI数据收发切换电路)以及SPI数据端口(或称数据端口)等组件。
示例性的，SPI控制器可用于在第一摄像头模组1001通过SPI协议获取第一传感器数据时，控制SPI数据端口获取第一传感器数据。其中，SPI数据端口用于第二摄像头模组1002进行与第一摄像头模组1001和/或第一传感器1003之间的SPI协议通信，第一摄像头模组1001为主SPI设备，第二摄像头模组1002和第一传感器1003为从SPI设备。
具体来说，SPI控制器可用于处理需要发送的数据，或用于处理通过数据线接收的数据。例如，SPI控制器可包括发送模块及接收模块，发送模块可用于处理并向发送端口发送需要发送的数据，接收模块可用于接收并处理来自接收端口的数据。SPI控制器还可根据第二摄像头模组1002所处的工作模式控制数据的接收和/或发送。比如，当第二摄像头模组1002处于数据侦听模式，SPI控制器可控制SPI数据端口不向发送端口传输需要发送的数据。又比如，当第二摄像头模组1002处于未选通模式，SPI控制器可控制SPI数据端口不向数据线发送需要发送的数据，以及控制SPI数据端口不通过接收模块处理来自接收数据线的数据。
SPI控制逻辑单元可接收第一片选信号以及第二片选信号，并根据第一片选信号以及第二片选信号进行双片选判断逻辑结果判断，其判断结果可如图2或表1所示。SPI控制逻辑单元还可用于向SPI控制器输出该逻辑判断结果，以指示第二摄像头模组1002所处的工作模式。SPI控制逻辑单元还可用于根据该逻辑判断结果配置SPI数据端口的传输方向。SPI控制逻辑单元还可用控制SPI数据收发切换单元连通SPI数据端口与SPI控制器中的发送模块和/或接收模块。
SPI数据收发切换单元可用于根据SPI控制逻辑单元的控制，连通SPI数据端口与SPI控制器中的发送模块，形成发送通路。发送通路可用于向SDO发送数据。SPI数据收发切换单元还可用于根据SPI控制逻辑单元的控制，连通SPI数据端口与SPI控制器中的接收模块，形成接收通路。接收通路可用于从SDI接收数据。
示例性的，该电路可包括至少一个SPI数据端口。当SPI数据端口数量为一个时，第二摄像头模组1002仅支持三线模式。当SPI数据端口数量为两个或两个以上时，第二摄像头模组1002可支持三线模式及四线模式。
以SPI数据端口包括SPI数据端口1以及SPI数据端口2为例，在进行端口切换时，对于三线模式，SPI控制逻辑单元可将SPI数据端口1(或数据端口2)切换为双向数据端口。具体的，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1(或数据端口2)的传输方向为双向传输，以及，通过配置接口2控制SPI数据端口1(或数据端口2)连通至SPI控制器的发送模块以及接收模块。
以SPI数据端口包括SPI数据端口1以及SPI数据端口2为例，在进行端口切换时，对于四线模式，当CS1＝0&CS2＝1时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合)时，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1以及数据端口2的传输方向。
示例性的，四线模式下，当CS1≠0或CS2≠1时，或者当CS1以及CS2为一种预设 的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合以外的任意组合)时，若SPI数据端口1的传输方向为发送方向，以及SPI数据端口2的传输方向为接收方向，即，SPI数据端口1为发送端口(此时与SPI数据端口1连通的数据线为SDO)，SPI数据端口2为接收端口(此时与SPI数据端口2连通的数据线为SDI)，则当CS1＝0&CS2＝1时，或者当CS1以及CS2为一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合)时，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1的传输方向为接收方向，以及通过配置接口1配置SPI数据端口2的传输方向为发送方向，即，SPI控制逻辑单元通过配置接口1配置SPI数据端口1为接收端口(此时与SPI数据端口1连通的数据线为SDI)，以及通过配置接口1配置SPI数据端口2为发送端口(此时与SPI数据端口2连通的数据线为SDO)。此外，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口1连接至SPI控制器的接收模块，以形成接收通路，以及，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口2连接至SPI控制器的发送模块，形成发送通路。至此完成发送端口以及接收端口的切换。
另外，四线模式下，当CS1以及CS2的状态从CS1＝0&CS2＝1变为CS1≠0或CS2≠1(例如，CS1＝1或CS2＝0)时，或者当CS1以及CS2由一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合)变为另一种预设的状态组合(如，第二摄像头模组1002的数据侦听模式对应的状态组合以外的任意组合)时，若SPI数据端口1的传输方向为接收方向，且SPI数据端口2的传输方向为发送方向，SPI控制逻辑单元可通过配置接口1配置SPI数据端口1的传输方向为发送方向(此时与SPI数据端口1连通的数据线为SDO)，以及通过配置接口1配置SPI数据端口2的传输方向为接收方向(此时与SPI数据端口2连通的数据线为SDI)。此外，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口1连接至SPI控制器的发送模块，以形成发送通路，以及，SPI控制逻辑单元还通过配置接口2控制SPI数据收发切换单元将SPI数据接口2连接至SPI控制器的接收模块，形成接收通路。至此完成发送端口以及接收端口的切换。
示例性的，以上图9所示SPI控制逻辑单元SPI控制器、SPI数据收发切换单元或SPI数据端口中的部分或全部组件的功能可由芯片、集成电路或逻辑电路实现。图9所示电路的各个组件可采用集成方式、分立方式或通过芯片或多个芯片组成的芯片系统实现。
基于相同的构思，本申请还提供一种电路，该电路可连接至第二摄像头，以实现以上第二摄像头模组1002所示的功能。
示例性的，该电路可具有如图9所示结构。如图9所示，该电路可包括SPI控制器、SPI控制逻辑单元(或称SPI控制逻辑电路)、SPI数据收发切换单元(或称SPI数据收发切换电路)以及SPI数据端口(或称数据端口)等组件。
其中，SPI控制器可用于在第一摄像头通过SPI协议获取第一传感器数据时，控制SPI数据端口获取第一传感器数据。其中，SPI数据端口用于第二摄像头进行与第一摄像头和/或第一传感器之间的SPI协议通信，第一摄像头为主SPI设备，第二摄像头和第一传感器为从SPI设备。
在一种可能的设计中，SPI数据端口可将获取的第一传感器数据发送至所述第二摄像头。
在一种可能的设计中，SPI数据端口通过数据线与第一摄像头以及第一传感器连接。
在一种可能的设计中，电路还包括SPI控制逻辑单元，用于从第一摄像头接收第一片选信号以及第二片选信号，第一片选信号以及第二片选信号的组合用于控制是否使能第二摄像头。当第一片选信号为有效状态且第二片选信号为非有效状态时，SPI控制逻辑电路可控制SPI控制器控制SPI数据端口接收数据线中第一传感器发送给第一摄像头的数据。
在一种可能的设计中，电路还包括SPI控制逻辑单元，用于从第一摄像头接收第一片选信号以及第二片选信号，第一片选信号以及第二片选信号的组合用于控制是否使能第二摄像头。当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑电路可控制SPI控制器控制SPI数据端口接收数据线中第一传感器发送给第一摄像头的数据。
在一种可能的设计中，SPI控制逻辑单元还可控制所述SPI控制器控制SPI数据端口接收所述数据线中所述第一摄像头发送给第一传感器的数据。
在一种可能的设计中，若第二摄像头的发送端口与第一摄像头的接收端口通过第一数据线相连，第二摄像头的接收端口与第一摄像头的发送端口通过第二数据线相连，数据线包括第一数据线以及所述第二数据线，第二摄像头的发送端口以及第一摄像头的发送端口用于数据的发送，第二摄像头的接收端口以及第一摄像头的接收端口用于数据的接收，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元还可将发送端口配置为用于接收数据线中传输的数据。
在一种可能的设计中，该电路还包括SPI数据收发切换电路，SPI控制器包括发送模块以及接收模块，发送模块用于数据的发送，接收模块用于数据的接收；当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元还可控制所述SPI数据收发切换电路将所述发送端口连接至所述接收模块。
在一种可能的设计中，SPI控制逻辑单元还可将所述SPI数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元还可控制所述SPI控制器不响应于所述数据线传输的第一指示进行数据的发送，所述第一指示用于控制数据的发送。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元可控制SPI控制器通过SPI数据端口接收数据线中传输的第二指示。SPI控制器可响应于该第二指示，控制SPI数据端口接收数据线中传输的数据，第二指示用于控制数据的接收。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元可控制SPI控制器通过SPI数据端口接收数据线中传输的第一指示。SPI控制器可响应于该第一指示，控制SPI数据端口向数据线发送数据，第一指示用于控制数据的发送。
在一种可能的设计中，当第一片选信号为非有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，SPI控制逻辑单元可控制SPI控制器不通过数据线发送数据，以及控制SPI控制器不通过数据线接收数据。
基于相同的构思，本申请还提供一种电路，该电路可连接至第一摄像头，以实现以上 第一摄像头模组1001所示的功能。
示例性的，该电路可具有如图14所示结构。如图14所示，该电路可包括控制单元(或者控制电路)以及SPI数据端口(或称数据端口)等组件。
SPI数据端口可用于第一摄像头模组1001通过SPI协议获取第一传感器数据。控制电路可用于控制第二摄像头模组1002通过SPI协议同时获取第一传感器数据，第一摄像头模组1001为主SPI设备，第二摄像头模组1002和第一传感器1003为从SPI设备。第一传感器数据来自于该第一传感器1003。
在一种可能的设计中，SPI数据端口通过数据线与第二摄像头模组1002以及第一传感器1003连接。
在一种可能的设计中，控制电路可将第一片选信号输出至第二摄像头模组1002和第一传感器1003，以及将第二片选信号输出至第二摄像头模组1002和第一传感器1003，第一片选信号以及第二片选信号的状态组合用于控制是否使能第二摄像头模组1002以及用于控制是否使能第一传感器1003。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，控制电路可控制第一传感器1003通过所述数据线发送数据，并控制SPI数据端口通过所述数据线接收所述第一传感器1003发送的数据，以及控制第二摄像头模组1002通过数据线接收第一传感器1003发送给第一摄像头模组1001的数据。
在一种可能的设计中，当第一片选信号以及第二片选信号为预设的状态组合(如，第二摄像头模组1002模组102的数据侦听模式对应的状态组合)时，控制电路可控制第一传感器1003通过所述数据线发送数据，并控制SPI数据端口通过所述数据线接收所述第一传感器1003发送的数据，以及控制第二摄像头模组1002通过数据线接收第一传感器1003发送给第一摄像头模组1001的数据。
在一种可能的设计中，控制电路还可控制SPI数据端口通过数据线向第一传感器1003发送数据，并控制第二摄像头模组1002通过数据线接收第一摄像头模组1001发送给第一传感器1003的数据。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，控制电路可控制SPI数据端口通过数据线发送第一指示，第一指示用于控制数据的发送。
在一种可能的设计中，当第一片选信号为有效状态且第二片选信号为非有效状态时，或者，当第一片选信号以及第二片选信号为预设的状态组合时，控制电路可控制SPI数据端口通过数据线发送第一指示，第一指示用于控制数据的发送。
基于相同的构思，本申请还提供一种摄像头模组。摄像头模组可包括以上第一摄像头模组1001或第二摄像头模组1002。
示例性的，第一摄像头模组1001可包括图14所示电路、马达以及第一摄像头。图14所示电路具体可由马达驱动IC，或作为摄像头模组中的马达驱动IC的组件实现。
第二摄像头模组1002可包括图9所示电路、马达以及第二摄像头。图9所示电路具体可由马达驱动IC，或作为摄像头模组中的马达驱动IC的组件实现。
当第一传感器包括陀螺仪传感器时，第一摄像头模组1001以及第二摄像头模组1002中的马达可用于通过电路获取陀螺仪传感器的数据，并根据陀螺仪传感器的数据对所述摄像头执行抖动控制和/或自动对焦。
第一摄像头模组1001作为主SPI装置、第二摄像头模组1002以及陀螺仪传感器作为从SPI装置时，该第一摄像头模组1001可在驱动第一片选信号为有效状态且驱动第二片选信号为非有效状态时，通过数据线从陀螺仪传感器接收陀螺仪信息，此时，第二摄像头模组1002也可通过数据线接收陀螺仪信息，而不再需要按照现有技术，先由第一摄像头模组1001从陀螺仪传感器接收陀螺仪数据，再由第一摄像头模组1001将陀螺仪数据发送至第一摄像头模组102。因此，本申请实施例可提摄像头模组接收陀螺仪信息的效率，提高摄像头模组的抖动补偿效果。
基于相同的构思，本申请还提供一种终端设备。该终端设备可以是智能手机、可移动智能设备、职能家居设备或者平板电脑等等，也可以是便携式、袖珍式、手持式、计算机内置的或者车载的终端设备。
该终端设备可以是可拍照设备，该可拍照设备可通过第一摄像头模组和/或第二摄像头模组进行拍摄，并实现拍摄过程中的抖动补偿和自动对焦。该终端设备还可包括图像处理芯片，用于从所述摄像头模组获取图像信号，并对所述图像信号进行处理。
该终端设备可包括图9所示电路、图14所示电路、第一摄像头(或第一摄像头模组1001)、第二摄像头(或第二摄像头模组1002)中的部分或全部组件。该终端设备还可包括第一传感器，第一传感器包括陀螺仪传感器。
或者，该终端设备可包括第一摄像头模组、第二摄像头模组，以及用于输出陀螺仪信息的陀螺仪传感器。其中，该第一摄像头模组、该第二摄像头模组与该陀螺仪传感器通过串行外设接口SPI连接。该第一摄像头模组作为主SPI装置，该陀螺仪传感器以及该第二摄像头模组均作为从SPI装置，该第一摄像头模组与该第二摄像头模组在该第一摄像头模组发送的SPI片选信号的控制下，同时从所述陀螺仪传感器获得所述陀螺仪信息。该图像处理单元，用于从该第一摄像头模组以及该第二摄像头模组获取图像信号。
在一种可能的设计中，该第一摄像头模组与该第二摄像头模组均通过数据线与该陀螺仪传感器连接；该第一摄像头模组发送的SPI片选信号为预设的状态组合时，该第一摄像头模组与该第二摄像头模组同时从该陀螺仪传感器获得该陀螺仪信息。
在一种可能的设计中，该第一摄像头模组与该第二摄像头模组均通过数据线与该陀螺仪传感器连接；该第一摄像头模组发送的SPI片选信号使能该第二摄像头模块以及该陀螺仪传感器时，该第一摄像头模组与该第二摄像头模组同时从该陀螺仪传感器获得该陀螺仪信息。
在一种可能的设计中，该第二摄像头模组与该陀螺仪传感器同时从该第一摄像头模组接收数据。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (32)

  1. 一种数据传输系统，其特征在于，包括主SPI装置、第一从SPI装置以及第二从SPI装置；
    所述主SPI装置用于：
    将第一片选信号输出至第一从SPI装置和第二从SPI装置，以及将第二片选信号输出至所述第一从SPI装置，所述第一片选信号以及所述第二片选信号的组合用于使能所述第一从SPI装置，所述第一片选信号用于使能所述第二从SPI装置，所述主SPI装置、所述第一从SPI装置以及所述第二从SPI装置还通过数据线相连；
    所述主SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述第二从SPI装置通过所述数据线发送数据，以及通过所述数据线接收所述第二从SPI装置发送的数据；
    所述第二SPI装置用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，根据所述主SPI装置的控制通过所述数据线发送数据；
    所述第一从SPI装置用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，通过所述数据线接收所述第二从SPI装置发送的数据。
  2. 如权利要求1所述的数据传输系统，其特征在于，若所述第一从SPI装置的发送端口与所述主SPI装置的接收端口通过第一数据线相连，所述第一从SPI装置的接收端口与所述主SPI装置的发送端口通过第二数据线相连，所述数据线包括所述第一数据线以及所述第二数据线，所述第一从SPI装置的发送端口以及所述主SPI装置的发送端口用于数据的发送，所述第一从SPI装置的接收端口以及所述主SPI装置的接收端口用于数据的接收；
    所述第一从SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，将所述第一从SPI装置的发送端口切换为接收端口，以及，将所述第一从SPI装置的接收端口切换为发送端口。
  3. 如权利要求1所述的数据传输系统，其特征在于，所述第一从SPI装置还用于：
    将所述第一从SPI装置的数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
  4. 如权利要求1-3中任一所述的数据传输系统，其特征在于，所述主SPI装置具体用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，通过所述数据线发送第一指示，所述第一指示用于控制数据的发送；
    所述第一从SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，不响应于所述第一指示进行数据的发送。
  5. 如权利要求1-4中任一所述的数据传输系统，其特征在于，所述主SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有 效状态时，通过所述数据线发送第二指示以及数据，所述第二指示用于控制数据的接收；
    所述第一从SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，通过所述数据线接收所述第二指示，并响应于所述第二指示通过所述数据线接收数据。
  6. 如权利要求1-5中任一所述的数据传输系统，其特征在于，所述主SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，通过所述数据线发送第一指示以及通过所述数据线接收来自所述第一从SPI装置的数据，所述第一指示用于控制数据的发送；
    所述第一从SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，通过所述数据线接收所述第一指示，并响应于所述第一指示通过所述数据线发送数据。
  7. 如权利要求1-6中任一所述的数据传输系统，其特征在于，
    所述第一从SPI装置还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为非有效状态时，不通过所述数据线发送数据，以及不通过所述数据线接收数据。
  8. 一种芯片，其特征在于，所述芯片包括SPI控制逻辑电路、SPI控制器以及SPI数据端口：
    SPI控制逻辑电路用于从主SPI装置接收第一片选信号以及第二片选信号，所述第一片选信号以及所述第二片选信号的组合用于使能所述芯片；
    SPI数据端口通过数据线与所述主SPI装置以及第二从SPI装置连接；
    所述SPI控制逻辑电路用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中所述第二从SPI装置发送的数据。
  9. 如权利要求8所述的芯片，其特征在于，所述SPI数据端口包括发送端口以及接收端口，所述发送端口通过数据线与所述主SPI装置的接收端口连接，以及所述接收端口通过数据线与所述主SPI装置的发送端口连接，所述发送端口用于所述芯片向所述数据线发送数据，所述接收端口用于所述芯片接收所述数据线中传输的数据；
    所述SPI控制逻辑电路还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，将所述发送端口配置为用于接收所述数据线中传输的数据。
  10. 如权利要求9所述的芯片，其特征在于，所述芯片还包括SPI数据收发切换电路，所述SPI控制器包括发送模块以及接收模块，所述发送模块用于数据的发送，所述接收模块用于数据的接收；
    所述SPI控制逻辑电路还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制SPI数据收发切换电路将所述发送端口连接至所述接收模块。
  11. 如权利要求8所述的芯片，其特征在于，所述SPI控制逻辑电路还用于：
    将所述SPI数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
  12. 如权利要求8-11中任一所述的芯片，其特征在于，所述SPI控制逻辑电路还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器不响应于所述数据线传输的第一指示进行数据的发送，所述第一指示用于控制数据的发送。
  13. 如权利要求8-12中任一所述的芯片，其特征在于，所述SPI控制逻辑电路还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中传输的数据；
    所述SPI控制器还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，接收所述数据线中传输的第二指示，并响应于所述第二指示通过所述SPI数据端口接收所述数据线中传输的数据，所述第二指示用于控制数据的接收。
  14. 如权利要求8-13中任一所述的芯片，其特征在于，所述SPI控制逻辑电路还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为有效状态时，控制所述SPI控制器通过所述SPI数据端口接收所述数据线中传输的数据；
    所述SPI控制器还用于：
    当所述主SPI装置驱动所述第一片选信号为有效状态且驱动所述第二片选信号为非有效状态时，接收所述数据线中传输的第一指示，并响应于所述第一指示通过所述SPI数据端口向所述数据线发送数据，所述第一指示用于控制数据的发送。
  15. 如权利要求8-13中任一所述的芯片，其特征在于，所述SPI控制逻辑电路还用于：
    当所述主SPI装置驱动所述第一片选信号为非有效状态且驱动所述第二片选信号为非有效状态时，控制所述SPI控制器不通过所述数据线发送数据，以及控制所述SPI控制器不通过所述数据线接收数据。
  16. 一种摄像头模组，其特征在于，所述摄像头模组包括如权利要求8～15任一项所述的芯片；
    所述摄像头模组还包括马达以及摄像头；
    所述第二从SPI装置包括陀螺仪传感器；
    所述马达用于：
    从所述芯片获取陀螺仪传感器的数据，对所述摄像头执行抖动控制和/或自动对焦。
  17. 一种终端设备，其特征在于，所述终端设备包括如权利要求16所述的摄像头模组；
    所述终端设备还包括：
    图像处理芯片，用于从所述摄像头模组获取图像信号，并对所述图像信号进行处理。
  18. 一种摄像头系统，其特征在于，所述系统包括第一摄像头，第二摄像头和第一传感器，所述第一摄像头、所述第二摄像头和所述第一传感器之间通过SPI协议进行通信，所述第一摄像头为主SPI设备，所述第二摄像头和所述第一传感器为从SPI设备，其中，当所述第一摄像头和所述第二摄像头同时运行时，所述第一摄像头通过所述SPI协议获取第一传感器数据，且所述第二摄像头通过所述SPI协议同时获取所述第一传感器数据。
  19. 如权利要求18所述的摄像头系统，其特征在于，所述第一摄像头具体用于：
    将第一片选信号输出至所述第二摄像头和所述第一传感器，以及将第二片选信号输出至所述第二摄像头和所述第一传感器，所述第一片选信号以及所述第二片选信号的状态组合用于控制是否使能所述第二摄像头以及用于控制是否使能所述第一传感器，所述第一摄像头、所述第二摄像头和所述第一传感器还通过数据线相连；
    当所述第一片选信号为有效状态且所述第二片选信号为非有效状态时，控制所述第二摄像头通过所述数据线发送数据，以及通过所述数据线接收所述第二摄像头发送的数据；
    所述第一传感器具体用于：
    当所述第一片选信号为有效状态且所述第二片选信号为非有效状态时，根据所述第一摄像头的控制通过所述数据线发送数据；
    所述第二摄像头具体用于：
    当所述第一片选信号为有效状态且所述第二片选信号为非有效状态时，通过所述数据线接收所述第一传感器发送给所述第一摄像头的数据。
  20. 如权利要求18所述的摄像头系统，其特征在于，所述第一摄像头具体用于：
    将第一片选信号输出至所述第二摄像头和所述第一传感器，以及将第二片选信号输出至所述第二摄像头和所述第一传感器，所述第一片选信号以及所述第二片选信号的状态组合用于控制是否使能所述第二摄像头以及所述第一传感器，所述第一摄像头、所述第二摄像头和所述第一传感器还通过数据线相连；
    当所述第一片选信号以及所述第二片选信号为预设的状态组合时，控制所述第二摄像头通过所述数据线发送数据，以及通过所述数据线接收所述第二摄像头发送的数据；
    所述第一传感器具体用于：
    当所述第一片选信号以及所述第二片选信号为所述状态组合时，根据所述第一摄像头的控制通过所述数据线发送数据；
    所述第二摄像头具体用于：
    当所述第一片选信号以及所述第二片选信号为所述状态组合时，通过所述数据线接收所述第一传感器发送给所述第一摄像头的数据。
  21. 如权利要求19或20所述的摄像头系统，其特征在于，所述第一摄像头还用于：
    通过所述数据线向所述第二摄像头发送数据；
    所述第一传感器还用于：
    通过所述数据线接收所述第一摄像头发送的数据；
    所述第二摄像头还用于：
    通过所述数据线接收所述第一摄像头发送给所述第一传感器的数据。
  22. 如权利要求18-21中任一所述的摄像头系统，其特征在于，若所述第二摄像头的发送端口与所述第一摄像头的接收端口通过第一数据线相连，所述第二摄像头的接收端口与所述第一摄像头的发送端口通过第二数据线相连，所述数据线包括所述第一数据线以及所述第二数据线，所述第二摄像头的发送端口以及所述第一摄像头的发送端口用于数据的发送，所述第二摄像头的接收端口以及所述第一摄像头的接收端口用于数据的接收；
    所述第二摄像头还用于：
    当所述第一片选信号为有效状态且所述第二片选信号为非有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，将所述第二摄像头的发送端口切换为接收端口，以及，将所述第二摄像头的接收端口切换为发送端口。
  23. 如权利要求18-22中任一所述的摄像头系统，其特征在于，所述第二摄像头还用于：
    将所述第二摄像头的数据端口配置为双向数据端口，所述双向数据端口支持数据的接收及发送。
  24. 如权利要求18-23中任一所述的摄像头系统，其特征在于，所述第一摄像头具体用于：
    当所述第一片选信号为有效状态且所述第二片选信号为非有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，通过所述数据线发送第一指示，所述第一指示用于控制数据的发送；
    所述第二摄像头还用于：
    当所述第一片选信号为有效状态且所述第二片选信号为非有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，不响应于所述第一指示进行数据的发送。
  25. 如权利要求18-24中任一所述的摄像头系统，其特征在于，所述第一摄像头还用于：
    当所述第一片选信号为非有效状态且所述第二片选信号为有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，通过所述数据线发送第二指示以及数据，所述第二指示用于控制数据的接收；
    所述第二摄像头还用于：
    当所述第一片选信号为非有效状态且所述第二片选信号为有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，通过所述数据线接收所述第二指示，并响应于所述第二指示通过所述数据线接收数据。
  26. 如权利要求18-23或25中任一所述的摄像头系统，其特征在于，所述第一摄像头还用于：
    当所述第一片选信号为非有效状态且所述第二片选信号为有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，通过所述数据线发送第一指示以及通过所述数据线接收来自所述第二摄像头的数据，所述第一指示用于控制数据的发送；
    所述第二摄像头还用于：
    当所述第一片选信号为非有效状态且所述第二片选信号为有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，通过所述数据线接收所述第一指示，并响应于所述第一指示通过所述数据线发送数据。
  27. 如权利要求18-26中任一所述的摄像头系统，其特征在于，所述第二摄像头还用于：
    当所述第一片选信号为非有效状态且所述第二片选信号为非有效状态时，或者，当所述第一片选信号以及所述第二片选信号为预设的状态组合时，不通过所述数据线发送数据， 以及不通过所述数据线接收数据。
  28. 如权利要求18-27中任一所述的摄像头系统，其特征在于，所述第一传感器包括陀螺仪传感器。
  29. 一种终端设备，其特征在于，所述终端设备包括：第一摄像头模组、第二摄像头模组、用于输出陀螺仪信息的陀螺仪传感器，以及图像处理单元；所述第一摄像头模组、所述第二摄像头模组与所述陀螺仪传感器通过串行外设接口SPI连接，
    所述第一摄像头模组作为主master SPI装置，所述陀螺仪传感器以及所述第二摄像头模组均作为从slave SPI装置，所述第一摄像头模组与所述第二摄像头模组在所述第一摄像头模组发送的SPI片选信号的控制下，同时从所述陀螺仪传感器获得所述陀螺仪信息，
    所述图像处理单元，用于从所述第一摄像头模组以及所述第二摄像头模组获取图像信号。
  30. 如权利要求29所述的终端设备，其特征在于，所述第一摄像头模组与所述第二摄像头模组均通过数据线与所述陀螺仪传感器连接；所述第一摄像头模组发送的SPI片选信号为预设的状态组合时，所述第一摄像头模组与所述第二摄像头模组同时从所述陀螺仪传感器获得所述陀螺仪信息。
  31. 如权利要求29所述的终端设备，其特征在于，所述第一摄像头模组与第二摄像头模组均通过数据线与所述陀螺仪传感器连接；所述第一摄像头模组发送的SPI片选信号使能所述第二摄像头模组以及所述陀螺仪传感器时，所述第一摄像头模组与所述第二摄像头模组同时从所述陀螺仪传感器获得所述陀螺仪信息。
  32. 如权利要求30或31所述的终端设备，其特征在于，所述第二摄像头模组与所述陀螺仪传感器同时从所述第一摄像头模组接收数据。
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US11979695B2 (en) 2024-05-07
CN115174804A (zh) 2022-10-11
JP2023532689A (ja) 2023-07-31
CN112153278A (zh) 2020-12-29
CN115174804B (zh) 2024-02-20
US20230117027A1 (en) 2023-04-20

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