WO2022000699A1 - Oled显示面板及其制备方法 - Google Patents

Oled显示面板及其制备方法 Download PDF

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Publication number
WO2022000699A1
WO2022000699A1 PCT/CN2020/107032 CN2020107032W WO2022000699A1 WO 2022000699 A1 WO2022000699 A1 WO 2022000699A1 CN 2020107032 W CN2020107032 W CN 2020107032W WO 2022000699 A1 WO2022000699 A1 WO 2022000699A1
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layer
gate
display panel
source
away
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French (fr)
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周星宇
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/047,076 priority Critical patent/US11957004B2/en
Publication of WO2022000699A1 publication Critical patent/WO2022000699A1/zh
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
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    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
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    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the field of display technology, and in particular, to an OLED display panel and a preparation method thereof.
  • metal electrodes are usually arranged on the substrate to stabilize the back channel potential of the thin film transistor.
  • this layer and the metal oxide electrode of the film layer above the buffer layer together form a transparent capacitor, and the area where the transparent capacitor is located can also be used as a light-emitting area, so as to increase the aperture ratio.
  • the metal electrode and the indium tin oxide electrode with this structure require two processes to complete, and the manufacturing process is many, resulting in an increase in cost.
  • the existing OLED display panel with bottom emission structure has technical problems of many manufacturing processes, and needs to be improved.
  • Embodiments of the present application provide an OLED display panel and a manufacturing method thereof, so as to alleviate the technical problem of many manufacturing processes in the existing OLED display panel with bottom emission structure.
  • the present application provides an OLED display panel, including:
  • a transparent conductive layer formed on one side of the substrate, patterned to form a conductive electrode and a first plate of a transparent capacitor;
  • a buffer layer formed on the side of the transparent conductive layer away from the substrate;
  • a metal oxide semiconductor layer formed on the side of the buffer layer away from the transparent conductive layer, patterned to form the active layer of the thin film transistor and the second electrode plate of the transparent capacitor;
  • a gate insulating layer formed on the side of the active layer away from the buffer layer;
  • a gate layer formed on the side of the gate insulating layer away from the active layer, and patterned to form the gate of the thin film transistor
  • an interlayer insulating layer formed on the side of the gate layer away from the gate insulating layer;
  • a source and drain layer formed on the side of the interlayer insulating layer away from the gate layer, patterned to form the source and drain of the thin film transistor, the drain and the drain region of the active layer connection, the source electrode is connected to the source region of the active layer and the conductive electrode;
  • the OLED device layer is formed on the side of the source and drain layers away from the interlayer insulating layer, and the light-emitting direction of the OLED device layer faces the substrate.
  • the material of the transparent conductive layer includes at least one of indium tin oxide and indium zinc oxide.
  • the material of the metal oxide semiconductor layer includes at least one of indium gallium zinc oxide, indium tin zinc oxide and indium gallium zinc titanium oxide.
  • the projection of the active layer on the substrate is located within the projection range of the conductive electrode on the substrate.
  • the OLED device layer includes a pixel definition layer and a pixel electrode layer, the pixel definition layer defines a plurality of light-emitting regions, and the pixel electrode layer is located in the light-emitting region and is connected to the light-emitting regions.
  • the source electrode of the thin film transistor is connected, and both the first electrode plate and the second electrode plate of the transparent capacitor are arranged corresponding to the light emitting area.
  • the thickness of the transparent conductive layer is 200 to 2000 angstroms.
  • the thickness of the metal oxide semiconductor layer is 100 to 1000 angstroms.
  • the present application also provides a method for preparing an OLED display panel, comprising:
  • a transparent conductive layer and a buffer layer are sequentially prepared on one side of the substrate, and the transparent conductive layer is patterned to form a conductive electrode and a first electrode plate of a transparent capacitor;
  • a metal oxide semiconductor layer is prepared on the side of the buffer layer away from the transparent conductive layer, and patterned to form the active layer of the thin film transistor and the second electrode plate of the transparent capacitor;
  • a gate insulating layer, a gate layer and an interlayer insulating layer are sequentially prepared on the side of the active layer away from the buffer layer, and the gate layer is patterned to form the gate of the thin film transistor;
  • a source and drain layer is prepared on the side of the interlayer insulating layer away from the active layer, the source and drain layers are patterned to form the source and drain electrodes of the thin film transistor, and the drain electrode is connected to the active layer.
  • the drain region of the source layer is connected, and the source electrode is connected to the source region of the active layer and the conductive electrode;
  • An OLED device layer is prepared on the source and drain layers, and the light-emitting direction of the OLED device layer faces the substrate.
  • the step of sequentially preparing a transparent conductive layer and a buffer layer on one side of the substrate includes: preparing a transparent conductive layer on one side of the substrate, the transparent conductive layer
  • the layer material includes at least one of indium tin oxide and indium zinc oxide.
  • the step of preparing the metal oxide semiconductor layer on the side of the buffer layer away from the transparent conductive layer includes: the buffer layer is far away from the transparent conductive layer.
  • a metal oxide semiconductor layer is prepared on one side of the metal oxide semiconductor layer, and the material of the metal oxide semiconductor layer includes at least one of indium gallium zinc oxide, indium tin zinc oxide and indium gallium zinc titanium oxide.
  • a metal oxide semiconductor layer is prepared on the side of the buffer layer away from the transparent conductive layer, and patterned to form the active layer of the thin film transistor and the transparent capacitor.
  • the step of the second electrode plate includes: patterning the metal oxide semiconductor layer to form an active layer of a thin film transistor, and the projection of the active layer on the substrate is located on the conductive electrode on the substrate. within the projection range.
  • the step of preparing an OLED device layer on the source and drain layers includes: preparing pixels on a side of the source and drain layers away from the interlayer insulating layer A definition layer and a pixel electrode layer, the pixel definition layer defines a plurality of light-emitting regions, the pixel electrode layer is located in the light-emitting region, and is connected to the source of the thin film transistor, and the first electrode of the transparent capacitor Both the plate and the second polar plate are arranged corresponding to the light-emitting area.
  • the step of sequentially preparing the transparent conductive layer and the buffer layer on one side of the substrate includes: preparing a thickness of 200 to 2000 angstroms on the side of the substrate Transparent conductive layer.
  • the step of preparing the metal oxide semiconductor layer on the side of the buffer layer away from the transparent conductive layer includes: the buffer layer is far away from the transparent conductive layer.
  • a metal oxide semiconductor layer with a thickness of 100 to 1000 angstroms is prepared on one side.
  • the method further includes: preparing a package on a side of the OLED device layer away from the driving circuit layer Floor.
  • the gate insulating layer, the gate layer and the interlayer insulating layer are sequentially prepared on the side of the active layer away from the buffer layer, and the pattern of the gate layer is
  • the step of forming the gate of the thin film transistor includes:
  • a whole-layer interlayer insulating layer is formed on the side of the gate away from the gate insulating layer.
  • the step of sequentially preparing the gate insulating layer, the gate layer and the interlayer insulating layer on the side of the active layer away from the buffer layer includes: A gate insulating layer is prepared on the side of the active layer away from the buffer layer, and the thickness of the gate insulating layer is 1000 to 3000 angstroms.
  • the step of sequentially preparing the gate insulating layer, the gate layer and the interlayer insulating layer on the side of the active layer away from the buffer layer includes: A gate layer is prepared on the side of the gate insulating layer away from the active layer, and the gate layer material includes at least one of Mo, Al, Cu, Ti element or alloy.
  • the step of preparing the gate layer on the side of the gate insulating layer away from the active layer includes: preparing a gate with a thickness of 2000 to 8000 angstroms Floor.
  • the step of preparing the source and drain layers on the side of the interlayer insulating layer away from the active layer includes: preparing the source and drain layers, and the The material of the source and drain layers includes at least one of Mo, Al, Cu, Ti, or alloys.
  • the present application provides an OLED display panel and a preparation method thereof.
  • the OLED display panel includes a substrate, a transparent conductive layer, a buffer layer, a metal oxide semiconductor layer, a gate insulating layer, a gate layer, and an interlayer.
  • a transparent conductive layer is formed on one side of the substrate, patterned to form a conductive electrode and a first plate of a transparent capacitor;
  • a buffer layer is formed on the transparent conductive layer away from all one side of the substrate;
  • a metal oxide semiconductor layer is formed on the side of the buffer layer away from the transparent conductive layer, and patterned to form the active layer of the thin film transistor and the second plate of the transparent capacitor;
  • gate The polar insulating layer is formed on the side of the metal oxide semiconductor layer away from the buffer layer;
  • the gate layer is formed on the side of the gate insulating layer away from the metal oxide semiconductor layer, and the thin film is formed by patterning
  • the interlayer insulating layer is formed on the side of the gate layer away from the gate insulating layer;
  • the source and drain layers are formed on the side of the interlayer insulating layer away from the gate layer, and the pattern forming a source electrode and a drain electrode of the thin film transistor, the drain electrode
  • FIG. 1 is a schematic structural diagram of an OLED display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for fabricating an OLED display panel according to an embodiment of the present application.
  • Embodiments of the present application provide an OLED display panel and a manufacturing method thereof, so as to alleviate the technical problem of many manufacturing processes in the existing OLED display panel with bottom emission structure.
  • FIG. 1 it is a schematic structural diagram of an OLED display panel provided by the present application.
  • the OLED display panel includes a substrate 101, a transparent conductive layer, a buffer layer 103, a metal oxide semiconductor layer, a gate insulating layer 105, a gate layer, an interlayer insulating layer 107, a source and drain layer and an OLED device layer;
  • the transparent conductive layer is formed on one side of the substrate 101, and the conductive electrodes 1021 and the first plate 1022 of the transparent capacitor are formed by patterning;
  • the buffer layer 103 is formed on the side of the transparent conductive layer away from the substrate 101;
  • the metal oxide semiconductor layer is formed on the side of the buffer layer 103 away from the transparent conductive layer, and patterned to form the active layer 1041 of the thin film transistor and the second electrode plate 1042 of the transparent capacitor;
  • the gate insulating layer 105 is formed on the side of the active layer 1041 away from the buffer layer;
  • the gate layer is formed on the side of the gate insulating layer 105 away from the active layer 1041, and the gate 106 of the thin film transistor is formed by patterning;
  • the interlayer insulating layer 107 is formed on the side of the gate layer away from the gate insulating layer 105;
  • the source and drain layers are formed on the side of the interlayer insulating layer 107 away from the gate layer, patterned to form the source 108 and the drain 109 of the thin film transistor, the drain 109 is connected to the drain region of the active layer 1041, and the source 108 is connected to the The source region of the active layer 1041 is connected to the conductive electrode 1021;
  • the OLED device layer is formed on the side of the source and drain layers away from the interlayer insulating layer 107 , and the light-emitting direction of the OLED device layer faces the substrate 101 .
  • the substrate 101 may be a flexible substrate, and its material may include polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone. At least one; it can also be a rigid substrate, specifically a glass substrate or other rigid substrates. This embodiment of the present application does not limit the type and material of the substrate 101 .
  • the material of the transparent conductive layer includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO), the thickness is 200 to 2000A, and the pattern is made by photolithography to form the conductive electrode 1021 and the first transparent capacitor.
  • a polar plate 1022 is made by photolithography to form the conductive electrode 1021 and the first transparent capacitor.
  • the material of the buffer layer 103 is at least one of silicon nitride (SiN x ) and silicon oxide (SiO x ), and the thickness is 1000 to 5000A.
  • the material of the metal oxide semiconductor layer includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) and Indium Gallium Zinc Titanium Oxide (IGZTO), the thickness is 100 to 1000A, and is photoetched
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • IGZTO Indium Gallium Zinc Titanium Oxide
  • the active layer 1041 forming the thin film transistor and the second electrode plate 1042 of the transparent capacitor are not in contact with each other, and subsequently the two are independently connected to each other to perform corresponding work.
  • the projection of the active layer 1041 on the substrate 101 is located within the projection range of the conductive electrode 1021 on the substrate 101 .
  • the material of the gate insulating layer 105 is generally at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and may be a single-layer or multi-layer structure with a thickness of 1000 to 3000A.
  • the material of the gate layer can be Mo, Al, Cu, Ti or alloy, the thickness is 2000 to 8000A, and the gate 106 is formed by patterning.
  • the gate insulating layer 105 and the gate 106 are formed, the gate insulating layer 105 and the gate layer are firstly arranged on the entire surface, and then the gate 106 is etched with a yellow light, and then the gate 106 is used for self-alignment and etching.
  • the gate insulating layer 105 after the etching is completed, the gate insulating layer 105 only exists in the region covered by the gate electrode 106, and the gate insulating layer 105 in other regions is completely etched away.
  • the entire surface of the pre-process film layer is subjected to plasma treatment.
  • the composition of the part not covered by the gate electrode 106 and the gate insulating layer 105 is changed, and the resistance value is significantly reduced, forming the source and drain regions of the thin film transistor, which are covered by the gate electrode 106 and the gate electrode.
  • the part covered by the insulating layer 105 maintains the semiconductor properties and forms the channel region of the thin film transistor, and the resistance value of the second electrode plate 1042 of the transparent capacitor is also significantly reduced.
  • the material of the interlayer insulating layer 107 is usually at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and can be a single-layer or multi-layer structure with a thickness of 2000 to 10000A, and an interlayer insulation is formed on the entire surface
  • yellow light and etching are performed to form a first via hole, a second via hole and a third via hole, wherein the first via hole corresponds to the drain region of the active layer 1041, and the second via hole corresponds to the drain region of the active layer 1041.
  • the third via hole corresponds to the conductive electrode 1021 .
  • the material of the source and drain layers includes simple substances or alloys such as Mo, Al, Cu, Ti, etc., with a thickness of 2000 to 8000 A.
  • the whole layer is formed first and then the pattern is lithographically etched to form the source electrode 108 and the drain electrode 109, of which the drain electrode 109
  • the first via hole is connected to the drain region of the active layer 1041
  • the source electrode 108 is connected to the source region of the active layer 1041 via the second via hole
  • the OLED display panel further includes a passivation layer 110 disposed on the source and drain layers, a color resist layer 111 formed on the passivation layer 110, and a planarization layer 112 formed on the color resist layer 111.
  • the material is usually at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and can be a single-layer or multi-layer structure with a thickness of 1000 to 5000A, and the material of the planarization layer 112 is photoresist, with a thickness of 0.5 to 4um.
  • the OLED device layer is formed on the side of the source and drain layers away from the interlayer insulating layer 107, and the light-emitting direction faces the substrate 101, and specifically includes a pixel electrode layer, a pixel definition layer 113, and a light-emitting material layer disposed on the planarization layer 112. , common electrode and encapsulation layer.
  • the material of the pixel electrode layer includes a stack of ITO/Ag/ITO, patterned to form a plurality of pixel electrodes 114, a pixel definition layer 113 is arranged between adjacent pixel electrodes 114, and a light-emitting region is formed between adjacent pixel definition layers 113 , a light-emitting material layer (not shown in the figure) is formed in the light-emitting region, then a common electrode (not shown in the figure) is formed on the light-emitting material layer and the pixel definition layer 113 , and finally an encapsulation layer (not shown in the figure) is formed on the common electrode not shown).
  • the OLED display panel has a bottom emission structure.
  • the conductive electrode 1021 is connected to the source electrode 108, and the source electrode 108 is connected to the active layer 1041.
  • a fixed low-potential signal is given to the conductive electrode 1021, so that the conductive electrode 1021 can be a thin film transistor.
  • the back channel of the active layer 1021 provides a stable low potential, thereby making the back channel potential of the thin film transistor stable, outputting stable electrical properties, and better driving the OLED device to emit light.
  • Both the first electrode plate 1022 and the second electrode plate 1042 of the transparent capacitor are disposed corresponding to the light-emitting area, so the area where the transparent capacitor is located can allow light to pass through, and the aperture ratio is relatively high.
  • the conductive electrode 1021 is made of an opaque metal material
  • the first plate 1022 of the transparent capacitor is made of a transparent conductive material.
  • the two materials are different, so two processes are required to form them respectively.
  • both of them are formed by patterning a transparent conductive layer, and only one process is required, so a mask is saved, and the cost is reduced without affecting the performance of the device.
  • the present application also provides a method for preparing an OLED display panel, comprising the following steps:
  • 202 preparing a transparent conductive layer and a buffer layer in sequence on one side of the substrate, and patterning the transparent conductive layer to form a conductive electrode and a first polar plate of a transparent capacitor;
  • 203 preparing a metal oxide semiconductor layer on the side of the buffer layer away from the transparent conductive layer, and patterning to form the active layer of the thin film transistor and the second electrode plate of the transparent capacitor;
  • 205 Prepare a source and drain layer on the side of the interlayer insulating layer away from the active layer, the source and drain layers are patterned to form the source and drain of the thin film transistor, the drain is connected to the drain region of the active layer, and the source and The source region of the active layer is connected to the conductive electrode;
  • a substrate 101 is provided.
  • the substrate 101 may be a flexible substrate, and its material may include polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone. At least one; it can also be a rigid substrate, specifically a glass substrate or other rigid substrates. This embodiment of the present application does not limit the type and material of the substrate 101 .
  • a transparent conductive layer and a buffer layer 103 are sequentially prepared on one side of the substrate 101, and the transparent conductive layer is patterned to form a conductive electrode 1021 and a first electrode plate 1022 of a transparent capacitor.
  • the material of the transparent conductive layer includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO), the thickness is 200 to 2000A, and the pattern is made by photolithography to form the conductive electrode 1021 and the first transparent capacitor.
  • a polar plate 1022 is made by photolithography to form the conductive electrode 1021 and the first transparent capacitor.
  • a metal oxide semiconductor layer is formed on the side of the buffer layer 103 away from the transparent conductive layer, and patterned to form the active layer 1041 of the thin film transistor and the second electrode plate 1042 of the transparent capacitor.
  • the material of the metal oxide semiconductor layer includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO) and Indium Gallium Zinc Titanium Oxide (IGZTO), the thickness is 100 to 1000A, and is photoetched
  • IGZO Indium Gallium Zinc Oxide
  • ITZO Indium Tin Zinc Oxide
  • IGZTO Indium Gallium Zinc Titanium Oxide
  • the active layer 1041 forming the thin film transistor and the second electrode plate 1042 of the transparent capacitor are not in contact with each other, and subsequently the two are independently connected to each other to perform corresponding work.
  • the projection of the active layer 1041 on the substrate 101 is located within the projection range of the conductive electrode 1021 on the substrate 101 .
  • a gate insulating layer 105, a gate layer and an interlayer insulating layer 107 are sequentially prepared on the side of the active layer 1041 away from the buffer layer 103, and the gate layer is patterned to form the gate 106 of the thin film transistor.
  • the material of the gate insulating layer 105 is generally at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and may be a single-layer or multi-layer structure with a thickness of 1000 to 3000A.
  • the material of the gate layer can be Mo, Al, Cu, Ti or alloy, the thickness is 2000 to 8000A, and the gate 106 is formed by patterning.
  • the gate insulating layer 105 and the gate 106 are formed, the gate insulating layer 105 and the gate layer are firstly arranged on the whole surface, and then the gate 106 is etched with a cucumber, and then the gate 106 is used for self-alignment, and the gate is etched.
  • the gate insulating layer 105 is only formed in the region covered by the gate electrode 106, and the gate insulating layer 105 in other regions is completely etched away.
  • the entire surface of the pre-process film layer is subjected to plasma treatment.
  • the composition of the part not covered by the gate electrode 106 and the gate insulating layer 105 is changed, and the resistance value is significantly reduced, forming the source and drain regions of the thin film transistor, which are covered by the gate electrode 106 and the gate electrode.
  • the part covered by the insulating layer 105 maintains the semiconductor properties and forms the channel region of the thin film transistor, and the resistance value of the second electrode plate 1042 of the transparent capacitor is also significantly reduced.
  • the material of the interlayer insulating layer 107 is usually at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and can be a single-layer or multi-layer structure, with a thickness of 2000 to 10000A, and interlayer insulation is formed on the entire surface
  • yellow light and etching are performed to form a first via hole, a second via hole and a third via hole, wherein the first via hole corresponds to the drain region of the active layer 1041, and the second via hole corresponds to the drain region of the active layer 1041.
  • the third via hole corresponds to the conductive electrode 1021 .
  • a source and drain layer is prepared on the side of the interlayer insulating layer 107 away from the active layer 1041, the source and drain layers are patterned to form the source electrode 108 and the drain electrode 109 of the thin film transistor, the drain electrode 109 and the active layer 1041 The drain region of the active layer 108 is connected to the source region of the active layer 1042 and the conductive electrode 1021 is connected.
  • the material of the source and drain layers includes simple substances or alloys such as Mo, Al, Cu, Ti, etc., with a thickness of 2000 to 8000A.
  • the whole layer is formed first and then the pattern is photolithographically formed to form the source electrode 108 and the drain electrode 109, of which the drain electrode 109
  • the first via hole is connected to the drain region of the active layer 1041
  • the source electrode 108 is connected to the source region of the active layer 1041 via the second via hole
  • the OLED display panel further includes a passivation layer 110 disposed on the source and drain layers, a color resist layer 111 formed on the passivation layer 110, and a planarization layer 112 formed on the color resist layer 111.
  • the material is usually at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and can be a single-layer or multi-layer structure, with a thickness of 1000 to 5000A, and the planarization layer 112 is a photoresist material with a thickness of 0.5 to 4um.
  • an OLED device layer is prepared on the source and drain layers, and the light-emitting direction of the OLED device layer faces the substrate 101 .
  • the OLED device layer is formed on the side of the source and drain layers away from the interlayer insulating layer 107, and the light-emitting direction faces the substrate 101, and specifically includes a pixel electrode layer, a pixel definition layer 113, and a light-emitting material layer disposed on the planarization layer 112. , common electrode and encapsulation layer.
  • the material of the pixel electrode layer includes a stack of ITO/Ag/ITO, patterned to form a plurality of pixel electrodes 114, a pixel definition layer 113 is arranged between adjacent pixel electrodes 114, and a light-emitting region is formed between adjacent pixel definition layers 113 , a light-emitting material layer (not shown in the figure) is formed in the light-emitting region, then a common electrode (not shown in the figure) is formed on the light-emitting material layer and the pixel definition layer 113 , and finally an encapsulation layer (not shown in the figure) is formed on the common electrode not shown).
  • the prepared OLED display panel has a bottom emission structure.
  • the conductive electrode 1021 is connected to the source electrode 108, and the source electrode 108 is connected to the active layer 1041.
  • a fixed low-potential signal is given to the conductive electrode 1021, so that the conductive electrode 1021 can be a thin film transistor.
  • the back channel of the active layer 1021 provides a stable low potential, thereby making the back channel potential of the thin film transistor stable, outputting stable electrical properties, and better driving the OLED device to emit light.
  • Both the first electrode plate 1022 and the second electrode plate 1042 of the transparent capacitor are disposed corresponding to the light-emitting area, so the area where the transparent capacitor is located can allow light to pass through, and the aperture ratio is relatively high.
  • the conductive electrode 1021 is made of an opaque metal material
  • the first plate 1022 of the transparent capacitor is made of a transparent conductive material.
  • the two materials are different, so two processes are required to form them respectively.
  • both are formed by patterning a transparent conductive layer, and only one process is required, thus saving a mask, reducing the cost without affecting the performance of the device.
  • the present application provides an OLED display panel and a preparation method thereof.
  • the OLED display panel includes a substrate, a transparent conductive layer, a buffer layer, a metal oxide semiconductor layer, a gate insulating layer, a gate electrode layer, an interlayer insulating layer, a source and drain layer layer and OLED device layer;
  • a transparent conductive layer is formed on one side of the substrate, patterned to form a conductive electrode and a first plate of a transparent capacitor;
  • a buffer layer is formed on the side of the transparent conductive layer away from the substrate;
  • a metal oxide semiconductor layer It is formed on the side of the buffer layer away from the transparent conductive layer, and patterned to form the active layer of the thin film transistor and the second plate of the transparent capacitor;
  • the gate insulating layer is formed on the side of the metal oxide semiconductor layer away from the buffer layer;
  • the electrode layer is formed on the side of the gate insulating layer away from the metal oxide semiconductor layer, and patterned to form the gate of the thin film transistor;

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Abstract

一种OLED显示面板及其制备方法，OLED显示面板包括层叠设置的衬底（101）、透明导电层、缓冲层（103）、金属氧化物半导体层、栅极绝缘层（105）、栅极层、层间绝缘层（107）、源漏极层和OLED器件层，OLED器件层的发光方向朝向衬底（101）。导电电极（1021）和透明电容的第一极板（1022）均为透明导电层图案化形成，仅需一道工序，因此节省了一道光罩，降低了成本。

Description

OLED显示面板及其制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示面板及其制备方法。
 背景技术
现有的底发射结构的OLED显示面板中，通常会在衬底上设置金属电极来稳定薄膜晶体管的背沟道电势，同时，为实现高的解析度，还需要在衬底上制备一层氧化铟锡电极，该层与缓冲层上方膜层的金属氧化物电极共同形成透明电容，透明电容所在区域也可以作为发光区，以此来增大开口率。然而，此种结构金属电极和氧化铟锡电极需要两道工序完成，制程较多，造成成本的增加。
因此，现有的底发射结构的OLED显示面板存在制作工序较多的技术问题，需要改进。
 技术问题
本申请实施例提供一种OLED显示面板及其制备方法，用以缓解现有的底发射结构的OLED显示面板中制作工序较多的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种OLED显示面板，包括：
衬底；
透明导电层，形成在所述衬底一侧，图案化形成导电电极、以及透明电容的第一极板；
缓冲层，形成在所述透明导电层远离所述衬底的一侧；
金属氧化物半导体层，形成在所述缓冲层远离所述透明导电层的一侧，图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板；
栅极绝缘层，形成在所述有源层远离所述缓冲层的一侧；
栅极层，形成在所述栅极绝缘层远离所述有源层的一侧，图案化形成所述薄膜晶体管的栅极；
层间绝缘层，形成在所述栅极层远离所述栅极绝缘层的一侧；
源漏极层，形成在所述层间绝缘层远离所述栅极层的一侧，图案化形成所述薄膜晶体管的源极和漏极，所述漏极与所述有源层的漏区连接，所述源极与所述有源层的源区和所述导电电极连接；
OLED器件层，形成在所述源漏极层远离所述层间绝缘层的一侧，所述OLED器件层的发光方向朝向所述衬底。
在本申请的OLED显示面板中，所述透明导电层的材料包括铟锡氧化物和铟锌氧化物中的至少一种。
在本申请的OLED显示面板中，所述金属氧化物半导体层的材料包括铟镓锌氧化物、铟锡锌氧化物和铟镓锌钛氧化物中的至少一种。
在本申请的OLED显示面板中，所述有源层在所述衬底的投影位于所述导电电极在所述衬底的投影范围内。
在本申请的OLED显示面板中，所述OLED器件层包括像素定义层和像素电极层，所述像素定义层定义出多个发光区，所述像素电极层位于所述发光区内，且与所述薄膜晶体管的源极连接，所述透明电容的第一极板和第二极板均对应所述发光区设置。
在本申请的OLED显示面板中，所述透明导电层的厚度为200至2000埃米。
在本申请的OLED显示面板中，所述金属氧化物半导体层的厚度为100至1000埃米。
本申请还提供一种OLED显示面板的制备方法，包括：
提供衬底；
在所述衬底一侧依次制备透明导电层和缓冲层，将所述透明导电层图案化形成导电电极、以及透明电容的第一极板；
在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层，并图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板；
在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层，所述栅极层图案化形成所述薄膜晶体管的栅极；
在所述层间绝缘层远离所述有源层的一侧制备源漏极层，所述源漏极层图案化形成所述薄膜晶体管的源极和漏极，所述漏极与所述有源层的漏区连接，所述源极与所述有源层的源区和所述导电电极连接；
在所述源漏极层上制备OLED器件层，所述OLED器件层的发光方向朝向所述衬底。
在本申请的OLED显示面板的制备方法中，所述在所述衬底一侧依次制备透明导电层和缓冲层的步骤，包括：在所述衬底一侧制备透明导电层，所述透明导电层材料包括铟锡氧化物和铟锌氧化物中的至少一种。
在本申请的OLED显示面板的制备方法中，所述在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层的步骤，包括：在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层，所述金属氧化物半导体层的材料包括铟镓锌氧化物、铟锡锌氧化物和铟镓锌钛氧化物中的至少一种。
在本申请的OLED显示面板的制备方法中，在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层，并图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板的步骤，包括：将所述金属氧化物半导体层图案化形成薄膜晶体管的有源层，且所述有源层在所述衬底的投影位于所述导电电极在所述衬底的投影范围内。
在本申请的OLED显示面板的制备方法中，所述在所述源漏极层上制备OLED器件层的步骤，包括：在所述源漏极层远离所述层间绝缘层的一侧制备像素定义层和像素电极层，所述像素定义层定义出多个发光区，所述像素电极层位于所述发光区内，且与所述薄膜晶体管的源极连接，所述透明电容的第一极板和第二极板均对应所述发光区设置。
在本申请的OLED显示面板的制备方法中，所述在所述衬底一侧依次制备透明导电层和缓冲层的步骤，包括：在所述衬底一侧制备厚度为200至2000埃米的透明导电层。
在本申请的OLED显示面板的制备方法中，所述在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层的步骤，包括：在所述缓冲层远离所述透明导电层的一侧制备厚度为100至1000埃米的金属氧化物半导体层。
在本申请的OLED显示面板的制备方法中，所述在所述源漏极层上制备OLED器件层的步骤之后，还包括：在所述OLED器件层远离所述驱动电路层的一侧制备封装层。
在本申请的OLED显示面板的制备方法中，所述在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层，所述栅极层图案化形成所述薄膜晶体管的栅极的步骤，包括：
整面沉积所述栅极绝缘层和所述栅极层后，将所述栅极层图案化形成栅极；
利用所述栅极为自对准，蚀刻所述栅极绝缘层；
对所述栅极层、所述栅极和所述金属氧化物半导体形成的前制程膜层进行整面的等离子处理；
在所述栅极远离所述栅极绝缘层的一侧形成整层的层间绝缘层。
在本申请的OLED显示面板的制备方法中，所述在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层的步骤，包括：在所述有源层远离所述缓冲层的一侧制备栅极绝缘层，所述栅极绝缘层厚度为1000至3000埃米。
在本申请的OLED显示面板的制备方法中，所述在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层的步骤，包括：在所述栅极绝缘层远离所述有源层的一侧制备栅极层，所述栅极层材料包括Mo、Al、Cu、Ti单质或合金中的至少一种。
在本申请的OLED显示面板的制备方法中，所述在所述栅极绝缘层远离所述有源层的一侧制备栅极层的步骤，包括：制备厚度为2000至8000埃米的栅极层。
在本申请的OLED显示面板的制备方法中，所述在所述层间绝缘层远离所述有源层的一侧制备源漏极层的步骤，包括：制备所述源漏极层，所述源漏极层的材料包括Mo、Al、Cu、Ti单质或合金中的至少一种。
 有益效果
本申请的有益效果：本申请提供一种OLED显示面板及其制备方法，OLED显示面板包括衬底、透明导电层、缓冲层、金属氧化物半导体层、栅极绝缘层、栅极层、层间绝缘层、源漏极层和OLED器件层；透明导电层形成在所述衬底一侧，图案化形成导电电极、以及透明电容的第一极板；缓冲层形成在所述透明导电层远离所述衬底的一侧；金属氧化物半导体层形成在所述缓冲层远离所述透明导电层的一侧，图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板；栅极绝缘层形成在所述金属氧化物半导体层远离所述缓冲层的一侧；栅极层形成在所述栅极绝缘层远离所述金属氧化物半导体层的一侧，图案化形成所述薄膜晶体管的栅极；层间绝缘层形成在所述栅极层远离所述栅极绝缘层的一侧；源漏极层形成在所述层间绝缘层远离所述栅极层的一侧，图案化形成所述薄膜晶体管的源极和漏极，所述漏极与所述有源层的漏区连接，所述源极与所述有源层的源区和所述导电电极连接；所述OLED器件层形成在源漏极层远离层间绝缘层的一侧，所述OLED器件层的发光方向朝向所述衬底。本申请中导电电极和透明电容的第一极板均为透明导电层图案化形成，仅需一道工序，因此节省了一道光罩，降低了成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的OLED显示面板的结构示意图。
图2为本申请实施例提供的OLED显示面板的制备方法流程示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
本申请实施例提供一种OLED显示面板及其制备方法，用以缓解现有的底发射结构的OLED显示面板中制作工序较多的技术问题。
如图1所示，为本申请提供的OLED显示面板的结构示意图。OLED显示面板包括衬底101、透明导电层、缓冲层103、金属氧化物半导体层、栅极绝缘层105、栅极层、层间绝缘层107、源漏极层和OLED器件层；
透明导电层形成在衬底101一侧，图案化形成导电电极1021、以及透明电容的第一极板1022；
缓冲层103形成在透明导电层远离衬底101的一侧；
金属氧化物半导体层形成在缓冲层103远离透明导电层的一侧，图案化形成薄膜晶体管的有源层1041、以及透明电容的第二极板1042；
栅极绝缘层105形成在有源层1041远离缓冲层的一侧；
栅极层形成在栅极绝缘层105远离有源层1041的一侧，图案化形成薄膜晶体管的栅极106；
层间绝缘层107形成在栅极层远离栅极绝缘层105的一侧；
源漏极层形成在层间绝缘层107远离栅极层的一侧，图案化形成薄膜晶体管的源极108和漏极109，漏极109与有源层1041的漏区连接，源极108与有源层1041的源区和导电电极1021连接；
OLED器件层形成在源漏极层远离层间绝缘层107的一侧，OLED器件层的发光方向朝向衬底101。
衬底101可以为柔性衬底，其材料可以包括聚酰亚胺、聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚碳酸酯、聚芳酯以及聚醚砜中的至少一种；也可以为刚性衬底，具体可以为玻璃衬底或者其他刚性衬底。本申请实施例不对衬底101的种类以及材料进行限定。
透明导电层的材料包括铟锡氧化物(ITO)和铟锌氧化物(IZO)中的至少一种，厚度为200至2000A，利用光刻做出图形，形成导电电极1021、以及透明电容的第一极板1022。
缓冲层103的材料为氮化硅(SiN x)和氧化硅(SiO x)中的至少一种，厚度为1000至5000A。
金属氧化物半导体层的材料包括铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)和铟镓锌钛氧化物(IGZTO)中的至少一种，厚度为100至1000A，经光刻形成薄膜晶体管的有源层1041、以及透明电容的第二极板1042，两者之间相互不接触，后续两者独立通信号进行相应的工作。有源层1041在衬底101的投影位于导电电极1021在衬底101的投影范围内。
栅极绝缘层105的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种，并且可以是单层或多层结构，厚度为1000至3000A。
栅极层的材料可以是Mo，Al，Cu，Ti单质或者是合金，厚度为2000至8000A，图案化形成栅极106。
在形成栅极绝缘层105和栅极106时，先整面设置栅极绝缘层105和栅极层，然后先利用一道黄光蚀刻出栅极106，再利用栅极106为自对准，蚀刻栅极绝缘层105，在蚀刻完成后，仅在栅极106覆盖的区域有栅极绝缘层105，其他区域的栅极绝缘层105全部被蚀刻掉。蚀刻完成后，在栅极106远离栅极绝缘层105的一侧，对前制程膜层进行整面的等离子(Plasma)处理，具体为，在真空机台中通入Ar、He、N 2、O 2、NH 3等气体并使其解离，然后轰击金属氧化物半导体层表面。在处理后，对于有源层1041，上方没有栅极106和栅极绝缘层105覆盖的部分成分发生改变，电阻值明显降低，形成薄膜晶体管的源区和漏区，被栅极106和栅极绝缘层105覆盖的部分保持半导体特性，形成薄膜晶体管的沟道区，而对于透明电容的第二极板1042，电阻值也明显降低。
层间绝缘层107的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种，并且可以是单层或多层结构，厚度为2000至10000A，在整面形成层间绝缘层107后，进行黄光和蚀刻做出第一过孔、第二过孔和第三过孔，其中第一过孔对应有源层1041的漏区，第二过孔对应有源层1041的源区，第三过孔对应导电电极1021。
源漏极层的材料包括Mo、Al、Cu、Ti等的单质或合金，厚度为2000至8000A，先整层形成后再光刻出图形，形成源极108和漏极109，其中漏极109通过第一过孔与有源层1041的漏区连接，源极108通过第二过孔与有源层1041的源区连接，通过第三过孔与导电电极1021连接。
此外，OLED显示面板还包括设置在源漏极层上的钝化层110、形成在钝化层110上的色阻层111、形成在色阻层111上的平坦化层112，钝化层的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种，并且可以是单层或多层结构，厚度为1000至5000A，平坦化层112材料为光刻胶，厚度0.5至4um。
OLED器件层形成在源漏极层远离层间绝缘层107的一侧，且发光方向朝向衬底101，具体包括设置在在平坦化层112上的像素电极层、像素定义层113、发光材料层、公共电极和封装层。像素电极层的材料包括ITO/Ag/ITO的叠层，图案化形成多个像素电极114，在相邻像素电极114之间设置有像素定义层113，相邻像素定义层113之间形成发光区，在发光区内形成有发光材料层（图未示出），然后在发光材料层和像素定义层113上形成有公共电极（图未示出），最后在公共电极上形成有封装层（图未示出）。在本申请实施例中OLED显示面板为底发射结构。
在OLED显示面板中，导电电极1021与源极108连接，而源极108又与有源层1041连接，在工作时给导电电极1021一个固定的低电位信号，可以使导电电极1021为薄膜晶体管中有源层1021的背沟道提供一个稳定的低电势，进而使得薄膜晶体管的背沟道电势稳定，输出稳定的电性，更好地驱动OLED器件发光。
透明电容的第一极板1022和第二极板1042均对应发光区设置，因此透明电容所在区域可以允许光透过，开口率较高。
在现有技术中，导电电极1021采用不透光的金属材料制备，透明电容的第一极板1022采用透明导电材料制备，两者材料不同，因此需要两道工序分别成型。而本申请中，两者均由透明导电层图案化形成，仅需一道工序，因此节省了一道光罩，在不影响器件性能的同时又降低了成本。
如图2所示，本申请还提供一种OLED显示面板的制备方法，包括以下步骤：
201：提供衬底；
202：在衬底一侧依次制备透明导电层和缓冲层，将透明导电层图案化形成导电电极、以及透明电容的第一极板；
203：在缓冲层远离透明导电层的一侧制备金属氧化物半导体层，并图案化形成薄膜晶体管的有源层、以及透明电容的第二极板；
204：在有源层远离缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层，栅极层图案化形成薄膜晶体管的栅极；
205：在层间绝缘层远离有源层的一侧制备源漏极层，源漏极层图案化形成薄膜晶体管的源极和漏极，漏极与有源层的漏区连接，源极与有源层的源区和导电电极连接；
206：在源漏极层上制备OLED器件层，OLED器件层的发光方向朝向衬底。
下面结合图1对该制备方法进行具体说明。
在201中，提供衬底101。
衬底101可以为柔性衬底，其材料可以包括聚酰亚胺、聚对苯二甲酸乙二醇酯、聚萘二甲酸乙二醇酯、聚碳酸酯、聚芳酯以及聚醚砜中的至少一种；也可以为刚性衬底，具体可以为玻璃衬底或者其他刚性衬底。本申请实施例不对衬底101的种类以及材料进行限定。
在202中，在衬底101一侧依次制备透明导电层和缓冲层103，将透明导电层图案化形成导电电极1021、以及透明电容的第一极板1022。
透明导电层的材料包括铟锡氧化物(ITO)和铟锌氧化物(IZO)中的至少一种，厚度为200至2000A，利用光刻做出图形，形成导电电极1021、以及透明电容的第一极板1022。
在203中，在缓冲层103远离透明导电层的一侧制备金属氧化物半导体层，并图案化形成薄膜晶体管的有源层1041、以及透明电容的第二极板1042。
金属氧化物半导体层的材料包括铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)和铟镓锌钛氧化物(IGZTO)中的至少一种，厚度为100至1000A，经光刻形成薄膜晶体管的有源层1041、以及透明电容的第二极板1042，两者之间相互不接触，后续两者独立通信号进行相应的工作。有源层1041在衬底101的投影位于导电电极1021在衬底101的投影范围内。
在204中，在有源层1041远离缓冲层103的一侧依次制备栅极绝缘层105、栅极层和层间绝缘层107，栅极层图案化形成薄膜晶体管的栅极106。
栅极绝缘层105的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种，并且可以是单层或多层结构，厚度为1000至3000A。
栅极层的材料可以是Mo，Al，Cu，Ti单质或者是合金，厚度为2000至8000A，图案化形成栅极106。
在形成栅极绝缘层105和栅极106时，先整面设置栅极绝缘层105和栅极层，然后先利用一道黄瓜蚀刻出栅极106，再利用栅极106为自对准，蚀刻栅极绝缘层105，在蚀刻完成后，仅在栅极106覆盖的区域有栅极绝缘层105，其他区域的栅极绝缘层105全部被蚀刻掉。蚀刻完成后，在栅极106远离栅极绝缘层105的一侧，对前制程膜层进行整面的等离子(Plasma)处理，具体为，在真空机台中通入Ar、He、N 2、O 2、NH 3等气体并使其解离，然后轰击金属氧化物半导体层表面。在处理后，对于有源层1041，上方没有栅极106和栅极绝缘层105覆盖的部分成分发生改变，电阻值明显降低，形成薄膜晶体管的源区和漏区，被栅极106和栅极绝缘层105覆盖的部分保持半导体特性，形成薄膜晶体管的沟道区，而对于透明电容的第二极板1042，电阻值也明显降低。
层间绝缘层107的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种，并且可以是单层或多层结构，厚度为2000至10000A，在整面形成层间绝缘层107后，进行黄光和蚀刻做出第一过孔、第二过孔和第三过孔，其中第一过孔对应有源层1041的漏区，第二过孔对应有源层1041的源区，第三过孔对应导电电极1021。
在205中，在层间绝缘层107远离有源层1041的一侧制备源漏极层，源漏极层图案化形成薄膜晶体管的源极108和漏极109，漏极109与有源层1041的漏区连接，源极108与有源层1042的源区和导电电极1021连接。
源漏极层的材料包括Mo、Al、Cu、Ti等的单质或合金，厚度为2000至8000A，先整层形成后再光刻出图形，形成源极108和漏极109，其中漏极109通过第一过孔与有源层1041的漏区连接，源极108通过第二过孔与有源层1041的源区连接，通过第三过孔与导电电极1021连接。
此外，OLED显示面板还包括设置在源漏极层上的钝化层110、形成在钝化层110上的色阻层111、形成在色阻层111上的平坦化层112，钝化层的材料通常为氮化硅(SiNx)和氧化硅(SiOx)中的至少一种，并且可以是单层或多层结构，厚度为1000至5000A，平坦化层112材料为光刻胶，厚度0.5至4um。
在206中，在源漏极层上制备OLED器件层，OLED器件层的发光方向朝向衬底101。
OLED器件层形成在源漏极层远离层间绝缘层107的一侧，且发光方向朝向衬底101，具体包括设置在在平坦化层112上的像素电极层、像素定义层113、发光材料层、公共电极和封装层。像素电极层的材料包括ITO/Ag/ITO的叠层，图案化形成多个像素电极114，在相邻像素电极114之间设置有像素定义层113，相邻像素定义层113之间形成发光区，在发光区内形成有发光材料层（图未示出），然后在发光材料层和像素定义层113上形成有公共电极（图未示出），最后在公共电极上形成有封装层（图未示出）。制备的OLED显示面板为底发射结构。
在OLED显示面板中，导电电极1021与源极108连接，而源极108又与有源层1041连接，在工作时给导电电极1021一个固定的低电位信号，可以使导电电极1021为薄膜晶体管中有源层1021的背沟道提供一个稳定的低电势，进而使得薄膜晶体管的背沟道电势稳定，输出稳定的电性，更好地驱动OLED器件发光。
透明电容的第一极板1022和第二极板1042均对应发光区设置，因此透明电容所在区域可以允许光透过，开口率较高。
在现有技术中，导电电极1021采用不透光的金属材料制备，透明电容的第一极板1022采用透明导电材料制备，两者材料不同，因此需要两道工序分别成型。而本申请的制备方法中，两者均由透明导电层图案化形成，仅需一道工序，因此节省了一道光罩，在不影响器件性能的同时又降低了成本。
根据以上实施例可知：
本申请提供一种OLED显示面板及其制备方法，OLED显示面板包括衬底、透明导电层、缓冲层、金属氧化物半导体层、栅极绝缘层、栅极层、层间绝缘层、源漏极层和OLED器件层；透明导电层形成在衬底一侧，图案化形成导电电极、以及透明电容的第一极板；缓冲层形成在透明导电层远离衬底的一侧；金属氧化物半导体层形成在缓冲层远离透明导电层的一侧，图案化形成薄膜晶体管的有源层、以及透明电容的第二极板；栅极绝缘层形成在金属氧化物半导体层远离缓冲层的一侧；栅极层形成在栅极绝缘层远离金属氧化物半导体层的一侧，图案化形成薄膜晶体管的栅极；层间绝缘层，形成在栅极层远离栅极绝缘层的一侧；源漏极层形成在层间绝缘层远离栅极层的一侧，图案化形成薄膜晶体管的源极和漏极，漏极与有源层的漏区连接，源极与有源层的源区和导电电极连接；OLED器件层形成在源漏极层远离层间绝缘层的一侧，OLED器件层的发光方向朝向衬底。本申请中导电电极和透明电容的第一极板均为透明导电层图案化形成，仅需一道工序，因此节省了一道光罩，降低了成本。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种OLED显示面板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种OLED显示面板，其包括：
    衬底；
    透明导电层，形成在所述衬底一侧，图案化形成导电电极、以及透明电容的第一极板；
    缓冲层，形成在所述透明导电层远离所述衬底的一侧；
    金属氧化物半导体层，形成在所述缓冲层远离所述透明导电层的一侧，图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板；
    栅极绝缘层，形成在所述有源层远离所述缓冲层的一侧；
    栅极层，形成在所述栅极绝缘层远离所述有源层的一侧，图案化形成所述薄膜晶体管的栅极；
    层间绝缘层，形成在所述栅极层远离所述栅极绝缘层的一侧；
    源漏极层，形成在所述层间绝缘层远离所述栅极层的一侧，图案化形成所述薄膜晶体管的源极和漏极，所述漏极与所述有源层的漏区连接，所述源极与所述有源层的源区和所述导电电极连接；
    OLED器件层，形成在所述源漏极层远离所述层间绝缘层的一侧，所述OLED器件层的发光方向朝向所述衬底。
  2. 如权利要求1所述的OLED显示面板，其中，所述透明导电层的材料包括铟锡氧化物和铟锌氧化物中的至少一种。
  3. 如权利要求1所述的OLED显示面板，其中，所述金属氧化物半导体层的材料包括铟镓锌氧化物、铟锡锌氧化物和铟镓锌钛氧化物中的至少一种。
  4. 如权利要求1所述的OLED显示面板，其中，所述有源层在所述衬底的投影位于所述导电电极在所述衬底的投影范围内。
  5. 如权利要求1所述的OLED显示面板，其中，所述OLED器件层包括像素定义层和像素电极，所述像素定义层定义出多个发光区，所述像素电极位于所述发光区内，且与所述薄膜晶体管的源极连接，所述透明电容的第一极板和第二极板均对应所述发光区设置。
  6. 如权利要求1所述的OLED显示面板，其中，所述透明导电层的厚度为200至2000埃米。
  7. 如权利要求1所述的OLED显示面板，其中，所述金属氧化物半导体层的厚度为100至1000埃米。
  8. 一种OLED显示面板的制备方法，其包括：
    提供衬底；
    在所述衬底一侧依次制备透明导电层和缓冲层，将所述透明导电层图案化形成导电电极、以及透明电容的第一极板；
    在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层，并图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板；
    在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层，所述栅极层图案化形成所述薄膜晶体管的栅极；
    在所述层间绝缘层远离所述有源层的一侧制备源漏极层，所述源漏极层图案化形成所述薄膜晶体管的源极和漏极，所述漏极与所述有源层的漏区连接，所述源极与所述有源层的源区和所述导电电极连接；
    在所述源漏极层上制备OLED器件层，所述OLED器件层的发光方向朝向所述衬底。
  9. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述衬底一侧依次制备透明导电层和缓冲层的步骤，包括：在所述衬底一侧制备透明导电层，所述透明导电层材料包括铟锡氧化物和铟锌氧化物中的至少一种。
  10. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层的步骤，包括：在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层，所述金属氧化物半导体层的材料包括铟镓锌氧化物、铟锡锌氧化物和铟镓锌钛氧化物中的至少一种。
  11. 如权利要求8所述的OLED显示面板的制备方法，其中，在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层，并图案化形成薄膜晶体管的有源层、以及所述透明电容的第二极板的步骤，包括：将所述金属氧化物半导体层图案化形成薄膜晶体管的有源层，且所述有源层在所述衬底的投影位于所述导电电极在所述衬底的投影范围内。
  12. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述源漏极层上制备OLED器件层的步骤，包括：在所述源漏极层远离所述层间绝缘层的一侧制备像素定义层和像素电极，所述像素定义层定义出多个发光区，所述像素电极位于所述发光区内，且与所述薄膜晶体管的源极连接，所述透明电容的第一极板和第二极板均对应所述发光区设置。
  13. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述衬底一侧依次制备透明导电层和缓冲层的步骤，包括：在所述衬底一侧制备厚度为200至2000埃米的透明导电层。
  14. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述缓冲层远离所述透明导电层的一侧制备金属氧化物半导体层的步骤，包括：在所述缓冲层远离所述透明导电层的一侧制备厚度为100至1000埃米的金属氧化物半导体层。
  15. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述源漏极层上制备OLED器件层的步骤之后，还包括：在所述OLED器件层远离所述驱动电路层的一侧制备封装层。
  16. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层，所述栅极层图案化形成所述薄膜晶体管的栅极的步骤，包括：
    整面沉积所述栅极绝缘层和所述栅极层后，将所述栅极层图案化形成栅极；
    利用所述栅极为自对准，蚀刻所述栅极绝缘层；
    对所述栅极层、所述栅极和所述金属氧化物半导体形成的前制程膜层进行整面的等离子处理；
    在所述栅极远离所述栅极绝缘层的一侧形成整层的层间绝缘层。
  17. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层的步骤，包括：在所述有源层远离所述缓冲层的一侧制备栅极绝缘层，所述栅极绝缘层厚度为1000至3000埃米。
  18. 如权利要求17所述的OLED显示面板的制备方法，其中，所述在所述有源层远离所述缓冲层的一侧依次制备栅极绝缘层、栅极层和层间绝缘层的步骤，包括：在所述栅极绝缘层远离所述有源层的一侧制备栅极层，所述栅极层材料包括Mo、Al、Cu、Ti单质或合金中的至少一种。
  19. 如权利要求18所述的OLED显示面板的制备方法，其中，所述在所述栅极绝缘层远离所述有源层的一侧制备栅极层的步骤，包括：制备厚度为2000至8000埃米的栅极层。
  20. 如权利要求8所述的OLED显示面板的制备方法，其中，所述在所述层间绝缘层远离所述有源层的一侧制备源漏极层的步骤，包括：制备所述源漏极层，所述源漏极层的材料包括Mo、Al、Cu、Ti单质或合金中的至少一种。
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