WO2021259311A1 - 阵列基板及其制作方法、显示面板及显示装置 - Google Patents

阵列基板及其制作方法、显示面板及显示装置 Download PDF

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Publication number
WO2021259311A1
WO2021259311A1 PCT/CN2021/101770 CN2021101770W WO2021259311A1 WO 2021259311 A1 WO2021259311 A1 WO 2021259311A1 CN 2021101770 W CN2021101770 W CN 2021101770W WO 2021259311 A1 WO2021259311 A1 WO 2021259311A1
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Prior art keywords
layer
light
electrode
switch tube
color depth
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PCT/CN2021/101770
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English (en)
French (fr)
Inventor
王智勇
宋勇
尹岩岩
薛静
梁士龙
邢红燕
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US17/780,263 priority Critical patent/US20220416138A1/en
Publication of WO2021259311A1 publication Critical patent/WO2021259311A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.
  • the self-luminous display adopts an array of tiny luminous lamp groups, which dynamically control the brightness and darkness through the chip to realize the display function. Since self-luminescence can have an absolute black state, theoretically the contrast can be infinite, and the product thickness reduction brought by no backlight is unmatched by traditional transmissive displays.
  • An embodiment of the present disclosure provides an array substrate, including:
  • the first electrode layer, the first insulating layer and the second electrode layer are sequentially arranged on the base substrate,
  • a light-emitting element group located on the second electrode layer includes one or more light-emitting elements, each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode.
  • the first electrode layer is connected, and the second electrode is connected to the second electrode layer to drive the light-emitting layer to emit light.
  • the array substrate further includes a flat layer located on a side of the light-emitting element group away from the base substrate;
  • the driving circuit layer further includes a scan signal line, a second switch tube, a data signal line, a storage capacitor, and a common electrode layer.
  • the control electrode of the first switch tube communicates with the second switch tube through a via hole.
  • the first pole of the second switch tube is connected to the first pole plate of the storage capacitor, the data signal line is connected to the second pole of the second switch tube, and the scan signal The wire is connected to the control electrode of the second switch tube, and the common electrode layer is used as the second electrode plate of the storage capacitor.
  • the array substrate further includes a second insulating layer located on the flat layer and the driving circuit layer, the first via penetrates the second insulating layer and part of the flat layer, and the first Two via holes penetrate the second electrode layer.
  • the flat layer is made of resin material.
  • the orthographic projections of the first electrode layer and the second electrode layer on the base substrate overlap with the orthographic projections of all the light-emitting elements on the base substrate.
  • the array substrate further includes an auxiliary layer, the auxiliary layer and the second electrode layer are provided with the same layer and the same material, and are provided at a distance from the second electrode layer, and the first electrode is provided on the auxiliary layer.
  • the layer is away from the side of the base substrate.
  • the orthographic projection of the first electrode and the second electrode on the base substrate are located on both sides of the orthographic projection of the light-emitting layer on the base substrate.
  • the light-emitting element group includes a plurality of light-emitting elements
  • the plurality of light-emitting elements are arranged in parallel or in series.
  • Another embodiment of the present disclosure provides a display panel, including the array substrate as described above.
  • Yet another embodiment of the present disclosure provides a display device, including the display panel as described above.
  • Yet another embodiment of the present disclosure provides a manufacturing method of an array substrate, including:
  • a light-emitting element group is formed on the side of the second electrode layer away from the base substrate.
  • the light-emitting element group includes a single light-emitting element or a plurality of light-emitting elements, and each light-emitting element includes a first electrode, a light-emitting layer, and a second light-emitting element.
  • An electrode, the first electrode is connected to the first electrode layer, and the second electrode is connected to the second electrode layer to drive the light emitting layer to emit light.
  • the method further includes:
  • a drive circuit layer is formed on the side of the flat layer away from the base substrate, and the drive circuit layer includes a first switch tube for controlling the turn-off between the first electrode and the first electrode layer
  • the first pole of the first switch tube is connected to the auxiliary layer through a first via hole
  • the second pole of the first switch tube is connected to the first electrode layer through a second via hole.
  • the driving circuit layer further includes a scanning signal line, a second switch tube and a storage capacitor,
  • the method further includes:
  • a data signal line, a first pole and a second pole of the first switch tube, a first pole and a second pole of the second switch tube, and a storage device are formed on the side of the semiconductor layer away from the base substrate.
  • the first electrode plate of the capacitor; the first electrode of the first switch tube is connected to the first electrode layer through a via hole, the second electrode of the first switch tube is connected to the first electrode of the light-emitting element, the
  • the control pole of the first switch tube is connected to the first pole of the second switch tube through a via hole, the first pole of the second switch tube is connected to the first pole plate of the storage capacitor, and the data signal line Connected with the second pole of the second switch tube, and the scan signal line is connected with the control pole of the second switch tube;
  • a third insulating layer and a common electrode layer are formed, and the common electrode layer constitutes the second plate of the storage capacitor, and the common electrode layer and the first plate of the storage capacitor are on the positive side of the base substrate.
  • the projections overlap at least partially.
  • forming the second electrode layer includes:
  • the second electrode layer and the auxiliary layer are formed at the same time by using the same mask and the same patterning process, the auxiliary layer and the second electrode layer are spaced apart, and the first electrode is disposed on the auxiliary layer away from the substrate One side of the substrate.
  • the flat layer is made of resin material.
  • Yet another embodiment of the present disclosure provides a brightness adjustment method for the above-mentioned array substrate, and the method includes:
  • the first scan times of the array substrate in one frame are determined, wherein in each scan process, each row of the array substrate is scanned once.
  • the method further includes:
  • the corresponding relationship between the data voltage and the color depth is determined.
  • the determining the brightness values of all light-emitting element groups in the array substrate corresponding to different data voltages includes:
  • the brightness values of the light-emitting element group corresponding to different data voltages are determined.
  • the first color depth bit number constitutes the high bit number of the third color depth bit number
  • the second color depth bit number constitutes the low bit number of the third color depth bit number
  • the method further includes:
  • the image data to be displayed is displayed according to the voltage of the data to be output and/or the number of first scans in one frame.
  • the array substrate further includes an enable signal input terminal.
  • the method When scanning each row of the array substrate, the method further includes:
  • FIG. 1 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of forming a first electrode layer and a second electrode layer provided by an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of forming or placing a light emitting device group on a second electrode layer provided by an embodiment of the disclosure
  • FIG. 4 is a schematic diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 5 is one of the schematic diagrams of forming a driving circuit layer provided by an embodiment of the disclosure.
  • FIG. 6 is the second schematic diagram of forming a driving circuit layer provided by an embodiment of the disclosure.
  • FIG. 7 is the third schematic diagram of forming a driving circuit layer provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • Fig. 9 is a schematic cross-sectional view along A-A in Fig. 8;
  • Figure 10 is a schematic cross-sectional view along B-B in Figure 8.
  • FIG. 11 is a schematic diagram of current-luminance characteristics of a light-emitting device group provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of current-voltage characteristics of a light emitting device group provided by an embodiment of the disclosure.
  • FIG. 13 is a schematic diagram of the corresponding relationship between current-brightness and current-voltage provided by the embodiments of the disclosure.
  • FIG. 14 is a timing diagram of a pixel circuit provided by an embodiment of the disclosure.
  • FIG. 15 is a schematic diagram of the timing relationship between OE and G1 and S1 provided by an embodiment of the disclosure.
  • FIG. 16 is a timing control diagram of different brightness of the light-emitting device group provided by the embodiments of the disclosure.
  • FIG. 17 is a schematic diagram of a flow of brightness setting and display data output provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of an array substrate provided by an embodiment of the disclosure.
  • each lamp (group) needs to be equipped with at least one driving line, a proportional driving chip is required, and the wiring difficulty is greatly increased.
  • the current drive brings a lot of lead loss, which is often referred to as IR Drop. This problem will affect the normal operation of the light-emitting lamp (group), and will also increase the power consumption of the product.
  • the current common glass-based self-luminous Take the product as an example, the line loss can account for 10% to 25% of the total power consumption of the entire product.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a manufacturing method of an array substrate, and the manufacturing method may include the following steps:
  • Step 11 sequentially forming a first electrode layer, a first insulating layer and a second electrode layer on the base substrate.
  • the first electrode layer and the second electrode layer are laid down as a whole.
  • FIG. 2 is a schematic diagram of forming a first electrode layer and a second electrode layer according to an embodiment of the present disclosure.
  • the first electrode layer 101 is laid on the base substrate.
  • the first electrode layer 101 can be laid as a whole layer, and then the display area and the flexible circuit board/drive chip connection are made through a wet etching process. Alignment marks of pins and subsequent processes, etc.
  • an insulating protective layer i.e., the first insulating layer
  • the insulating protective layer can be made of resin or nitrogen-silicon compound. If photosensitive resin is used, it needs to be exposed and developed later to form connection holes.
  • a connecting hole can be formed at the same position of several insulating protective layers by dry etching at a later stage. Then, continue to lay the second electrode layer 103.
  • the second electrode layer 103 can also be laid as a whole.
  • the display area, flexible circuit board/drive chip connection pins, upper circuit connection holes, etc. can be made by wet etching.
  • the first electrode layer 101 can be used as an anode
  • the second electrode layer 103 can be used as a cathode.
  • IP drop voltage distortion
  • Step 12 At least one light-emitting element group is formed on the side of the second electrode layer away from the base substrate.
  • the light-emitting element group includes one or more light-emitting elements, and each light-emitting element includes a first electrode and a light-emitting layer. And a second electrode, the first electrode is connected to the first electrode layer, and the second electrode is connected to the second electrode layer to drive the light emitting layer to emit light.
  • a flat layer is formed on the side of the light-emitting element away from the base substrate, and the second electrode of the light-emitting device group is connected to the second electrode layer.
  • FIG. 3 is a schematic diagram of forming at least one light-emitting element group on the second electrode layer according to an embodiment of the present disclosure.
  • the light-emitting element group 105 can be directly formed on the second electrode layer 103 by evaporation, printing, etc., or at least one light-emitting element formed on another substrate such as a silicon base can be formed.
  • the element group 105 is placed on the second electrode layer 103 by means of (mass) transfer or the like.
  • the light emitting element group 105 includes a first electrode 1051 and a second electrode 1052, wherein the first electrode 1051 can be the anode of the light emitting element 105, and the second electrode 1052 can be the cathode of the light emitting element 105.
  • the second electrode 1052 of the light-emitting element 105 is directly connected to the second electrode layer 103.
  • the method further includes:
  • a drive circuit layer is formed on the side of the flat layer away from the base substrate, and the drive circuit layer includes a first switch tube for controlling the turn-off between the first electrode and the first electrode layer
  • the first pole of the first switch tube is connected to the auxiliary layer through a first via hole
  • the second pole of the first switch tube is connected to the first electrode layer through a second via hole.
  • a flat layer is formed on the side of the light-emitting element group 105 away from the base substrate.
  • the flat layer is used to cover and protect the light-emitting element group 105 and form a relatively flat surface to facilitate subsequent processes.
  • the multiple light-emitting elements may be arranged in parallel or in series. By connecting multiple light-emitting elements in parallel or in series, it is possible to control multiple light-emitting elements with a single control switch. Turning on and off the light-emitting element.
  • the light-emitting element may be a light-emitting diode, and the light-emitting diode may be an LED, Mini-LED or Micro-LED.
  • the light-emitting element group occupies only 10%-40% of the entire display area, that is, the light-emitting source is relatively scattered and sparse. Compared with the transmissive display in the related art, the brightness continuity is not good.
  • the protective glue is coated to soften the light and protect the light-emitting element.
  • the flat layer may be formed of a resin material.
  • some components with different refractive indexes can be mixed to achieve the purpose of astigmatism.
  • the driving circuit layer further includes a scan signal line, a second switch tube and a storage capacitor,
  • the method further includes:
  • a data signal line, a first pole and a second pole of the first switch tube, a first pole and a second pole of the second switch tube, and a storage device are formed on the side of the semiconductor layer away from the base substrate.
  • the first electrode plate of the capacitor; the first electrode of the first switch tube is connected to the first electrode layer through a via hole, the second electrode of the first switch tube is connected to the first electrode of the light-emitting element, the
  • the control pole of the first switch tube is connected to the first pole of the second switch tube through a via hole, the first pole of the second switch tube is connected to the first pole plate of the storage capacitor, and the data signal line Connected with the second pole of the second switch tube, and the scan signal line is connected with the control pole of the second switch tube;
  • a third insulating layer and a common electrode layer are formed, and the common electrode layer constitutes the second plate of the storage capacitor, and the common electrode layer and the first plate of the storage capacitor are on the positive side of the base substrate.
  • the projections overlap at least partially.
  • the driving circuit layer includes a scan signal line, a first switch tube, a second switch tube, a data signal line, a storage capacitor, and a common electrode layer, and the source of the first switch tube is connected to a via hole.
  • the first electrode layer is connected, the drain of the first switching tube is connected to the first electrode of the light emitting device group, and the gate of the first switching tube is connected to the source of the second switching tube through a via hole ,
  • the source of the second switch tube is connected to the first plate of the storage capacitor, the data signal line is connected to the drain of the second switch tube, and the scan signal line is connected to the second switch
  • the gate of the tube is connected, and the common electrode layer is used as the second plate of the storage capacitor.
  • FIG. 4 is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit includes a set of anodes and cathodes for providing current, corresponding to the above-mentioned first electrode layer 101 and the second electrode layer 103, and also includes a first switch tube T1, The second switching tube T2 and the storage capacitor C, wherein the source of the first switching tube T1 is connected to the anode, the drain of the first switching tube T1 is connected to the first electrode 1051 of the light-emitting element group 105, and the first electrode 1051 of the light-emitting element group 105 is connected.
  • the two electrodes 1052 are connected to the cathode, the gate of the first switch tube T1 is connected to the first plate of the storage capacitor C, the second plate of the storage capacitor C is connected to the common electrode 110, and the source of the second switch tube T2 is connected to the The gate of the first switch tube T1 is connected to the first plate of the storage capacitor C, the drain of the second switch tube T2 is connected to the data signal line, and the gate of the second switch tube T2 is connected to the scan signal line.
  • the first switch tube T1 is used to control the on and off of the light-emitting element group 105, and the storage capacitor C is used to maintain the gate voltage of the first switch tube T1, and then the light-emitting element group 105 is kept on/off, and the second switch tube T2 is used to control the on or off of the first switch tube T1.
  • the gate of the second switch tube T2 receives the scan signal from the scan signal line, and the drain of the second switch T2 receives the data signal line.
  • the incoming data signal is used to turn on or turn off the first switch tube T1 under the control of the scan signal and the data signal.
  • the step of forming the driving circuit layer may specifically include the following steps.
  • the scan signal line, the gates of the first switch tube and the second switch tube on the flat layer are formed, and the scan signal line is connected to the gate of the second switch tube.
  • FIG. 5 is one of the schematic diagrams of forming a driving circuit layer provided by an embodiment of the present disclosure.
  • a layer of metal is laid on the flat layer covering the light-emitting device group 105, and the scan signal line 111, the gate 1124 of the first switch tube T1, and the second switch tube T2 are formed by a wet etching process. Grid 1134.
  • a protective layer (ie, a second insulating layer) may be laid on the scan signal line 111, and the protective layer may be a silicon nitride compound.
  • an active layer located on the side of the gate away from the base substrate is formed.
  • FIG. 6 is a second schematic diagram of forming a driving circuit layer according to an embodiment of the present disclosure. As shown in Figure 6, continue to form the active layer 1123 of the first switching tube T1 on the side of the first switching tube T1 away from the base substrate and the gate 1134 of the second switching tube T2 away from everything. The active layer 1133 of the second switch tube T2 is formed on one side of the base substrate.
  • the self-luminous element driven by current in this embodiment requires a relatively large turn-on current
  • the light-emitting element group 105 in the embodiment of the present disclosure includes 9 LED lights arranged in series
  • the conduction is estimated When the current is about 20 mA, when polysilicon is used to form the active layer of the first switch tube T1, the required aspect ratio is about 1000.
  • the light-emitting element group 105 occupies a low proportion of the area, there is enough space for the active layer with such an aspect ratio to be arranged.
  • the aspect ratio setting in the related art is Can meet the requirements (usually the aspect ratio is less than 10).
  • the above description is only exemplary, and the number of LEDs in the light-emitting element group 105 can be increased or decreased.
  • the aspect ratio of the active layer will also be changed accordingly.
  • a data signal line, the source and drain of the first switch tube and the second switch tube, and the first plate of the storage capacitor are formed, and the source of the first switch tube is connected to the first plate through the via hole.
  • the electrode layer is connected, the drain of the first switch tube is connected to the first electrode of the light emitting device group through a via hole, and the gate of the first switch tube is connected to the source electrode of the second switch tube through a via hole.
  • the drain of the second switch tube is connected to the first plate of the storage capacitor in the same layer, and the data signal line is connected to the drain of the second switch tube in the same layer.
  • FIG. 7 is the third schematic diagram of forming a driving circuit layer according to an embodiment of the present disclosure.
  • a metal layer is further laid, and the data signal line 114, the source 1121 and the drain 1122 of the first switching tube T1, the source 1131 and the source 1131 of the second switching tube T2 are formed by a wet etching process.
  • the drain 1132 and the first plate C1 of the storage capacitor C wherein the data signal line 114 is connected to the drain 1132 of the second switching tube T2, and the source 1131 of the second switching tube T2 is directly connected to the first plate C1 of the storage capacitor C
  • a plate C1 is connected, the source 1121 of the first switch tube T1 is connected to the first electrode layer 101 through the second via 1092, and the drain 1122 of the first switch tube T1 is connected to the light-emitting element group through the first via 1091
  • the first electrode 1051 of 105 is connected, and the gate 1124 of the first switch tube T1 is connected to the first plate C1 of the storage capacitor C through a via.
  • a third insulating layer and a common electrode layer are sequentially formed.
  • the common electrode layer constitutes the second plate of the storage capacitor, and the common electrode layer and the first plate of the storage capacitor are on the base substrate.
  • the orthographic projections overlap at least partially.
  • FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the third insulating layer is continuously formed to cover and protect the data signal line 114 and the like.
  • the third insulating layer can be made of resin material, or can be made of nitrogen-silicon compound.
  • the common electrode layer 110 is laid.
  • the portion of the common electrode layer 110 directly above the first plate C1 of the storage capacitor C is formed as the second plate C2 of the storage capacitor C; the size of the storage capacitor C is mainly determined by the scan period and the second plate C2.
  • the off-state current of the switching tube T2 and the current-voltage characteristic of the first switching tube T1 are jointly determined, that is, the plate size of the storage capacitor C is adjusted according to the above factors to obtain a suitable capacitance.
  • FIG. 9 is a schematic cross-sectional view along A-A in FIG. 8
  • FIG. 10 is a schematic cross-sectional view along B-B in FIG. 8.
  • the gate 1124 of the first switching tube T1 is connected to the source 1131 of the second switching tube T2 (also the first plate C1 of the storage capacitor C) through the via hole opened in the insulating layer 114,
  • the source 1131 of the second switch tube T2 (which is also the first plate C1 of the storage capacitor C) and the common electrode layer 110 above the second insulating layer 115 together form the storage capacitor C, which is located at the first electrode of the storage capacitor C
  • the common electrode layer 110 above the plate C1 is also the second plate C2 of the storage capacitor C.
  • the array substrate includes a first electrode layer 101 (as an anode in this embodiment) on a base substrate, a first insulating layer 102 on the first electrode layer 101, and a first insulating layer 102 on the first insulating layer 102.
  • the second electrode layer 103 (as the cathode in this embodiment) is located on the light-emitting element group 105 on the second electrode layer 103, wherein the second electrode 1052 of the light-emitting element group 105 is directly connected to the second electrode layer 103, and then covers The flat layer 106 (using resin material) on the light-emitting element group 105, then the third insulating layer 107, and the common electrode layer 110 on the third insulating layer 107, where the drain 1122 of the first switch transistor T1 passes
  • the first via hole 1091 is connected to the first electrode 1051 of the light emitting element group 105, and the source electrode 1021 of the first switch tube T1 is connected to the first electrode layer 101 through the second via hole 1092.
  • forming the second electrode layer includes:
  • the second electrode layer and the auxiliary layer are formed at the same time by using the same mask and the same patterning process, the auxiliary layer and the second electrode layer are spaced apart, and the first electrode is disposed on the auxiliary layer away from the substrate One side of the substrate.
  • an auxiliary layer is formed at the same time as the second electrode layer is formed, and the first electrode of the light-emitting element group is disposed on the auxiliary layer.
  • the auxiliary layer 104 is formed by a wet etching method. That is, the auxiliary layer 104 and the second electrode layer 103 are arranged in the same layer and the same material, but they are spaced apart from each other.
  • the auxiliary layer 104 can support the first electrode 1051 of the light-emitting element 105, thereby making The light-emitting element 105 remains flat when transferred and fixed, which improves the flatness of the array substrate.
  • the light-emitting element in the embodiment of the present disclosure may be a self-luminous device, so there is no need to use a transparent electrode, and a metal material with better conductivity may be used to achieve a lower resistivity. It should be noted that if the metal used is easily oxidized and deteriorated in the environment, it is also necessary to lay a protective layer to isolate water vapor and oxygen in the environment before the final completion of the array substrate.
  • the protective layer can be made of epoxy resin.
  • the driver chip After the array substrate is completed, the driver chip needs to be connected.
  • a flexible circuit board can be used to connect to the reserved connection position of the array substrate, or the driver chip can be directly placed in the reserved position of the array substrate, saving the cost of the circuit board and related processes.
  • this disclosure is a voltage driving method
  • a circuit can be directly fabricated on the above-mentioned array substrate to realize the function of the scan driver chip, so as to reduce the frame, The purpose of reducing costs.
  • the embodiment of the present disclosure also provides a brightness adjustment method, which is used in the above-mentioned array substrate, and the method includes:
  • the number of scans of the array substrate in one frame is determined, wherein in each scan process, each row of the array substrate is scanned once.
  • the preset first color depth bit number can be selected according to needs.
  • the first color depth bit number is 6 bits.
  • it can be determined that the number of scans of the array substrate in one frame is 64 times.
  • each row of the array substrate is scanned row by row.
  • the method further includes:
  • the corresponding relationship between the data voltage and the color depth is determined.
  • the brightness of the array substrate (which can be the average value of the brightness values of each light-emitting element) is measured by an optical instrument to form the data voltage and Correspondence of brightness value.
  • different data voltages can be selected with a voltage resolution (interval) of 5mV.
  • multiple data voltages such as 5mV, 10mV, 15mV, etc. can be selected in sequence.
  • data voltages of 16 brightness levels can be selected, thereby achieving a brightness depth of 4 bits.
  • the array substrate in the embodiment of the present disclosure can realize a 10-bit brightness depth display.
  • the multi-color depth display of the array substrate can be realized.
  • the verification product can independently control the turning on and off of each light-emitting element (group).
  • the determining the brightness values of all the light-emitting element groups in the array substrate corresponding to different data voltages includes:
  • the brightness values of the light-emitting element group corresponding to different data voltages are determined.
  • the preset correspondence between the brightness value and the current of the light-emitting element group may be as shown in FIG. 11, and the preset correspondence between the current and the voltage of the light-emitting element group may be as shown in FIG. 12.
  • FIG. 11 is a schematic diagram of the current-luminance characteristics of the light-emitting element provided by an embodiment of the disclosure
  • FIG. 12 is a schematic diagram of the current-voltage characteristics of the light-emitting element provided by the embodiment of the disclosure
  • 13 is a schematic diagram of the corresponding relationship between current-brightness and current-voltage provided by the embodiments of the disclosure.
  • step b) & step c) Combining step b) & step c), the achievable brightness depth can reach 10 bits, and the color formed by the three primary colors can reach more than 1 billion colors.
  • step e) Write the number of scans in one frame of the array substrate in step b) and the correspondence between the data voltage and color depth in step c) into the data drive chip, which can set the brightness/color depth of the image to be displayed Converted into the voltage of the data signal of each frame of the light (group) and the number of times that it is turned on.
  • the first color depth bit number constitutes the high bit number of the third color depth bit number
  • the second color depth bit number constitutes the low bit number of the third color depth bit number
  • the first color depth bit is 6 bits, which constitutes the upper 6 bits of the third color depth bit
  • the second color depth bit is 4 bits, which constitutes the lower 4 bits of the third color depth bit.
  • the color formed by the three primary colors can reach more than 1 billion colors, and the required color depth display can be determined according to the image data to be displayed, for example, a color depth display of 5bit, 8bit, etc. can be selected.
  • the image data to be displayed may be displayed in the following manner, and the method further includes:
  • the image data to be displayed is displayed according to the voltage of the data to be output and the number of first scans in one frame.
  • the display of the image data to be displayed can be realized by the number of scans in one frame.
  • the method of adjusting the data voltage in the present disclosure can be combined.
  • the input of the valid scan signal must precede the input of the valid data signal voltage, and the input of the invalid scan signal must also precede the input of the invalid data signal voltage. In some embodiments, this can be achieved through an enable signal.
  • the array substrate further includes an enable signal input terminal.
  • the method further includes:
  • FIG. 14 is a timing diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the enable signal (OE) controls the turn-on and turn-off of the scan signal of each row through the rising edge signal and the falling edge signal, and also controls the transmission period of the data signal (which can be a data voltage), where each row scan The signal is turned on before the data signal, and it is also turned off before the data signal.
  • G1 is the scan signal input in the first row
  • G2 is the scan signal input in the second row
  • Gn is the scan signal input in the second row.
  • S1 corresponds to the data signal input to each row.
  • FIG. 15 is a schematic diagram of the timing relationship between OE and G1 and S1 according to an embodiment of the present disclosure.
  • the enable signal (OE) can be divided into three independently adjustable stages OE-1, OE-2 and OE-3, which are used to control the turn-on time of G1 (the rising edge of OE1), S1 The turn-on time (the rising edge of OE-2), the turn-off time of G1 (the falling edge of OE-2), and the turn-off time of S1 (the falling edge of OE-3); in other words, in the enable signal (OE)
  • the scan signal line transmits the scan signal to the gate of the second switch tube, and the second switch tube is controlled to be turned on.
  • the data The signal line transmits the data signal to the drain of the second switch tube, and transmits it to the grid of the first switch tube through the second switch tube, and controls the first switch tube to be turned on, so that the light-emitting device group is turned on and emits light.
  • the scan signal line stops transmitting the scan signal to the gate of the second switch tube, and the second switch tube is controlled to turn off.
  • the data The signal line stops transmitting data.
  • FIG. 16 is a timing control diagram of different brightness of the light-emitting element provided by the embodiment of the present disclosure.
  • the data signal is given a positive voltage when the second switch tube is turned on to indicate that it is turned on, and a negative voltage indicates that it is turned off), so as to realize the light emission Control of different brightness of component groups.
  • FIG. 17 is a schematic diagram of a flow of brightness setting and display data output provided by an embodiment of the present disclosure.
  • FIG. 17 shows a specific example of a brightness adjustment method provided by an embodiment of the present disclosure, which includes the following steps.
  • Step 1701 Determine a preset first color depth bit number according to needs, and determine the first scan number of the array substrate in one frame according to the first color depth bit number.
  • the data driver IC (Source IC) outputs the data voltage Vi (step 1702), and then
  • the optical test equipment is used to capture the luminous intensity Li of the array substrate (step 1703), and record each set of corresponding data voltage and luminous intensity data (Vi, Li) (step 1704). Steps 1702-1704 are performed in multiple cycles, and then the curve relationship between the output data voltage (V) and the luminous intensity data (L) can be obtained, and then the V-L curve is output (step 1705).
  • the corresponding relationship between the data voltage and the color depth is determined, and a voltage value table Utable is formed, and the voltage value table Utable is stored in the data driving chip (step 1706) .
  • Step 1707 The data driving chip receives the image display data to be output, and determines the color depth bits of the image display data to be output.
  • Step 1708 when the color depth bit is less than or equal to the first color depth bit, determine the second scan number of the array substrate in one frame according to the color depth bit.
  • Step 1709 When the color depth bit number is greater than the first color depth bit number, determine the first scan number of the array substrate in one frame according to the first color depth bit number.
  • Step 1710 Determine the first number of the different data voltages according to the difference between the number of color depth bits and the first number of color depth bits.
  • Step 1711 Select the low-order bit number of the first number from the third color depth bit number, and determine the data voltage corresponding to the selected low-order bit number.
  • the first color depth bit number constitutes the high bit number of the third color depth bit number
  • the second color depth bit number constitutes the low bit number of the third color depth bit number.
  • the first color depth bit number can be selected as the high bit first, and the first scan number of the array substrate in one frame is determined.
  • the first number of the different data voltages can be determined according to the difference between the number of color depth bits and the first number of color depth bits, and the first number of the different data voltages can be selected from the third number of color depth bits.
  • the number of low-order bits of the number, and the data voltage corresponding to the selected number of low-order bits is determined.
  • the third color depth bit is 4bit
  • the image data to be displayed includes a low-bit color depth of 2bit.
  • Step 1712 Display the image data to be displayed according to the data voltage to be output and/or the number of scans in one frame.
  • steps 1707-1712 are executed cyclically, and different image data to be displayed can be displayed.
  • the data driving chip determines the voltage of each valid data signal according to the voltage value taken from the voltage value table Utable, and finally outputs the data signal, the light-emitting element group (group) is lit, and the image to be displayed is displayed.
  • the active matrix is used to control the turn-on and turn-off of the light-emitting element, which can reduce the number of control chips, and the large-area cathode and anode layered laying can minimize the voltage distortion of the signal. , Reduce the difficulty of wiring, and eliminate the problem of increased power consumption caused by line loss.
  • an embodiment further provides an array substrate, which can be prepared by the manufacturing method of the array substrate in the above embodiment, and the array substrate may include:
  • a light-emitting element group located on the second electrode layer includes one or more light-emitting elements, each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode.
  • the first electrode layer is connected, and the second electrode is connected to the second electrode layer to drive the light-emitting layer to emit light.
  • the array substrate further includes a flat layer located on a side of the light-emitting element group away from the base substrate;
  • the driving circuit layer further includes a scan signal line, a second switch tube, a data signal line, a storage capacitor, and a common electrode layer.
  • the control electrode of the first switch tube communicates with the second switch tube through the via hole.
  • the first pole of the switching tube is connected, the first pole of the second switching tube is connected to the first pole plate of the storage capacitor, the data signal line is connected to the second pole of the second switching tube, the The scan signal line is connected to the control electrode of the second switch tube, and the common electrode layer is used as the second electrode plate of the storage capacitor.
  • the driving circuit layer includes a scan signal line, a first switch tube, a second switch tube, a data signal line, a storage capacitor, and a common electrode layer.
  • the source of the first switch tube passes through the via hole and the first electrode.
  • Layer connection the drain of the first switching tube is connected to the first electrode of the light-emitting device group, the gate of the first switching tube is connected to the source of the second switching tube through a via, the The source of the second switch tube is connected to the first plate of the storage capacitor, the data signal line is connected to the drain of the second switch tube, and the scan signal line is connected to the gate of the second switch tube. ⁇ Pole connection.
  • the array substrate may further include: a second insulating layer located on the flat layer and the driving circuit layer, and the first via hole penetrates the second insulating layer and a part of the insulating layer. In the flat layer, the second via hole penetrates the second electrode layer.
  • the flat layer is made of resin material.
  • the orthographic projections of the first electrode layer and the second electrode layer on the base substrate overlap with the orthographic projections of all light-emitting elements on the base substrate.
  • the first electrode layer and the second electrode layer are laid out as a whole, and their orthographic projections on the base substrate overlap with the orthographic projections of all the light-emitting elements on the base substrate.
  • the array substrate may further include an auxiliary layer, the auxiliary layer and the second electrode layer are provided with the same layer and the same material, and are provided at an interval from the second electrode layer, and the first The electrode is arranged on the side of the auxiliary layer away from the base substrate.
  • the first electrode of the light-emitting element can be supported and heightened, so that the light-emitting device group can be kept flat when transferring and fixing, and the flatness of the array substrate can be improved.
  • the orthographic projection of the first electrode and the second electrode on the base substrate is located on the light-emitting layer on the substrate. Both sides of the orthographic projection of the substrate.
  • the light-emitting element group may be a single light-emitting element or a plurality of light-emitting elements, and when the light-emitting element group includes a plurality of light-emitting elements, the plurality of light-emitting elements are arranged in parallel or in series.
  • a single control switch can be used to control the on and off of multiple light-emitting elements.
  • the light-emitting element may be a light-emitting diode, and the light-emitting diode may be an LED, Mini-LED or Micro-LED
  • the flat layer may be made of insulating resin material, and by replacing the lamp (group) protective glue in the related art with an insulating resin with a light astigmatism function, it can play a soft light effect, improve the process accuracy, and reduce the process flow.
  • the composition of the resin material can be adjusted. For example, some components with different refractive indexes can be mixed to achieve the purpose of astigmatism. You can also adjust the overall chromaticity of the product by adding some color groups. Even by adding a certain amount of fluorescent agent, the same light-emitting element (group) can produce light of different colors.
  • the active matrix is used to control the turn-on and turn-off of the light-emitting device, which can reduce the number of control chips, and adopt large-area cathode and anode layered laying, which can minimize signal voltage distortion and reduce wiring Difficulty, while eliminating the problem of increased power consumption caused by line loss.
  • an embodiment further provides a display panel including the array substrate described in the foregoing embodiment.
  • the display panel in the embodiment of the present disclosure uses an active matrix to control the on and off of light-emitting devices. It can reduce the number of control chips and adopt large-area cathode and anode layered laying, which can minimize signal voltage distortion, reduce wiring difficulty, and eliminate the problem of increased power consumption caused by line loss.
  • the display device includes the display panel described in the above-mentioned embodiment. Reducing the number of control chips and adopting a large area of cathode and anode layered laying can minimize signal voltage distortion, reduce wiring difficulty, and eliminate the problem of increased power consumption caused by line loss.

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Abstract

一种阵列基板及其制作方法、显示面板及显示装置，阵列基板包括：衬底基板；依次设置于衬底基板上的第一电极层（101）、第一绝缘层（102）和第二电极层（103），位于在第二电极层（103）上的发光元件组（105）。发光元件组（105）包括一个或多个发光元件，每个发光元件包括第一电极（1051）、发光层和第二电极（1052），第一电极（1051）与第一电极层（101）连接，第二电极（1052）与第二电极层（103）连接，以驱动发光层发光。另外，通过调节校正步骤，能实现阵列基板的多色深度显示。

Description

阵列基板及其制作方法、显示面板及显示装置
相关申请的交叉引用
本申请主张在2020年6月23日在中国提交的中国专利申请号No.202010581627.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，具体涉及一种阵列基板及其制作方法、显示面板及显示装置。
背景技术
自发光显示器采用阵列式的微小可发光灯组，通过芯片动态控制亮暗，实现显示功能。由于自发光可以有绝对的黑态，理论上对比度可实现无穷大，无背光带来的产品厚度降低等优势都是传统透射式显示器无法比拟的。
发明内容
本公开一方面实施例提供了一种阵列基板，包括：
衬底基板；
依次设置于所述衬底基板上的第一电极层、第一绝缘层和第二电极层，
位于在所述第二电极层上的发光元件组，所述发光元件组包括一个或多个发光元件，每个发光元件包括第一电极、发光层和第二电极，所述第一电极与所述第一电极层连接，所述第二电极与所述第二电极层连接，以驱动所述发光层发光。
可选地，所述阵列基板还包括位于所述发光元件组远离所述衬底基板的一侧的平坦层；
位于所述平坦层上的驱动电路层，所述驱动电路层包括第一开关管，用于控制所述第一电极与所述第一电极层之间的关断，所述第一开关管的第一极通过第一过孔与所述辅助层连接，所述第一开关管的第二极通过第二过孔与所述第一电极层连接。
可选地，所述驱动电路层还包括扫描信号线、第二开关管、数据信号线、存储电容和公共电极层，所述第一开关管的控制极通过过孔与所述第二开关管的第一极连接，所述第二开关管的第一极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的第二极连接，所述扫描信号线与所述第二开关管的控制极连接，所述公共电极层用作所述存储电容的第二极板。
可选地，所述阵列基板还包括位于所述平坦层和所述驱动电路层的第二绝缘层，所述第一过孔贯穿所述第二绝缘层和部分所述平坦层，所述第二过孔贯穿所述第二电极层。
可选地，所述平坦层采用树脂材料制成。
可选地，所述第一电极层和所述第二电极层在所述衬底基板上的正投影与所有发光元件在所述衬底基板上的正投影重叠。
可选地，所述阵列基板还包括辅助层，所述辅助层与所述第二电极层同层同材料设置且与所述第二电极层间隔设置，所述第一电极设置在所述辅助层远离所述衬底基板的一侧。
可选地，所述第一电极和所述第二电极在所述衬底基板上的正投影位于所述发光层在所述衬底基板的正投影的两侧。
可选地，在所述发光元件组包括多个发光元件的情况下，所述多个发光元件并联或串联设置。
本公开再一方面实施例提供了一种显示面板，包括：如上所述的阵列基板。
本公开又一方面实施例提供了一种显示装置，包括：如上所述的显示面板。
本公开又一方面实施例提供了一种阵列基板的制作方法，包括：
在衬底基板上依次形成第一电极层、第一绝缘层和第二电极层；
在所述第二电极层远离所述衬底基板的一侧形成发光元件组，所述发光元件组包括单个发光元件或多个发光元件，每个发光元件包括第一电极、发光层和第二电极，所述第一电极与所述第一电极层连接，所述第二电极与所述第二电极层连接，以驱动所述发光层发光。
可选地，所述方法还包括：
在所述发光元件组远离所述衬底基板的一侧形成平坦层；
在所述平坦层远离所述衬底基板的一侧形成驱动电路层，所述驱动电路层包括第一开关管，用于控制所述第一电极与所述第一电极层之间的关断，所述第一开关管的第一极通过第一过孔与所述辅助层连接，所述第一开关管的第二极通过第二过孔与所述第一电极层连接。
可选地，所述驱动电路层还包括扫描信号线、第二开关管和存储电容，
所述在所述发光元件组远离所述衬底基板的一侧形成平坦层之后，所述方法还包括：
在所述平坦层远离所述衬底基板的一侧形成所述扫描信号线、所述第一开关管的控制极和所述第二开关管的控制极；
形成第二绝缘层；
在所述第二绝缘层远离所述衬底基板的一侧形成半导体层；
在所述半导体层远离所述衬底基板的一侧形成数据信号线、所述第一开关管的第一极和第二极、所述第二开关管的第一极和第二极以及存储电容的第一极板；所述第一开关管的第一极通过过孔与第一电极层连接，所述第一开关管的第二极与所述发光元件的第一电极连接，所述第一开关管的控制极通过过孔与所述第二开关管的第一极连接，所述第二开关管的第一极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的第二极连接，所述扫描信号线与所述第二开关管的控制极连接；
形成第三绝缘层和公共电极层，所述公共电极层构成所述存储电容的第二极板，所述公共电极层和所述存储电容的第一极板在所述衬底基板上的正投影至少部分重叠。
可选地，形成所述第二电极层，包括：
采用同一掩膜板同一构图工艺同时形成所述第二电极层和辅助层，所述辅助层与所述第二电极层间隔设置，所述第一电极设置在所述辅助层远离所述衬底基板的一侧。
可选地，所述平坦层采用树脂材料制成。
本公开又一方面实施例提供了一种亮度调节方法，用于如上所述的阵列基板，所述方法包括：
根据预设的第一色彩深度位数，确定所述阵列基板在一帧内的第一扫描次数，其中，在每一次扫描过程中，对所述阵列基板的每一行均进行一次扫描。
可选地，所述方法还包括：
通过给所述阵列基板中各第二开关管的控制极输入扫描信号，开启所述各第二开关管；
通过给所述第二开关管的第二极输入不同的数据电压；
确定不同的数据电压所对应的所述阵列基板中所有发光元件组的亮度值，并建立数据电压与所述亮度值之间的对应关系；其中，所述不同的数据电压的个数根据预设第二色彩深度位数确定，所述第一色彩深度位数和所述第二色彩深度位数组成第三色彩深度位数；
根据亮度值与色彩深度的预设对应关系，确定所述数据电压与色彩深度之间的对应关系。
可选地，所述确定不同的数据电压所对应的所述阵列基板中所有发光元件组的亮度值，包括：
根据所述发光元件组的亮度值与电流的预设对应关系和所述发光元件组的电流和电压的预设对应关系，确定不同的数据电压所对应的所述发光元件组的亮度值。
可选地，所述第一色彩深度位数构成所述第三色彩深度位数的高位比特数，所述第二色彩深度位数构成所述第三色彩深度位数的低位比特数。
可选地，所述方法还包括：
接收待显示的图像数据；
确定所述待显示的图像数据的色彩深度位数；
在所述色彩深度位数小于或等于所述第一色彩深度位数时，根据所述色彩深度位数，确定所述阵列基板在一帧内的第二扫描次数；
在所述色彩深度位数大于所述第一色彩深度位数时，根据第一所述色彩深度位数，确定所述阵列基板在一帧内的所述第一扫描次数；
根据所述色彩深度位数与所述第一色彩深度位数的差值确定所述不同数据电压的第一个数；
在所述第三色彩深度位数中选取所述第一个数的低位比特数，并确定选取的低位比特数对应的待输出数据电压；及
根据所述待输出数据电压和/或一帧内的第一扫描次数显示所述待显示的图像数据。
可选地，所述阵列基板还包括使能信号输入端，在对阵列基板的每一行进行扫描时，所述方法还包括：
向所述使能信号输入端输入使能信号；
在所述使能信号第一个上升沿时刻给每一行中的各第二开关管控制极输入有效扫描信号，开启所述各第二开关管；
在所述使能信号第二个上升沿时刻给每一行中的各第二开关管第二极输入有效数据电压；
经过预设时间段后，在所述使能信号第一个下降沿时刻给每一行中的各第二开关管控制极输入非有效扫描信号；及
在所述使能信号第二个下降沿时刻给每一行中的各第二开关管第二极输入非有效数据电压。
附图说明
图1为本公开实施例提供的一种阵列基板的制作方法的流程示意图；
图2为本公开实施例提供的形成第一电极层和第二电极层的示意图；
图3为本公开实施例提供的在第二电极层上形成或放置发光器件组的示意图；
图4为本公开实施例提供的像素电路的示意图；
图5为本公开实施例提供的形成驱动电路层的示意图之一；
图6为本公开实施例提供的形成驱动电路层的示意图之二；
图7为本公开实施例提供的形成驱动电路层的示意图之三；
图8为本公开实施例提供的阵列基板的结构示意图；
图9为图8中沿A-A的剖面示意图；
图10为图8中沿B-B的剖面示意图；
图11为本公开实施例提供的发光器件组的电流-亮度特性的示意图；
图12为本公开实施例提供的发光器件组的电流-电压特性的示意图；
图13为本公开实施例提供的电流-亮度与电流-电压的对应关系示意图；
图14为本公开实施例提供的的像素电路的时序图；
图15为本公开实施例提供的OE与G1、S1的时序关系示意图；
图16为本公开实施例提供的发光器件组的不同亮度的时序控制图；
图17为本公开实施例提供的亮度设定和显示数据输出的流程示意图；
图18为本公开实施例提供的阵列基板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
由于自发光显示器的发光组件基本都是以电流驱动的功率部件，一般的单一有源矩阵开关无法实现驱动功能。如果使用无源驱动方式，需要为每一个灯(组)至少配备一条驱动线，需要等比例的驱动芯片，并且大大增加了布线难度。
另外，电流驱动带来很大的引线损耗，即常说的IR Drop，此问题会影响发光灯(组)的正常工作，也会带来产品功耗的上升，以目前常见的玻璃基自发光产品为例，线损的占比可以达到整个产品总功耗的10％～25％。
请参考图1，为本公开实施例提供的一种阵列基板的制作方法的流程示意图。如图1所示，本公开实施例提供一种阵列基板的制作方法，所述制作方法可以包括以下步骤：
步骤11：在衬底基板上依次形成第一电极层、第一绝缘层和第二电极层。
在一些实施例中，所述第一电极层和所述第二电极层整层铺设。
请参考图2，为本公开实施例提供的形成第一电极层和第二电极层的示意图。如图2所示，本步骤中，在衬底基板上铺设第一电极层101，第一电极层101可以为整层铺设，然后通过湿刻工艺制作出显示区域、柔性电路板/驱 动芯片连接引脚以及后续工艺的对位标识等。然后，在第一电极层101上铺设绝缘保护层(即第一绝缘层)，绝缘保护层可以采用树脂或氮硅化合物，其中，如果使用感光树脂，需要在之后进行曝光显影，形成连接孔，如果使用氮硅化合物，则可以通过后期一次干法刻蚀将若干绝缘保护层在同一位置形成一个连接孔。接着，继续铺设第二电极层103，第二电极层103同样可以整层铺设，通过湿法刻蚀的方法，制作出显示区域、柔性电路板/驱动芯片连接引脚、上层电路连接孔等。
本公开实施例中，第一电极层101可以作为阳极，而第二电极层103可以作为阴极，通过采用大面积阴阳极分层铺设，可以最大程度降低产品信号的电压失真(IP drop)，降低布线难度，同时消除了线损带来的功耗上升问题。
步骤12：在所述第二电极层远离所述衬底基板的一侧形成至少一个发光元件组，所述发光元件组包括一个或多个发光元件，每个发光元件包括第一电极、发光层和第二电极，所述第一电极与所述第一电极层连接，所述第二电极与所述第二电极层连接，以驱动所述发光层发光。
并在所述发光元件远离所述衬底基板的一侧形成平坦层，所述发光器件组的第二电极与所述第二电极层连接。
请参考图3，为本公开实施例提供的在第二电极层上形成至少一个发光元件组的示意图。如图3所示，本公开实施例中，可以通过蒸镀、印刷等方式直接在第二电极层103上形成发光元件组105，也可以将在硅基等其他基材上形成的至少一个发光元件组105通过(巨量)转移等方式放置在第二电极层103上。发光元件组105包括第一电极1051和第二电极1052，其中，第一电极1051可以发光元件105的阳极，第二电极1052可以发光元件105的阴极。发光元件105的第二电极1052直接与第二电极层103连接。
在一些实施例中，所述方法还包括：
在所述发光元件组远离所述衬底基板的一侧形成平坦层；
在所述平坦层远离所述衬底基板的一侧形成驱动电路层，所述驱动电路层包括第一开关管，用于控制所述第一电极与所述第一电极层之间的关断，所述第一开关管的第一极通过第一过孔与所述辅助层连接，所述第一开关管的第二极通过第二过孔与所述第一电极层连接。
而后，在发光元件组105远离所述衬底基板的一侧形成平坦层，平坦层用于对发光元件组105进行覆盖保护，并形成相对平坦的表面，便于后续工序的进行。
本公开实施例中，在发光元件组105包括多个发光元件时，所述多个发光元件可以并联或者串联设置，通过将多个发光元件并联或串联设置，可以实现利用单个控制开关控制多个发光元件的开启和关闭。所述发光元件可以为发光二极管，所述的发光二极管可以是LED、Mini-LED或者Micro-LED。
通常，所述发光元件组占整个显示区域的面积只有10％～40％，即发光源是比较分散和稀疏的，与相关技术中的透射式显示器相比，亮度的连续性并不好，需要涂覆保护胶，起到柔化光线和保护发光元件的目的。本公开实施例中，所述平坦层可以采用树脂材料形成。通过将具有散光功能的绝缘树脂代替相关技术中的保护胶，可以起到柔光作用，提高工艺精度，减少工艺流程。其中，根据发光元件组105的柔光需要，可以对树脂材料的成分进行调配，例如混入一些不同折射率的成分，可以达到散光的目的，还可以通过加入一些色组，对产品的整体色度进行调整，甚至，还可以通过加入一定量的荧光剂，实现相同发光元件(组)产生不同颜色的光。
在一些实施例中，所述驱动电路层还包括扫描信号线、第二开关管和存储电容，
所述在所述发光元件组远离所述衬底基板的一侧形成平坦层之后，所述方法还包括：
在所述平坦层远离所述衬底基板的一侧形成所述扫描信号线、所述第一开关管的控制极和所述第二开关管的控制极；
形成第二绝缘层；
在所述第二绝缘层远离所述衬底基板的一侧形成半导体层；
在所述半导体层远离所述衬底基板的一侧形成数据信号线、所述第一开关管的第一极和第二极、所述第二开关管的第一极和第二极以及存储电容的第一极板；所述第一开关管的第一极通过过孔与第一电极层连接，所述第一开关管的第二极与所述发光元件的第一电极连接，所述第一开关管的控制极通过过孔与所述第二开关管的第一极连接，所述第二开关管的第一极与所述 存储电容的第一极板连接，所述数据信号线与所述第二开关管的第二极连接，所述扫描信号线与所述第二开关管的控制极连接；
形成第三绝缘层和公共电极层，所述公共电极层构成所述存储电容的第二极板，所述公共电极层和所述存储电容的第一极板在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述驱动电路层包括扫描信号线、第一开关管、第二开关管、数据信号线、存储电容和公共电极层，所述第一开关管的源极通过过孔与第一电极层连接，所述第一开关管的漏极与所述发光器件组的第一电极连接，所述第一开关管的栅极通过过孔与所述第二开关管的源极连接，所述第二开关管的源极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的漏极连接，所述扫描信号线与所述第二开关管的栅极连接，所述公共电极层用作所述存储电容的第二极板。
请参考图4，为本公开实施例提供的像素电路的示意图。如图4所示，本公开实施例中，像素电路包括一组用于提供电流的阳极和阴极，对应于上述的第一电极层101和第二电极层103，还包括第一开关管T1、第二开关管T2和存储电容C，其中，第一开关管T1的源极与阳极连接，第一开关管T1的漏极与发光元件组105的第一电极1051连接，发光元件组105的第二电极1052与阴极连接，第一开关管T1的栅极与存储电容C的第一极板连接，存储电容C的第二极板与公共电极110连接，第二开关管T2的源极分别与第一开关管T1的栅极和存储电容C的第一极板连接，第二开关管T2的漏极与数据信号线连接，第二开关管T2的栅极与扫描信号线连接。
第一开关管T1用于控制发光元件组105的开启和关闭，而存储电容C则用于保持第一开关管T1的栅极电压，继而使发光元件组105保持开启/关闭，第二开关管T2用于控制第一开关管T1的导通或关闭，具体来说，第二开关管T2的栅极接收扫描信号线传来的扫描信号，而第二开关T2的漏极接收数据信号线传来的数据信号，用于在扫描信号和数据信号的控制下实现第一开关管T1的导通或关闭。
本公开实施例中，所述形成驱动电路层的步骤，具体可以包括如下步骤。
首先，形成位于所述平坦层上的扫描信号线、第一开关管和第二开关管 的栅极，所述扫描信号线与所述第二开关管的栅极连接。
请参考图5，为本公开实施例提供的形成驱动电路层的示意图之一。如图5所示，在覆盖发光器件组105的平坦层上铺设一层金属，并通过湿法刻蚀工艺形成扫描信号线111、第一开关管T1的栅极1124和第二开关管T2的栅极1134。
进一步的，还可以在扫描信号线111上铺设保护层(即第二绝缘层)，所述保护层可以采用氮硅化合物。
其次，形成位于所述栅极远离所述衬底基板的一侧的有源层。
请参考图6，为本公开实施例提供的形成驱动电路层的示意图之二。如图6所示，继续在第一开关管T1的栅极1124远离所述衬底基板的一侧形成第一开关管T1的有源层1123和在第二开关管T2的栅极1134远离所述衬底基板的一侧形成第二开关管T2的有源层1133。
考虑到本实施例中为电流驱动的自发光元件，需要较大的开启电流，举例来说，假定本公开实施例中的发光元件组105包括9颗串联设置的LED灯，则预估导通电流约为20mA，则采用多晶硅形成第一开关管T1有源层时，需要的宽长比大约为1000。而考虑到发光元件组105所占面积比例不高，这样的宽长比的有源层有足够的空间布置开来，而对于第二开关管T2而言，相关技术中的宽长比设置即可满足要求(通常宽长比小于10即可)。当然，上述描述仅为示例性的，发光元件组105中的LED等的数量可以增加或减少，相对应的，有源层的宽长比也将对应改变。
再次，形成数据信号线、所述第一开关管和所述第二开关管的源极和漏极以及存储电容的第一极板，所述第一开关管的源极通过过孔与第一电极层连接，所述第一开关管的漏极通过过孔与所述发光器件组的第一电极连接，所述第一开关管的栅极通过过孔与所述第二开关管的源极连接，所述第二开关管的漏极与所述存储电容的第一极板同层连接，所述数据信号线与所述第二开关管的漏极同层连接。
请参考图7，为本公开实施例提供的形成驱动电路层的示意图之三。如图7所示，进一步铺设一层金属层，并通过湿法刻蚀工艺形成数据信号线114、第一开关管T1的源极1121和漏极1122、第二开关管T2的源极1131和漏极 1132以及存储电容C的第一极板C1，其中，数据信号线114与第二开关管T2的漏极1132连接，而第二开关管T2的源极1131则直接与存储电容C的第一极板C1连接，第一开关管T1的源极1121通过第二过孔1092与第一电极层101连接，而第一开关管T1的漏极1122则通过第一过孔1091与发光元件组105的第一电极1051连接，第一开关管T1的栅极1124则通过过孔与存储电容C的第一极板C1连接。
最后，依次形成第三绝缘层和公共电极层，所述公共电极层构成所述存储电容的第二极板，所述公共电极层和所述存储电容的第一极板在所述衬底基板上的正投影至少部分重叠。
请参考图8，为本公开实施例提供的阵列基板的结构示意图。如图8所示，继续形成第三绝缘层，用于覆盖保护数据信号线114等，所述第三绝缘层可以采用树脂材料，也可以采用氮硅化合物。然后铺设公共电极层110，公共电极层110在存储电容C的第一极板C1的正上方的部分形成为存储电容C的第二极板C2；存储电容C的大小主要由扫描周期、第二开关管T2的关态电流，以及第一开关管T1的电流-电压特性共同决定，也即根据上述因素调整存储电容C的极板大小以得到合适的电容量。
为更清楚的了解本公开实施例中各层的层叠设置关系，请参考图9和图10，图9为图8中沿A-A的剖面示意图，图10为图8中沿B-B的剖面示意图。
如图9所示，第一开关管T1的栅极1124则通过绝缘层114上开设的过孔与第二开关管T2的源极1131(同时也是存储电容C的第一极板C1)连接，第二开关管T2的源极1131(同时也是存储电容C的第一极板C1)与第二绝缘层115上方的公共电极层110共同构成存储电容C，也即位于存储电容C的第一极板C1上方的公共电极层110同时也是存储电容C的第二极板C2。
如图10所示，阵列基板包括位于衬底基板上的第一电极层101(本实施例中作为阳极)、位于第一电极层101上的第一绝缘层102，位于第一绝缘层102上的第二电极层103(本实施例中作为阴极)，位于第二电极层103上的发光元件组105，其中发光元件组105的第二电极1052直接与第二电极层 103连接，而后是覆盖在发光元件组105上的平坦层106(采用树脂材料)，然后是第三绝缘层107,以及位于第三绝缘层107上的公共电极层110，其中，第一开关管T1的漏极1122通过第一过孔1091与发光元件组105的第一电极1051连接，而第一开关管T1的源极1021通过第二过孔1092与第一电极层101连接。
在一些实施例中，形成所述第二电极层，包括：
采用同一掩膜板同一构图工艺同时形成所述第二电极层和辅助层，所述辅助层与所述第二电极层间隔设置，所述第一电极设置在所述辅助层远离所述衬底基板的一侧。
本公开实施例中，形成所述第二电极层的同时，形成辅助层，所述发光元件组的第一电极设置在所述辅助层上。
如图10所示，在整层铺设第二电极层103时，通过湿法刻蚀的方法，形成辅助层104。也即辅助层104与第二电极层103为同层同材料设置，但是两者之间相互间隔开，利用辅助层104可以对发光元件105的第一电极1051起到支撑垫高作用，从而使得发光元件105转移固定时保持平整，提高阵列基板的平坦度。
在一些实施例中，本公开实施例中的发光元件可以为自发光器件，从而并不需要使用透明电极，可以使用导电性更好的金属材质，以达到更低的电阻率。需要注意的是，如果采用的金属容易在环境中氧化变质，还需要在阵列基板最终完成前，铺设一层保护层隔绝环境中的水汽氧气等，所述保护层可以使用环氧树脂制成。
阵列基板完成后，需要连接驱动芯片，可以使用柔性电路板与阵列基板预留的连接位置相连，也可以直接将驱动芯片安置在阵列基板预留位置，节省掉电路板的费用和相关工艺。更进一步的，扫描驱动芯片由于设计相对简单，且不再需要考虑功率因素(本公开为电压驱动的方式)，可以直接在上述阵列基板上制作电路实现扫描驱动芯片功能，以达到减小边框、降低成本的目的。
本公开实施例还提供一种亮度调节方法，用于如上所述的阵列基板，所述方法包括：
根据预设的第一色彩深度位数，确定所述阵列基板在一帧内的扫描次数，其中，在每一次扫描过程中，对所述阵列基板的每一行均进行一次扫描。
在一些实施例中，可以根据需要选择预设的第一色彩深度位数，例如，第一色彩深度位数为6bit，此时，可以确定所述阵列基板在一帧内的扫描次数为64次。其中，在每一次扫描过程中，对所述阵列基板的各行进行逐行扫描。
在一些实施例中，还可以通过调节输入的数据电压，实现更多位数的色彩深度，所述方法还包括：
通过给所述阵列基板中各第二开关管的控制极输入扫描信号，开启所述各第二开关管；
通过给所述第二开关管的第二极输入不同的数据电压；
确定不同的数据电压所对应的所述阵列基板中所有发光元件组的亮度值，并建立数据电压与所述亮度值之间的对应关系；其中，所述不同的数据电压的个数根据预设第二色彩深度位数确定，所述第一色彩深度位数和所述第二色彩深度位数组成第三色彩深度位数；
根据亮度值与色彩深度的预设对应关系，确定所述数据电压与色彩深度之间的对应关系。
具体地，通过输入不同的数据电压，一帧内所有发光元件(组)保持点亮，利用光学仪器测量出阵列基板的亮度(可以为各发光元件的亮度值的平均值)，形成数据电压与亮度值的对应关系。在一些实施例中，可以以5mV的电压分辨率(间隔)选取不同的数据电压，例如可以依次选取5mV、10mV、15mV……等多个数据电压。在一些实施例中，可以选取出16个亮度等级的数据电压，从而又实现了4bit的亮度深度。此时，结合上述通过阵列基板在一帧内的扫描次数，本公开实施例中的阵列基板可以实现10bit的亮度深度显示。
下面，通过调节校正步骤，可以实现所述阵列基板的多色深度显示。
a)通过简单地开启和关闭，验证产品可以实现独立控制每个发光元件(组)的开启、关闭。
b)接下来，在一帧内进行多次扫描，通过每次扫描数据信号电压的高低，控制发光元件(组)在一帧内开启和关闭的时间占比。假设一帧内可以进行 64次扫描，原理上可以实现每个发光元件(组)的64级亮度可调，即实现了6bit亮度深度。
c)通过输入不同的数据电压，一帧内所有发光元件(组)保持点亮，利用光学仪器测量出阵列基板的亮度(可以为各发光元件的亮度值的平均值)，形成数据电压与亮度值的对应关系。
在一些实施例中，所述确定不同的数据电压所对应的所述阵列基板中所有发光元件组的亮度值，包括：
根据所述发光元件组的亮度值与电流的预设对应关系和所述发光元件组的电流和电压的预设对应关系，确定不同的数据电压所对应的所述发光元件组的亮度值。
在一些实施例中，所述发光元件组的亮度值与电流的预设对应关系可以如图11所示，所述发光元件组的电流和电压的预设对应关系可以如图12所示。
请参考图11、图12以及图13，图11为本公开实施例提供的发光元件的电流-亮度特性的示意图，图12为本公开实施例提供的发光元件的电流-电压特性的示意图，图13为本公开实施例提供的电流-亮度与电流-电压的对应关系示意图。接下来，通过给入不同数据信号电压，帧内所有发光元件(组)保持点亮，利用光学仪器测量出产品的亮度，最终形成数据信号电压与产品亮度的对应关系，从而通过给入不同电压得到不同发光强度；选取容易控制(通常，数据驱动芯片输出的电压分辨率可以达到5mV以内)的电压，例如可以选取出16个亮度等级的控制电压，即又实现了4bit的亮度深度；
d)结合步骤b)&步骤c)，可以实现的亮度深度达到10bit，由三基色混色形成颜色可以达到10亿色以上。
e)将步骤b)的所述阵列基板在一帧内的扫描次数以及步骤c)的所述数据电压与色彩深度之间的对应关系写入数据驱动芯片，可以把待显示画面亮度/色彩深度转化为该灯(组)每帧数据信号的电压以及开启的次数。
在一些实施例中，所述第一色彩深度位数构成所述第三色彩深度位数的高位比特数，所述第二色彩深度位数构成所述第三色彩深度位数的低位比特数。
例如，第一色彩深度位数为6bit，构成第三色彩深度位数的高6位，第二色彩深度位数为4bit，构成第三色彩深度位数的低4位。
由于本公开可以实现10bit的色彩深度显示，由三基色混色形成颜色可以达到10亿色以上，可以根据待显示的图像数据确定需要的色彩深度显示，如，选择5bit、8bit等的色彩深度显示。
在一些实施例中，可以根据如下方式显示待显示的图像数据，所述方法还包括：
接收待显示的图像数据；
确定所述待显示的图像数据的色彩深度位数；
在所述色彩深度位数小于或等于所述第一色彩深度位数时，根据所述色彩深度位数，确定所述阵列基板在一帧内的第二扫描次数；
在所述色彩深度位数大于所述第一色彩深度位数时，根据第一所述色彩深度位数，确定所述阵列基板在一帧内的所述第一扫描次数；
根据所述色彩深度位数与所述第一色彩深度位数的差值确定所述不同数据电压的第一个数；
在所述第三色彩深度位数中选取所述第一个数的低位比特数，并确定选取的低位比特数对应的待输出数据电压；及
根据所述待输出数据电压及一帧内的第一扫描次数显示所述待显示的图像数据。
具体地，在所述待显示的图像数据的色彩深度位数较少时，可以选择通过一帧内的扫描次数实现该待显示的图像数据的显示。在所述待显示的图像数据的色彩深度位数较大，且超过所述第一色彩深度位数时，可以结合本公开中调节数据电压的方式。
在一些实施例中，对于每一个发光元件(组)，其有效扫描信号的输入要先于有效数据信号电压的输入，非有效扫描信号的输入也要先于非有效数据信号电压的输入。在一些实施例中，这可以通过使能信号来实现。
具体地，所述阵列基板还包括使能信号输入端，在对阵列基板的每一行进行扫描时，所述方法还包括：
向所述使能信号输入端输入使能信号；
在所述使能信号第一个上升沿时刻给每一行中的各第二开关管控制极输入有效扫描信号，开启所述各第二开关管；
在所述使能信号第二个上升沿时刻给每一行中的各第二开关管第二极输入有效数据电压；
经过预设时间段后，在所述使能信号第一个下降沿时刻给每一行中的各第二开关管控制极输入非有效扫描信号；及
在所述使能信号第二个下降沿时刻给每一行中的各第二开关管第二极输入非有效数据电压。
请参考图14，为本公开实施例提供的像素电路的时序图。如图14所示，使能信号(OE)通过上升沿信号和下降沿信号控制每一行扫描信号的开启和关闭，同时也控制数据信号(可以为数据电压)的传输周期，其中，每一行扫描信号先于数据信号开启，也先于数据信号关闭。其中，G1为第一行输入的扫描信号，G2为第二行输入的扫描信号，Gn为第二行输入的扫描信号。这里，S1对应输入各行的数据信号。
请参考图15，为本公开实施例提供的OE与G1、S1的时序关系示意图。如图15所示，使能信号(OE)可以分为三个独立可调的阶段OE-1、OE-2和OE-3，分别用来控制G1的开启时间(OE1的上升沿)、S1的开启时间(OE-2的上升沿)、G1的关闭时间(OE-2的下降沿)、S1的关闭时间(OE-3的下降沿)；也就是说，在使能信号(OE)的第一个上升沿时刻，使扫描信号线传输扫描信号至第二开关管的栅极，控制第二开关管导通，而后，在使能信号(OE)的第二个上升沿时刻，使数据信号线传输数据信号至第二开关管的漏极，并经由第二开关管传输至第一开关管的栅极，控制第一开关管导通，从而发光器件组导通发光。在使能信号(OE2)的下降沿时刻，使扫描信号线停止传输扫描信号至第二开关管的栅极，控制第二开关管关闭，在使能端(OE3)的下降沿时刻，使数据信号线停止传输数据。
请参考图16，为本公开实施例提供的发光元件的不同亮度的时序控制图。如图16所示，通过改变一帧之内每次扫描时第一开关管开启的次数(数据信号在第二开关管开启时给入正电压表明开启，负电压表明关闭)，从而实现对发光元件组的不同亮度的控制。
请参考图17，为本公开实施例提供的亮度设定和显示数据输出的流程示意图。
图17所示为本公开实施例提供的亮度调节方法的一个具体举例，其包括如下步骤。
步骤1701，根据需要，确定预设的第一色彩深度位数，并根据第一色彩深度位数确定所述阵列基板在一帧内的第一扫描次数。
数据驱动芯片(Source IC)输出数据电压Vi(步骤1702)，然后
利用光学测试设备捕捉阵列基板的发光强度Li(步骤1703)，记录每一组对应的数据电压和发光强度数据(Vi，Li)(步骤1704)。多次循环执行步骤1702-1704，继而可以得到输出数据电压(V)与发光强度数据(L)之间的曲线关系，然后输出V-L曲线(步骤1705)。
而后，根据亮度值与色彩深度的预设对应关系，确定所述数据电压与色彩深度之间的对应关系，并形成电压值表Utable，将该电压值表Utable存入数据驱动芯片(步骤1706)。
步骤1707，数据驱动芯片接收到待输出的图像显示数据，并确定待输出的图像显示数据的色彩深度位数。
步骤1708，在所述色彩深度位数小于或等于所述第一色彩深度位数时，根据所述色彩深度位数，确定所述阵列基板在一帧内的第二扫描次数。
步骤1709，在所述色彩深度位数大于所述第一色彩深度位数时，根据第一所述色彩深度位数，确定所述阵列基板在一帧内的第一扫描次数。
步骤1710，根据所述色彩深度位数与所述第一色彩深度位数的差值确定所述不同数据电压的第一个数。
步骤1711，在所述第三色彩深度位数中选取所述第一个数的低位比特数，并确定选取的低位比特数对应的数据电压。
在一些实施例中，所述第一色彩深度位数构成所述第三色彩深度位数的高位比特数，所述第二色彩深度位数构成所述第三色彩深度位数的低位比特数。在所述色彩深度位数大于所述第一色彩深度位数时，可以先选择第一色彩深度位数为高位，并确定阵列基板在一帧内的第一扫描次数。之后，可以根据所述色彩深度位数与所述第一色彩深度位数的差值确定所述不同数据电 压的第一个数，及在所述第三色彩深度位数中选取所述第一个数的低位比特数，并确定选取的低位比特数对应的数据电压。例如，第三色彩深度位数为4bit，待显示的图像数据包括2bit的低位色彩深度，此时，可以在在第三色彩深度位数中依次选择2bit进行显示，并根据确定的2bit色彩深度确定对应的待输出数据电压。
步骤1712，根据所述待输出数据电压和/或一帧内的扫描次数显示所述待显示的图像数据。
其中，循环执行步骤1707-1712，可以显示不同的待显示的图像数据。
数据驱动芯片根据电压值表Utable中取出的电压值，决定每次有效数据信号的电压，最终输出数据信号，发光元件组(组)点亮，显示所述待显示的图像。
根据本公开实施例的阵列基板的制作方法，利用有源矩阵控制发光元件的开启和关闭，能够减少控制芯片的数量，采用大面积的阴、阳极分层铺设，可以最大程度降低信号的电压失真，降低布线难度，同时消除了线损带来的功耗上升的问题。
本公开另一方面实施例还提供了一种阵列基板，所述阵列基板可以通过上述实施例中的阵列基板的制作方法制备得到，所述阵列基板可以包括：
衬底基板；
依次设置于所述衬底基板上的第一电极层、第一绝缘层和第二电极层；
位于在所述第二电极层上的发光元件组，所述发光元件组包括一个或多个发光元件，每个发光元件包括第一电极、发光层和第二电极，所述第一电极与所述第一电极层连接，所述第二电极与所述第二电极层连接，以驱动所述发光层发光。
在一些实施例中，所述阵列基板还包括位于所述发光元件组远离所述衬底基板的一侧的平坦层；
位于所述平坦层上的驱动电路层，所述驱动电路层包括第一开关管，用于控制所述第一电极与所述第一电极层之间的关断，所述第一开关管的第一极通过第一过孔与所述辅助层连接，所述第一开关管的第二极通过第二过孔与所述第一电极层连接。
在一些实施例中，所述驱动电路层还包括扫描信号线、第二开关管、数据信号线、存储电容和公共电极层，所述第一开关管的控制极通过过孔与所述第二开关管的第一极连接，所述第二开关管的第一极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的第二极连接，所述扫描信号线与所述第二开关管的控制极连接，所述公共电极层用作所述存储电容的第二极板。
具体地，所述驱动电路层包括扫描信号线、第一开关管、第二开关管、数据信号线、存储电容和公共电极层，所述第一开关管的源极通过过孔与第一电极层连接，所述第一开关管的漏极与所述发光器件组的第一电极连接，所述第一开关管的栅极通过过孔与所述第二开关管的源极连接，所述第二开关管的源极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的漏极连接，所述扫描信号线与所述第二开关管的栅极连接。
在本公开的一些实施例中，所述阵列基板还可以包括：位于所述平坦层和所述驱动电路层的第二绝缘层，所述第一过孔贯穿所述第二绝缘层和部分所述平坦层，所述第二过孔贯穿所述第二电极层。
在本公开的一些实施例中，所述平坦层采用树脂材料制成。
在本公开的一些实施例中，所述第一电极层和所述第二电极层在所述衬底基板上的正投影与所有发光元件在所述衬底基板上的正投影重叠。
如图18所示，第一电极层和第二电极层整层铺设，其在所述衬底基板上的正投影与所有发光元件在所述衬底基板上的正投影重叠。
图18中，101为第一电极层，103为第二电极层，P11、P12……等代表各像素，1092代表在第二电极层103上开设的第二过孔，1801为扫描驱动芯片(Gate IC)，1802代表数据驱动芯片(Source IC)。在本公开的一些实施例中，所述阵列基板还可以包括辅助层，所述辅助层与所述第二电极层同层同材料设置且与所述第二电极层间隔设置，所述第一电极设置在所述辅助层远离所述衬底基板的一侧。
通过增设辅助层，可以对发光元件的第一电极起到支撑垫高作用，从而使得发光器件组转移固定时保持平整，提高阵列基板的平坦度。
在本公开的一些实施例中，如图3、5-7所示，所述第一电极和所述第二 电极在所述衬底基板上的正投影位于所述发光层在所述衬底基板的正投影的两侧。
本公开实施例中，所述发光元件组可以为单个发光元件或多个发光元件，在所述发光元件组包括多个发光元件时，所述多个发光元件并联或串联设置。通过将多个发光元件并联或串联设置，可以实现利用单个控制开关控制多个发光元件的开启和关闭。所述发光元件可以为发光二极管，所述的发光二极管可以是LED、Mini-LED或者Micro-LED
本公开实施例中，所述平坦层可以采用绝缘树脂材料，通过采用具有散光功能的绝缘树脂代替相关技术中的灯(组)保护胶，可以起到柔光作用，提高工艺精度，减少工艺流程。根据发光元件组的柔光需要，可以对树脂材料的成分进行调配，例如混入一些不同折射率的成分，可以达到散光的目的，还可以通过加入一些色组，对产品的整体色度进行调整，甚至，还可以通过加入一定量的荧光剂，实现相同发光元件(组)产生不同颜色的光。
根据本公开实施例的阵列基板，利用有源矩阵控制发光器件的开启和关闭，能够减少控制芯片的数量，采用大面积的阴、阳极分层铺设，可以最大程度降低信号的电压失真，降低布线难度，同时消除了线损带来的功耗上升的问题。
本公开再一方面实施例还提供了一种显示面板，所述显示面板包括上述实施例中所述的阵列基板，本公开实施例中的显示面板利用有源矩阵控制发光器件的开启和关闭，能够减少控制芯片的数量，采用大面积的阴、阳极分层铺设，可以最大程度降低信号的电压失真，降低布线难度，同时消除了线损带来的功耗上升的问题。
本公开又一方面实施例提供了一种显示装置，所述显示装置包括上述实施例中所述的显示面板，本公开实施例中的显示装置利用有源矩阵控制发光器件的开启和关闭，能够减少控制芯片的数量，采用大面积的阴、阳极分层铺设，可以最大程度降低信号的电压失真，降低布线难度，同时消除了线损带来的功耗上升的问题。
以上所述是本公开的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和 润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种阵列基板，包括：
    衬底基板；
    依次设置于所述衬底基板上的第一电极层、第一绝缘层和第二电极层，
    位于在所述第二电极层上的发光元件组，所述发光元件组包括一个或多个发光元件，每个发光元件包括第一电极、发光层和第二电极，所述第一电极与所述第一电极层连接，所述第二电极与所述第二电极层连接，以驱动所述发光层发光。
  2. 根据权利要求1所述的阵列基板，还包括位于所述发光元件组远离所述衬底基板的一侧的平坦层；
    位于所述平坦层上的驱动电路层，所述驱动电路层包括第一开关管，用于控制所述第一电极与所述第一电极层之间的关断，所述第一开关管的第一极通过第一过孔与所述辅助层连接，所述第一开关管的第二极通过第二过孔与所述第一电极层连接。
  3. 根据权利要求2所述的阵列基板，其中，所述驱动电路层还包括扫描信号线、第二开关管、数据信号线、存储电容和公共电极层，所述第一开关管的控制极通过过孔与所述第二开关管的第一极连接，所述第二开关管的第一极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的第二极连接，所述扫描信号线与所述第二开关管的控制极连接，所述公共电极层用作所述存储电容的第二极板。
  4. 根据权利要求3所述的阵列基板，还包括位于所述平坦层和所述驱动电路层的第二绝缘层，所述第一过孔贯穿所述第二绝缘层和部分所述平坦层，所述第二过孔贯穿所述第二电极层。
  5. 根据权利要求2-4任一项所述的阵列基板，其中，所述平坦层采用树脂材料制成。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，所述第一电极层和所述第二电极层在所述衬底基板上的正投影与所有发光元件在所述衬底基板上的正投影重叠。
  7. 根据权利要求1-6任一项所述的阵列基板，还包括辅助层，所述辅助层与所述第二电极层同层同材料设置且与所述第二电极层间隔设置，所述第一电极设置在所述辅助层远离所述衬底基板的一侧。
  8. 根据权利要求1-7任一项所述的阵列基板，其中，所述第一电极和所述第二电极在所述衬底基板上的正投影位于所述发光层在所述衬底基板的正投影的两侧。
  9. 根据权利要求1-8任一项所述的阵列基板，其中，在所述发光元件组包括多个发光元件的情况下，所述多个发光元件并联或串联设置。
  10. 一种显示面板，包括：如权利要求1～9中任一项所述的阵列基板。
  11. 一种显示装置，包括：如权利要求10所述的显示面板。
  12. 一种显示基板的制作方法，包括：
    在衬底基板上依次形成第一电极层、第一绝缘层和第二电极层；
    在所述第二电极层远离所述衬底基板的一侧形成发光元件组，所述发光元件组包括单个发光元件或多个发光元件，每个发光元件包括第一电极、发光层和第二电极，所述第一电极与所述第一电极层连接，所述第二电极与所述第二电极层连接，以驱动所述发光层发光。
  13. 根据权利要求12所述的方法，还包括：
    在所述发光元件组远离所述衬底基板的一侧形成平坦层；
    在所述平坦层远离所述衬底基板的一侧形成驱动电路层，所述驱动电路层包括第一开关管，用于控制所述第一电极与所述第一电极层之间的关断，所述第一开关管的第一极通过第一过孔与所述辅助层连接，所述第一开关管的第二极通过第二过孔与所述第一电极层连接。
  14. 根据权利要求13所述的方法，其中，所述驱动电路层还包括扫描信号线、第二开关管和存储电容，
    所述在所述发光元件组远离所述衬底基板的一侧形成平坦层之后，所述方法还包括：
    在所述平坦层远离所述衬底基板的一侧形成所述扫描信号线、所述第一开关管的控制极和所述第二开关管的控制极；
    形成第二绝缘层；
    在所述第二绝缘层远离所述衬底基板的一侧形成半导体层；
    在所述半导体层远离所述衬底基板的一侧形成数据信号线、所述第一开关管的第一极和第二极、所述第二开关管的第一极和第二极以及存储电容的第一极板；所述第一开关管的第一极通过过孔与第一电极层连接，所述第一开关管的第二极与所述发光元件的第一电极连接，所述第一开关管的控制极通过过孔与所述第二开关管的第一极连接，所述第二开关管的第一极与所述存储电容的第一极板连接，所述数据信号线与所述第二开关管的第二极连接，所述扫描信号线与所述第二开关管的控制极连接；
    形成第三绝缘层和公共电极层，所述公共电极层构成所述存储电容的第二极板，所述公共电极层和所述存储电容的第一极板在所述衬底基板上的正投影至少部分重叠。
  15. 根据权利要求12所述的方法，其中，形成所述第二电极层，包括：
    采用同一掩膜板同一构图工艺同时形成所述第二电极层和辅助层，所述辅助层与所述第二电极层间隔设置，所述第一电极设置在所述辅助层远离所述衬底基板的一侧。
  16. 根据权利要求12所述的方法，其中，所述平坦层采用树脂材料制成。
  17. 一种亮度调节方法，用于如权利要求3～9中任一项所述的阵列基板，所述方法包括：
    根据预设的第一色彩深度位数，确定所述阵列基板在一帧内的第一扫描次数，其中，在每一次扫描过程中，对所述阵列基板的每一行均进行一次扫描。
  18. 根据权利要求17所述的亮度调节方法，还包括：
    通过给所述阵列基板中各第二开关管的控制极输入扫描信号，开启所述各第二开关管；
    通过给所述第二开关管的第二极输入不同的数据电压；
    确定不同的数据电压所对应的所述阵列基板中所有发光元件组的亮度值，并建立数据电压与所述亮度值之间的对应关系；其中，所述不同的数据电压的个数根据预设第二色彩深度位数确定，所述第一色彩深度位数和所述第二色彩深度位数组成第三色彩深度位数；
    根据亮度值与色彩深度的预设对应关系，确定所述数据电压与色彩深度之间的对应关系。
  19. 根据权利要求18所述的亮度调节方法，其中，所述确定不同的数据电压所对应的所述阵列基板中所有发光元件组的亮度值，包括：
    根据所述发光元件组的亮度值与电流的预设对应关系和所述发光元件组的电流和电压的预设对应关系，确定不同的数据电压所对应的所述发光元件组的亮度值。
  20. 根据权利要求18所述的亮度调节方法，其中，所述第一色彩深度位数构成所述第三色彩深度位数的高位比特数，所述第二色彩深度位数构成所述第三色彩深度位数的低位比特数。
  21. 根据权利要求20所述的亮度调节方法，还包括：
    接收待显示的图像数据；
    确定所述待显示的图像数据的色彩深度位数；
    在所述色彩深度位数小于或等于所述第一色彩深度位数时，根据所述色彩深度位数，确定所述阵列基板在一帧内的第二扫描次数；
    在所述色彩深度位数大于所述第一色彩深度位数时，根据第一所述色彩深度位数，确定所述阵列基板在一帧内的所述第一扫描次数；
    根据所述色彩深度位数与所述第一色彩深度位数的差值确定所述不同数据电压的第一个数；
    在所述第三色彩深度位数中选取所述第一个数的低位比特数，并确定选取的低位比特数对应的待输出数据电压；及
    根据所述待输出数据电压和/或一帧内的第一扫描次数显示所述待显示的图像数据。
  22. 根据权利要求17所述的亮度调节方法，其中，所述阵列基板还包括使能信号输入端，在对阵列基板的每一行进行扫描时，所述方法还包括：
    向所述使能信号输入端输入使能信号；
    在所述使能信号第一个上升沿时刻给每一行中的各第二开关管控制极输入有效扫描信号，开启所述各第二开关管；
    在所述使能信号第二个上升沿时刻给每一行中的各第二开关管第二极输 入有效数据电压；
    经过预设时间段后，在所述使能信号第一个下降沿时刻给每一行中的各第二开关管控制极输入非有效扫描信号；及
    在所述使能信号第二个下降沿时刻给每一行中的各第二开关管第二极输入非有效数据电压。
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