WO2021254053A9 - 显示基板及其制备方法、驱动方法、显示装置 - Google Patents

显示基板及其制备方法、驱动方法、显示装置 Download PDF

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Publication number
WO2021254053A9
WO2021254053A9 PCT/CN2021/093676 CN2021093676W WO2021254053A9 WO 2021254053 A9 WO2021254053 A9 WO 2021254053A9 CN 2021093676 W CN2021093676 W CN 2021093676W WO 2021254053 A9 WO2021254053 A9 WO 2021254053A9
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region
layer
doping
electrode
substrate
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PCT/CN2021/093676
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English (en)
French (fr)
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WO2021254053A1 (zh
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刘鹏
徐敬义
刘弘
霍培荣
张永强
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US17/642,957 priority Critical patent/US11764232B2/en
Publication of WO2021254053A1 publication Critical patent/WO2021254053A1/zh
Publication of WO2021254053A9 publication Critical patent/WO2021254053A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display substrate, a method for manufacturing the same, a method for driving the same, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the high-frequency driving of the display product will reduce the charging time of each row of pixels in the display product, which reduces the charging rate of the display product and affects the display effect of the display product.
  • an embodiment of the present disclosure provides a display substrate, comprising: a substrate and a switch structure disposed on the substrate, the switch structure being electrically connected to a control signal terminal, a signal input terminal and a signal output terminal, and configured as Under the control of the control signal terminal, the signal of the signal input terminal is provided to the signal output terminal;
  • the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the first transistor and the second transistor are of opposite types;
  • the first transistor includes: a first active layer, a first gate electrode, a first source electrode and a first drain electrode
  • the second transistor includes: a second active layer, a second gate electrode, and a second source electrode and the second drain electrode;
  • the first gate electrode and the second gate electrode are electrically connected to the control signal terminal, the first source electrode and the second source electrode are electrically connected to the signal input terminal, and the first drain electrode and the second drain electrode is electrically connected to the signal output terminal;
  • the orthographic projection of the first active layer on the substrate coincides with the orthographic projection of the second active layer on the substrate.
  • the number of the switch units is N;
  • the first source electrode of the first switch unit is electrically connected to the signal input terminal
  • the first drain electrode of the jth switch unit is electrically connected to the first source electrode of the j+1th switch unit
  • the Nth switch unit is electrically connected to the first source electrode of the j+1th switch unit.
  • the first drain electrode is electrically connected to the signal output terminal;
  • the first gate electrode and the second gate electrode of all switch units are electrically connected to the control signal terminal, N ⁇ 1, 1 ⁇ j ⁇ N.
  • the display substrate further includes: scan signal lines, data signal lines, common electrodes and pixel electrodes disposed on the substrate;
  • the scanning signal line is electrically connected to the control signal terminal, and is configured to provide a signal to the control signal terminal;
  • the data signal line is connected to the signal input terminal, and is configured to provide a signal to the signal input terminal;
  • the signal output terminal is connected to the pixel electrode, and is configured to provide a signal to the pixel electrode;
  • the common electrode is located on the side of the pixel electrode close to the substrate, and is arranged to form an electric field with the pixel electrode.
  • the first gate electrode and the second gate electrode are configured as the same electrode
  • the first active layer is located on the side of the first gate electrode close to the substrate; the second active layer is located on the side of the first gate electrode away from the substrate; the second active layer A layer is connected to the first active layer.
  • the first transistor is an N-type transistor and the second transistor is a P-type transistor:
  • the first active layer includes: a first channel region, a first doped region, and a second doped region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer , a third doped region and a fourth doped region;
  • the first doped region and the second doped region have the same doping type and are located on both sides of the first channel region respectively;
  • the third doping region and the fourth doping region have the same doping type, the third doping region is located on a side of the first doping region away from the first channel region, and the a fourth doped region is located on a side of the second doped region away from the first channel region;
  • the doping concentration of the third doping region is greater than the doping concentration of the first doping region
  • the second active layer includes: a second channel region, a fifth doped region and a sixth doped region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer ;
  • the fifth doping region and the sixth doping region have the same doping type, and are respectively located on both sides of the second channel region.
  • the second source electrode and the second drain electrode are disposed on the second active layer away from the substrate
  • the second source electrode is electrically connected to the third doping region through the fifth doping region, and the second source electrode and the fifth doping region are multiplexed into a first source electrode
  • the second drain electrode is electrically connected to the fourth doping region through the sixth doping region, and the second drain electrode and the sixth doping region are multiplexed into a first drain electrode
  • each switch unit the second source electrode and the second drain electrode are disposed on the side of the second active layer away from the substrate; the first Two source electrodes are electrically connected to the third doping region through the fifth doping region, and the second source electrode and the fifth doping region are multiplexed into a first source electrode; the second drain electrode The sixth doping region is electrically connected to the fourth doping region, the second drain electrode and the sixth doping region are multiplexed into a first drain electrode; the second leakage current of the i-th switch unit The electrode is the same electrode as the second source electrode of the i+1th switch unit, 1 ⁇ i ⁇ N;
  • the second source electrode of the first switch unit is disposed on the side of the second active layer of the first switch unit away from the substrate, and the second source electrode of the last switch unit Two drain electrodes are disposed on the side of the second active layer of the last switch unit away from the substrate; in the first switch unit, the second source electrode is connected to the third dopant through the fifth doping region The impurity region is electrically connected, the second source electrode is multiplexed with the fifth impurity region as a first source electrode; the sixth impurity region multiplexes into a second drain electrode, and the fourth impurity region multiplexes is used as the first drain electrode; in the jth switch unit, the fifth doped region is multiplexed as the second source electrode, the third doped region is multiplexed as the first source electrode, and the sixth doped region is multiplexed as the first source electrode.
  • the impurity region is multiplexed into the second drain electrode, and the fourth impurity region is multiplexed into the first drain electrode, 1 ⁇ j ⁇ N; the sixth doped region of the j-1th switch unit and the jth switch unit
  • the fifth doping region of is the same doping region, and the fourth doping region of the j-1th switch unit and the third doping region of the jth switching unit are the same doping region; in the last switch unit,
  • the fifth doping region is multiplexed as a second source electrode, the third doping region is multiplexed as a first source electrode, and the second drain electrode passes through the sixth doping region and the fourth doping region electrically connected, the second drain electrode is multiplexed with the sixth doped region as a first drain electrode.
  • the first transistor when the first transistor is a P-type transistor and the second transistor is an N-type transistor;
  • the first active layer includes: a first channel region, a first doped region and a second doped region arranged in a direction perpendicular to the arrangement of the first active layer and the second active layer ;
  • the first doped region and the second doped region have the same doping type and are located on both sides of the first channel region respectively;
  • the second active layer includes: a second channel region, a third doped region, and a fourth doped region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer , the fifth doped region and the sixth doped region;
  • the third doping region and the fourth doping region have the same doping type and are respectively located on both sides of the second channel region;
  • the fifth doping region and the sixth doping region are of the same doping type, the fifth doping region is located on a side of the third doping region away from the second channel region, and the a sixth doped region is located on a side of the fourth doped region away from the second channel region;
  • the doping concentration of the fifth doping region is greater than the doping concentration of the third doping region.
  • the second source electrode and the second drain electrode are disposed on the second active layer away from the substrate
  • the second source electrode is electrically connected to the first doped region through the fifth doped region, and the second source electrode and the fifth doped region are multiplexed into a first source electrode
  • the second drain electrode is electrically connected to the second doping region through the sixth doping region, and the second drain electrode and the sixth doping region are multiplexed into a first drain electrode
  • each switch unit the second source electrode and the second drain electrode are disposed on the side of the second active layer away from the substrate; the first Two source electrodes are electrically connected to the first doped region through the fifth doped region, the second source electrode and the fifth doped region are multiplexed into a first source electrode; the second drain electrode The sixth doping region is electrically connected to the second doping region, and the second drain electrode and the sixth doping region are multiplexed into a first drain electrode; the second leakage current of the i-th switch unit The electrode is the same electrode as the second source electrode of the i+1th switch unit, 1 ⁇ i ⁇ N;
  • the second source electrode of the first switch unit is disposed on the side of the second active layer of the first switch unit away from the substrate, and the second source electrode of the last switch unit Two drain electrodes are disposed on the side of the second active layer of the last switch unit away from the substrate; in the first switch unit, the second source electrode is connected to the first dopant through the fifth doping region The impurity region is electrically connected, the second source electrode is multiplexed with the fifth impurity region as a first source electrode; the sixth impurity region multiplexes into a second drain electrode, and the second impurity region multiplexes is used as the first drain electrode; in the jth switch unit, the fifth doping region is multiplexed as the second source electrode, the first doping region is multiplexed as the first source electrode, and the sixth doping region is multiplexed as the first source electrode.
  • the impurity region is multiplexed into the second drain electrode, and the second impurity region is multiplexed into the first drain electrode, 1 ⁇ j ⁇ N; the sixth doped region of the j-1th switch unit and the jth switch unit
  • the fifth doped region is the same doped region, the second doped region of the j-1th switch unit and the first doped region of the jth switch unit are the same doped region; in the last switch unit,
  • the fifth doping region is multiplexed as a second source electrode, the first doping region is multiplexed as a first source electrode, and the second drain electrode is connected to the second doping region through the sixth doping region
  • the impurity region is electrically connected, and the second drain electrode is multiplexed with the sixth impurity region as a first drain electrode.
  • the orthographic projection of the first channel region on the substrate coincides with the orthographic projection of the second channel region on the substrate
  • the orthographic projection of the first channel region on the substrate at least partially overlaps the orthographic projection of the first gate electrode on the substrate.
  • the display substrate further includes: a light shielding layer
  • the light shielding layer is located on the side of the first active layer close to the substrate, and the orthographic projection of the light shielding layer on the substrate covers the orthographic projection of the first channel region on the substrate.
  • the display substrate includes: a first metal layer, a first insulating layer, a first polysilicon layer, a second insulating layer, a second metal layer, a first metal layer, a first insulating layer, a first three insulating layers, a second polysilicon layer, a fourth insulating layer and a third metal layer;
  • the first metal layer includes a light shielding layer
  • the first polysilicon layer includes a first active layer
  • the second metal layer includes a first gate electrode and a scan signal line
  • the second polysilicon layer includes a first active layer.
  • the silicon layer includes a second active layer
  • the third metal layer includes a second source electrode, a second drain electrode and a data signal line.
  • the display substrate further includes: a flat layer, a first transparent conductive layer, a fifth insulating layer and a second transparent conductive layer;
  • the flat layer is located on a side of the third metal layer away from the substrate, and a first via hole exposing the second drain electrode is disposed on the flat layer;
  • the first transparent conductive layer is located on the side of the flat layer away from the substrate, and a second via hole exposing the first via hole is arranged on the first transparent conductive layer;
  • the orthographic projection on the substrate covers the orthographic projection of the first via hole on the substrate;
  • the first transparent conductive layer includes: a common electrode;
  • the fifth insulating layer is located on a side of the first transparent conductive layer away from the substrate, and a third via hole exposing the second via hole is disposed on the fifth insulating layer;
  • the second transparent conductive layer is located on the side of the fifth insulating layer away from the substrate, the second transparent conductive layer includes: a pixel electrode, the pixel electrode passes through the first via hole, the second transparent conductive layer The via hole and the third via hole are connected to the second drain electrode.
  • an embodiment of the present disclosure further provides a display device, including: the above-mentioned display substrate.
  • an embodiment of the present disclosure also provides a method for preparing a display substrate, which is configured to form the above-mentioned display substrate, and the method includes:
  • a switch structure is formed on the substrate; the switch structure is electrically connected to a control signal terminal, a signal input terminal and a signal output terminal, respectively, and is configured to provide the signal output terminal with the control signal terminal under the control of the control signal terminal.
  • the signal at the signal input end; the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the first transistor and the second transistor are of opposite types; the first transistor includes: a first active layer, a first gate electrode, a first source electrode and a first drain electrode, the second transistor includes: a second active layer, a second gate electrode, a second source electrode and a second drain electrode; the The first gate electrode and the second gate electrode are respectively electrically connected to the control signal terminal, the first source electrode and the second source electrode are respectively electrically connected to the signal input terminal, and the first leakage current electrode and the second drain electrode are respectively electrically connected to the signal output terminal; the orthographic projection of the first active layer on the substrate coincides with the orthographic projection of the second active layer on
  • the forming the switch structure on the substrate includes:
  • a first metal layer and a first insulating layer are sequentially formed on the substrate; the first metal layer includes: a light shielding layer;
  • a first polysilicon layer is formed on the first insulating layer; the first polysilicon layer includes: a first active layer;
  • a second insulating layer and a second metal layer are sequentially formed on the first insulating layer formed with the first polysilicon layer;
  • the second metal layer includes: a first gate electrode and a scan signal line; the first gate electrode and the second gate electrode is the same electrode;
  • a second polysilicon layer is formed on the third insulating layer, the second polysilicon layer includes: a second active layer;
  • a fourth insulating layer and a third metal layer are sequentially formed on the third insulating layer formed with the second polysilicon layer, and the third metal layer includes: a second source electrode, a second drain electrode and a data signal line.
  • the method further includes:
  • a first transparent conductive layer is formed on the flat layer, and the first transparent conductive layer includes: a common electrode;
  • a second transparent conductive layer is formed on the fifth insulating layer, and the second transparent conductive layer includes: a pixel electrode.
  • the first transistor is an N-type transistor and the second transistor is a P-type transistor
  • the forming the first polysilicon layer on the first insulating layer includes:
  • the first polysilicon thin film includes: a first region, a second region, a third region, a fourth region and a fifth region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer, The second area and the third area are respectively located on both sides of the first area, the fourth area is located on the side of the second area away from the first area, and the fifth area is located on the side of the second area away from the first area. a side of the third area away from the first area;
  • the forming the second polysilicon layer on the third insulating layer includes:
  • the second polysilicon thin film includes: a first region, a second region and a third region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer, the second region and the The third areas are respectively located on both sides of the first area;
  • the first transistor is a P-type transistor and the second transistor is an N-type transistor
  • the forming the first polysilicon layer on the first insulating layer includes:
  • the first polysilicon thin film includes: a first region, a second region and a third region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer, the second region and the The third areas are respectively located on both sides of the first area;
  • the forming the second polysilicon layer on the third insulating layer includes:
  • a second amorphous silicon film is deposited on the third insulating layer, the second amorphous silicon film is crystallized, and the crystallized second amorphous silicon film is processed through a patterning process to form a second polysilicon film ;
  • the second polysilicon film includes: a first region, a second region, a third region, a fourth region and a fifth region arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer , the second area and the third area are located on both sides of the first area, the fourth area is located on the side of the second area away from the first area, and the fifth area is located on the side of the second area away from the first area. a side of the third area away from the first area;
  • N-type light doping treatment is performed on the second region and the third region of the second polysilicon thin film to form a second polysilicon layer.
  • an embodiment of the present disclosure further provides a method for driving a display substrate, which is used for driving the above-mentioned display substrate, and the method includes:
  • a control signal is provided to the control signal terminal to provide the signal of the signal input terminal to the signal output terminal.
  • the providing the control signal to the control signal terminal includes:
  • the providing the control signal to the control signal terminal includes:
  • a second control signal is provided to the control signal terminal, and the second control signal is a high level signal.
  • FIG. 1 is a schematic diagram of a switch structure provided by an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a switch structure provided by an exemplary embodiment
  • FIG. 4A is a cross-sectional view of a display substrate provided by an exemplary embodiment
  • 4B is a cross-sectional view of a display substrate provided by another exemplary embodiment
  • FIG. 5 is a top view of a display substrate provided by an exemplary embodiment
  • FIG. 6 is a cross-sectional view of forming a first insulating layer
  • FIG. 7 is a top view of forming a first insulating layer
  • FIG. 8 is a cross-sectional view of forming a first polysilicon layer
  • FIG. 9 is a top view of forming a first polysilicon layer
  • FIG. 10 is a cross-sectional view of forming a second metal layer
  • FIG. 11 is a top view of forming a second metal layer
  • FIG. 12 is a cross-sectional view of forming a second polysilicon layer
  • FIG. 13 is a top view of forming a second polysilicon layer
  • FIG. 14 is a cross-sectional view of forming a fourth insulating layer
  • 16 is a cross-sectional view of forming a third metal layer
  • 17 is a top view of forming a third metal layer
  • 19 is a cross-sectional view of forming a first transparent conductive layer.
  • Embodiments of the present disclosure include and contemplate combinations with features and elements known to those of ordinary skill in the art.
  • the embodiments, features and elements that have been disclosed in this disclosure can also be combined with any conventional features or elements to form solutions defined by the claims.
  • Any features or elements of any embodiment may also be combined with features or elements from other solutions to form another solution defined by the claims. Accordingly, any of the features shown and/or discussed in embodiments of the present disclosure may be implemented individually or in any suitable combination. Accordingly, the embodiments are not to be limited except in accordance with the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
  • electrically connected includes a case where constituent elements are connected together by an element having a certain electrical effect.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
  • perpendicular refers to a state in which an angle formed by two straight lines is 80° or more and 100° or less, and therefore includes a state in which an angle of 85° or more and 95° or less is included.
  • area a and area b are located on both sides of area c respectively means that area a is located on one side of area c, and area b is located on the other side of area c away from area a".
  • FIG. 1 is a schematic diagram of a switch structure provided by an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure
  • a display substrate provided by an embodiment of the present disclosure includes: a substrate 10 and a switch structure disposed on the substrate 10 .
  • the switch structure is electrically connected to the control signal terminal G, the signal input terminal IN and the signal output terminal OUT, and is configured to provide the signal output terminal OUT with the signal of the signal input terminal IN under the control of the control signal terminal G.
  • the switch structure includes: a switch unit 1, and the switch unit 1 includes: a first transistor T1 and a second transistor T2; the types of the first transistor T1 and the second transistor T2 are opposite.
  • FIG. 2 illustrates by taking an example that the switch structure includes one switch unit.
  • the first transistor T1 includes: a first active layer 11, a first gate electrode 12, a first source electrode 13 and a first drain electrode 14, and the second transistor T2 includes: a second active layer 21, a second gate electrode 22, The second source electrode 23 and the second drain electrode 24 .
  • the first gate electrode and the second gate electrode are electrically connected to the control signal terminal G
  • the first source electrode and the second source electrode are electrically connected to the signal input terminal IN
  • the first drain electrode and the second drain electrode are electrically connected to the signal input terminal IN.
  • the signal output terminal OUT is electrically connected.
  • the orthographic projection of the first active layer 11 on the substrate 10 coincides with the orthographic projection of the second active layer 21 on the substrate 10 .
  • the substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be but not limited to one or more of glass and metal foil; the flexible substrate may be but not limited to Not limited to polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, poly One or more of vinyl chloride, polyethylene, textile fibers.
  • the first transistor T1 and the second transistor T2 may be P-type, or may be N-type.
  • the first transistor T1 is of N type
  • the second transistor T2 is of P type.
  • the first transistor T1 is P-type
  • the second transistor T2 is N-type.
  • the first active layer 11 and the second active layer 21 are made of polysilicon material.
  • the types are opposite, and the first transistor T1 and the second transistor T2 arranged in parallel constitute a transmission gate.
  • the switch structure is turned off when the voltage of the signal of the first gate electrode is 0V and the voltage of the signal of the second gate electrode is 0V.
  • the switch structure is turned on when at least one of the voltages of the signal of the first gate electrode and the signal of the second gate electrode is not 0.
  • the control signal terminal when the signal at the signal input terminal is a high-level signal, the control signal terminal can be supplied with a high-level signal.
  • the signal or the low-level signal turns on the switch structure, thereby providing the signal output terminal with the signal at the signal input terminal.
  • the control signal terminal provides a high level signal, the first transistor T1 is turned on, the second transistor T2 is turned off, and the absolute value of the gate-source voltage difference of the first transistor is the first difference.
  • the control signal terminal When the control signal terminal provides a low-level signal, the first transistor T1 is turned off, the second transistor T2 is turned on, and the absolute value of the gate-source voltage difference of the second transistor T2 is the second difference. is smaller than the voltage value of the high-level signal, therefore, the second difference value is greater than the first difference value.
  • the voltage value of the signal provided by the signal input terminal As 8V as an example, when the control signal terminal provides a high-level signal, the voltage value of the signal at the control signal terminal is 6V, and the first difference is 2V.
  • the control signal terminal When the control signal terminal provides a low-level signal
  • the voltage value of the signal at the control signal terminal When the signal is flat, the voltage value of the signal at the control signal terminal is -6V, and the second difference value is 14V.
  • the resistance of the switch structure when the control signal terminal provides a low-level signal is smaller than the resistance of the switch structure when the control signal terminal provides a high-level signal.
  • the disclosed embodiments can provide a low-level signal to the control signal terminal to turn on the switch structure, thereby improving the charging capability of the switch structure.
  • the second difference value is smaller than the first difference value. Taking the voltage value of the signal provided by the signal input terminal as -8V as an example, when the control signal terminal provides a high level signal, the voltage value of the signal at the control signal terminal is 6V, and the first difference is 14V.
  • the control signal terminal When the control signal terminal provides a low level signal When the level signal is used, the voltage value of the signal at the control signal terminal is -6V, and the second difference value is 2V. Since the second difference is smaller than the first difference, the resistance of the switch structure when the control signal terminal provides a high-level signal is smaller than the resistance of the switch structure when the control signal terminal provides a low-level signal.
  • the disclosed embodiments can provide a high-level signal to the control signal terminal to turn on the switch structure, thereby improving the charging capability of the switch structure.
  • the signal of the control signal terminal can be controlled according to the signal of the signal input terminal.
  • the switch structure can be turned on by providing a low-level signal to the control signal terminal.
  • the switch structure can be turned on by providing a high-level signal to the control signal terminal, which improves the charging capability of the switch structure, increases the flexibility of the switch structure, and avoids the charging capability caused by the use of a single transistor. insufficient problem.
  • the display substrate includes: a plurality of sub-pixels arranged on the substrate.
  • the switch structure may be applied in a gate drive circuit, in a sub-pixel, or in a multiplexer.
  • the orthographic projection of the first active layer 11 on the substrate 10 coincides with the orthographic projection of the second active layer 21 on the substrate 10, which can affect the aperture ratio of the sub-pixel.
  • the display substrate provided by the embodiment of the present disclosure includes: a substrate and a switch structure disposed on the substrate, the switch structure is electrically connected to a control signal terminal, a signal input terminal and a signal output terminal respectively, and is arranged to be controlled by the control signal terminal to send a signal to the signal terminal.
  • the output terminal provides the signal of the signal input terminal;
  • the switch structure includes: a switch unit; the switch unit includes: a first transistor and a second transistor; the types of the first transistor and the second transistor are opposite;
  • the first transistor includes: a first active layer, a second transistor a gate electrode, a first source electrode and a first drain electrode,
  • the second transistor includes: a second active layer, a second gate electrode, a second source electrode and a second drain electrode; the first gate electrode and the second gate electrode are respectively It is electrically connected to the control signal terminal, the first source electrode and the second source electrode are respectively electrically connected to the signal input terminal, the first drain electrode and the second drain electrode are electrically connected to the signal output terminal respectively;
  • the orthographic projection coincides with the orthographic projection of the second active layer on the substrate.
  • the charging capability of the switch structure can be improved, the charging rate of the display product can be effectively improved to support high-frequency driving of the display product, and the display effect can be improved .
  • FIG. 3 is a schematic diagram of a switch structure provided by an exemplary embodiment
  • FIG. 4A is a cross-sectional view of a display substrate provided by an exemplary embodiment
  • FIG. 4B is a cross-sectional view of a display substrate provided by another exemplary embodiment.
  • the number of switch units is N.
  • FIG. 3 and FIG. 4 are described by taking the switch structure including two switch units as an example.
  • the first source electrode of the first switch unit is electrically connected to the signal input terminal IN
  • the first drain electrode of the jth switch unit is electrically connected to the first source electrode of the j+1th switch unit
  • the Nth switch unit is electrically connected to the first source electrode of the j+1th switch unit.
  • the first drain electrode is electrically connected to the signal output terminal OUT.
  • the first gate electrodes and the second gate electrodes of all switch units are electrically connected to the control signal terminal G, N ⁇ 1, 1 ⁇ j ⁇ N.
  • the display substrate further includes: scan signal lines (not shown in the figure), data signal lines (not shown in the figure), a common electrode 41 and pixel electrode 42 .
  • the scanning signal line is electrically connected to the control signal terminal, and is set to provide a signal to the control signal terminal;
  • the data signal line is connected to the signal input terminal, and is set to provide a signal to the signal input terminal;
  • the signal output terminal is set to provide a signal. It is connected to the pixel electrode, and is configured to provide signals to the pixel electrode;
  • the common electrode 41 is located on the side of the pixel electrode 42 close to the substrate 10, and is configured to form an electric field with the pixel electrode.
  • the common electrode 41 and the pixel electrode 42 are transparent electrodes, and the material for making the transparent electrodes may be indium tin oxide, or may be zinc tin oxide.
  • the first gate electrode 12 and the second gate electrode 22 are configured as the same electrode.
  • the first active layer 11 is located on the side of the first gate electrode 12 close to the substrate 10 ; the second active layer 21 is located on the first gate electrode 12 away from the substrate 10 ; the second active layer 21 is connected to the first active layer 11 .
  • the first active layer 11 when the first transistor is an N-type transistor and the second transistor is a P-type transistor; the first active layer 11 includes: along a row perpendicular to the first active layer and the second active layer The first channel region 111 , the first doped region 112 , the second doped region 113 , the third doped region 114 and the fourth doped region 115 are arranged in the distribution direction (ie, along the direction parallel to the substrate).
  • the second active layer 21 includes: a second channel region 211 , a fifth doping region 212 and a sixth doping region 213 arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer.
  • the first doped region 112 , the second doped region 113 , the third doped region 114 , the fourth doped region 115 , the fifth doped region 212 and the sixth doped region 213 may be conductive.
  • the first doping region 112 and the second doping region 113 have the same doping type and are located on both sides of the first channel region 111 respectively; the third doping region 114 and the fourth doping region 115 have the same doping type , the third doped region 114 is located on the side of the first doped region 112 away from the first channel region 111 , and the fourth doped region 115 is located on the side of the second doped region 113 away from the first channel region 111 .
  • the fifth doping region 212 and the sixth doping region 213 have the same doping type and are located on both sides of the second channel region 211 respectively.
  • the second source electrode 23 and the second drain electrode 24 are disposed on the second active layer 21 away from the substrate. 10 side.
  • the second source electrode 23 is electrically connected to the third doping region 114 through the fifth doping region 212 , and the second source electrode 23 and the fifth doping region 212 are multiplexed into the first source electrode 13 .
  • the second drain electrode 24 is electrically connected to the fourth doping region 115 through the sixth doping region 213 , and the second drain electrode 24 and the sixth doping region 213 are multiplexed into the first drain electrode 14 .
  • the second source electrode 23 and the second drain electrode 24 are disposed on a part of the second active layer 21 away from the substrate 10 . side.
  • the second source electrode 23 is electrically connected to the third doping region 114 through the fifth doping region 212 , and the second source electrode 23 and the fifth doping region 212 are multiplexed into the first source electrode 13 .
  • the second drain electrode 24 is electrically connected to the fourth doping region 115 through the sixth doping region 213 , and the second drain electrode 24 and the sixth doping region 213 are multiplexed into the first drain electrode 14 .
  • the second drain electrode of the i-th switch unit and the second source electrode of the i+1-th switch unit are the same electrode, 1 ⁇ i ⁇ N.
  • FIG. 4A takes two switch units as an example for description. As shown in FIG. 4A , the second drain electrode of the first switch unit and the second source electrode of the second switch unit are the same electrode.
  • the second source electrode of the first switch unit is disposed on the side of the second active layer of the first switch unit away from the substrate, and finally The second drain electrode of one switch unit is arranged on the side of the second active layer of the last switch unit away from the substrate; in the first switch unit, the second source electrode is connected to the third dopant through the fifth doping region
  • the second source electrode is multiplexed with the fifth doping region as the first source electrode;
  • the sixth doping region is multiplexed as the second drain electrode, and the fourth doping region is multiplexed as the first drain electrode;
  • the fifth doped region is multiplexed as the second source electrode
  • the third doped region is multiplexed as the first source electrode
  • the sixth doped region is multiplexed as the second drain electrode
  • the fourth doped region is multiplexed as the second drain electrode.
  • FIG. 4B illustrates two switch units as an example.
  • the sixth doping region of the first switching unit and the fifth doping region of the second switching unit are the same doping region
  • the first The fourth doping region of the first switching unit and the third doping region of the second switching unit are the same doping region.
  • the third doped region of the switch unit is equivalent to a parallel resistance, which can reduce the resistance of the switch structure, thereby improving the charging rate of the switch structure.
  • the first transistor has a top-gate structure
  • the second transistor has a bottom-gate structure
  • the doping concentrations of the first doped region 112 and the second doped region 113 may be equal.
  • the doping concentrations of the third doped region 114 and the fourth doped region 115 may be equal.
  • the doping concentrations of the fifth doping region 212 and the sixth doping region 213 may be equal.
  • the doping concentration of the third doped region 114 is greater than the doping concentration of the first doped region 112 .
  • the first doped region 112 and the second doped region 113 are lightly doped with N type, and the third doped region 114 and the fourth doped region 115 are heavily doped with N type.
  • the first active layer is provided with a first doped region 112 and a second doped region 113 with high resistance, which can reduce the acceleration distance of electrons under the action of an electric field, can effectively reduce the heat generation of the first transistor, and suppress leakage current.
  • the fifth doping region 212 and the sixth doping region 213 may be lightly doped with P-type, or may be heavily doped with P-type.
  • control of the lengths of the first to sixth doped regions may be achieved by adjusting the doped ion species and the doping concentration.
  • the first transistor when a high-level signal is provided to the first gate electrode, the The first channel region 111 is in an on state, and the second channel region 211 is in a high resistance state.
  • the first channel region 111 is in an on state, the second source electrode 23, the fifth doping region 212, the third doping region 114, the first doping region 112, the first channel region 111, the second doping region A via is formed between the 113, the fourth doping region 115, the sixth doping region 213 and the second drain electrode 24.
  • the second source electrode 23 and the fifth doping region 212 are multiplexed into the first source electrode 13, the The second drain electrode 24 and the sixth doping region 213 are multiplexed to form the first drain electrode 14. Therefore, the above-mentioned paths are the first source electrode 13, the third doping region 114, the first doping region 112, and the first channel region 111, the second doped region 113, the fourth doped region 115 and the first drain electrode 14, the voltage signal of the first source electrode is transmitted to the first drain electrode through this path, in this case, the first transistor is in conduction. pass status.
  • the second channel region 211 Since the second channel region 211 is in a high resistance state, the second source electrode 23 , the fifth doping region 212 , the second channel region 211 , the sixth doping region 213 and the second drain electrode 24 cannot be formed channel, and the second transistor is in an off state.
  • the first gate electrode When a low-level signal is supplied to the first gate electrode, the first channel region 111 is in a high resistance state, and the second channel region 211 is in a conducting state.
  • the first channel region 111 is in a high resistance state
  • the second source electrode 23, the fifth doping region 212, the third doping region 114, the first doping region 112, the first channel region 111, the second doping region 113, the fourth doping region 115, the sixth doping region 213 and the second drain electrode 24 cannot form a via, that is, the first source electrode 13, the third doping region 114, the first doping region 112, the first A path cannot be formed between the channel region 111 , the second doping region 113 , the fourth doping region 115 and the first drain electrode 14 , and in this case, the first transistor is in an off state.
  • the second channel region 211 is in an on state, a path is formed between the second source electrode 23, the fifth doping region 212, the second channel region 211, the sixth doping region 213 and the second drain electrode 24, and the first The voltage signal of the two source electrodes 23 is transmitted to the second drain electrode 24 through the path, and the second transistor is in an on state.
  • first gate electrode 12 and the second gate electrode 22 are the same electrode, that is, the first transistor and the second transistor share a gate, which not only ensures the normal operation of the switch structure, but also simplifies the process and saves costs.
  • FIG. 2 and FIG. 4 are described by taking an example that the first transistor is an N-type transistor and the second transistor is a P-type transistor.
  • the first active layer when the first transistor is a P-type transistor and the second transistor is an N-type transistor; the first active layer includes: arranging along the vertical direction of the first active layer and the second active layer A first channel region, a first doped region and a second doped region are arranged in a direction.
  • the second active layer includes: a second channel region, a third doping region, a fourth doping region, and a fifth doping region, which are arranged in a direction perpendicular to the arrangement direction of the first active layer and the second active layer and the sixth doped region.
  • the doping type of the first doping region and the second doping region are the same, and they are located on both sides of the first channel region; the doping type of the third doping region and the fourth doping region are the same, and they are located on the Two sides of the channel region; the fifth doping region and the sixth doping region are of the same doping type, the fifth doping region is located on the side of the third doping region away from the second channel region, and the sixth doping region is located on the side of the third doping region away from the second channel region.
  • the region is located on a side of the fourth doped region away from the second channel region.
  • the second source electrode is connected to the first doping region through the fifth doping region, and the second source electrode and the fifth doping region are multiplexed into the first source electrode;
  • the second drain electrode is connected to the second doping region through the sixth doping region The impurity region is connected, and the second drain electrode and the sixth impurity region are multiplexed into the first drain electrode.
  • the doping concentrations of the first doped region and the second doped region may be equal.
  • the doping concentrations of the third doped region and the fourth doped region may be equal.
  • the doping concentrations of the fifth doping region and the sixth doping region may be equal
  • the doping concentration of the fifth doping region is greater than the doping concentration of the third doping region.
  • the second source electrode and the second drain electrode are disposed on the side of the second active layer away from the substrate; the second source electrode passes through the The fifth doping region is electrically connected to the first doping region, the second source electrode and the fifth doping region are multiplexed into a first source electrode; the second drain electrode is electrically connected to the second doping region through the sixth doping region , the second drain electrode and the sixth doping region are multiplexed into the first drain electrode.
  • the second source electrode and the second drain electrode are disposed on a side of the second active layer away from the substrate; the second The source electrode is electrically connected to the first doping region through the fifth doping region, the second source electrode and the fifth doping region are multiplexed into a first source electrode; the second drain electrode is connected to the second doping region through the sixth doping region The second drain electrode and the sixth doped region are multiplexed as the first drain electrode; the second drain electrode of the i-th switch unit and the second source electrode of the i+1-th switch unit are the same electrode, 1 ⁇ i ⁇ N.
  • the second source electrode of the first switch unit is disposed on the side of the second active layer of the first switch unit away from the substrate, and finally The second drain electrode of one switch unit is arranged on the side of the second active layer of the last switch unit away from the substrate; in the first switch unit, the second source electrode is connected to the first dopant through the fifth doping region
  • the second source electrode is multiplexed with the fifth doping region as the first source electrode;
  • the sixth doping region is multiplexed as the second drain electrode, and the second doping region is multiplexed as the first drain electrode;
  • the fifth doped region is multiplexed as the second source electrode
  • the first doped region is multiplexed as the first source electrode
  • the sixth doped region is multiplexed as the second drain electrode
  • the second doped region is multiplexed as the second drain electrode.
  • the sixth doping region of the j-1th switching unit and the fifth doping region of the jth switching unit are the same doping region, and the j-1th doping region
  • the second doping region of the switch unit and the first doping region of the jth switch unit are the same doping region; in the last switching unit, the fifth doping region is multiplexed as the second source electrode, and the first doping region
  • the region is multiplexed into the first source electrode, the second drain electrode is electrically connected to the second doped region through the sixth doped region, and the second drain electrode and the sixth doped region are multiplexed into the first drain electrode.
  • the sixth doping region of the first switching unit and the fifth doping region of the second switching unit, and the second doping region and the second doping region of the first switching unit is equivalent to a parallel resistance, which can reduce the resistance of the switch structure, thereby improving the charging rate of the switch structure.
  • the orthographic projection of the first channel region 111 on the substrate 10 coincides with the orthographic projection of the second channel region 211 on the substrate 10; the first channel The orthographic projection of the region 111 on the substrate 10 at least partially overlaps the orthographic projection of the first gate electrode 12 on the substrate 10 .
  • FIG. 5 is a top view of a display substrate provided by an exemplary embodiment. As shown in FIG. 2 , FIG. 4 and FIG. 5 , a display substrate provided by an exemplary embodiment further includes: a light shielding layer 20 .
  • the light shielding layer 20 is located on the side of the first active layer 11 close to the substrate 10 , and the orthographic projection of the light shielding layer 20 on the substrate 10 covers the orthographic projection of the first channel region 111 on the substrate 10 .
  • a display substrate provided by an exemplary embodiment includes: a first metal layer, a first insulating layer 31 , a first polysilicon layer, a first metal layer, a first insulating layer 31 , a first polysilicon layer, The second insulating layer 32, the second metal layer, the third insulating layer 33, the second polysilicon layer, the fourth insulating layer 34, and the third metal layer.
  • the first metal layer includes a light shielding layer 20, the first polysilicon layer includes a first active layer 11, the second metal layer includes a first gate electrode 12 and a scan signal line, and the second polysilicon layer includes: a first Two active layers 21, the third metal layer includes: a second source electrode 23, a second drain electrode 24 and a data signal line.
  • a display substrate provided by an exemplary embodiment further includes: a flat layer 35 , a first transparent conductive layer, a fifth insulating layer 36 and a second transparent conductive layer.
  • the first transparent conductive layer includes: a common electrode 41
  • the second transparent conductive layer includes: a pixel electrode 42 .
  • the flat layer 35 is located on the side of the third metal layer away from the substrate 10
  • the first transparent conductive layer is located on the side of the flat layer 35 away from the substrate 10
  • the fifth insulating layer 36 is located on the side of the first transparent conductive layer away from the substrate 10
  • the two transparent conductive layers are located on the side of the fifth insulating layer 36 away from the substrate 10 .
  • the flat layer 35 is provided with a first via hole exposing the second drain electrode, and the first transparent conductive layer is provided with a second via hole exposing the first via hole.
  • the orthographic projection of the second via hole on the substrate covers the orthographic projection of the first via hole on the substrate.
  • the fifth insulating layer 36 is provided with a third via hole exposing the second via hole.
  • the pixel electrode 42 is connected to the second drain electrode 24 through the first via hole, the second via hole and the third via hole.
  • the first metal layer, the second metal layer, and the third metal layer may use metal materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo).
  • Any one or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo and the like.
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) one or more, which can be a single layer, a multi-layer or a composite layer.
  • the first insulating layer is called the buffer layer, which is set to improve the water and oxygen resistance of the substrate
  • the second insulating layer is called the first gate insulating layer
  • the third insulating layer is called the second gate insulating layer
  • the fourth insulating layer is called the layer
  • the intermediate insulating layer, the fifth insulating layer is called the passivation layer.
  • the thickness of the second insulating layer may be smaller than the thickness of the third insulating layer, and the thickness of the first insulating layer may be smaller than the sum of the thicknesses of the second insulating layer and the third insulating layer, so as to ensure the insulating effect.
  • the capacity of the storage capacitor can be increased.
  • the planarization layer may employ an organic material.
  • the charging rate of the display substrate can reach 99.75%, which improves the display effect of the display substrate and ensures that the display substrate has no risk of poor display. Poor display refers to bad phenomena such as vertical lines.
  • the structure of a display substrate provided by an exemplary embodiment is described below through a manufacturing process of the display substrate.
  • the "patterning process” includes deposition of film layers, photoresist coating, mask exposure, development, etching and photoresist stripping processes. Deposition can use any one or more of sputtering, evaporation and chemical vapor deposition, coating can use any one or more of spray coating and spin coating, and etching can use any one or more of dry etching and wet etching. one or more.
  • “Film” refers to a thin film made of a material on a substrate by a deposition or coating process. If the “film” does not require a patterning process during the entire fabrication process, the “film” may also be referred to as a “layer”. If the "film” needs a patterning process during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process.
  • (1) forming a first metal layer and a first insulating layer on a substrate comprising: depositing a first metal film on the substrate, patterning the first metal film through a patterning process to form a first metal layer, and forming a first metal film on the substrate
  • a first insulating film is deposited on the first insulating layer of the layer, and the first insulating film is patterned through a patterning process to form the first insulating layer 31 .
  • the first metal layer includes: a light shielding layer, as shown in FIGS. 6 and 7 .
  • the first polysilicon layer comprises: depositing a first amorphous silicon film on the first insulating layer, crystallizing the first amorphous silicon film, and performing a patterning process on the crystallized first amorphous silicon film.
  • the crystalline silicon film is patterned to form a first polysilicon film, the threshold voltage doping treatment is performed on the first polysilicon film, and the N-type heavy doping is performed on the first polysilicon film to form the third doping region 114 and
  • the fourth doping region 115 is P-type lightly doped to the first polysilicon thin film to form a first doping region 112 and a second doping region 113 to form a first polysilicon layer.
  • the first polysilicon layer includes: a first active layer 11 , as shown in FIGS. 8 and 9 .
  • the second metal layer comprises: depositing a second insulating film on the first insulating layer formed with the first polysilicon layer, and patterning the second insulating film by a patterning process to form
  • a second metal thin film is deposited on the second insulating layer 32, and the second metal thin film is patterned through a patterning process to form a second metal layer.
  • the second metal layer includes: scan signal lines and first gate electrodes 11 , as shown in FIGS. 10 and 11 .
  • the third insulating layer and the second polysilicon layer comprising: depositing a third insulating film on the second insulating layer formed with the second metal layer, patterning the third metal film by a patterning process, and forming a third insulating film
  • Two polysilicon films, P-type doping is performed on the first polysilicon film to form a fifth doping region 212 and a sixth doping region 213 to form a second polysilicon layer.
  • the second polysilicon layer includes: a second active layer 21 , as shown in FIGS. 12 and 13 .
  • a fourth via hole V4 exposing the third doped region 114 and a fifth via hole V5 exposing the fourth doped region 115 are provided on the second insulating layer 32 and the third insulating layer 33 .
  • the fifth doped region 212 is electrically connected to the third doped region 114 through the fourth via V4, and the sixth doped region 213 is electrically connected to the third doped region 114 through the fifth via V5.
  • forming the fourth insulating layer comprising: depositing a fourth insulating film on the third insulating layer formed with the second polysilicon layer, patterning the fourth insulating film by a patterning process, and forming the fourth insulating layer 34, As shown in Figures 14 and 15.
  • the fourth insulating layer 34 is provided with a sixth via hole V6 exposing the fifth doping region 212 and a seventh via hole V7 exposing the sixth doping region 213 .
  • (6) forming the third metal layer including: depositing a third metal film on the fourth insulating layer 34, patterning the third metal film through a patterning process, and forming a third metal layer, the third metal layer comprising: a second source
  • the electrode 23 , the second drain electrode 24 and the data signal line are shown in FIGS. 16 and 17 .
  • the fourth insulating layer 34 is provided with a sixth via hole exposing the fifth doping region 212 and a seventh via hole exposing the sixth doping region 213 .
  • the second source electrode 23 is electrically connected to the fifth doped region 212 through the sixth via hole, and the second drain electrode 24 is electrically connected to the sixth doped region 213 through the seventh via hole.
  • Forming the flat layer includes: coating a flat film on the fourth insulating layer formed with the third metal layer, and forming the flat layer 35 by masking, exposing and developing the flat film.
  • a first via hole V1 is opened on the flat layer, and the first via hole V1 exposes the second drain electrode 24 , as shown in FIG. 18 .
  • Forming the first transparent conductive layer includes: depositing a first transparent conductive film on the flat layer, and patterning the first transparent conductive film through a patterning process to form the first transparent conductive layer.
  • the first transparent conductive layer includes the common electrode 41 .
  • a second via hole V2 exposing the first via hole V1 is arranged on the first transparent conductive layer, and the orthographic projection of the second via hole V2 on the substrate covers the orthographic projection of the first via hole V1 on the substrate, as shown in FIG. 19 .
  • forming the fifth insulating layer and the second transparent conductive layer comprising: depositing a fifth insulating film on the first transparent conductive layer, patterning the fifth insulating film by a patterning process, forming a fifth insulating layer 36, A second transparent conductive film is deposited on the five insulating layers 36, and the second transparent conductive film is patterned through a patterning process to form a second transparent conductive layer.
  • the second transparent conductive layer includes the pixel electrode 42 , as shown in FIG. 2 .
  • the fifth insulating layer is provided with a third via hole exposing the second via hole, and the pixel electrode is connected to the second drain electrode through the first via hole, the second via hole and the third via hole.
  • An embodiment of the present disclosure further provides a method for preparing a display substrate, and the method for preparing a display substrate provided by an embodiment of the present disclosure includes:
  • Step S1 providing a substrate.
  • Step S2 forming a switch structure on the substrate.
  • the switch structure is electrically connected with the control signal terminal, the signal input terminal and the signal output terminal respectively, and is arranged to provide the signal output terminal with the signal of the signal input terminal under the control of the control signal terminal;
  • the switch structure includes: a switch unit; the switch unit includes: a first A transistor and a second transistor; the types of the first transistor and the second transistor are opposite;
  • the first transistor includes: a first active layer, a first gate electrode, a first source electrode and a first drain electrode, and the second transistor includes: a first Two active layers, a second gate electrode, a second source electrode and a second drain electrode; the first gate electrode and the second gate electrode are respectively electrically connected to the control signal terminal, and the first source electrode and the second source electrode are respectively connected to the signal input
  • the terminals are electrically connected, and the first drain electrode and the second drain electrode are respectively electrically connected to the signal output terminals; the orthographic projection of the first active layer on the substrate coincides with the orthographic projection of the second active layer on the substrate.
  • the display substrate is the display substrate provided in any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.
  • forming the switch structure on the substrate in step S2 includes:
  • Step S21 forming a first metal layer and a first insulating layer on the substrate in sequence.
  • the first metal layer includes: a light shielding layer.
  • Step S22 forming a first polysilicon layer on the first insulating layer.
  • the first polysilicon layer includes: a first active layer
  • Step S23 sequentially forming a second insulating layer and a second metal layer on the first insulating layer formed with the first polysilicon layer.
  • the second metal layer includes: a first gate electrode and a scan signal line; the first gate electrode and the second gate electrode are the same electrode;
  • Step S24 forming a third insulating layer on the second insulating layer on which the second metal layer is formed.
  • Step S25 forming a second polysilicon layer on the third insulating layer.
  • the second polysilicon layer includes: a second active layer
  • step S26 a fourth insulating layer and a third metal layer are sequentially formed on the third insulating layer formed with the second polysilicon layer.
  • the third metal layer includes: a second source electrode, a second drain electrode and a data signal line.
  • step S26 the method for preparing a display substrate provided by an exemplary embodiment further includes:
  • Step S27 forming a flat layer on the fourth insulating layer on which the third metal layer is formed.
  • Step S28 forming a first transparent conductive layer on the flat layer.
  • the first transparent conductive layer includes: a common electrode;
  • Step S29 forming a fifth insulating layer on the first transparent conductive layer, and forming a second transparent conductive layer on the fifth insulating layer.
  • the second transparent conductive layer includes: a pixel electrode.
  • step S22 includes: depositing a first amorphous silicon film on the first insulating layer, and depositing the first amorphous silicon film on the first insulating layer.
  • the silicon film is crystallized, and the crystallized first amorphous silicon film is processed by a patterning process to form a first polysilicon film.
  • the first polysilicon film includes: along the vertical direction of the first active layer and the second active layer The first area, the second area, the third area, the fourth area and the fifth area arranged in the layer arrangement direction, the second area and the third area are respectively located on both sides of the first area, and the fourth area is located in the second area One side away from the first area, the fifth area is located at the side of the third area away from the first area; threshold voltage doping treatment is performed on the first polysilicon film; N-type heavy doping treatment is performed on five regions; N-type light doping treatment is performed on the second region and the third region of the first polysilicon thin film to form a first polysilicon layer.
  • performing N-type heavy doping treatment on the fourth region and the fifth region of the first polysilicon film includes: coating photoresist on the first polysilicon film, and performing a patterning process A first opening is formed in the photoresist, the first opening is located above the positions of the fourth region and the fifth region, and the fourth region and the fifth region of the first polysilicon film are ion implanted through the first opening to form the first opening.
  • performing N-type light doping treatment on the second region and the third region of the first polysilicon thin film includes: coating photoresist on the first polysilicon thin film, and patterning The process forms a second opening in the photoresist, the second opening is located above the positions of the second area and the third area, and the second area and the third area of the first polysilicon film are formed by ion implantation through the second opening The third doped region and the fourth doped region.
  • step S25 includes: depositing a second amorphous silicon film on the third insulating layer, and depositing the second amorphous silicon film on the third insulating layer.
  • the silicon film is crystallized, and the crystallized second amorphous silicon film is processed by a patterning process to form a second polysilicon film;
  • the second polysilicon film includes: along the vertical direction of the first active layer and the second active layer The first area, the second area and the third area arranged in the layer arrangement direction, the second area and the third area are respectively located on both sides of the first area; for the second area and the third area of the second polysilicon film A P-type doping process is performed to form a second polysilicon layer.
  • performing the P-type doping treatment on the second region and the third region of the second polysilicon thin film includes: coating photoresist on the second polysilicon thin film, and performing a patterning process on the second polysilicon thin film.
  • An opening is formed in the photoresist, the opening is located above the positions of the second region and the third region, and the second region and the third region of the second polysilicon film are ion implanted through the opening to form the fifth doping region and the sixth region doped region.
  • step S22 includes: depositing a first amorphous silicon film on the first insulating layer, and depositing the first amorphous silicon film on the first insulating layer.
  • the silicon film is crystallized, and the crystallized first amorphous silicon film is processed by a patterning process to form a first polysilicon film;
  • the first polysilicon film includes: along the vertical direction of the first active layer and the second active layer The first area, the second area and the third area are arranged in the layer arrangement direction, and the second area and the third area are respectively located on both sides of the first area; for the second area and the third area of the first polysilicon film A P-type doping process is performed to form a first polysilicon layer.
  • performing the P-type doping treatment on the second region and the third region of the first polysilicon thin film includes: coating photoresist on the first polysilicon thin film, and performing a patterning process on the first polysilicon thin film. An opening is formed in the photoresist, the opening is located above the positions of the second region and the third region, and the second region and the third region of the first polysilicon film are ion implanted through the opening to form the first doped region and the second doped region;
  • step S25 includes: depositing a second amorphous silicon film on the third insulating layer, and depositing the second amorphous silicon film on the third insulating layer.
  • the silicon film is crystallized, and the crystallized second amorphous silicon film is processed by a patterning process to form a second polysilicon film;
  • the second polysilicon film includes: a direction perpendicular to the first active layer and the second
  • the first area, the second area, the third area, the fourth area and the fifth area are arranged in the arrangement direction of the source layer, the second area and the third area are respectively located on both sides of the first area, and the fourth area is located in the second area the region away from the first region, the fifth region is located at the side of the third region away from the first region;
  • the threshold voltage doping treatment is performed on the second polysilicon film;
  • the fourth region and N-type heavy doping treatment is performed on the fifth region;
  • N-type light doping treatment is performed on the second region and the third region of the second polysilicon thin film to form a second polysilicon layer.
  • performing the N-type heavy doping treatment on the fourth region and the fifth region of the second polysilicon film includes: coating a photoresist on the second polysilicon film, and performing a patterning process on the second polysilicon film A first opening is formed in the photoresist, the first opening is located above the positions of the fourth region and the fifth region, and the fourth region and the fifth region of the second polysilicon film are ion implanted through the first opening to form the fifth region. doped region and a sixth doped region.
  • performing the N-type light doping process on the second region and the third region of the second polysilicon film includes: coating photoresist on the second polysilicon film, and performing a patterning process A second opening is formed in the photoresist, the second opening is located above the positions of the second region and the third region, and the second region and the third region of the second polysilicon film are ion-implanted through the second opening to form the second opening. Three doped regions and a fourth doped region.
  • An embodiment of the present disclosure further provides a method for driving a display substrate, which is used to drive the display substrate.
  • the method for driving a display substrate provided by an embodiment of the present disclosure includes: providing a control signal to a control signal terminal to provide a signal input to a signal output terminal terminal signal.
  • the display substrate is the display substrate provided in any of the foregoing embodiments, and the implementation principle and effect are similar.
  • providing the control signal to the control signal terminal includes: providing a first control signal to the control signal terminal, where the first control signal is a low-level signal;
  • providing the control signal to the control signal terminal includes: providing a second control signal to the control signal terminal, and the second control signal is a high-level signal.
  • Embodiments of the present disclosure also provide a display device, including: a display substrate.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • the display substrate is the display substrate provided in any of the foregoing embodiments, and the implementation principle and effect are similar.

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Abstract

一种显示基板及其制备方法、驱动方法、显示装置，显示基板包括：基底以及设置在基底上的开关结构，开关结构与控制信号端、信号输入端和信号输出端电连接；开关结构包括：开关单元；开关单元包括：第一晶体管和第二晶体管；第一晶体管和第二晶体管的类型相反；第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；第一栅电极和第二栅电极与控制信号端电连接，第一源电极和第二源电极与信号输入端电连接，第一漏电极和第二漏电极与信号输出端电连接；第一有源层在基底上的正投影与第二有源层在基底上的正投影重合。

Description

显示基板及其制备方法、驱动方法、显示装置
本申请要求于2020年6月17日提交中国专利局、申请号为202010553328.1、发明名称为“一种显示基板及其制备方法、驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种显示基板及其制备方法、驱动方法、显示装置。
背景技术
近年来，平板显示器，如薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有源矩阵有机发光二极管显示器(Active Matrix Organic Light Emitting Diode，AMOLED)，由于具有重量轻，厚度薄以及低功耗等优点，因而被广泛应用于电视、手机等电子产品中。
随着显示技术的发展，高频驱动的显示产品成为发展的趋势。但是，显示产品的高频驱动会导致显示产品中每行像素充电时间减少，使得显示产品的充电率降低，影响了显示产品的显示效果。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示基板，包括：基底以及设置在所述基底上的开关结构，所述开关结构与控制信号端、信号输入端和信号输出端电连接，设置为在所述控制信号端的控制下，向所述信号输出端提供所述信号输入端的信号；
所述开关结构包括：开关单元；所述开关单元包括：第一晶体管和第二 晶体管；所述第一晶体管和所述第二晶体管的类型相反；
所述第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，所述第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；
所述第一栅电极和所述第二栅电极与所述控制信号端电连接，所述第一源电极和所述第二源电极与所述信号输入端电连接，所述第一漏电极和所述第二漏电极与所述信号输出端电连接；
所述第一有源层在所述基底上的正投影与所述第二有源层在所述基底上的正投影重合。
在一些可能的实现方式中，所述开关单元的数量为N个；
第一个开关单元的第一源电极与所述信号输入端电连接，第j个开关单元的第一漏电极与第j+1个开关单元的第一源电极电连接，第N个开关单元的第一漏电极与所述信号输出端电连接；
所有开关单元的第一栅电极和第二栅电极与所述控制信号端电连接，N≥1，1<j<N。
在一些可能的实现方式中，所述显示基板还包括：设置在所述基底上的扫描信号线、数据信号线、公共电极和像素电极；
所述扫描信号线与所述控制信号端电连接，设置为向所述控制信号端提供信号；
所述数据信号线与所述信号输入端连接，设置为向所述信号输入端提供信号；
所述信号输出端与所述像素电极连接，设置为向所述像素电极提供信号；
所述公共电极位于所述像素电极靠近所述基底的一侧，设置为与所述像素电极之间形成电场。
在一些可能的实现方式中，所述第一栅电极和所述第二栅电极配置为同一电极；
所述第一有源层位于所述第一栅电极靠近所述基底的一侧；所述第二有 源层位于所述第一栅电极远离所述基底的一侧；所述第二有源层与所述第一有源层连接。
在一些可能的实现方式中，当第一晶体管为N型晶体管，第二晶体管为P型晶体管时：
所述第一有源层包括：沿垂直于所述第一有源层和所述第二有源层排布方向排布的第一沟道区、第一掺杂区、第二掺杂区、第三掺杂区和第四掺杂区；
所述第一掺杂区和所述第二掺杂区的掺杂类型相同，且分别位于所述第一沟道区的两侧；
所述第三掺杂区和所述第四掺杂区的掺杂类型相同，所述第三掺杂区位于所述第一掺杂区远离所述第一沟道区的一侧，所述第四掺杂区位于所述第二掺杂区远离所述第一沟道区的一侧；
所述第三掺杂区的掺杂浓度大于所述第一掺杂区的掺杂浓度；
所述第二有源层包括：沿垂直于所述第一有源层和所述第二有源层排布方向排布的第二沟道区、第五掺杂区和第六掺杂区；
所述第五掺杂区和所述第六掺杂区的掺杂类型相同，且分别位于所述第二沟道区的两侧。
在一些可能的实现方式中，当所述开关单元的数量为一个时，在所述开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第三掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第四掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；
当所述开关单元数量为至少两个时，在每个开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第三掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第四掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；第 i个开关单元的第二漏电极与第i+1个开关单元的第二源电极为同一电极，1≤i<N；
或者，当所述开关单元为数量为至少两个时，第一个开关单元的第二源电极设置在第一个开关单元的第二有源层远离基底的一侧，最后一个开关单元的第二漏电极设置在最后一个开关单元的第二有源层的远离基底的一侧；在第一个开关单元中，所述第二源电极通过所述第五掺杂区与所述第三掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第六掺杂区复用为第二漏电极，所述第四掺杂区复用为第一漏电极；在第j个开关单元中，所述第五掺杂区复用为第二源电极，所述第三掺杂区复用为第一源电极，所述第六掺杂区复用为第二漏电极，所述第四掺杂区复用为第一漏电极，1<j<N；第j-1个开关单元的第六掺杂区与第j个开关单元的第五掺杂区为同一掺杂区，第j-1个开关单元的第四掺杂区与第j个开关单元的第三掺杂区为同一掺杂区；在最后一个开关单元中，所述第五掺杂区复用为第二源电极，所述第三掺杂区复用为第一源电极，第二漏电极通过所述第六掺杂区与所述第四掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极。
在一些可能的实现方式中，当第一晶体管为P型晶体管，第二晶体管为N型晶体管时；
所述第一有源层包括：沿垂直于所述第一有源层和所述第二有源层排布方向排布的第一沟道区、第一掺杂区和第二掺杂区；
所述第一掺杂区和所述第二掺杂区的掺杂类型相同，且分别位于所述第一沟道区的两侧；
所述第二有源层包括：沿垂直于所述第一有源层和所述第二有源层排布方向排布的第二沟道区、第三掺杂区、第四掺杂区、第五掺杂区和第六掺杂区；
所述第三掺杂区和所述第四掺杂区的掺杂类型相同，且分别位于所述第二沟道区的两侧；
所述第五掺杂区和所述第六掺杂区的掺杂类型相同，所述第五掺杂区位于所述第三掺杂区远离所述第二沟道区的一侧，所述第六掺杂区位于所述第 四掺杂区远离所述第二沟道区的一侧；
所述第五掺杂区的掺杂浓度大于所述第三掺杂区的掺杂浓度。
在一些可能的实现方式中，当所述开关单元的数量为一个时，在所述开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第一掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第二掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；
当所述开关单元数量为至少两个时，在每个开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第一掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第二掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；第i个开关单元的第二漏电极与第i+1个开关单元的第二源电极为同一电极，1≤i<N；
或者，当所述开关单元为数量为至少两个时，第一个开关单元的第二源电极设置在第一个开关单元的第二有源层远离基底的一侧，最后一个开关单元的第二漏电极设置在最后一个开关单元的第二有源层的远离基底的一侧；在第一个开关单元中，所述第二源电极通过所述第五掺杂区与所述第一掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第六掺杂区复用为第二漏电极，所述第二掺杂区复用为第一漏电极；在第j个开关单元中，所述第五掺杂区复用为第二源电极，所述第一掺杂区复用为第一源电极，所述第六掺杂区复用为第二漏电极，所述第二掺杂区复用为第一漏电极，1<j<N；第j-1个开关单元的第六掺杂区与第j个开关单元的第五掺杂区为同一掺杂区，第j-1个开关单元的第二掺杂区与第j个开关单元的第一掺杂区为同一掺杂区；在最后一个开关单元中，所述第五掺杂区复用为第二源电极，所述第一掺杂区复用为第一源电极，所述第二漏电极通过所述第六掺杂区与所述第二掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极。
在一些可能的实现方式中，所述第一沟道区在基底上的正投影与所述第二沟道区在基底上的正投影重合；
所述第一沟道区在所述基底上的正投影与所述第一栅电极在所述基底上的正投影至少部分重叠。
在一些可能的实现方式中，所述显示基板还包括：遮光层；
所述遮光层位于所述第一有源层靠近所述基底的一侧，所述遮光层在基底上的正投影覆盖所述第一沟道区在所述基底上的正投影。
在一些可能的实现方式中，所述显示基板包括：沿垂直于基底方向依次设置的第一金属层、第一绝缘层、第一多晶硅层、第二绝缘层、第二金属层、第三绝缘层、第二多晶硅层、第四绝缘层和第三金属层；
所述第一金属层包括：遮光层，所述第一多晶硅层包括：第一有源层，所述第二金属层包括：第一栅电极和扫描信号线，所述第二多晶硅层包括：第二有源层，所述第三金属层包括：第二源电极、第二漏电极和数据信号线。
在一些可能的实现方式中，所述显示基板还包括：平坦层、第一透明导电层、第五绝缘层和第二透明导电层；
所述平坦层位于所述第三金属层远离所述基底的一侧，所述平坦层上设置有暴露出第二漏电极的第一过孔；
所述第一透明导电层位于所述平坦层远离所述基底的一侧，所述第一透明导电层上设置暴露出所述第一过孔的第二过孔；所述第二过孔在基底上的正投影覆盖所述第一过孔在基底上的正投影；所述第一透明导电层包括：公共电极；
所述第五绝缘层位于所述第一透明导电层远离所述基底的一侧，所述第五绝缘层上设置有暴露出所述第二过孔的第三过孔；
所述第二透明导电层位于所述第五绝缘层远离所述基底的一侧，所述第二透明导电层包括：像素电极，所述像素电极通过所述第一过孔、所述第二过孔和所述第三过孔与所述第二漏电极连接。
第二方面，本公开实施例还提供了一种显示装置，包括：上述显示基板。
第三方面，本公开实施例还提供了一种显示基板的制备方法，设置为形 成上述显示基板，所述方法包括：
提供一基底；
在所述基底上形成开关结构；所述开关结构，分别与控制信号端、信号输入端和信号输出端电连接，设置为在所述控制信号端的控制下，向所述信号输出端提供所述信号输入端的信号；所述开关结构包括：开关单元；所述开关单元包括：第一晶体管和第二晶体管；所述第一晶体管和所述第二晶体管的类型相反；所述第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，所述第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；所述第一栅电极和所述第二栅电极分别与所述控制信号端电连接，所述第一源电极和所述第二源电极分别与所述信号输入端电连接，所述第一漏电极和所述第二漏电极分别与所述信号输出端电连接；所述第一有源层在所述基底上的正投影与所述第二有源层在所述基底上的正投影重合。
在一些可能的实现方式中，所述在所述基底上形成开关结构包括：
在基底上依次形成第一金属层和第一绝缘层；所述第一金属层包括：遮光层；
在第一绝缘层上形成第一多晶硅层；所述第一多晶硅层包括：第一有源层；
在形成有第一多晶硅层的第一绝缘层上依次形成第二绝缘层和第二金属层；所述第二金属层包括：第一栅电极和扫描信号线；所述第一栅电极和所述第二栅电极为同一电极；
在形成有第二金属层的第二绝缘层上形成第三绝缘层；
在第三绝缘层上形成第二多晶硅层，所述第二多晶硅层包括：第二有源层；
在形成有第二多晶硅层的第三绝缘层上依次形成第四绝缘层和第三金属层，所述第三金属层包括：第二源电极、第二漏电极和数据信号线。
在一些可能的实现方式中，所述在形成有第二多晶硅层的第三绝缘层上依次形成第四绝缘层和第三金属层之后，所述方法还包括：
在形成有第三金属层的第四绝缘层上形成平坦层；
在平坦层上形成第一透明导电层，所述第一透明导电层包括：公共电极；
在所述第一透明导电层上形成第五绝缘层；
在第五绝缘层上形成第二透明导电层，所述第二透明导电层包括：像素电极。
在一些可能的实现方式中，当所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管时，
所述在所述第一绝缘层上形成第一多晶硅层包括：
在第一绝缘层上沉积第一非晶硅薄膜，将所述第一非晶硅薄膜晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行处理形成第一多晶硅薄膜；所述第一多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域、第三区域、第四区域和第五区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧，所述第四区域位于所述第二区域远离所述第一区域的一侧，所述第五区域位于所述第三区域远离所述第一区域的一侧；
对所述第一多晶硅薄膜进行阈值电压掺杂处理；
对所述第一多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理；
对所述第一多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，以形成第一多晶硅层；
所述在所述第三绝缘层上形成第二多晶硅层包括：
在第三绝缘层上沉积第二非晶硅薄膜，将所述第二非晶硅薄膜晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行处理形成第二多晶硅薄膜；所述第二多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域和第三区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧；
对所述第二多晶硅薄膜的第二区域和第三区域进行P型掺杂处理，以形成第二多晶硅层；
当所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管时，
所述在所述第一绝缘层上形成第一多晶硅层包括：
在第一绝缘层上沉积第一非晶硅薄膜，将所述第一非晶硅薄膜晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行处理形成第一多晶硅薄膜；所述第一多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域和第三区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧；
对所述第一多晶硅薄膜的第二区域和第三区域进行P型掺杂处理，以形成第一多晶硅层；
所述在所述第三绝缘层上形成第二多晶硅层包括：
在第三绝缘层上沉积第二非晶硅薄膜，将所述第二非晶硅薄膜晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行处理，形成第二多晶硅薄膜；所述第二多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域、第三区域、第四区域和第五区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧，所述第四区域位于所述第二区域远离所述第一区域的一侧，所述第五区域位于所述第三区域远离所述第一区域的一侧；
对所述第二多晶硅薄膜进行阈值电压掺杂处理；
对所述第二多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理；
对所述第二多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，以形成第二多晶硅层。
第四方面，本公开实施例还提供了一种显示基板的驱动方法，用于驱动上述显示基板，所述方法包括：
向控制信号端提供控制信号，以向信号输出端提供信号输入端的信号。
在一些可能的实现方式中，当信号输入端的信号为高电平信号时，所述向控制信号端提供控制信号包括：
向控制信号端提供第一控制信号，所述第一控制信号为低电平信号；
当信号输入端的信号为低电平信号时，所述向控制信号端提供控制信号包括：
向控制信号端提供第二控制信号，所述第二控制信号为高电平信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开实施例技术方案的理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开实施例的技术方案，并不构成对本公开实施例的技术方案的限制。
图1为本公开实施例提供的开关结构的示意图；
图2为本公开实施例提供的显示基板的剖视图；
图3为一种示例性实施例提供的开关结构的示意图；
图4A为一种示例性实施例提供的显示基板的剖视图；
图4B为另一示例性实施例提供的显示基板的剖视图；
图5为一种示例性实施例提供的显示基板的俯视图；
图6为形成第一绝缘层的剖视图；
图7为形成第一绝缘层的俯视图；
图8为形成第一多晶硅层的剖视图；
图9为形成第一多晶硅层的俯视图；
图10为形成第二金属层的剖视图；
图11为形成第二金属层的俯视图；
图12为形成第二多晶硅层的剖视图；
图13为形成第二多晶硅层的俯视图；
图14为形成第四绝缘层的剖视图；
图15为形成第四绝缘层的俯视图；
图16为形成第三金属层的剖视图；
图17为形成第三金属层的俯视图；
图18为形成平坦层的剖视图；
图19为形成第一透明导电层的剖视图。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开实施例包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，在本公开实施例中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的 电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
文中所述“a区和b区分别位于c区的两侧是指：a区位于c区的一侧，b区位于c区远离a区的另一侧”。
图1为本公开实施例提供的开关结构的示意图，图2为本公开实施例提供的显示基板的剖视图。如图1和2所示，本公开实施例提供的一种显示基板包括：基底10以及设置在基底10上的开关结构。开关结构与控制信号端G、信号输入端IN和信号输出端OUT电连接，设置为在控制信号端G的控制下，向信号输出端OUT提供信号输入端IN的信号。开关结构包括：开关单元1，开关单元1包括：第一晶体管T1和第二晶体管T2；第一晶体管T1和第二晶体管T2的类型相反。图2是以开关结构包括一个开关单元为例进行说明的。
第一晶体管T1包括：第一有源层11、第一栅电极12、第一源电极13和第一漏电极14，第二晶体管T2包括：第二有源层21、第二栅电极22、第二源电极23和第二漏电极24。
如图1所示，第一栅电极和第二栅电极与控制信号端G电连接，第一源电极和第二源电极与信号输入端IN电连接，第一漏电极和第二漏电极与信号输出端OUT电连接。
如图2所示，第一有源层11在基底10上的正投影与第二有源层21在基底10上的正投影重合。
在一种示例性实施例中，基底10可以为刚性衬底或柔性衬底，其中，刚性衬底可以为但不限于玻璃、金属箔片中的一种或多种；柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，第一晶体管T1和第二晶体管T2可以为P型，或者可以为N型。当第一晶体管T1为N型时，第二晶体管T2为P型。当第一晶体管T1为P型时，第二晶体管T2为N型。
在一种示例性实施例中，第一有源层11和第二有源层21采用多晶硅材料制成。
本实施例中，类型相反，且并联设置的第一晶体管T1和第二晶体管T2构成了传输门。
在一种示例性实施例中，开关结构在第一栅电极的信号的电压为0V和第二栅电极的信号的电压为0V时截止。开关结构在第一栅电极的信号和第二栅电极的信号的电压至少一个不为0时导通。
在一种示例性实施例中，以第一晶体管T1为N型，第二晶体管T2为P型为例，当信号输入端的信号为高电平信号时，可以通过向控制信号端提供高电平信号或者低电平信号使开关结构导通，进而向信号输出端提供信号输入端的信号。当控制信号端提供高电平信号时，第一晶体管T1导通，第二晶体管T2截止，第一晶体管的栅源电压差的绝对值为第一差值。当控制信号端提供低电平信号时，第一晶体管T1截止，第二晶体管T2导通，第二晶体管T2的栅源电压差的绝对值为第二差值，由于低电平信号的电压值小于高电平信号的电压值，因此，第二差值大于第一差值。以信号输入端提供的信号的电压值为8V为例，当控制信号端提供高电平信号时，控制信号端的信号的电压值为6V，第一差值为2V，当控制信号端提供低电平信号时，控制信号端的信号的电压值为-6V，第二差值为14V。由于第二差值大于第一差值，因此，当控制信号端提供低电平信号时开关结构的电阻要小于当控制信号端提供高电平信号时开关结构的电阻，这种情况下，本公开实施例可以向控制信号端提供低电平信号导通开关结构，进而提升开关结构的充电能力。同理，当信号输入端提供的信号为低电平信号时，第二差值小于第一差值。以信号输入端提供的信号的电压值为-8V为例，当控制信号端提供高电平信号时，控制信号端的信号的电压值为6V，第一差值为14V，当控制信号端提供低电平信号时，控制信号端的信号的电压值为-6V，第二差值为2V。由于第二差值小于第一差值，因此，当控制信号端提供高电平信号时开关结构的 电阻要小于当控制信号端提供低电平信号时开关结构的电阻，这种情况下，本公开实施例可以向控制信号端提供高电平信号导通开关结构，进而提升开关结构的充电能力。
本实施例可以根据信号输入端的信号来控制控制信号端的信号，当信号输入端的信号为高电平信号时，可以通过向控制信号端提供低电平信号以导通开关结构，当信号输入端的信号为低电平信号时，可以通过向控制信号端提供高电平信号以导通开关结构，提高了开关结构的充电能力，增大了开关结构的灵活性，避免了采用单一晶体管导致的充电能力不足的问题。
显示基板包括：设置在基底上的多个子像素。在一种示例性实施例中，开关结构可以应用在栅极驱动电路中、子像素中或者多路选择器中。
当开关结构应用在子像素中时，第一有源层11在基底10上的正投影与第二有源层21在基底10上的正投影重合，可以影响子像素的开口率。
本公开实施例提供的显示基板包括：基底以及设置在基底上的开关结构，开关结构，分别与控制信号端、信号输入端和信号输出端电连接，设置为在控制信号端的控制下，向信号输出端提供信号输入端的信号；开关结构包括：开关单元；开关单元包括：第一晶体管和第二晶体管；第一晶体管和第二晶体管的类型相反；第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；第一栅电极和第二栅电极分别与控制信号端电连接，第一源电极和第二源电极分别与信号输入端电连接，第一漏电极和第二漏电极分别与信号输出端电连接；第一有源层在基底上的正投影与第二有源层在基底上的正投影重合。本公开实施例通过设置包括类型相反的第一晶体管和第二晶体管的开关结构，可以提升开关结构的充电能力，有效地提高显示产品的充电率以支持显示产品的高频驱动，提升了显示效果。
图3为一种示例性实施例提供的开关结构的示意图，图4A为一种示例性实施例提供的显示基板的剖视图，图4B为另一示例性实施例提供的显示基板的剖视图。如图3和4所示，在一种示例性实施例中，开关单元的数量为N个。图3和图4是以开关结构包括两个开关单元为例进行说明的。
第一个开关单元的第一源电极与信号输入端IN电连接，第j个开关单元 的第一漏电极与第j+1个开关单元的第一源电极电连接，第N个开关单元的第一漏电极与信号输出端OUT电连接。所有开关单元的第一栅电极和第二栅电极与控制信号端G电连接，N≥1，1<j<N。
如图2和4所示，在一种示例性实施例中，显示基板还包括：设置在基底上的扫描信号线(图中未示出)、数据信号线(图中未示出)、公共电极41和像素电极42。
当开关结构应用在子像素中时，扫描信号线与控制信号端电连接，设置为向控制信号端提供信号；数据信号线与信号输入端连接，设置为向信号输入端提供信号；信号输出端与像素电极连接，设置为向像素电极提供信号；公共电极41位于像素电极42靠近基底10的一侧，设置为与像素电极之间形成电场。
在一种示例性实施例中，公共电极41和像素电极42为透明电极，透明电极的制作材料可以为氧化铟锡，或者可以为氧化锌锡。
在一种示例性实施例中，如图2和4所示，第一栅电极12和第二栅电极22配置为同一电极。
在一种示例性实施例中，如图2和4所示，第一有源层11位于第一栅电极12靠近基底10的一侧；第二有源层21位于第一栅电极12远离基底10的一侧；第二有源层21与第一有源层11连接。
在一种示例性实施例中，当第一晶体管为N型晶体管，第二晶体管为P型晶体管时；第一有源层11包括：沿垂直于第一有源层和第二有源层排布方向(即沿平行于基底方向)排布的第一沟道区111、第一掺杂区112、第二掺杂区113、第三掺杂区114和第四掺杂区115。第二有源层21包括：沿垂直于第一有源层和第二有源层排布方向排布的第二沟道区211、第五掺杂区212和第六掺杂区213。
第一掺杂区112、第二掺杂区113、第三掺杂区114、第四掺杂区115、第五掺杂区212和第六掺杂区213可以导电。
第一掺杂区112和第二掺杂区113的掺杂类型相同，且分别位于第一沟道区111的两侧；第三掺杂区114和第四掺杂区115的掺杂类型相同，第三 掺杂区114位于第一掺杂区112远离第一沟道区111的一侧，第四掺杂区115位于第二掺杂区113远离第一沟道区111的一侧。
第五掺杂区212和第六掺杂区213的掺杂类型相同，且分别位于第二沟道区211的两侧。
在一种示例性实施例中，如图2所示，当开关单元的数量为一个时，在开关单元中，第二源电极23和第二漏电极24设置在第二有源层21远离基底10的一侧。第二源电极23通过第五掺杂区212与第三掺杂区114电连接，第二源电极23与第五掺杂区212复用为第一源电极13。第二漏电极24通过第六掺杂区213与第四掺杂区115电连接，第二漏电极24与第六掺杂区213复用为第一漏电极14。
在一种示例性实施例中，当开关单元数量为至少两个时，在每个开关单元中，第二源电极23和第二漏电极24设置在第二有源层21远离基底10的一侧。第二源电极23通过第五掺杂区212与第三掺杂区114电连接，第二源电极23与第五掺杂区212复用为第一源电极13。第二漏电极24通过第六掺杂区213与第四掺杂区115电连接，第二漏电极24与第六掺杂区213复用为第一漏电极14。第i个开关单元的第二漏电极与第i+1个开关单元的第二源电极为同一电极，1≤i<N。图4A是以两个开关单元为例进行说明，如图4A所示，第一个开关单元的第二漏电极与第二个开关单元的第二源电极为同一电极。
在一种示例性实施例中，当开关单元为数量为至少两个时，第一个开关单元的第二源电极设置在第一个开关单元的第二有源层远离基底的一侧，最后一个开关单元的第二漏电极设置在最后一个开关单元的第二有源层的远离基底的一侧；在第一个开关单元中，第二源电极通过第五掺杂区与第三掺杂区电连接，第二源电极与第五掺杂区复用为第一源电极；第六掺杂区复用为第二漏电极，第四掺杂区复用为第一漏电极；在第j个开关单元中，第五掺杂区复用为第二源电极，第三掺杂区复用为第一源电极，第六掺杂区复用为第二漏电极，第四掺杂区复用为第一漏电极，1<j<N；第j-1个开关单元的第六掺杂区与第j个开关单元的第五掺杂区为同一掺杂区，第j-1个开关单元的第四掺杂区与第j个开关单元的第三掺杂区为同一掺杂区；在最后一个开 关单元中，第五掺杂区复用为第二源电极，第三掺杂区复用为第一源电极，第二漏电极通过第六掺杂区与第四掺杂区电连接，第二漏电极与第六掺杂区复用为第一漏电极。图4B是以两个开关单元为例进行说明，如图4B所示，第一个开关单元的第六掺杂区与第二个开关单元的第五掺杂区为同一掺杂区，第一个开关单元的第四掺杂区与第二个开关单元的第三掺杂区为同一掺杂区。这种情况下，当开关晶体管导通时，第一开关单元的第六掺杂区与第二个开关单元的第五掺杂区以及第一个开关单元的第四掺杂区与第二个开关单元的第三掺杂区相当于并联的电阻，可以减小开关结构的电阻，进而提升了开关结构的充电率。
如图2和4所示，第一晶体管为顶栅结构，第二晶体管为底栅结构。
在一种示例性实施例中，第一掺杂区112和第二掺杂区113的掺杂浓度可以相等。
在一种示例性实施例中，第三掺杂区114和第四掺杂区115的掺杂浓度可以相等。
在一种示例性实施例中，第五掺杂区212和第六掺杂区213的掺杂浓度可以相等。
在一种示例性实施例中，第三掺杂区114的掺杂浓度大于第一掺杂区112的掺杂浓度。第一掺杂区112和第二掺杂区113采用N型轻掺杂，第三掺杂区114和第四掺杂区115采用N型重掺杂。第一有源层中设置有高阻值的第一掺杂区112和第二掺杂区113，可以降低电子在电场作用下的加速距离，可以有效降低第一晶体管的热量产生，并抑制漏电流。
在一种示例性实施例中，第五掺杂区212和第六掺杂区213可以采用P型轻掺杂，或者可以采用P型重掺杂。
在一种示例性实施例中，可以通过对掺杂的离子种类以及掺杂浓度的调节实现对第一掺杂区至第六掺杂区的长度的控制。
在一种示例性实施例中，如图2和4所示，以第一晶体管为N型晶体管，第二晶体管为P型晶体管为例，当向第一栅电极提供高电平信号时，第一沟道区111处于导通状态，第二沟道区211呈高阻状态。第一沟道区111处于 导通状态，第二源电极23、第五掺杂区212、第三掺杂区114、第一掺杂区112、第一沟道区111、第二掺杂区113、第四掺杂区115、第六掺杂区213和第二漏电极24之间形成了通路，由于第二源电极23和第五掺杂区212复用为第一源电极13，第二漏电极24与第六掺杂区213复用为第一漏电极14，因此，上述通路为第一源电极13、第三掺杂区114、第一掺杂区112、第一沟道区111、第二掺杂区113、第四掺杂区115和第一漏电极14，第一源电极的电压信号通过该通路传输至第一漏电极中，这种情况下，第一晶体管处于导通状态。由于第二沟道区211呈高阻状态，因此，第二源电极23、第五掺杂区212、第二沟道区211、第六掺杂区213和第二漏电极24之间无法形成通路，第二晶体管处于截止状态。当向第一栅电极提供低电平信号时，第一沟道区111处于高阻状态，第二沟道区211呈导通状态。第一沟道区111处于高阻状态，第二源电极23、第五掺杂区212、第三掺杂区114、第一掺杂区112、第一沟道区111、第二掺杂区113、第四掺杂区115、第六掺杂区213和第二漏电极24之间无法形成通路，即第一源电极13、第三掺杂区114、第一掺杂区112、第一沟道区111、第二掺杂区113、第四掺杂区115和第一漏电极14之间无法形成通路，这种情况下，第一晶体管处于截止状态。第二沟道区211呈导通状态，第二源电极23、第五掺杂区212、第二沟道区211、第六掺杂区213和第二漏电极24之间形成了通路，第二源电极23的电压信号通过该通路传输至第二漏电极24中，第二晶体管处于导通状态。
由上述分析可知，第一栅电极12和第二栅电极22为同一电极，即第一晶体管和第二晶体管共用栅极，不仅可以保证开关结构的正常工作，而且可以简化工艺，节省成本。
图2和图4是以第一晶体管为N型晶体管，第二晶体管为P型晶体管为例进行说明的。
在一种示例性实施例中，当第一晶体管为P型晶体管，第二晶体管为N型晶体管时；第一有源层包括：沿垂直于第一有源层和第二有源层排布方向排布的第一沟道区、第一掺杂区和第二掺杂区。第二有源层包括：沿垂直于第一有源层和第二有源层排布方向排布的第二沟道区、第三掺杂区、第四掺杂区、第五掺杂区和第六掺杂区。
第一掺杂区和第二掺杂区的掺杂类型相同，且分别位于第一沟道区的两侧；第三掺杂区和第四掺杂区的掺杂类型相同，且分别位于第二沟道区的两侧；第五掺杂区和第六掺杂区的掺杂类型相同，第五掺杂区位于第三掺杂区远离第二沟道区的一侧，第六掺杂区位于第四掺杂区远离第二沟道区的一侧。
第二源电极通过第五掺杂区与第一掺杂区连接，第二源电极与第五掺杂区复用为第一源电极；第二漏电极通过第六掺杂区与第二掺杂区连接，第二漏电极与第六掺杂区复用为第一漏电极。
在一种示例性实施例中，第一掺杂区和第二掺杂区的掺杂浓度可以相等。
在一种示例性实施例中，第三掺杂区和第四掺杂区的掺杂浓度可以相等。
在一种示例性实施例中，第五掺杂区和第六掺杂区的掺杂浓度可以相等
在一种示例性实施例中，第五掺杂区的掺杂浓度大于第三掺杂区的掺杂浓度。
在一种示例性实施例中，当开关单元的数量为一个时，在开关单元中，第二源电极和第二漏电极设置在第二有源层远离基底的一侧；第二源电极通过第五掺杂区与第一掺杂区电连接，第二源电极与第五掺杂区复用为第一源电极；第二漏电极通过第六掺杂区与第二掺杂区电连接，第二漏电极与第六掺杂区复用为第一漏电极。
在一种示例性实施例中，当开关单元数量为至少两个时，在每个开关单元中，第二源电极和第二漏电极设置在第二有源层远离基底的一侧；第二源电极通过第五掺杂区与第一掺杂区电连接，第二源电极与第五掺杂区复用为第一源电极；第二漏电极通过第六掺杂区与第二掺杂区电连接，第二漏电极与第六掺杂区复用为第一漏电极；第i个开关单元的第二漏电极与第i+1个开关单元的第二源电极为同一电极，1≤i<N。
在一种示例性实施例中，当开关单元为数量为至少两个时，第一个开关单元的第二源电极设置在第一个开关单元的第二有源层远离基底的一侧，最后一个开关单元的第二漏电极设置在最后一个开关单元的第二有源层的远离基底的一侧；在第一个开关单元中，第二源电极通过第五掺杂区与第一掺杂区电连接，第二源电极与第五掺杂区复用为第一源电极；第六掺杂区复用为 第二漏电极，第二掺杂区复用为第一漏电极；在第j个开关单元中，第五掺杂区复用为第二源电极，第一掺杂区复用为第一源电极，第六掺杂区复用为第二漏电极，第二掺杂区复用为第一漏电极，1<j<N；第j-1个开关单元的第六掺杂区与第j个开关单元的第五掺杂区为同一掺杂区，第j-1个开关单元的第二掺杂区与第j个开关单元的第一掺杂区为同一掺杂区；在最后一个开关单元中，第五掺杂区复用为第二源电极，第一掺杂区复用为第一源电极，第二漏电极通过第六掺杂区与第二掺杂区电连接，第二漏电极与第六掺杂区复用为第一漏电极。这种情况下，当开关晶体管导通时，第一开关单元的第六掺杂区与第二个开关单元的第五掺杂区以及第一个开关单元的第二掺杂区与第二个开关单元的第一掺杂区相当于并联的电阻，可以减小开关结构的电阻，进而提升了开关结构的充电率。
如图2和4所示，在一种示例性实施例中，第一沟道区111在基底10上的正投影与第二沟道区211在基底10上的正投影重合；第一沟道区111在基底10上的正投影与第一栅电极12在基底10上的正投影至少部分重叠。
图5为一种示例性实施例提供的显示基板的俯视图。如图2、图4和图5所示，一种示例性实施例提供的显示基板还包括：遮光层20。
遮光层20位于第一有源层11靠近基底10的一侧，遮光层20在基底10上的正投影覆盖第一沟道区111在基底10上的正投影。
如图2、图4和图5所示，一种示例性实施例提供的显示基板包括：沿垂直于基底方向依次设置的第一金属层、第一绝缘层31、第一多晶硅层、第二绝缘层32、第二金属层、第三绝缘层33、第二多晶硅层、第四绝缘层34和第三金属层。
第一金属层包括：遮光层20，第一多晶硅层包括：第一有源层11，第二金属层包括：第一栅电极12和扫描信号线，第二多晶硅层包括：第二有源层21，第三金属层包括：第二源电极23、第二漏电极24和数据信号线。
如图2和图4所示，一种示例性实施例提供的显示基板还包括：平坦层35、第一透明导电层、第五绝缘层36和第二透明导电层。
第一透明导电层包括：公共电极41，第二透明导电层包括：像素电极42。
平坦层35位于第三金属层远离基底10的一侧，第一透明导电层位于平坦层35远离基底10的一侧，第五绝缘层36位于第一透明导电层远离基底10的一侧，第二透明导电层位于第五绝缘层36远离基底10的一侧。
平坦层35上设置有暴露出第二漏电极的第一过孔，第一透明导电层上设置暴露出第一过孔的第二过孔。第二过孔在基底上的正投影覆盖第一过孔在基底上的正投影。第五绝缘层36上设置有暴露出第二过孔的第三过孔。像素电极42通过第一过孔、第二过孔和第三过孔与第二漏电极24连接。
在一种示例性实施例中，第一金属层、第二金属层和第三金属层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称为缓冲层，设置为提高基底的抗水氧能力，第二绝缘层称为第一栅绝缘层，第三绝缘层称为第二栅绝缘层，第四绝缘层称为层间绝缘层，第五绝缘层称为钝化层。
在一种示例性实施例中，第二绝缘层的厚度可以小于第三绝缘层的厚度，第一绝缘层的厚度可以小于第二绝缘层和第三绝缘层的厚度之和，在保证绝缘效果的前提下，可以提高存储电容的容量。
在一种示例性实施例中，平坦层可以采用有机材料。
一种示例性实施例提供的显示基板高频驱动时，显示基板的充电率可达到99.75％，提升了显示基板的显示效果，保证了显示基板无显示不良风险。显示不良指的是竖纹等不良现象。
以开关结构包括一个开关单元，且第一晶体管为N型晶体管，第二晶体管为P型晶体管为例，下面通过显示基板的制备过程说明一种示例性实施例提供的显示基板的结构。“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可 以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。
(1)在基底形成第一金属层和第一绝缘层，包括：在基底上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成第一金属层，在形成有第一金属层的第一绝缘层上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成第一绝缘层31。第一金属层包括：遮光层，如图6和7所示。
(2)形成第一多晶硅层，包括：在形成第一绝缘层上沉积第一非晶硅薄膜，对第一非晶硅薄膜进行晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行构图，形成第一多晶硅薄膜，对第一多晶硅薄膜进行阈值电压掺杂处理，对第一多晶硅薄膜进行N型重掺杂，形成第三掺杂区114和第四掺杂区115，对第一多晶硅薄膜进行P型轻掺杂，形成第一掺杂区112和第二掺杂区113，以形成第一多晶硅层。第一多晶硅层包括：第一有源层11，如图8和9所示。
(3)形成第二绝缘层和第二金属层，包括：在形成有第一多晶硅层的第一绝缘层上，沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成第二绝缘层32，在第二绝缘层32上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成第二金属层。第二金属层包括：扫描信号线和第一栅电极11，如图10和11所示。
(4)形成第三绝缘层和第二多晶硅层，包括：在形成有第二金属层的第二绝缘层上沉积第三绝缘薄膜，通过构图工艺对第三金属薄膜进行构图，形成第三绝缘层33，在第三绝缘层33上沉积第二非晶硅薄膜，对第二非晶硅薄膜进行晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行构图，形成第二多晶硅薄膜，对第一多晶硅薄膜进行P型掺杂，形成第五掺杂区212和第六掺杂区213，以形成第二多晶硅层。第二多晶硅层包括：第二有源层21，如图12和13所示。
第二绝缘层32和第三绝缘层33上设置有暴露出第三掺杂区114的第四过孔V4和暴露出第四掺杂区115的第五过孔V5。第五掺杂区212通过第四 过孔V4与第三掺杂区114电连接，第六掺杂区213通过第五过孔V5与第三掺杂区114电连接。
(5)形成第四绝缘层，包括：在形成有第二多晶硅层的第三绝缘层上沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成第四绝缘层34，如图14和15所示。
第四绝缘层34上设置有暴露出第五掺杂区212的第六过孔V6和暴露出第六掺杂区213的第七过孔V7。
(6)形成第三金属层，包括：在第四绝缘层34上沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，形成第三金属层，第三金属层包括：第二源电极23、第二漏电极24和数据信号线，如图16和17所示。
第四绝缘层34上设置有暴露出第五掺杂区212的第六过孔和暴露出第六掺杂区213的第七过孔。第二源电极23通过第六过孔与第五掺杂区212电连接，第二漏电极24通过第七过孔与第六掺杂区213电连接。
(6)形成平坦层，包括：在形成有第三金属层的第四绝缘层上，涂覆平坦薄膜，通过平坦薄膜的掩膜、曝光和显影，形成平坦层35。平坦层上开设有第一过孔V1，第一过孔V1暴露出第二漏电极24，如图18所示。
(7)形成第一透明导电层，包括：在平坦层上沉积第一透明导电薄膜，通过构图工艺对第一透明导电薄膜进行构图，形成第一透明导电层。第一透明导电层包括公共电极41。第一透明导电层上设置暴露出第一过孔V1的第二过孔V2，第二过孔V2在基底上的正投影覆盖第一过孔V1在基底上的正投影，如图19所示。
(8)形成第五绝缘层和第二透明导电层，包括：在第一透明导电层上沉积第五绝缘薄膜，通过构图工艺对第五绝缘薄膜进行构图，形成第五绝缘层36，在第五绝缘层36上沉积第二透明导电薄膜，通过构图工艺对第二透明导电薄膜进行构图，形成第二透明导电层。第二透明导电层包括像素电极42，如图2所示。
第五绝缘层上设置有暴露出第二过孔的第三过孔，像素电极通过第一过孔、第二过孔和第三过孔与第二漏电极连接。
本公开实施例还提供一种显示基板的制备方法，本公开实施例提供的显示基板的制备方法包括：
步骤S1、提供一基底。
步骤S2、在基底上形成开关结构。
开关结构，分别与控制信号端、信号输入端和信号输出端电连接，设置为在控制信号端的控制下，向信号输出端提供信号输入端的信号；开关结构包括：开关单元；开关单元包括：第一晶体管和第二晶体管；第一晶体管和第二晶体管的类型相反；第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；第一栅电极和第二栅电极分别与控制信号端电连接，第一源电极和第二源电极分别与信号输入端电连接，第一漏电极和第二漏电极分别与信号输出端电连接；第一有源层在基底上的正投影与第二有源层在基底上的正投影重合。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，步骤S2在基底上形成开关结构包括：
步骤S21、在基底上依次形成第一金属层和第一绝缘层。
第一金属层包括：遮光层。
步骤S22、在第一绝缘层上形成第一多晶硅层。
第一多晶硅层包括：第一有源层；
步骤S23、在形成有第一多晶硅层的第一绝缘层上依次形成第二绝缘层和第二金属层。
第二金属层包括：第一栅电极和扫描信号线；第一栅电极和第二栅电极为同一电极；
步骤S24、在形成有第二金属层的第二绝缘层上形成第三绝缘层。
步骤S25、在第三绝缘层上形成第二多晶硅层。
第二多晶硅层包括：第二有源层；
步骤S26、在形成有第二多晶硅层的第三绝缘层上依次形成第四绝缘层和第三金属层.
第三金属层包括：第二源电极、第二漏电极和数据信号线。
在步骤S26之后，一种示例性实施例提供的显示基板的制备方法还包括：
步骤S27、在形成有第三金属层的第四绝缘层上形成平坦层。
步骤S28、在平坦层上形成第一透明导电层。
第一透明导电层包括：公共电极；
步骤S29、在第一透明导电层上形成第五绝缘层，在第五绝缘层上形成第二透明导电层。
第二透明导电层包括：像素电极。
在一种示例性实施例中，当第一晶体管为N型晶体管，第二晶体管为P型晶体管时，步骤S22包括：在第一绝缘层上沉积第一非晶硅薄膜，将第一非晶硅薄膜晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行处理形成第一多晶硅薄膜，第一多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域、第三区域、第四区域和第五区域，第二区域和第三区域分别位于第一区域的两侧，第四区域位于第二区域远离第一区域的一侧，第五区域位于第三区域远离第一区域的一侧；对第一多晶硅薄膜进行阈值电压掺杂处理；对第一多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理；对第一多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，以形成第一多晶硅层。
在一种示例性实施例中，对第一多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理包括：在第一多晶硅薄膜上涂覆光刻胶，通过构图工艺在光刻胶中形成第一开口，第一开口位于第四区域和第五区域所在位置的上方，通过第一开口对第一多晶硅薄膜的第四区域和第五区域进行离子注入形成第三掺杂区和第四掺杂区；
在一种示例性实施例中，对第一多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，包括：在第一多晶硅薄膜上涂覆光刻胶，通过构图工艺在光刻胶中形成第二开口，第二开口位于第二区域和第三区域所在位置的上方， 通过第二开口对第一多晶硅薄膜的第二区域和第三区域进行离子注入形成第三掺杂区和第四掺杂区。
在一种示例性实施例中，当第一晶体管为N型晶体管，第二晶体管为P型晶体管时，步骤S25包括：在第三绝缘层上沉积第二非晶硅薄膜，将第二非晶硅薄膜晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行处理形成第二多晶硅薄膜；第二多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域和第三区域，第二区域和第三区域分别位于第一区域的两侧；对第二多晶硅薄膜的第二区域和第三区域进行P型掺杂处理，以形成第二多晶硅层。
在一种示例性实施例中，对第二多晶硅薄膜的第二区域和第三区域进行P型掺杂处理包括：在第二多晶硅薄膜上涂覆光刻胶，通过构图工艺在光刻胶中形成开口，开口位于第二区域和第三区域所在位置的上方，通过开口对第二多晶硅薄膜的第二区域和第三区域进行离子注入形成第五掺杂区和第六掺杂区。
在一种示例性实施例中，当第一晶体管为P型晶体管，第二晶体管为N型晶体管时，步骤S22包括：在第一绝缘层上沉积第一非晶硅薄膜，将第一非晶硅薄膜晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行处理形成第一多晶硅薄膜；第一多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域和第三区域，第二区域和第三区域分别位于第一区域的两侧；对第一多晶硅薄膜的第二区域和第三区域进行P型掺杂处理，以形成第一多晶硅层。
在一种示例性实施例中，对第一多晶硅薄膜的第二区域和第三区域进行P型掺杂处理包括：在第一多晶硅薄膜上涂覆光刻胶，通过构图工艺在光刻胶中形成开口，开口位于第二区域和第三区域所在位置的上方，通过开口对第一多晶硅薄膜的第二区域和第三区域进行离子注入形成第一掺杂区和第二掺杂区；
在一种示例性实施例中，当第一晶体管为P型晶体管，第二晶体管为N型晶体管时，步骤S25包括：在第三绝缘层上沉积第二非晶硅薄膜，将第二非晶硅薄膜晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行处理，形成 第二多晶硅薄膜；第二多晶硅薄膜包括：沿垂直于第一有源层和第二有源层排布方向排布的第一区域、第二区域、第三区域、第四区域和第五区域，第二区域和第三区域分别位于第一区域的两侧，第四区域位于第二区域远离第一区域的一侧，第五区域位于第三区域远离第一区域的一侧；对第二多晶硅薄膜进行阈值电压掺杂处理；对第二多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理；对第二多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，以形成第二多晶硅层。
在一种示例性实施例中，对第二多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理包括：第二多晶硅薄膜上涂覆光刻胶，通过构图工艺在光刻胶中形成第一开口，第一开口位于第四区域和第五区域所在位置的上方，通过第一开口对第二多晶硅薄膜的第四区域和第五区域进行离子注入形成第五掺杂区和第六掺杂区。
在一种示例性实施例中，对第二多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理包括：在第二多晶硅薄膜上涂覆光刻胶，通过构图工艺在光刻胶中形成第二开口，第二开口位于第二区域和第三区域所在位置的上方，通过第二开口对第二多晶硅薄膜的第二区域和第三区域进行离子注入形成第三掺杂区和第四掺杂区。
本公开实施例还提供了一种显示基板的驱动方法，用于驱动显示基板，本公开实施例提供的显示基板的驱动方法包括：向控制信号端提供控制信号，以向信号输出端提供信号输入端的信号。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似。
在一种示例性实施例中，当信号输入端的信号为高电平信号时，向控制信号端提供控制信号包括：向控制信号端提供第一控制信号，第一控制信号为低电平信号；
在一种示例性实施例中，当信号输入端的信号为低电平信号时，向控制信号端提供控制信号包括：向控制信号端提供第二控制信号，第二控制信号为高电平信号。
本公开实施例还提供了一种显示装置，包括：显示基板。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或者导航仪。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似。
本公开实施例中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开实施例的附图中，层或微结构的厚度和尺寸被放大。当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (19)

  1. 一种显示基板，包括：基底以及设置在所述基底上的开关结构，所述开关结构与控制信号端、信号输入端和信号输出端电连接，设置为在所述控制信号端的控制下，向所述信号输出端提供所述信号输入端的信号；
    所述开关结构包括：开关单元；所述开关单元包括：第一晶体管和第二晶体管；所述第一晶体管和所述第二晶体管的类型相反；
    所述第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，所述第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；
    所述第一栅电极和所述第二栅电极与所述控制信号端电连接，所述第一源电极和所述第二源电极与所述信号输入端电连接，所述第一漏电极和所述第二漏电极与所述信号输出端电连接；
    所述第一有源层在所述基底上的正投影与所述第二有源层在所述基底上的正投影重合。
  2. 根据权利要求1所述的显示基板，其中，所述开关单元的数量为N个；
    第一个开关单元的第一源电极与所述信号输入端电连接，第j个开关单元的第一漏电极与第j+1个开关单元的第一源电极电连接，第N个开关单元的第一漏电极与所述信号输出端电连接；
    所有开关单元的第一栅电极和第二栅电极与所述控制信号端电连接，N≥1，1<j<N。
  3. 根据权利要求1所述的显示基板，还包括：设置在所述基底上的扫描信号线、数据信号线、公共电极和像素电极；
    所述扫描信号线与所述控制信号端电连接，设置为向所述控制信号端提供信号；
    所述数据信号线与所述信号输入端连接，设置为向所述信号输入端提供信号；
    所述信号输出端与所述像素电极连接，设置为向所述像素电极提供信号；
    所述公共电极位于所述像素电极靠近所述基底的一侧，设置为与所述像素电极之间形成电场。
  4. 根据权利要求3所述的显示基板，其中，所述第一栅电极和所述第二栅电极配置为同一电极；
    所述第一有源层位于所述第一栅电极靠近所述基底的一侧；所述第二有源层位于所述第一栅电极远离所述基底的一侧；所述第二有源层与所述第一有源层连接。
  5. 根据权利要求4所述的显示基板，其中，当第一晶体管为N型晶体管，第二晶体管为P型晶体管时：
    所述第一有源层包括：沿平行于基底方向方向排布的第一沟道区、第一掺杂区、第二掺杂区、第三掺杂区和第四掺杂区；
    所述第一掺杂区和所述第二掺杂区的掺杂类型相同，且分别位于所述第一沟道区的两侧；
    所述第三掺杂区和所述第四掺杂区的掺杂类型相同，所述第三掺杂区位于所述第一掺杂区远离所述第一沟道区的一侧，所述第四掺杂区位于所述第二掺杂区远离所述第一沟道区的一侧；
    所述第三掺杂区的掺杂浓度大于所述第一掺杂区的掺杂浓度；
    所述第二有源层包括：沿垂直于所述第一有源层和所述第二有源层排布方向排布的第二沟道区、第五掺杂区和第六掺杂区；
    所述第五掺杂区和所述第六掺杂区的掺杂类型相同，且分别位于所述第二沟道区的两侧。
  6. 根据权利要求5所述的显示基板，其中，当所述开关单元的数量为一个时，在所述开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第三掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第四掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；
    当所述开关单元数量为至少两个时，在每个开关单元中，所述第二源电 极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第三掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第四掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；第i个开关单元的第二漏电极与第i+1个开关单元的第二源电极为同一电极，1≤i<N；
    或者，当所述开关单元为数量为至少两个时，第一个开关单元的第二源电极设置在第一个开关单元的第二有源层远离基底的一侧，最后一个开关单元的第二漏电极设置在最后一个开关单元的第二有源层的远离基底的一侧；在第一个开关单元中，所述第二源电极通过所述第五掺杂区与所述第三掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第六掺杂区复用为第二漏电极，所述第四掺杂区复用为第一漏电极；在第j个开关单元中，所述第五掺杂区复用为第二源电极，所述第三掺杂区复用为第一源电极，所述第六掺杂区复用为第二漏电极，所述第四掺杂区复用为第一漏电极，1<j<N；第j-1个开关单元的第六掺杂区与第j个开关单元的第五掺杂区为同一掺杂区，第j-1个开关单元的第四掺杂区与第j个开关单元的第三掺杂区为同一掺杂区；在最后一个开关单元中，所述第五掺杂区复用为第二源电极，所述第三掺杂区复用为第一源电极，第二漏电极通过所述第六掺杂区与所述第四掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极。
  7. 根据权利要求6所述的显示基板，其中，当第一晶体管为P型晶体管，第二晶体管为N型晶体管时；
    所述第一有源层包括：沿平行于基底方向排布的第一沟道区、第一掺杂区和第二掺杂区；
    所述第一掺杂区和所述第二掺杂区的掺杂类型相同，且分别位于所述第一沟道区的两侧；
    所述第二有源层包括：沿平行于基底方向排布的第二沟道区、第三掺杂区、第四掺杂区、第五掺杂区和第六掺杂区；
    所述第三掺杂区和所述第四掺杂区的掺杂类型相同，且分别位于所述第 二沟道区的两侧；
    所述第五掺杂区和所述第六掺杂区的掺杂类型相同，所述第五掺杂区位于所述第三掺杂区远离所述第二沟道区的一侧，所述第六掺杂区位于所述第四掺杂区远离所述第二沟道区的一侧；
    所述第五掺杂区的掺杂浓度大于所述第三掺杂区的掺杂浓度。
  8. 根据权利要求7所述的显示基板，其中，当所述开关单元的数量为一个时，在所述开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第一掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第二掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；
    当所述开关单元数量为至少两个时，在每个开关单元中，所述第二源电极和所述第二漏电极设置在第二有源层远离所述基底的一侧；所述第二源电极通过所述第五掺杂区与所述第一掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第二漏电极通过所述第六掺杂区与所述第二掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极；第i个开关单元的第二漏电极与第i+1个开关单元的第二源电极为同一电极，1≤i<N；
    或者，当所述开关单元为数量为至少两个时，第一个开关单元的第二源电极设置在第一个开关单元的第二有源层远离基底的一侧，最后一个开关单元的第二漏电极设置在最后一个开关单元的第二有源层的远离基底的一侧；在第一个开关单元中，所述第二源电极通过所述第五掺杂区与所述第一掺杂区电连接，所述第二源电极与所述第五掺杂区复用为第一源电极；所述第六掺杂区复用为第二漏电极，所述第二掺杂区复用为第一漏电极；在第j个开关单元中，所述第五掺杂区复用为第二源电极，所述第一掺杂区复用为第一源电极，所述第六掺杂区复用为第二漏电极，所述第二掺杂区复用为第一漏电极，1<j<N；第j-1个开关单元的第六掺杂区与第j个开关单元的第五掺杂区为同一掺杂区，第j-1个开关单元的第二掺杂区与第j个开关单元的第一掺杂区为同一掺杂区；在最后一个开关单元中，所述第五掺杂区复用为第二源 电极，所述第一掺杂区复用为第一源电极，所述第二漏电极通过所述第六掺杂区与所述第二掺杂区电连接，所述第二漏电极与所述第六掺杂区复用为第一漏电极。
  9. 根据权利要求5至8任一项所述的显示基板，其中，所述第一沟道区在基底上的正投影与所述第二沟道区在基底上的正投影重合；
    所述第一沟道区在所述基底上的正投影与所述第一栅电极在所述基底上的正投影至少部分重叠。
  10. 根据权利要求9所述的显示基板，还包括：遮光层；
    所述遮光层位于所述第一有源层靠近所述基底的一侧，所述遮光层在基底上的正投影覆盖所述第一沟道区在所述基底上的正投影。
  11. 根据权利要求10所述的显示基板，其中，所述显示基板包括：沿垂直于基底方向依次设置的第一金属层、第一绝缘层、第一多晶硅层、第二绝缘层、第二金属层、第三绝缘层、第二多晶硅层、第四绝缘层和第三金属层；
    所述第一金属层包括：遮光层，所述第一多晶硅层包括：第一有源层，所述第二金属层包括：第一栅电极和扫描信号线，所述第二多晶硅层包括：第二有源层，所述第三金属层包括：第二源电极、第二漏电极和数据信号线。
  12. 根据权利要求11所述的显示基板，还包括：平坦层、第一透明导电层、第五绝缘层和第二透明导电层；
    所述平坦层位于所述第三金属层远离所述基底的一侧，所述平坦层上设置有暴露出第二漏电极的第一过孔；
    所述第一透明导电层位于所述平坦层远离所述基底的一侧，所述第一透明导电层上设置暴露出所述第一过孔的第二过孔；所述第二过孔在基底上的正投影覆盖所述第一过孔在基底上的正投影；所述第一透明导电层包括：公共电极；
    所述第五绝缘层位于所述第一透明导电层远离所述基底的一侧，所述第五绝缘层上设置有暴露出所述第二过孔的第三过孔；
    所述第二透明导电层位于所述第五绝缘层远离所述基底的一侧，所述第二透明导电层包括：像素电极，所述像素电极通过所述第一过孔、所述第二 过孔和所述第三过孔与所述第二漏电极连接。
  13. 一种显示装置，包括：如权利要求1至12任一项所述的显示基板。
  14. 一种显示基板的制备方法，设置为形成如权利要求1至12任一项所述的显示基板，所述方法包括：
    提供一基底；
    在所述基底上形成开关结构；所述开关结构，分别与控制信号端、信号输入端和信号输出端电连接，设置为在所述控制信号端的控制下，向所述信号输出端提供所述信号输入端的信号；所述开关结构包括：开关单元；所述开关单元包括：第一晶体管和第二晶体管；所述第一晶体管和所述第二晶体管的类型相反；所述第一晶体管包括：第一有源层、第一栅电极、第一源电极和第一漏电极，所述第二晶体管包括：第二有源层、第二栅电极、第二源电极和第二漏电极；所述第一栅电极和所述第二栅电极分别与所述控制信号端电连接，所述第一源电极和所述第二源电极分别与所述信号输入端电连接，所述第一漏电极和所述第二漏电极分别与所述信号输出端电连接；所述第一有源层在所述基底上的正投影与所述第二有源层在所述基底上的正投影重合。
  15. 根据权利要求14所述的方法，其中，所述在所述基底上形成开关结构包括：
    在基底上依次形成第一金属层和第一绝缘层；所述第一金属层包括：遮光层；
    在第一绝缘层上形成第一多晶硅层；所述第一多晶硅层包括：第一有源层；
    在形成有第一多晶硅层的第一绝缘层上依次形成第二绝缘层和第二金属层；所述第二金属层包括：第一栅电极和扫描信号线；所述第一栅电极和所述第二栅电极为同一电极；
    在形成有第二金属层的第二绝缘层上形成第三绝缘层；
    在第三绝缘层上形成第二多晶硅层，所述第二多晶硅层包括：第二有源层；
    在形成有第二多晶硅层的第三绝缘层上依次形成第四绝缘层和第三金属 层，所述第三金属层包括：第二源电极、第二漏电极和数据信号线。
  16. 根据权利要求15所述的方法，其中，所述在形成有第二多晶硅层的第三绝缘层上依次形成第四绝缘层和第三金属层之后，所述方法还包括：
    在形成有第三金属层的第四绝缘层上形成平坦层；
    在平坦层上形成第一透明导电层，所述第一透明导电层包括：公共电极；
    在所述第一透明导电层上形成第五绝缘层；
    在第五绝缘层上形成第二透明导电层，所述第二透明导电层包括：像素电极。
  17. 根据权利要求16所述的方法，其中，当所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管时，
    所述在所述第一绝缘层上形成第一多晶硅层包括：
    在第一绝缘层上沉积第一非晶硅薄膜，将所述第一非晶硅薄膜晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行处理形成第一多晶硅薄膜；所述第一多晶硅薄膜包括：沿平行于基底方向排布的第一区域、第二区域、第三区域、第四区域和第五区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧，所述第四区域位于所述第二区域远离所述第一区域的一侧，所述第五区域位于所述第三区域远离所述第一区域的一侧；
    对所述第一多晶硅薄膜进行阈值电压掺杂处理；
    对所述第一多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理；
    对所述第一多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，以形成第一多晶硅层；
    所述在所述第三绝缘层上形成第二多晶硅层包括：
    在第三绝缘层上沉积第二非晶硅薄膜，将所述第二非晶硅薄膜晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行处理形成第二多晶硅薄膜；所述第二多晶硅薄膜包括：沿平行于所述基底方向排布的第一区域、第二区域和第三区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧；
    对所述第二多晶硅薄膜的第二区域和第三区域进行P型掺杂处理，以形 成第二多晶硅层；
    当所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管时，
    所述在所述第一绝缘层上形成第一多晶硅层包括：
    在第一绝缘层上沉积第一非晶硅薄膜，将所述第一非晶硅薄膜晶化，通过构图工艺对晶化后的第一非晶硅薄膜进行处理形成第一多晶硅薄膜；所述第一多晶硅薄膜包括：沿平行于所述基底方向排布的第一区域、第二区域和第三区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧；
    对所述第一多晶硅薄膜的第二区域和第三区域进行P型掺杂处理，以形成第一多晶硅层；
    所述在所述第三绝缘层上形成第二多晶硅层包括：
    在第三绝缘层上沉积第二非晶硅薄膜，将所述第二非晶硅薄膜晶化，通过构图工艺对晶化后的第二非晶硅薄膜进行处理，形成第二多晶硅薄膜；所述第二多晶硅薄膜包括：沿平行于所述基底方向排布的第一区域、第二区域、第三区域、第四区域和第五区域，所述第二区域和所述第三区域分别位于所述第一区域的两侧，所述第四区域位于所述第二区域远离所述第一区域的一侧，所述第五区域位于所述第三区域远离所述第一区域的一侧；
    对所述第二多晶硅薄膜进行阈值电压掺杂处理；
    对所述第二多晶硅薄膜的第四区域和第五区域进行N型重掺杂处理；
    对所述第二多晶硅薄膜的第二区域和第三区域进行N型轻掺杂处理，以形成第二多晶硅层。
  18. 一种显示基板的驱动方法，用于驱动如权利要求1至12任一项所述的显示基板，所述方法包括：
    向控制信号端提供控制信号，以向信号输出端提供信号输入端的信号。
  19. 根据权利要求18所述的方法，其特征在于，当信号输入端的信号为高电平信号时，所述向控制信号端提供控制信号包括：
    向控制信号端提供第一控制信号，所述第一控制信号为低电平信号；
    当信号输入端的信号为低电平信号时，所述向控制信号端提供控制信号 包括：
    向控制信号端提供第二控制信号，所述第二控制信号为高电平信号。
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