WO2021244304A1 - 一种芯片封装结构及电子设备 - Google Patents

一种芯片封装结构及电子设备 Download PDF

Info

Publication number
WO2021244304A1
WO2021244304A1 PCT/CN2021/094996 CN2021094996W WO2021244304A1 WO 2021244304 A1 WO2021244304 A1 WO 2021244304A1 CN 2021094996 W CN2021094996 W CN 2021094996W WO 2021244304 A1 WO2021244304 A1 WO 2021244304A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
packaging
layer
electrode
insulating layer
Prior art date
Application number
PCT/CN2021/094996
Other languages
English (en)
French (fr)
Inventor
侯召政
彭浩
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21817520.6A priority Critical patent/EP4152376A4/en
Publication of WO2021244304A1 publication Critical patent/WO2021244304A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • This application relates to the field of electrical components, in particular to a chip packaging structure and electronic equipment.
  • Chip packaging refers to packaging the chip in a packaging structure, and leading the electrodes of the chip to the shell, so that the packaged chip packaging structure can be electrically connected to other structures.
  • the chip By encapsulating the chip in the housing, the chip can be isolated from the outside world, thereby preventing the corrosion or other influence of external impurities on the chip circuit and causing the problem of electrical performance degradation.
  • the packaged chip packaging structure can have higher strength than a single chip, which is more convenient for installation and transportation, and can also facilitate subsequent processes such as connecting the chip to other structures.
  • the electrodes in the chip are usually led out to the shell by means of solder balls.
  • the electrical connection between the chip and the circuit board is achieved by soldering the solder balls connected with the electrodes of the chip to the pads of the circuit board.
  • the positions of the electrodes in the chip are fixed, the positions of the solder balls are also relatively fixed.
  • the positions of the pads on the circuit boards of different specifications are also pre-designed.
  • the present application provides a chip packaging structure that can be applied to various circuit boards, and an electronic device including the chip packaging structure.
  • the present application provides a chip packaging structure that includes an insulating layer, a packaging layer, and a heat sink stacked in sequence;
  • the packaging layer includes a packaging substrate, a chip, and electrode traces, and the chip is embedded in
  • the chip includes a first surface and a second surface that are opposed to each other, the chip includes a first electrode provided on the first surface, and the electrode traces are formed on the surface of the packaging substrate.
  • the insulating layer covers the electrode traces, and an opening is provided on the insulation layer, and the opening corresponds to the electrode traces to expose part of the electrode traces ;
  • the heat sink and the packaging layer are in an integrated structure.
  • the first electrode of the chip of the chip package structure is led out through electrode traces, and windows are opened on the insulating layer covering the electrode traces, so as to realize the chip package structure and other electronic equipment by exposing the windowed electrode traces.
  • Structure electrical connection Therefore, it is possible to adjust the extension position of the electrode traces and the position of the opening on the insulating layer according to the type of the circuit board mounted on the chip package structure, thereby ensuring that the chip package structure can be flexibly applied to various types of circuit boards.
  • the heat sink and the packaging layer of the chip packaging structure of the present application are in an integrated structure.
  • the heat sink and the packaging layer Compared with the general method of fixing the heat sink and the packaging layer by welding, gluing or fixing parts, the heat sink and the packaging layer
  • the bonding position of the encapsulation layer is not prone to defects such as holes, so that the heat of the encapsulation layer can be efficiently transferred to the heat sink, and the connection between the radiator and the encapsulation layer is stronger.
  • welding, gluing, or fixing by fasteners are not required, the manufacturing process can be reduced.
  • the second surface of the chip is covered with a metal layer, and the metal layer is electrically connected to the electrode traces.
  • the heat generated on the first side of the chip can be transferred to the heat sink through the first electrode, electrode traces, and metal layer in sequence, and then the heat is dissipated through the heat sink, so as to avoid the heat generated on the first side of the chip.
  • the first side and the second side of the chip are connected through the first electrode, the electrode trace and the metal layer, so that the heat generated on the two sides of the chip can be transferred to each other, so that the heat at each position of the chip can be more uniform and avoid heat Gathering at a certain position of the chip affects the performance of the chip.
  • the heat sink can be more easily formed on one side of the second side of the chip by electroplating to achieve a better electroplating effect, thereby making the heat sink and The bonding between the chips is more stable, and the heat of the chips can be transferred to the heat sink more efficiently.
  • the chip includes a second electrode provided on the second surface, and the metal layer is the second electrode. That is, the metal layer realizes the function of heat transfer and can also be used to transmit signals.
  • the chip includes transistors for processing multiple functions, the number of electrodes in the chip is large, and a part of the second electrode may be provided on the second side of the chip to ensure the signal transmission effect.
  • the second electrode is provided on the second side, so that the heat generated by the work of the chip can be dissipated from the first side and the second side of the chip faster at the same time, so as to achieve better heat dissipation Effect.
  • the packaging substrate includes an accommodation cavity, the chip is accommodated in the accommodation cavity, there is a gap between the chip and the accommodation cavity, and a thermally conductive insulating material is filled in the gap.
  • the gap between the chip and the inner wall of the housing cavity is filled with a thermally conductive insulating material, so that the chip can be stably fixed in the housing cavity, and the heat generated in the chip can be transmitted through the thermally conductive insulating material to increase the heat in the chip The emission efficiency.
  • the heat sink is laminated on the packaging substrate and forms an integral structure with the packaging substrate, and the heat sink is in contact with the second surface of the chip, and the heat generated by the chip operation can be quickly transferred to Radiator, thereby improving heat dissipation efficiency.
  • the chip packaging structure further includes a thermally conductive insulating layer, the thermally conductive insulating layer covers the encapsulating layer, and the heat sink is located on a side of the thermally conductive insulating layer away from the encapsulating layer and is connected to the thermally conductive insulating layer.
  • the insulating layer has an integral structure, and the thermally conductive insulating layer is in contact with the second surface of the chip.
  • the chip package structure further includes a welding pad, the welding pad includes a first part and a second part that are connected, the first part covers the electrode traces and exposes the windowed area, so The second part covers the periphery of the opening of the insulating layer.
  • the chip package structure and other structures can be increased.
  • the size of the connecting pins when making electrical connections makes it easier and more stable for the chip package structure to be electrically connected to other structures.
  • the solder pads are covered on the insulating layer, compared to the way that solder balls or solder passes through the window of the insulating layer to connect to the electrode traces, the solder balls or solder do not need to pass through the window to connect to the electrode. Wire connection can also realize the electrical connection between the chip package structure and the circuit board, that is, the packaged chip can be electrically connected to other structures through welding pads more easily, and the connection yield rate is higher.
  • the heat sink includes a metal sheet, and the metal sheet is formed on the packaging layer by electroplating.
  • the metal sheet is made of metal material, and the metal material has better electrical conductivity, so as to achieve better heat dissipation effect.
  • the heat sink further includes a plurality of heat dissipation fins, the heat dissipation fins are formed on a side of the metal sheet away from the packaging layer, and there is a gap between each of the heat dissipation fins.
  • the present application also provides an electronic device, which includes a circuit board and the chip packaging structure described in any one of the above, in which the part of the electrode traces and the electrode traces exposed in the window of the chip packaging structure The circuit board is electrically connected.
  • the chip packaging structure can be flexibly applied to various types of circuit boards, production requirements and production costs can be reduced.
  • the chip packaging structure of the present application has better heat dissipation capability, so that the life of the chip packaging structure can be prolonged, and the quality of electronic equipment can be improved.
  • FIG. 1 is a schematic cross-sectional view of an electronic device according to some embodiments of the application.
  • FIG. 2 is a schematic structural diagram of a chip packaging structure according to an embodiment of this application.
  • FIG. 3 is a schematic structural diagram of a chip packaging structure according to another embodiment of this application.
  • FIG. 4 is a schematic structural diagram of a chip packaging structure according to another embodiment of this application.
  • FIG. 5 is a schematic structural diagram of a chip packaging structure according to another embodiment of this application.
  • FIG. 6 is a flowchart of the steps of a chip packaging method of this application.
  • FIG. 7-15 are schematic structural diagrams of the chip packaging structure in each step of the chip packaging method shown in FIG. 6.
  • This application provides an electronic device, which can be an electronic product such as a headset, a mobile phone, a tablet computer, a wearable watch, and a router.
  • Electronic devices include chips that can implement various functions. Take a mobile phone as an example.
  • the mobile phone can include a central processing chip that calls electronic device instructions to make the electronic device perform corresponding operations, a memory chip for data storage, a radio frequency chip for processing radio frequency signals, and an audio signal for processing audio signals. Chips and other types of chips.
  • the chip is electrically connected with other structures in the electronic device to perform and related functions. It should be noted that each chip in the electronic device is packaged in a chip packaging structure to prevent the circuit of the chip from being corroded by external impurities, and to facilitate the installation and transportation of the chip.
  • the chip packaging structure is electrically connected to other structures of the electronic device, thereby achieving electrical connection between the chip and other structures in the electronic device.
  • some electronic equipment includes a circuit board.
  • the packaged chip is mounted on the circuit board (rigid circuit board or flexible circuit board), and then the circuit board is connected with other structures in the electronic device.
  • the wiring connects the chip package structure and other structures of the electronic device to realize signal transmission between the chip package structure and other structures of the electronic device.
  • the chip packaging structure encapsulated with the audio chip is mounted on the circuit board, and then the circuit board is connected to the microphone, speaker and other structures of the electronic device, so that the audio information received by the microphone can be transmitted to the audio chip, which is processed by the audio chip. storage. Or, the stored audio information is processed by the audio chip and then transmitted to the speaker for playback.
  • FIG. 1 shows a schematic cross-sectional view of an electronic device 1000 according to some embodiments of the application.
  • the electronic device 1000 is a mobile phone.
  • the electronic device 1000 includes a housing 200, at least one chip packaging structure 100 disposed in the housing 200, and a main board 300, and the chip packaging structure 100 is mounted on the main board 300.
  • the main board 300 is a circuit board.
  • At least one chip packaging structure 100 is installed on the main board 300, and the chip packaging structure 100 is connected to other components 400 integrated on the main board 300 through a circuit on the main board 300 to form a processing circuit.
  • the other components 400 may be capacitors, inductors, resistors and other components.
  • the motherboard 300 is connected to the other structure 500 of the electronic device 1000 to realize signal transmission between the chip package structure 100 and the other structure 500 of the electronic device 1000.
  • the other structures 500 of the electronic device 1000 may be various structures such as a microphone, a speaker, a display screen, a touch layer, and an antenna.
  • the chip packaging structure 100 is electrically connected to different structures, so as to realize different functions of the chips.
  • FIG. 2 is a schematic structural diagram of a chip package structure 100 according to an embodiment of the application.
  • the chip packaging structure 100 includes a packaging layer 10, an insulating layer 20, and a heat sink 30 stacked in sequence.
  • the packaging layer 10 includes a packaging substrate 11, a chip 12 and electrode traces 13.
  • the chip 12 is embedded in the packaging substrate 11, and the chip 12 provided therein is protected by the packaging substrate 11.
  • the packaging substrate 11 may be formed of an insulating material such as resin.
  • the packaging substrate 11 is provided with a receiving cavity 14, and the receiving cavity 14 penetrates the packaging substrate 11. It can be understood that, in some other embodiments of the present application, the receiving cavity 14 may not penetrate the packaging substrate 11.
  • the receiving cavity 14 may be a groove recessed from one surface of the packaging substrate 11 to the other surface.
  • the chip 12 is received in the receiving cavity 14, and the gap between the chip 12 and the inner wall of the receiving cavity 14 is filled with the insulating material 15, so that the chip 12 can be stably fixed in the receiving cavity 14.
  • the insulating material 15 filled in the gap between the chip 12 and the inner wall of the receiving cavity 14 may be a thermally conductive insulating material, so that the heat generated by the chip 12 can be transmitted through the thermally conductive insulating material to increase the amount of heat in the chip 12 The heat dissipation efficiency.
  • the thermally conductive insulating material can be a thermally conductive resin, a plastic molding compound, or the like.
  • the insulating material 15 filled in the gap between the chip 12 and the inner wall of the receiving cavity 14 may be the same material as the packaging substrate 11.
  • the insulating material 15 When the insulating material 15 is filled between the chip 12 and the inner wall of the receiving cavity 14 The insulating material 15 filled in the gap between the chip 12 and the inner wall of the accommodating cavity 14 and the packaging substrate 11 can form an integrated structure, and since the insulating material 15 and the packaging substrate 11 are the same material, the insulating material The combination between 15 and the inner wall of the accommodating cavity 14 will be more stable, avoiding separation due to temperature changes or external forces, and ensuring the life of the chip packaging structure 100.
  • the number of chips 12 in the chip packaging structure 100 may be one or more.
  • the number of chips 12 in the chip packaging structure 100 is multiple, that is, multiple chips 12 are packaged in the same packaging structure, thereby reducing packaging steps, reducing production costs, and reducing the volume occupied by the chips 12 after packaging.
  • the multiple chips 12 may be arranged side by side or stacked in the thickness direction of the chip 12.
  • a plurality of chips 12 on the chip packaging structure 100 are arranged side by side, a plurality of accommodating cavities 14 arranged side by side and spaced apart are provided on the packaging substrate 11, and each chip 12 is correspondingly provided in one accommodating cavity 14.
  • the thickness of the packaging substrate 11 can be thicker, so that the multiple chips 12 can be housed in the same housing cavity 14 after being stacked, thereby saving the chip 12 packaging steps while at the same time. Therefore, the area occupied by the chip packaging structure 100 can also be reduced.
  • the chip 12 includes a first surface 12a and a second surface 12b disposed opposite to each other. Specifically, the side where the active area of the chip 12 is located is the first side 12a of the chip 12 in this application.
  • the chip 12 includes electrodes for drawing out signals or introducing signals into the chip 12.
  • the electrode includes a first electrode 121 provided on the first surface 12a of the chip 12.
  • the first electrode 121 is connected to the electrode trace 13, and the signal can be transmitted through the electrode trace 13 and the first electrode 121 in sequence.
  • the signal in the chip 12 can be output through the first electrode 121 and the electrode wiring 13 in sequence.
  • the number of the first electrodes 121 can be set to one or more according to actual conditions.
  • first electrodes 121 of the chip 12 there are three first electrodes 121 of the chip 12, and the three first electrodes 121 are respectively electrically connected to the gate, source, and drain of the transistors in the chip 12. Different signals are inputted to drive the chip 12 to work. In other embodiments of the present application, there may be more first electrodes 121 of the chip 12. For example, when transistors with multiple functions are integrated in the chip 12, there may be more first electrodes 121 in the chip 12 to transmit more different signals, so as to drive the chip 12 to implement different functions.
  • the insulating layer 20 is formed of an insulating material.
  • the insulating layer 20 is laminated on one side of the encapsulation layer 10 and covers the electrode traces 13, so as to protect the electrode traces 13 through the insulation layer 20 to prevent the electrode traces 13 from being corroded and causing electrical damage.
  • An opening 21 is provided on the insulating layer 20, and the opening 21 is arranged corresponding to the electrode wiring 13 to expose a part of the electrode wiring 13.
  • part of the electrode traces 13 exposed at the position of the window 21 can be electrically connected to the circuit board through solder balls or solder, so that the chip package structure 100 is mounted and fixed on the circuit board, and the chip The package structure 100 is electrically connected to the traces of the circuit board.
  • the chip packaging structure 100 is welded to the pad 301 of the main board 300 through solder balls 101, so as to realize the electrical connection between the chip packaging structure 100 and the main board 300.
  • the first electrode 121 can be extended to a desired position or at a desired position through the electrode wiring 13 according to the type of circuit board to be mounted on the chip package structure 100
  • the window 21 is opened, so that when the chip package structure 100 is electrically connected to the circuit board, the position of the window 21 of the insulating layer 20 of the chip package structure 100 can correspond to the pad of the circuit board, that is, the part of the window 21 is exposed
  • the electrode traces 13 correspond to the pads of the circuit board, so as to ensure that the chip packaging structure 100 can be easily connected to various types of circuit boards.
  • the extension position of the electrode wiring 13 and the insulating layer 20 can be adjusted according to the type of circuit board mounted on the chip packaging structure 100
  • the position of the window 21 on the upper side ensures that the chip packaging structure 100 can be flexibly applied to various types of circuit boards.
  • the insulating layer 20 may be a liquid photo-solder resist (ie green oil), which can protect the electrode wiring 13 and achieve an insulating effect while also playing a role of solder resist.
  • a liquid photo-solder resist ie green oil
  • the window is opened Part of the electrode traces 13 exposed at position 21 are electrically connected to the circuit board through solder balls or solder, and the solder can be easily concentrated on the opening 21 on the insulating layer 20, thereby improving the soldering yield.
  • the insulating layer 20 may also be other types of insulating materials such as resin.
  • the chip packaging structure 100 includes a heat sink 30 for dissipating heat for the chip 12 provided on the packaging layer 10.
  • the heat sink 30 is laminated on the side of the encapsulation layer 10 away from the insulating layer 20 and forms an integral structure with the encapsulation layer 10.
  • the integral structure of the heat sink 30 and the packaging layer 10 means that the heat sink 30 can be directly formed on the packaging layer 10 through processes such as electroplating or pressing.
  • the pre-molded heat sink 30 is fixed to the packaging layer 10. Compared with the method of fixing the pre-formed heat sink 30 and the encapsulation layer 10 by welding, gluing or fixing, the position where the heat sink 30 is combined with the encapsulation layer 10 is not prone to defects such as holes.
  • the heat of the packaging layer 10 can be transferred to the heat sink 30 more efficiently, a better heat dissipation effect is achieved, and a higher bonding strength between the heat sink 30 and the packaging layer 10 can be ensured.
  • the heat sink 30 is directly formed on the packaging layer 10 through electroplating or various molding processes in the present application, there is no need to fix the formed heat sink 30 to the package by welding, gluing, or fixing means. On the layer 10, the manufacturing process can be reduced, thereby reducing production costs and improving production efficiency.
  • the packaging layer 10 only includes the packaging substrate 11, the chip 12 provided in the receiving cavity 14 of the packaging substrate 11, and the electrode wiring 13 connecting the first electrode 121 of the chip 12.
  • the side of the heat sink 30 laminated on the packaging layer 10 away from the insulating layer 20 is the side of the heat sink 30 laminated on the packaging substrate 11 away from the insulating layer 20.
  • the heat sink 30 directly contacts the second surface 12b of the chip 12, so that the heat generated by the operation of the chip 12 It can be directly and quickly transferred to the radiator 30 and dissipated.
  • the heat sink 30 is a metal structure, which is formed on the packaging layer 10 by electroplating, so that the heat sink 30 and the packaging layer 10 have an integrated structure.
  • the metal can have a high thermal conductivity, so that the heat of the chip 12 can be quickly transferred out, and a good thermal conductivity effect can be achieved.
  • the heat sink 30 includes a metal sheet 31 formed on the packaging layer 10 by electroplating.
  • the surface 211 of the metal sheet 31 away from the encapsulation layer 10 may be an uneven surface, such as a jagged surface or a wavy surface, so as to increase the heat dissipation area of the metal sheet 31 for heat exchange with the outside, thereby improving the heat sink. 30's heat dissipation efficiency.
  • the heat sink 30 further includes a plurality of heat dissipation fins 32 formed on a side of the metal sheet 31 away from the packaging layer 10, and each of the heat dissipation fins 32 There is a gap between.
  • the heat dissipation fins 32 are provided on the side of the metal sheet 31 away from the packaging layer 10 to increase the heat dissipation area for heat exchange between the heat sink 30 and the outside, thereby improving the heat dissipation efficiency of the heat sink 30.
  • the shape and arrangement of the plurality of heat dissipation fins 32 can be changed arbitrarily.
  • the heat dissipation fins 32 of the heat sink 30 are strip-shaped, and a plurality of heat dissipation fins 32 are arranged in parallel and spaced along a direction perpendicular to the extension of the heat dissipation fins 32; in some embodiments, the heat dissipation of the heat sink 30 is The fins 32 are columnar or block-shaped, and a plurality of heat dissipation fins 32 are arranged in an array; in some embodiments, the heat dissipation fins 32 of the heat sink 30 are strip-shaped, and one end of the plurality of heat dissipation fins 32 is connected, and the other ends are respectively directed toward It extends radially in all directions.
  • the shape and arrangement of the heat dissipation fins 32 can also be other types, which are not listed here.
  • the heat sink 30 may also include only the heat dissipation fins 32, and the heat dissipation fins 32 are directly formed on the surface of the packaging layer 10.
  • the heat sink 30 may also have other structures.
  • the radiator 30 may be an air-cooled tube.
  • the air-cooling pipe has a tubular structure, including oppositely arranged air inlets and air outlets.
  • the cooling air enters from the air inlet, flows in the air-cooled tube 24 and absorbs the heat transferred from the chip 12 to the radiator 30, and then exits from the air outlet.
  • the air inlet is provided with a fan to increase the flow efficiency of the air in the air-cooled tube, thereby enhancing the efficiency of heat exchange between the air in the air-cooling tube and the heat dissipation wall, thereby improving the heat dissipation efficiency of the chip package structure 100.
  • FIG. 3 is a schematic structural diagram of a chip packaging structure 100 according to another embodiment of this application.
  • the chip package structure 100 of this embodiment further includes a bonding pad 40.
  • the welding pad 40 is a metal pad whose size is slightly larger than the size of the window 21 of the insulating layer 20.
  • the welding pad 40 is partially in contact with the area where the window 21 is exposed.
  • the welding pad 40 includes a first part 41 and a second part 42 that are connected.
  • the first part 41 covers the electrode trace 13 and the area where the window 21 is exposed, and the second part 42 covers The periphery of the opening 21 of the insulating layer 20.
  • a welding pad 40 with a larger area is formed at the position of the opening 21 of the insulating layer 20, and the first part 41 of the welding pad 40 is connected to the area where the electrode trace 13 exposes the opening 21, thereby enabling
  • the size of the pins when the chip packaging structure 100 is electrically connected to the circuit board is increased, so that the chip packaging structure 100 can be electrically connected to the pads of the circuit board more easily and more stably.
  • soldering pad 40 partially covers the periphery of the window 21 of the insulating layer 20, that is, part of the soldering pad 40 covers the insulating layer 20, compared to the solder ball or solder passing through the window 21 and the window 21 of the insulating layer 20 In terms of the connection method of the electrode traces 13, the solder balls or solder do not need to pass through the window 21 to connect to the electrode traces 13.
  • the soldering of the pad can be easier, so that the electrical connection between the chip package structure 100 and the circuit board is simpler and the yield rate is higher.
  • FIG. 4 is a schematic structural diagram of a chip package structure 100 according to another embodiment of the application.
  • the chip packaging structure 100 further includes a metal layer 50 covering the second surface 12b of the chip 12, and the metal layer 50 is connected to the electrode. 13 Electrical connection.
  • a via 51 is provided on the packaging substrate 11, and the metal layer 50 is electrically connected to the electrode wiring 13 through the via 51.
  • the cavity wall of the receiving cavity 14 may form a metal connection layer, and the metal layer 50 is electrically connected to the electrode wiring 13 through the metal connection layer.
  • the heat generated on the first surface 12a of the chip 12 can be transferred to the heat sink 30 through the first electrode 121, the electrode trace 13, and the via 51 in sequence, and then the heat is dissipated through the heat sink 30, thereby avoiding The problem that the heat generated by the first surface 12a of the chip 12 cannot be quickly dissipated, which affects the performance of the chip 12.
  • the first side 12a and the second side 12b of the chip 12 are connected through the first electrode 121, the electrode trace 13, the via 51, and the metal layer 50, so that the heat generated on the two sides of the chip 12 can be transferred to each other, thereby making The heat at various positions of the chip 12 can be relatively uniform, so as to prevent heat from accumulating at a certain position of the chip 12 and affecting the performance of the chip.
  • the via 51 passing through the encapsulation layer 10 in the present application refers to a structure formed by piercing the encapsulation layer 10 with a metal material.
  • a metal pillar may be formed first, and then the metal pillar is embedded in the packaging layer 10, and the metal pillar is the via 51 described in this application.
  • the heat sink 30 can directly contact the metal layer 50. That is, the heat sink 30 achieves indirect contact with the chip 12 through the metal layer 50, so that the heat generated by the operation of the chip 12 can be quickly transferred to the heat sink 30 through the metal layer 50 and dissipated.
  • the second surface 12b of the chip 12 is laminated with the metal layer 50, it is easier to form the heat sink 30 on one side of the chip 12 by electroplating, so as to achieve a better electroplating effect, so that the heat sink 30 and the chip The combination between 12 is more stable, and the heat of the chip 12 can be transferred to the heat sink 30 more efficiently.
  • the heat sink 30 can also directly contact the via hole 51. That is, in this embodiment, the via 51 can be electrically connected to the metal layer 50 through the heat sink 30, and the two ends of the via 51 are respectively connected to the electrode trace 13 and the heat sink 30, then the metal layer 50 can be connected to the electrode trace 13 The electrical connection is made through the radiator 51.
  • the surface of the package substrate 11 facing the heat sink 30 may also be provided with traces, and the metal layer 50 is electrically connected to the via 51 through the traces.
  • the chip packaging structure 100 of the embodiment shown in FIG. 4 also includes the bonding pads 40 of the chip packaging structure 100 of the embodiment shown in FIG. 3.
  • the setting method and structure are the same as the embodiment shown in FIG. 4, and will not be repeated here.
  • the chip 12 further includes a second electrode provided on the second surface 12b, and the metal layer 50 is the second electrode, that is, the second electrode of the chip covers the second surface of the chip 12 and is connected to The electrode wiring 13 is electrically connected through the via 51.
  • the chip 12 includes transistors for processing multiple functions, the number of electrodes in the chip 12 is relatively large, and part of the electrodes of the chip 12 can be arranged on the second surface 12b of the chip 12 to ensure the signal transmission effect.
  • the chip 12 when the chip 12 is a high-power chip 12, by providing a second electrode on the second side 12b, the heat generated by the operation of the chip 12 can be quickly dissipated from the first side 12a and the second side 12b of the chip 12 , In order to achieve better heat dissipation effect.
  • the metal layer 50 may not serve as the second electrode of the chip 12, and the second electrode of the chip 12 is located on the second surface 12b of the chip 12 and is in contact with the metal layer 50 for electrical connection.
  • FIG. 5 is a schematic structural diagram of a chip packaging structure 100 according to another embodiment of the application.
  • the chip packaging structure 100 further includes a thermally conductive insulating layer 60.
  • the thermally conductive insulating layer 60 covers the packaging layer 10, and the heat sink 30 is located on a side of the thermally conductive insulating layer 60 away from the packaging substrate 11, so that the chip 12 and the heat sink 30 are separated by the thermally conductive insulating layer 60. That is, the thermally conductive insulating layer 60 indirectly contacts the second surface 12 b of the chip 12 through the metal layer 50.
  • the thermally conductive insulating layer 60 separates the chip 12 from the heat sink 30, which can avoid the safety risk caused by the leakage of the chip 12.
  • the surface of the package substrate 11 facing the heat sink 30 is provided with a wire 52, and the metal layer 50 is electrically connected to the via 51 through the wire 52.
  • the thermally conductive insulating layer 60 may be one or more of thermally conductive silica gel, thermally conductive silicone grease, thermally conductive resin, or other types of thermally conductive materials.
  • the thermally conductive insulating layer 60 is a thermally conductive resin, which is formed by adding an insulating filler with high thermal conductivity to the resin material.
  • the insulating filler may be alumina ceramics, quartz sand and other materials.
  • the thermally conductive insulating layer 60 is formed on one side of the packaging substrate through a pressing process, so that the thermally conductive insulating layer 60 and the packaging substrate can have an integrated structure, so that the thermally conductive insulating layer 60 and the packaging substrate can be more integrated.
  • the heat sink 30 is formed on the surface of the thermally conductive insulating layer 60 away from the package substrate 11 by electroplating, so that the heat sink 30 and the thermally conductive insulating layer 60 can form an integrated structure, so that the thermally conductive insulating layer 60 and the heat sink 30 are combined It is more stable, and can reduce defects in the position where the thermally conductive insulating layer 60 is combined with the heat sink 30, so that the transmission to the thermally conductive insulating layer 60 can be efficiently transmitted to the heat sink 30 and dissipated.
  • the first electrode 121 can be extended to a desired position through the electrode wiring 13 or a window can be opened at the desired position according to the type of circuit board to be mounted on the chip package structure 100 21. Therefore, when the chip packaging structure 100 is electrically connected to the circuit board, the position of the opening 21 of the insulating layer 20 of the chip packaging structure 100 corresponding to the pads of the circuit board can be realized, that is, part of the electrodes of the opening window 21 are exposed.
  • the wires 13 correspond to the pads of the circuit board, so as to ensure that the chip package structure 100 can be easily connected to various types of circuit boards.
  • the extension position of the electrode wiring 13 and the insulating layer 20 can be adjusted according to the type of circuit board mounted on the chip packaging structure 100
  • the position of the window 21 on the upper side ensures that the chip packaging structure 100 can be flexibly applied to various types of circuit boards.
  • the present application also provides a chip packaging method, by which a chip is packaged to obtain the aforementioned chip packaging structure 100. Please refer to FIG. 6.
  • FIG. 6 is a flowchart of the steps of a chip packaging method of the present application.
  • the chip packaging method provided by this application mainly includes the following steps:
  • a metal carrier 1 is provided, and a metal pillar 2 is formed on one side of the metal carrier 1.
  • the metal pillars 2 are formed on one side of the metal carrier 1 by electroplating. Specifically, the surface of the metal carrier 1 is covered with a dry film, and the dry film corresponds to the position on the metal carrier 1 where the metal pillars 2 need to be electroplated to be hollowed out. After that, the surface of the metal carrier 1 is electroplated, so that the metal pillars 2 are electroplated in the areas not covered by the dry film.
  • the metal carrier 1 and the metal pillars 2 are both made of copper material with good electrical and thermal conductivity. It can be understood that in other embodiments of the present application, the metal carrier 1 and the metal pillars 2 may also be made of other metal materials.
  • resin is pressed on the side of the metal carrier 1 where the metal pillars 2 are formed.
  • a resin layer is formed on the side of the metal carrier 1 where the metal pillars 2 are formed by a pressing process, and the obtained resin layer is the packaging substrate 11 of the chip packaging structure 100 of this application, and the metal pillars 2 are the chips of this application.
  • part of the resin is ground away by a grinding process to expose the metal pillars 2.
  • the receiving cavity 14 is obtained through an etching process on the resin layer and the metal carrier 1 is removed. Wherein, the receiving cavity 14 penetrates the resin layer.
  • the chip 12 is fixedly arranged in the receiving cavity 14. Specifically, the adhesive tape 3 is pasted on one surface of the resin layer, and the adhesive tape 3 covers one end of the receiving cavity 14.
  • the chip 12 is arranged in the receiving cavity 14 and pasted on the adhesive tape 3 so that the position of the chip 12 in the receiving cavity 14 can be positioned by the adhesive tape 3.
  • the first surface 12 a of the chip 12 is stuck on the tape 3.
  • a metal layer 50 is pre-formed on the second surface 12b of the chip 12. When the metal layer 50 is the second electrode of the chip 12, the metal layer 50 is formed during the production process of the chip 12. When the metal layer 50 is not the second electrode of the chip 12, it is necessary to pre-form the metal layer 50 on the second surface 12b of the chip 12 by means of magnetron sputtering or vapor deposition.
  • the gap between the chip 12 and the receiving cavity 14 is filled with an insulating material 15 through a pressing process.
  • the insulating material 15 filled in the gap between the chip 12 and the housing cavity 14 is the same resin material as the resin layer.
  • the insulating material 15 filled in the gap between the chip 12 and the receiving cavity 14 may be a thermally conductive insulating material, such as thermally conductive resin, thermally conductive silicone grease, thermally conductive silica gel, and thermally conductive rubber.
  • the insulating material covering the second surface 12b of the chip 12 in step 150 can be removed by a grinding process or an etching process.
  • metal traces are formed on both sides of the packaging substrate 11, wherein the metal traces of the packaging substrate 11 corresponding to the first surface 12a of the chip 12 are connected to the first electrode 121 and one end of the metal pillar 2, and the packaging substrate 11 corresponds to the metal trace on the second surface 12b of the chip 12 connecting the metal sheet 50 and the other end of the metal pillar 2.
  • the metal trace connecting the first electrode 121 of the chip 12 is the electrode trace 13 of this application, and the metal trace connecting the metal sheet 50 of the chip 12 is the trace 52 of this application.
  • the first electrode 121 can be formed directly on the side of the package substrate 11 located on the first surface 12a of the chip 12, and directly on the side of the package substrate 11 corresponding to the second surface 12b of the chip 12.
  • the heat sink 30 is formed by an electroplating process, and then an insulating layer 20 with an opening 21 is formed on the side of the packaging substrate 11 corresponding to the first surface 12a of the chip 12, that is, the chip packaging structure 100 shown in FIG. 4 can be obtained.
  • a thermally conductive insulating layer 60 is formed on a side of the package substrate 11 corresponding to the second side 12 a of the chip 12 through a pressing process.
  • a heat sink 30 is formed by electroplating on the surface of the thermally conductive insulating layer 60 away from the resin layer.
  • methods such as vapor deposition, magnetron sputtering, electroless copper plating, etc. are provided to form an electroplating seed layer on the surface of the thermally conductive insulating layer 60 away from the resin layer, and then the heat sink 30 is formed on the basis of the electroplating seed layer through an electroplating process.
  • the method of forming the heat sink 30 on the surface of the thermally conductive insulating layer 60 away from the resin layer may also be injection molding or the like.
  • an insulating layer 20 with an opening 21 is formed on the side of the package substrate 11 corresponding to the first surface 12a of the chip 12, and the opening 21 corresponds to a part of the electrode trace 13, which is the result shown in FIG. 5 of the present application
  • the chip package structure 100 of the embodiment is shown.
  • the insulating layer 20 can be formed by spraying, inkjet printing, or the like.
  • the heat sink 30 is directly formed on the packaging substrate 11 or the thermally conductive insulating layer 60 by means of electroplating, injection molding, etc., so that the heat sink 30 and the packaging substrate 11 or the thermally conductive insulating layer 60 can be integrated.
  • the combination of the heat sink 30 and the packaging layer 10 is not prone to defects such as holes, so that the packaging The heat of the layer 10 can be transferred to the heat sink 30 more efficiently, to achieve a better heat dissipation effect, and to ensure a higher bonding strength between the heat sink 30 and the packaging layer 10.
  • the heat sink 30 is directly formed on the packaging layer 10 through electroplating or various molding processes in the present application, there is no need to fix the formed heat sink 30 to the package by welding, gluing, or fixing means. On the layer 10, the manufacturing process can be reduced, thereby reducing production costs and improving production efficiency.
  • the extension position of the electrode trace 13 and the position of the opening 21 on the insulating layer 20 can be adjusted according to the type of circuit board mounted on the chip packaging structure 100, so as to ensure that the chip packaging structure 100 can be flexibly applied to various applications. Types of circuit boards.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

一种芯片封装结构及电子设备。该芯片封装结构（100）包括绝缘层（20）、封装层（10）及散热器（30），散热器（30）与封装层（10）呈一体结构，相较于一般的通过焊接、胶粘或者固定件等将散热器（30）与封装层（10）进行固定的方式来说，散热器（30）与封装层（10）结合的位置不容易出现孔洞等缺陷，使得封装层（10）的热量能够高效的传输至散热器（30），并且能够减少制程。并且，该芯片封装结构（100）的芯片（12）的电极通过电极走线（13）引出，并在覆盖电极走线（13）的绝缘层（20）上开窗，以通过露出开窗的电极走线（13）实现芯片封装结构（100）与电子设备的其它结构电连接。因此，能够根据芯片封装结构（100）安装的电路板的类型，调整电极走线（13）延伸位置及绝缘层（20）上的开窗的位置，从而保证芯片封装结构（100）能够灵活的应用于各种类型的电路板中。

Description

一种芯片封装结构及电子设备
本申请要求于2020年5月30日提交中国专利局，申请号为202020965658.7、申请名称为“一种芯片封装结构及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电器元件领域，尤其涉及一种芯片封装结构及电子设备。
背景技术
芯片封装即为将芯片封装于封装结构内，并将芯片的电极引出至外壳，以便于封装后的芯片封装结构与其他的结构进行电连接。通过将芯片封装于外壳内，能够将芯片与外界隔离，从而防止外界的杂质对芯片电路的腐蚀或其它的影响而造成电气性能下降的问题。并且，封装后的芯片封装结构相较于单独的芯片能够有更高的强度，从而更加的方便安装和运输，也能够方便后续芯片与其它结构的连接等过程。
在一般的封装技术中，芯片中电极通常通过焊球焊接的方式引出引脚至外壳。当将封装好的封装结构安装于电路板上时，通过将与芯片的电极连接的焊球焊接至电路板的焊盘上，以实现芯片与电路板的电连接。但是，由于芯片中电极的位置固定，因此，焊球的位置也是相对固定的。而一般来说，不同规格的电路板上的焊盘位置也预先设计好的。当需要通过焊球焊接的方式将封装好的芯片与电路板进行连接时，需要将芯片中的电极位置与电路板上的焊盘位置相对应，因此，封装好的芯片只能与焊盘位置与其电极相对应的电路板进行连接，从而对电路板的可使用类型会造成限制。
发明内容
本申请提供一种能够适用于各种电路板的芯片封装结构，以及包括该芯片封装结构的电子设备。
第一方面，本申请提供一种芯片封装结构，该芯片封装结构包括依次层叠的绝缘层、封装层及散热器；所述封装层包括封装基板、芯片及电极走线，所述芯片嵌设于所述封装基板，所述芯片包括相对设置的第一面及第二面，所述芯片包括设于所述第一面的第一电极，所述电极走线形成于所述封装基板的表面并与所述第一电极电连接；所述绝缘层覆盖所述电极走线，所述绝缘层上设有开窗，所述开窗对应于所述电极走线设置以露出部分所述电极走线；所述散热器与所述封装层呈一体结构。
本申请中，芯片封装结构的芯片的第一电极通过电极走线引出，并在覆盖电极走线的绝缘层上开窗，以通过露出开窗的电极走线实现芯片封装结构与电子设备的其它结构电连接。因此，能够根据芯片封装结构安装的电路板的类型，调整电极走线延伸位置及绝缘层上的开窗的位置，从而保证芯片封装结构能够灵活的应用于各种类型的电路板中。并且，本申请的芯片封装结构的散热器与封装层呈一体结构，相较于一般的通过焊接、胶粘等方式或者固定件等将散热器与封装层进行固定的方式来说，散热器与封装层结合的位置不容 易出现孔洞等缺陷，使得封装层的热量能够高效的传输至散热器，且散热器与封装层的连接更加的牢固。并且，由于不需要焊接、胶粘或者固定件固定，从而能够减少制程。
一些实施方式中，所述芯片的所述第二面覆盖有金属层，所述金属层与所述电极走线电连接。
本实施方式中，芯片的第一面产生的热量能够依次通过第一电极、电极走线、金属层传输至散热器，再通过散热器将热量散出，从而避免在芯片的第一面产生的热量不能快速散出而影响芯片的性能的问题。并且，通过第一电极、电极走线及金属层将芯片的第一面与第二面连接，能够使得芯片的两面产生的热量能够相互传输，从而使得芯片的各个位置热量能够较为均匀，避免热量在芯片的某个位置聚集而影响芯片的性能。并且，由于芯片的第二面层叠有金属层，因此，散热器能够更容易的通过电镀的方式在芯片的第二面的一侧形成散热器，实现更好的电镀效果，从而使得散热器与芯片之间的结合更加的稳定，且芯片的热量能够更高效的传输至散热器。
一些实施方式中，所述芯片包括设于所述第二面的第二电极，所述金属层为所述第二电极。即金属层实现热量传输的作用，还能够用于传输信号。具体的，当芯片内包括用于处理多种功能的晶体管时，芯片中电极数量较多，可以在芯片的第二面设置部分的第二电极，以保证信号的传输效果。或者，当芯片为大功率芯片时，通过在第二面设置第二电极，使得芯片工作产生的热量能够更快的同时从芯片的第一面及第二面散出，以实现更好的散热效果。
一些实施方式中，所述封装基板包括有收容腔，所述芯片收容于所述收容腔内，所述芯片与所述收容腔之间有空隙，所述空隙内填充导热绝缘材料。芯片与收容腔的内壁之间的空隙通过导热绝缘材料进行填充，从而使得芯片能够稳定的固定于收容腔内，并能够使得芯片中工作产生的热量能够通过导热绝缘材料传输出去，提高芯片内热量的散出效率。
一些实施方式中，所述散热器层叠于所述封装基板并与所述封装基板呈一体结构，且所述散热器与所述芯片的第二面接触，芯片工作产生的热量能够快速的传输至散热器，从而提高散热效率。
一些实施方式中，所述芯片封装结构还包括导热绝缘层，所述导热绝缘层覆盖所述封装层，所述散热器位于所述导热绝缘层背离所述封装层的一侧并与所述导热绝缘层呈一体结构，所述导热绝缘层与所述芯片的第二面接触。当芯片为大功率芯片，即传输至芯片的电压较高时，通过导热绝缘层将芯片与散热器隔开，能够避免芯片的漏电而造成的安全风险。
一些实施方式中，所述芯片封装结构还包括焊接垫片，所述焊接垫片包括连接的第一部分及第二部分，所述第一部分覆盖所述电极走线露出所述开窗的区域，所述第二部分覆盖于所述绝缘层的所述开窗的周缘。
本实施方式中，通过在绝缘层的开窗位置形成面积较大的焊接垫片，并使得焊接垫片的第一部分与电极走线露出开窗的区域连接，从而能够增加芯片封装结构与其它结构进行电连接时的连接引脚的大小，从而使得芯片封装结构能够更容易且能够更稳定的与其它结构进行电连接。并且，由于部分焊接垫片覆盖于绝缘层上，相对于将焊球或者焊锡穿过绝缘层的开窗与电极走线连接的方式来说，焊球或者焊锡不需要穿过开窗与电极走线连接也 能够实现芯片封装结构与电路板的电连接，即封装芯片通过焊接垫片与其它结构电连接能够更容易，连接良率更高。
一些实施方式中，所述散热器包括金属片，所述金属片通过电镀形成于所述封装层。金属片为金属材料制成，金属材料具有较好的电导率，从而实现较好的散热效果。
一些实施方式中，所述散热器还包括多个散热鳍片，所述散热鳍片形成于所述金属片背离所述封装层的一侧，且各个所述散热鳍片之间有间隙。通过在金属片背离所述封装层的一侧设置散热鳍片，从而增加散热器与外界进行热交换的散热面积，从而提高散热器的散热效率。
第二方面，本申请还提供一种电子设备，该电子设备包括电路板及上述任意一项所述的芯片封装结构，所述芯片封装结构中露出所述开窗的部分所述电极走线与所述电路板电连接。本实施方式中，由于芯片封装结构能够灵活的应用于各种类型的电路板中，从而能够降低生产要求及生产成本。并且，本申请的芯片封装结构具有较好的散热能力，从而能够延长芯片封装结构的寿命，提高电子设备的品质。
附图说明
图1为本申请的一些实施方式的电子设备的截面示意图；
图2为本申请的一种实施方式的芯片封装结构的结构示意图；
图3为本申请另一种实施方式的芯片封装结构的结构示意图；
图4为本申请的另一种实施方式的芯片封装结构的结构示意图；
图5为本申请的另一种实施方式的芯片封装结构的结构示意图；
图6为本申请的一种芯片封装方法的步骤流程图；
图7-图15所示为图6所示芯片封装方法的各步骤的芯片封装结构的结构示意图。
具体实施方式
下面结合本申请实施方式中的附图对本申请的实施方式进行具体描述。
本申请提供一种电子设备，该电子设备可以为耳机、手机、平板电脑、穿戴手表、路由器等电子产品。电子设备中包括有能够实现各种功能的芯片。以手机为例，手机中可以包括调用电子设备指令以使电子设备执行相应的操作的中央处理芯片、用于数据存储的存储芯片、用于处理射频信号的射频芯片、用于处理音频信号的音频芯片等各种类型的芯片。芯片通过与电子设备内的其它结构进行电连接，从而执行及相关的功能。需要说明的是，电子设备中的各芯片均封装于芯片封装结构内，以防止芯片的电路受到外界的杂质腐蚀，并方便芯片的安装和运输。因此，本申请的电子设备中，通过将芯片封装结构与电子设备的其它结构进行电连接，从而实现芯片与电子设备内的其它结构的电连接。具体的，一些电子设备中包括有电路板，通过将封装芯片安装于电路板(刚性电路板或者柔性电路板)上，再将电路板与电子设备内的其它结构进行连接，从而通过电路板的走线连接芯片封装结构与电子设备的其它结构，以实现芯片封装结构与电子设备的其它结构之间的信号传输。例如，将封装有音频芯片的芯片封装结构安装于电路板上，再将电路板与电子设备的麦克风、扬声器等结构连接，使得麦克风接收的音频信息能够传输至音频芯片，经音频芯片处 理后进行存储。或者，存储的音频信息经音频芯片处理后传输至扬声器进行播放。
请参阅图1，图1所示为本申请的一些实施方式的电子设备1000的截面示意图。本实施方式中，电子设备1000为手机。电子设备1000中包括外壳200、设置于外壳200内的至少一个芯片封装结构100及主板300，芯片封装结构100安装于主板300上。主板300为电路板。主板300上安装有至少一个芯片封装结构100，芯片封装结构100通过主板300上的线路与集成于主板300上的其它元器件400进行连接形成处理电路。其中，其它的元器件400可以为电容、电感、电阻等元器件。或者，通过主板300连接至电子设备1000的其它结构500，以实现芯片封装结构100与电子设备1000的其它结构500之间信号传输。其中，电子设备1000的其它结构500可以为麦克风、扬声器、显示屏、触控层、天线等各种结构。根据芯片封装结构100中封装的芯片的类型不同，将芯片封装结构100与不同的结构进行电连接，从而实现芯片的不同功能。
请参阅图2，图2所示为本申请的一种实施方式的芯片封装结构100的结构示意图。该芯片封装结构100包括依次层叠的封装层10、绝缘层20及散热器30。本实施方式中，封装层10包括封装基板11、芯片12及电极走线13。芯片12嵌设于所述封装基板11，通过封装基板11保护设于其内的芯片12。封装基板11可以为树脂等绝缘材料形成。
本实施方式中，封装基板11设有收容腔14，收容腔14贯穿封装基板11。可以理解的是，本申请的其它一些实施方式中，收容腔14也可以为不贯穿封装基板11。例如，收容腔14可以为从封装基板11的一个表面向另一表面凹设的凹槽。芯片12收容于收容腔14内，且芯片12与收容腔14的内壁之间的空隙通过绝缘材料15进行填充，从而使得芯片12能够稳定的固定于收容腔14内。一些实施方式中，填充于芯片12与收容腔14的内壁之间的间隙内的绝缘材料15可以为导热绝缘材料，从而使得芯片12工作产生的热量能够通过导热绝缘材料传输出去，提高芯片12内热量的散出效率。例如，导热绝缘材料可以为导热树脂、塑封料等。一些实施方式中，填充于芯片12与收容腔14的内壁之间的空隙内的绝缘材料15可以为与封装基板11相同的材料，当绝缘材料15填充于芯片12与收容腔14的内壁之间的空隙时，填充于芯片12与收容腔14的内壁之间的空隙内的绝缘材料15与封装基板11能够形成一体结构，且由于绝缘材料15与封装基板11为同种材料，因此，绝缘材料15与收容腔14的内壁之间的结合会更加的稳定，避免受温度变化或者受外力作用时而产生分离，保证芯片封装结构100的寿命。
本申请中，芯片封装结构100内的芯片12的数量可以为一个或者多个。当芯片封装结构100内的芯片12数量为多个时，即将多个芯片12封装于同一封装结构内，从而能够减少封装步骤、降低生产成本，并能够减小芯片12封装后所占用的体积。芯片封装结构100内的芯片12的数量为多个时，多个芯片12可以并排设置或者在芯片12的厚度方向上堆叠设置。当芯片封装结构100上的多个芯片12并排设置时，封装基板11上设有多个并排间隔设置的收容腔14，每个芯片12对应的设于一个收容腔14内。当芯片封装结构100内的多个芯片12堆叠设置时，封装基板11的厚度可以较厚，以使多个芯片12堆叠后能够收容于同一收容腔14内，从而在节约芯片12封装步骤的同时，还能够减少芯片封装结构100占用的面积。
所述芯片12包括相对设置的第一面12a及第二面12b。具体的，芯片12中的有源区 所在的一面为本申请中芯片12的第一面12a。芯片12包括用于引出信号或者向芯片12内引入信号的电极。图2所示实施方式中，电极包括设于芯片12的第一面12a的第一电极121，第一电极121与电极走线13连接，信号能够依次通过电极走线13、第一电极121传输至芯片12内，或者，芯片12内的信号能够依次通过第一电极121、电极走线13输出。第一电极121的数量可以根据实际情况设置为一个或者多个。本申请一些实施方式中，芯片12的第一电极121有三个，三个第一电极121分别与芯片12中晶体管的栅极、源极及漏极进行电连接，通过在三个第一电极121中输入不同的信号，从而驱动芯片12进行工作。在本申请的其它实施方式中，芯片12的第一电极121可以为更多个。例如，芯片12内集成有多种功能的晶体管时，芯片12中的第一电极121可以更多，用于传输更多不同的信号，从而驱动芯片12实现不同的功能。
绝缘层20为绝缘材料形成，绝缘层20层叠于所述封装层10的一面并覆盖所述电极走线13，以通过绝缘层20保护电极走线13，避免电极走线13受到腐蚀而造成电气性能下降的问题，并能够避免外界对信号传输的干扰。
所述绝缘层20上设有开窗21，所述开窗21对应于所述电极走线13设置以露出部分所述电极走线13。将与电路板进行电连接时，可以将开窗21位置露出的部分电极走线13与电路板通过焊球或者焊锡进行电连接，从而将芯片封装结构100安装固定于电路板上，并使芯片封装结构100与电路板的走线进行电连接。如图1中所示，芯片封装结构100通过焊球101与主板300的焊盘301焊接，从而实现芯片封装结构100与主板300的电连接。本申请实施方式中，通过设计电极走线13的走线，可以根据芯片封装结构100需要安装的电路板的类型，将第一电极121通过电极走线13延伸至所需位置或者在所需位置开窗21，从而在将芯片封装结构100与电路板进行电连接时，可以实现芯片封装结构100的绝缘层20的开窗21位置与电路板的焊盘相对应，即露出开窗21的部分电极走线13与电路板的焊盘相对应，从而保证芯片封装结构100能够与各种类型的电路板方便的连接。换句话说，本申请中，由于通过电极走线13将芯片12的第一电极121引出，因此，能够根据芯片封装结构100安装的电路板的类型，调整电极走线13延伸位置及绝缘层20上的开窗21位置，从而保证芯片封装结构100能够灵活的应用于各种类型的电路板中。
本申请一些实施方式中，绝缘层20可以为液态光致阻焊剂(即绿油)，能够在实现保护电极走线13，并实现绝缘效果的同时，起到阻焊的作用，当将开窗21位置露出的部分电极走线13与电路板通过焊球或者焊锡进行电连接，焊料可以容易的集中于绝缘层20上的开窗21位置，从而提好焊接的良率。可以理解的是，本申请其它实施方式中，绝缘层20也可以为树脂等其它类型的绝缘材料。
本申请中，芯片封装结构100包括散热器30，散热器30用于为设于封装层10的芯片12进行散热。本申请中，所述散热器30层叠于所述封装层10背离绝缘层20的一面，并与所述封装层10呈一体结构。具体的，散热器30与封装层10呈一体结构是指散热器30能够通过电镀或者压合等工艺直接形成于封装层10上，而不需要通过焊接、胶粘或者固定件等固定的方式将预先成型好的散热器30与封装层10进行固定。相较于通过焊接、胶粘或者固定件等固定的方式将预先成型好的散热器30与封装层10进行固定的方式来说，散热器30与封装层10结合的位置不容易出现孔洞等缺陷，从而使得封装层10的热量能够更 高效的传输至散热器30，实现更好的散热效果，并能够保证散热器30与封装层10之间能够有更高的结合强度。并且，由于本申请中直接将散热器30通过电镀或者各种成型工艺直接成型于封装层10上，不需要将成型好的散热器30再通过焊接、胶粘或者固定件等固定方式固定于封装层10上，因而能够减少制程，从而减少生产成本、提高生产效率。
图2所述实施方式中，封装层10仅包括封装基板11及设于封装基板11的收容腔14内的芯片12，以及连接芯片12的第一电极121的电极走线13。散热器30层叠于封装层10背离绝缘层20的一面即为散热器30层叠于封装基板11背离绝缘层20的一面。本实施方式中，芯片12的第一面12a与朝向绝缘层20，散热器30层叠于封装层10时，散热器30与芯片12的第二面12b直接接触，从而使得芯片12工作产生的热量能够直接快速的传输至散热器30散出。
本申请一些实施方式中，散热器30为金属结构件，通过电镀的方式形成于封装层10，从而使得散热器30与封装层10呈一体结构。金属能够具有较高的导热系数，从而能够快速的将芯片12的热量传输出去，实现良好的导热效果。一些实施方式中，所述散热器30包括金属片31，所述金属片31通过电镀形成于所述封装层10。一些实施方式中，金属片31背离封装层10的表面211可以为凹凸不平的表面，如锯齿状表面、波浪形表面，从而能够增加金属片31与外界进行热交换的散热面积，从而提高散热器30的散热效率。
一些实施方式中，所述散热器30还包括多个散热鳍片32，所述散热鳍片32形成于所述金属片31背离所述封装层10的一侧，且各个所述散热鳍片32之间有间隙。通过在金属片31背离所述封装层10的一侧设置散热鳍片32，从而增加散热器30与外界进行热交换的散热面积，从而提高散热器30的散热效率。其中，多个散热鳍片32的形状及排布方式可以任意变化。例如，一些实施方式中，散热器30的散热鳍片32为条状，多个散热鳍片32沿垂直于散热鳍片32延伸的方向平行间隔排布；一些实施方式中，散热器30的散热鳍片32为柱状或块状，多个散热鳍片32阵列排布；一些实施方式中，散热器30的散热鳍片32为条状，多个散热鳍片32的一端连接，另一端分别向各个方向延伸呈放射状。可以理解的是，本申请中，散热鳍片32的形状及排布方式还可以为其它类型，在此不一一列举。本申请的其它一些实施方式中，散热器30还可以仅包括散热鳍片32，散热鳍片32直接形成于封装层10的表面。
可以理解的是，本申请的其它一些实施方式中，散热器30也可以为其它结构。例如，散热器30可以为风冷管。风冷管为管状结构，包括相对设置的进风口及出风口。冷却风从进风口进风，在风冷管24中流动并吸收芯片12传输至散热器30中的热量后从出风口出风。一些实施方式中，进风口设置有风扇，以增加风冷管中空气的流动效率，从而增强风冷管中的空气与散热壁发生热交换的效率，进而提高芯片封装结构100的散热效率。
请参阅图3，图3所示为本申请另一种实施方式的芯片封装结构100的结构示意图。本实施方式与图1所示实施方式的差别在于：本实施方式的芯片封装结构100还包括焊接垫片40。焊接垫片40为金属垫片，其大小略大于绝缘层20的开窗21的大小。焊接垫片40部分与露出所述开窗21的区域接触。具体的，所述焊接垫片40包括连接的第一部分41及第二部分42，所述第一部分41覆盖所述电极走线13露出所述开窗21的区域，所述第二部分42覆盖于所述绝缘层20的所述开窗21的周缘。本实施方式中，通过在绝缘层20 的开窗21位置形成面积较大的焊接垫片40，并使得焊接垫片40的第一部分41与电极走线13露出开窗21的区域连接，从而能够增加芯片封装结构100与电路板进行电连接时的引脚的大小，从而使得芯片封装结构100能够更容易且能够更稳定的与电路板的焊盘进行电连接。并且，由于焊接垫片40部分覆盖于绝缘层20的开窗21的周缘，即部分焊接垫片40覆盖于绝缘层20上，相对于将焊球或者焊锡穿过绝缘层20的开窗21与电极走线13连接的方式来说，焊球或者焊锡不需要穿过开窗21与电极走线13连接也能够实现芯片封装结构100与电路板的电连接，即焊接垫片40与电路板的焊盘焊接能够更容易，使得芯片封装结构100与电路板的电连接更简单且良率更高。
请参阅图4，图4所示为本申请的另一种实施方式的芯片封装结构100的结构示意图。本实施方式与图2所示的实施方式的差别在于：本实施方式中，芯片封装结构100还包括覆盖于芯片12第二面12b的金属层50，所述金属层50与所述电极走线13电连接。具体的，本实施方式中，封装基板11上设有过孔51，金属层50通过过孔51与电极走线13电连接。可以理解的是，本申请的其它一些实施方式中，收容腔14的腔壁可以形成金属连接层，金属层50通过金属连接层与电极走线13进行电连接。本实施方式中，芯片12的第一面12a产生的热量能够依次通过第一电极121、电极走线13、过孔51传输至散热器30，再通过散热器30将热量散出，从而避免在芯片12的第一面12a产生的热量不能快速散出而影响芯片12的性能的问题。并且，通过第一电极121、电极走线13、过孔51及金属层50将芯片12的第一面12a与第二面12b连接，能够使得芯片12的两面产生的热量能够相互传输，从而使得芯片12的各个位置热量能够较为均匀，避免热量在芯片12的某个位置聚集而影响芯片的性能。需要说明的是，本申请中所述的穿过所述封装层10的过孔51是指封装层10上穿设有穿孔，穿孔内填充金属材料而形成的结构。一些实施方式中，可以先形成金属柱，再将金属柱嵌设于封装层10内，金属柱即为本申请中所述的过孔51。
本实施方式中，由于芯片12的第二面12b层叠有金属层50，因此，散热器30层叠于封装基板11上时，散热器30能够与金属层50直接接触。即散热器30通过金属层50实现与芯片12的间接接触，使得芯片12工作产生的热量能够通过金属层50快速的传输至散热器30散出。并且，由于芯片12的第二面12b层叠有金属层50，因而能够更容易的通过电镀的方式在芯片12的一侧形成散热器30，实现更好的电镀效果，从而使得散热器30与芯片12之间的结合更加的稳定，且芯片12的热量能够更高效的传输至散热器30。并且，本实施方式中，由于过孔51为穿过封装基板11的结构，因此，散热器30也能够与过孔51直接接触。即本实施方式中，过孔51能够通过散热器30与金属层50电连接，过孔51的两端分别连接电极走线13及散热器30，则金属层50能够与所述电极走线13通过散热器51进行电连接。一些实施方式中，封装基板11朝向散热器30的表面还可以设置走线，通过走线连接金属层50与过孔51电连接。
一些实施方式中，图4所示实施方式的芯片封装结构100也包括图3所示实施方式的芯片封装结构100的焊接垫片40。其设置方式及结构与图4所示实施方式相同，再此不进行赘述。
一些实施方式中，芯片12还包括设于所述第二面12b的第二电极，所述金属层50为所述第二电极，即芯片的第二电极覆盖芯片12的第二面，并与电极走线13通过过孔51进 行电连接。例如，当芯片12内包括用于处理多种功能的晶体管时，芯片12中电极数量较多，可以将芯片12的部分电极设置于芯片12的第二面12b，以保证信号的传输效果。或者，当芯片12为大功率芯片12时，通过在第二面12b设置第二电极，使得芯片12工作产生的热量能够更快的同时从芯片12的第一面12a及第二面12b散出，以实现更好的散热效果。本申请的其它一些实施方式中，金属层50也可以不作为芯片12的第二电极，芯片12的第二电极位于其第二面12b，并与金属层50接触以进行电连接。
请参阅图5，图5所示为本申请的另一实施方式的芯片封装结构100的结构示意图。本实施方式与图4所示实施方式的差别在于：本实施方式中，所述芯片封装结构100还包括导热绝缘层60。所述导热绝缘层60覆盖封装层10，所述散热器30位于所述导热绝缘层60背离所述封装基板11的一侧，从而通过导热绝缘层60将芯片12与散热器30隔开。即导热绝缘层60通过金属层50间接的与所述芯片12的第二面12b接触。当芯片12为大功率芯片，即传输至芯片12的电压较高时，通过导热绝缘层60将芯片12与散热器30隔开，能够避免芯片12的漏电而造成的安全风险。并且，本实施方式中，封装基板11朝向散热器30的表面设置有走线52，通过走线52连接金属层50与过孔51电连接。
导热绝缘层60可以为导热硅胶、导热硅脂、导热树脂或者其它类型的导热材料中的一种或者几种。本实施方式中，导热绝缘层60为导热树脂，通过在树脂材料中添加具有较高的导热效率的绝缘的填料形成。具体的，绝缘的填料可以为氧化铝陶瓷、石英砂等材料。本实施方式中，导热绝缘层60通过压合工艺形成于封装基材的一面，从而使得导热绝缘层60与封装基材能够呈一体结构，使得导热绝缘层60与封装基材之间的结合更加的稳定，并能减少导热绝缘层60与封装基材结合的位置的缺陷，使得芯片12的热量能够高效的传输至导热绝缘层60。散热器30通过电镀的方式形成于导热绝缘层60背离封装基板11的表面，从而使得散热器30能够与所述导热绝缘层60呈一体结构，使得导热绝缘层60与散热器30之间的结合更加的稳定，并能减少导热绝缘层60与散热器30结合的位置的缺陷，使得传输至导热绝缘层60能够高效的传输至散热器30散出。
本申请中，通过设计电极走线13的走线，可以根据芯片封装结构100需要安装的电路板的类型，将第一电极121通过电极走线13延伸至所需位置或者在所需位置开窗21，从而在将芯片封装结构100与电路板进行电连接时，可以实现芯片封装结构100的绝缘层20的开窗21位置与电路板的焊盘相对应，即露出开窗21的部分电极走线13与电路板的焊盘相对应，从而保证芯片封装结构100能够与各种类型的电路板方便的连接。换句话说，本申请中，由于通过电极走线13将芯片12的第一电极121引出，因此，能够根据芯片封装结构100安装的电路板的类型，调整电极走线13延伸位置及绝缘层20上的开窗21位置，从而保证芯片封装结构100能够灵活的应用于各种类型的电路板中。
本申请还提供一种芯片封装方法，通过该芯片封装方法封装芯片以得到上述的芯片封装结构100。请参阅图6，图6所示为本申请的一种芯片封装方法的步骤流程图。本申请提供的芯片封装方法主要包括步骤：
请参阅图7，提供一金属载板1，在金属载板1的一面形成金属柱2。
本实施方式中，通过电镀的方式在金属载板1的一面形成金属柱2。具体的，在金属载板1的表面覆盖干膜，且干膜对应于金属载板1上需要电镀形成金属柱2的位置镂空。 之后，将金属载板1的表面进行电镀，从而在未被干膜覆盖的区域电镀形成金属柱2。本实施方式中，金属载板1及金属柱2均为具有较好的导电导热性能的铜材料制成。可以理解的是，本申请的其它实施方式中，金属载板1及金属柱2也可以为其它金属材料制成。
请参阅图8，在金属载板1形成有金属柱2的一面压合树脂。
具体的，通过压合工艺在金属载板1形成有金属柱2的一面形成树脂层，得到的树脂层即为本申请的芯片封装结构100的封装基板11，金属柱2即为本申请的芯片封装结构100的过孔51。一些实施方式中，当压合树脂覆盖金属柱2时，通过研磨工艺研磨掉部分树脂以露出金属柱2。
请参阅图9，在树脂层上通过蚀刻工艺得到收容腔14并去除金属载板1。其中，收容腔14穿透树脂层。
请参阅图10，将芯片12固定设置于收容腔14内。具体的，在树脂层的一个表面粘贴胶带3，胶带3覆盖收容腔14的一端。将芯片12设于收容腔14内并粘贴于胶带3上，以通过胶带3对芯片12在收容腔14中的位置进行定位。本实施方式中，将芯片12的第一面12a粘贴于胶带3上。一些实施方式中，芯片12的第二面12b上预先形成有金属层50。当金属层50为芯片12的第二电极时，则在芯片12的生产过程中形成有金属层50。当金属层50并非为芯片12的第二电极时，需要通过磁控溅射或者气相沉积等方式在芯片12的第二面12b上预先形成金属层50。
150、请参阅图11，通过压合工艺在芯片12与收容腔14之间的空隙内填充绝缘材料15。本实施方式中，在芯片12与收容腔14之间的空隙内填充的绝缘材料15为与树脂层相同的树脂材料。一些实施方式中，芯片12与收容腔14之间的空隙内填充的绝缘材料15可以为导热绝缘材料，如导热树脂、导热硅脂、导热硅胶、导热橡胶等材料。
160、请参阅图12，去除覆盖于芯片12的第二面12b的绝缘材料。具体的，可以通过研磨工艺或者刻蚀工艺除经步骤150时覆盖于芯片12的第二面12b的绝缘材料。
170、请参阅图13，在封装基板11的两面形成金属走线，其中，封装基板11对应于芯片12的第一面12a的金属走线连接第一电极121及金属柱2的一端，封装基板11对应于芯片12的第二面12b的金属走线连接金属片50及金属柱2的另一端。其中，连接芯片12的第一电极121的金属走线即为本申请的电极走线13，连接芯片12的金属片50的金属走线即为本申请的走线52。
需要说明的是，在本步骤中，可以直接再封装基板11位于芯片12的第一面12a的一侧形成第一电极121，在封装基板11对应于芯片12的第二面12b的一侧直接通过电镀工艺形成散热器30，再在封装基板11对应于芯片12的第一面12a的一侧形成具有开窗21的绝缘层20，即能够得到图4所示的芯片封装结构100。
请参阅图14，在封装基板11对应于芯片12的第二面12a的一面通过压合工艺形成导热绝缘层60。
请参阅图15，在导热绝缘层60背离树脂层的表面电镀形成散热器30。具体的，提供气相沉积、磁控溅射、化学镀铜法等方式在导热绝缘层60背离树脂层的表面先形成电镀种子层，再通过电镀工艺在电镀种子层的基础上形成散热器30。一些实施方式中，在导热绝缘层60背离树脂层的表面形成散热器30的方式还可以为注塑成型等方式。
请参阅图5，在封装基板11对应于芯片12的第一面12a的一侧形成具有开窗21的绝缘层20，开窗21对应于部分的电极走线13，即得到本申请图5所示实施方式的芯片封装结构100。具体的，绝缘层20可以通过喷涂、喷墨打印等方式形成。
上述芯片封装方法中，通过电镀、注塑成型等方式直接在封装基板11或导热绝缘层60上形成散热器30，能够使得散热器30与封装基板11或导热绝缘层60呈一体结构。相较于通过焊接、胶粘或者固定件等固定的方式将散热器30与封装层10进行固定的方式来说，散热器30与封装层10结合的位置不容易出现孔洞等缺陷，从而使得封装层10的热量能够更高效的传输至散热器30，实现更好的散热效果，并能够保证散热器30与封装层10之间能够有更高的结合强度。并且，由于本申请中直接将散热器30通过电镀或者各种成型工艺直接成型于封装层10上，不需要将成型好的散热器30再通过焊接、胶粘或者固定件等固定方式固定于封装层10上，因而能够减少制程，从而减少生产成本、提高生产效率。并且，本申请中，能够根据芯片封装结构100安装的电路板的类型，调整电极走线13延伸位置及绝缘层20上的开窗21的位置，从而保证芯片封装结构100能够灵活的应用于各种类型的电路板中。
需要说明的是，以上仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内；在不冲突的情况下，本申请的实施方式及实施方式中的特征可以相互组合。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种芯片封装结构，其特征在于，包括依次层叠的绝缘层、封装层及散热器；所述封装层包括封装基板、芯片及电极走线，所述芯片嵌设于所述封装基板，所述芯片包括相对设置的第一面及第二面，所述芯片包括设于所述第一面的第一电极，所述电极走线形成于所述封装基板的表面并与所述第一电极电连接；所述绝缘层覆盖所述电极走线，所述绝缘层上设有开窗，所述开窗对应于所述电极走线设置以露出部分所述电极走线；所述散热器与所述封装层呈一体结构。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述芯片的所述第二面覆盖有金属层，所述金属层与所述电极走线电连接。
  3. 根据权利要求2所述的芯片封装结构，其特征在于，所述芯片包括设于所述第二面的第二电极，所述金属层为所述第二电极。
  4. 根据权利要求1所述的芯片封装结构，其特征在于，所述封装基板包括有收容腔，所述芯片收容于所述收容腔内，所述芯片与所述收容腔之间有空隙，所述空隙内填充导热绝缘材料。
  5. 根据权利要求4所述的芯片封装结构，其特征在于，所述散热器层叠于所述封装基板并与所述封装基板呈一体结构，且所述散热器与所述芯片的第二面接触。
  6. 根据权利要求1-4任一项所述的芯片封装结构，其特征在于，所述芯片封装结构还包括导热绝缘层，所述导热绝缘层覆盖所述封装层，所述散热器位于所述导热绝缘层背离所述封装层的一侧并与所述导热绝缘层呈一体结构，所述导热绝缘层与所述芯片的第二面接触。
  7. 根据权利要求1所述的芯片封装结构，其特征在于，所述芯片封装结构还包括焊接垫片，所述焊接垫片包括连接的第一部分及第二部分，所述第一部分覆盖所述电极走线露出所述开窗的区域，所述第二部分覆盖于所述绝缘层的所述开窗的周缘。
  8. 根据权利要求1所述的芯片封装结构，其特征在于，所述散热器包括金属片，所述金属片通过电镀形成于所述封装层。
  9. 根据权利要求8所述的芯片封装结构，其特征在于，所述散热器还包括多个散热鳍片，所述散热鳍片形成于所述金属片背离所述封装层的一侧，且各个所述散热鳍片之间有间隙。
  10. 一种电子设备，其特征在于，包括电路板及权利要求1-9任意一项所述的芯片封装结构，所述芯片封装结构中露出所述开窗的部分所述电极走线与所述电路板电连接。
PCT/CN2021/094996 2020-05-30 2021-05-20 一种芯片封装结构及电子设备 WO2021244304A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP21817520.6A EP4152376A4 (en) 2020-05-30 2021-05-20 CHIP ENCAPSULATION STRUCTURE AND ELECTRONIC DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202020965658.7U CN212517170U (zh) 2020-05-30 2020-05-30 一种芯片封装结构及电子设备
CN202020965658.7 2020-05-30

Publications (1)

Publication Number Publication Date
WO2021244304A1 true WO2021244304A1 (zh) 2021-12-09

Family

ID=74392225

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/094996 WO2021244304A1 (zh) 2020-05-30 2021-05-20 一种芯片封装结构及电子设备

Country Status (3)

Country Link
EP (1) EP4152376A4 (zh)
CN (1) CN212517170U (zh)
WO (1) WO2021244304A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115440682A (zh) * 2022-09-09 2022-12-06 奇异摩尔(上海)集成电路设计有限公司 高散热三维系统级芯粒封装结构及工艺

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN212517170U (zh) * 2020-05-30 2021-02-09 华为技术有限公司 一种芯片封装结构及电子设备
CN113707623A (zh) * 2021-07-26 2021-11-26 华为技术有限公司 芯片封装组件、电子设备及芯片封装组件的制作方法
CN114203655B (zh) * 2021-11-19 2023-11-03 苏州浪潮智能科技有限公司 芯片封装结构
CN218867104U (zh) * 2022-11-30 2023-04-14 深圳飞骧科技股份有限公司 异构封装基板和模组
CN118507443B (zh) * 2024-07-18 2024-09-20 成都兴仁科技有限公司 一种堆叠式电容芯片封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956584A (zh) * 2011-08-18 2013-03-06 新光电气工业株式会社 半导体装置
CN103117275A (zh) * 2013-01-31 2013-05-22 华为技术有限公司 一种芯片封装结构及芯片封装方法
US20150035135A1 (en) * 2013-08-02 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Packages with Heat Sinks Attached to Heat Dissipating Rings
CN109830465A (zh) * 2018-12-12 2019-05-31 南方科技大学 一种芯片封装结构及芯片封装方法
CN111029332A (zh) * 2019-12-27 2020-04-17 广东佛智芯微电子技术研究有限公司 具有高散热和电磁屏蔽性的扇出型封装结构及其制备方法
CN212517170U (zh) * 2020-05-30 2021-02-09 华为技术有限公司 一种芯片封装结构及电子设备

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150008566A1 (en) * 2013-07-02 2015-01-08 Texas Instruments Incorporated Method and structure of panelized packaging of semiconductor devices
JP6770331B2 (ja) * 2016-05-02 2020-10-14 ローム株式会社 電子部品およびその製造方法
US10186467B2 (en) * 2016-07-15 2019-01-22 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10490479B1 (en) * 2018-06-25 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Packaging of semiconductor device with antenna and heat spreader
US11183460B2 (en) * 2018-09-17 2021-11-23 Texas Instruments Incorporated Embedded die packaging with integrated ceramic substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956584A (zh) * 2011-08-18 2013-03-06 新光电气工业株式会社 半导体装置
CN103117275A (zh) * 2013-01-31 2013-05-22 华为技术有限公司 一种芯片封装结构及芯片封装方法
US20150035135A1 (en) * 2013-08-02 2015-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Packages with Heat Sinks Attached to Heat Dissipating Rings
CN109830465A (zh) * 2018-12-12 2019-05-31 南方科技大学 一种芯片封装结构及芯片封装方法
CN111029332A (zh) * 2019-12-27 2020-04-17 广东佛智芯微电子技术研究有限公司 具有高散热和电磁屏蔽性的扇出型封装结构及其制备方法
CN212517170U (zh) * 2020-05-30 2021-02-09 华为技术有限公司 一种芯片封装结构及电子设备

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4152376A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115440682A (zh) * 2022-09-09 2022-12-06 奇异摩尔(上海)集成电路设计有限公司 高散热三维系统级芯粒封装结构及工艺

Also Published As

Publication number Publication date
EP4152376A1 (en) 2023-03-22
EP4152376A4 (en) 2023-11-22
CN212517170U (zh) 2021-02-09

Similar Documents

Publication Publication Date Title
WO2021244304A1 (zh) 一种芯片封装结构及电子设备
US11107766B2 (en) Substrate with embedded stacked through-silicon via die
US10453802B2 (en) Semiconductor package structure, semiconductor device and method for manufacturing the same
TWI644407B (zh) 封裝結構、電子設備及封裝方法
US6218731B1 (en) Tiny ball grid array package
US8592959B2 (en) Semiconductor device mounted on a wiring board having a cap
US6400010B1 (en) Substrate including a metal portion and a resin portion
WO2020228704A1 (zh) 一种埋入式封装结构及其制备方法、终端
TW201814876A (zh) 電子封裝結構及其製法
JP2004537169A (ja) 埋込アンテナを伴うリードレスチップキャリアの構造および製造方法
TWI725426B (zh) 半導體裝置
WO2022063283A1 (zh) 半导体封装结构及其制造方法和半导体器件
WO2018098649A1 (zh) 集成电路封装方法以及集成封装电路
TWI553828B (zh) 整合型功率模組
JP2003086726A (ja) 高電力モノリシックマイクロ波集積回路パッケージ
CN115066746A (zh) 封装结构及其制备方法和电子设备
TWI788191B (zh) 具有天線的封裝結構及其製作方法
CN107845610A (zh) 基板结构及其制作方法
WO2021143242A1 (zh) 封装结构及其制备方法
KR20150076816A (ko) 전자 부품 모듈
WO2021203726A1 (zh) 传感器及其制作方法、以及电子设备
JP2016219535A (ja) 電子回路装置
JP2006049602A (ja) 半導体装置およびその製造方法
KR20070030034A (ko) 적층 반도체 패키지
JP2003007914A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21817520

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021817520

Country of ref document: EP

Effective date: 20221215

NENP Non-entry into the national phase

Ref country code: DE