WO2021237734A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021237734A1
WO2021237734A1 PCT/CN2020/093514 CN2020093514W WO2021237734A1 WO 2021237734 A1 WO2021237734 A1 WO 2021237734A1 CN 2020093514 W CN2020093514 W CN 2020093514W WO 2021237734 A1 WO2021237734 A1 WO 2021237734A1
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WIPO (PCT)
Prior art keywords
layer
isolation
metal layer
insulating layer
base substrate
Prior art date
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PCT/CN2020/093514
Other languages
English (en)
French (fr)
Inventor
黄炜赟
程羽雕
顾品超
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/271,248 priority Critical patent/US11871605B2/en
Priority to EP20900704.6A priority patent/EP3993080A4/en
Priority to JP2021564336A priority patent/JP2023536012A/ja
Priority to CN202080000867.0A priority patent/CN114207860B/zh
Priority to PCT/CN2020/093514 priority patent/WO2021237734A1/zh
Priority to KR1020217035250A priority patent/KR20230035199A/ko
Publication of WO2021237734A1 publication Critical patent/WO2021237734A1/zh
Priority to US18/194,427 priority patent/US20230309337A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • AMOLED has the characteristics of thinner and lighter, active light emission (no backlight source), no viewing angle problems, high definition, high brightness, fast response, low energy consumption, wide operating temperature range, strong shock resistance, and soft display.
  • the light-emitting material used in the flexible AMOLED technology is an organic light-emitting material that is very sensitive to water and oxygen. It cannot be exposed to an environment with water and oxygen, otherwise it is prone to corrosion, causing the organic light-emitting material to fail and display abnormalities. Therefore, it must be isolated from water and oxygen. Indispensable.
  • the embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device, which can prevent water vapor and oxygen from entering the display area from the opening of the perforated area, thereby prolonging the service life of the product and the display effect.
  • the first aspect of the present disclosure provides a display panel including a display area, an opening area, and an isolation area between the display area and the opening area, the isolation area being at least partially arranged around the opening area; wherein ,
  • the display panel includes:
  • the driving circuit layer includes a thin film transistor and a storage capacitor formed on the base substrate and located in the display area.
  • the thin film transistor includes a gate electrode and a second layer formed on the side of the gate electrode away from the base substrate.
  • the storage capacitor includes a first electrode plate provided on the same layer as the gate electrode and a second electrode plate located between the first gate insulating layer and the interlayer dielectric layer;
  • the first isolation pillar is formed on the base substrate and is located in the isolation region; the first isolation pillar is arranged around the opening region, and it includes a first metal layer and is formed on the first metal layer A first insulating layer on the side away from the base substrate, a second insulating layer formed on the side of the first insulating layer away from the base substrate, and a second insulating layer formed on the second insulating layer away from the base substrate A second metal layer on one side; the first metal layer and the first electrode plate or the second electrode plate are provided in the same layer; the first insulating layer and the first gate insulating layer are provided in the same layer; The second insulating layer and the interlayer dielectric layer are provided in the same layer, and the second insulating layer includes a first part, a second part, and a first inclined part connecting the first part and the second part, so The slope angle of the first inclined portion is less than 90°; the second metal layer is provided in the same layer as the source and drain electrodes and is located on the side of the second portion away
  • the orthographic projection of the second metal layer on the base substrate is located within the orthographic projection of the first metal layer on the base substrate.
  • the first metal layer and the first electrode plate are provided in the same layer;
  • the first isolation pillar further includes a third metal layer, and the third metal layer is provided in the same layer as the second electrode plate.
  • the orthographic projection of the second metal layer on the base substrate is within the orthographic projection of the third metal layer on the base substrate;
  • the orthographic projection of the third metal layer on the base substrate is located within the orthographic projection of the first metal layer on the base substrate.
  • the ratio of the cross-sectional width of the second metal layer to the cross-sectional width of the first metal layer is greater than or equal to 0.4 and less than or equal to 0.7;
  • the ratio of the cross-sectional width of the second metal layer to the cross-sectional width of the third metal layer is greater than or equal to 0.5 and less than or equal to 0.9;
  • the ratio of the cross-sectional width of the third metal layer to the cross-sectional width of the first metal layer is greater than or equal to 0.58 and less than 1;
  • the cross-sectional plane is a plane extending in the radial direction of the first isolation column.
  • the cross-sectional width of the first metal layer is 6.5 ⁇ m to 8.5 ⁇ m;
  • the cross-sectional width of the second metal layer is 3.5 ⁇ m to 4.5 ⁇ m;
  • the cross-sectional width of the third metal layer is 5 ⁇ m to 7 ⁇ m.
  • the thickness of the first metal layer and the third metal layer is to The thickness of the second metal layer is to
  • the slope angle of the first inclined portion is 10° to 45°.
  • a buffer layer is further provided between the base substrate and the driving circuit layer;
  • the thin film transistor further includes a semiconductor layer and a second gate insulating layer sequentially formed on the buffer layer, and the second gate insulating layer is located between the gate and the semiconductor layer.
  • the first isolation pillar further includes a third insulating layer and a fourth insulating layer, the third insulating layer and the second gate insulating layer are provided in the same layer, and the The fourth insulating layer is provided in the same layer as the buffer layer.
  • the display panel further includes:
  • a planarization layer located in the display area and covering the thin film transistor
  • a pixel defining layer located in the display area and formed on the planarization layer for defining a plurality of pixel units
  • a first barrier dam is located in the isolation area and arranged around the opening area, and the first barrier dam is arranged on the same layer as the pixel defining layer;
  • the second barrier dam is located in the isolation area and arranged around the opening area; the second barrier dam is located on the side of the first barrier dam close to the opening area, and includes The first barrier portion provided in the same layer and the second barrier portion provided in the same layer as the pixel defining layer; the height of the second barrier dam is greater than the height of the first barrier dam.
  • the display panel further includes a second isolation pillar formed on the base substrate and located in the isolation region, and the second isolation pillar surrounds the opening region Provided, and the second isolation pillar at least includes a fourth metal layer, and the fourth metal layer and the second metal layer have the same structure and are provided in the same layer;
  • first barrier dam and the second barrier dam are located between the first isolation column and the second isolation column.
  • the second isolation pillar further includes a fifth metal layer, a fifth insulating layer, and a sixth insulating layer.
  • the second electrode plate is arranged in the same layer; the fifth insulating layer and the first gate insulating layer are arranged in the same layer; the sixth insulating layer and the interlayer dielectric layer are arranged in the same layer;
  • the sixth insulating layer includes a third part, a fourth part, and a second inclined part connecting the third part and the fourth part, and the slope angle of the second inclined part is greater than that of the first inclined part.
  • the slope angles of the parts are the same, and the fourth metal layer is located on the side of the fourth part away from the base substrate.
  • the fifth metal layer and the first electrode plate are provided in the same layer;
  • the second isolation pillar further includes a sixth metal layer, and the sixth metal layer is provided in the same layer as the second electrode plate.
  • the second isolation pillar further includes a seventh insulating layer and an eighth insulating layer, the seventh insulating layer and the second gate insulating layer are provided in the same layer, and the The eighth insulating layer is provided in the same layer as the buffer layer.
  • the second isolation pillar further includes an insulating stack located on the fourth metal layer close to the base substrate, the insulating stack and the buffer layer,
  • the second gate insulating layer, the first gate insulating layer, and the interlayer dielectric layer are arranged in the same layer, and are combined with the buffer layer, the second gate insulating layer, the first gate insulating layer, and the interlayer dielectric layer.
  • the interlayer dielectric layers are disconnected from each other; wherein, the insulating laminate has a slope surface with a slope angle of 50° to 70°.
  • one of the first isolation column and the second isolation column is located on the side of the first barrier dam close to the display area, and the other is located at the side of the display area.
  • the side of the second barrier dam close to the opening area;
  • first isolation pillars there are a plurality of the first isolation pillars, and/or there are a plurality of the second isolation pillars.
  • the display panel further includes an encapsulation film, the encapsulation film includes at least a first inorganic encapsulation layer, and the first inorganic encapsulation layer is located in the display area and the isolation area , And cover the driving circuit layer and the first isolation pillar.
  • a second aspect of the present disclosure provides a display device, which is characterized by comprising the display panel described in any one of the above.
  • a second aspect of the present disclosure provides a method for manufacturing a display panel.
  • the display panel includes a display area, an opening area, and an isolation area between the display area and the opening area, and the isolation area at least partially surrounds the display area.
  • the opening area is set; wherein, the manufacturing method includes:
  • a driving circuit layer and a first isolation pillar are formed on the base substrate; wherein,
  • the driving circuit layer includes a thin film transistor and a storage capacitor located in the display area, the thin film transistor includes a gate, a first gate insulating layer formed on a side of the gate away from the base substrate, and The interlayer dielectric layer on the side of the first gate insulating layer away from the base substrate and the source and drain electrodes formed on the side of the interlayer dielectric layer away from the base substrate; A first electrode plate arranged in the same layer and a second electrode plate located between the first gate insulating layer and the interlayer dielectric layer;
  • the first isolation pillar is arranged around the opening area, and it includes a first metal layer, a first insulating layer formed on the side of the first metal layer away from the base substrate, and formed on the first metal layer.
  • the second insulating layer on the side of the insulating layer away from the base substrate and the second metal layer formed on the side of the second insulating layer away from the base substrate; the first metal layer and the first electrode Plate or the second electrode plate are arranged in the same layer; the first insulating layer and the first gate insulating layer are arranged in the same layer; the second insulating layer and the interlayer dielectric layer are arranged in the same layer, and the
  • the second insulating layer includes a first part, a second part, and a first inclined part connecting the first part and the second part.
  • the slope angle of the first inclined part is less than 90°;
  • the source and drain electrodes are arranged in the same layer and located on the side of the second part away from the base substrate, and the side facing the display area and/or the side facing the opening area is provided with a surrounding area. The notch in the opening area.
  • the first metal layer and the first electrode plate are provided in the same layer;
  • the first isolation pillar further includes a third metal layer, and the third metal layer is provided in the same layer as the second electrode plate.
  • a second isolation pillar located in the isolation region is formed on the base substrate; the second isolation pillar is arranged around the opening region, and the second isolation pillar includes at least a fourth metal layer, and the second isolation pillar includes at least a fourth metal layer.
  • the four metal layers have the same structure as the second metal layer and are arranged in the same layer;
  • a first barrier dam and a second barrier dam are formed in the isolation area, the first barrier dam is arranged around the opening area, and the first barrier dam is arranged in the same layer as the pixel defining layer;
  • a second barrier dam is arranged around the opening area and is located on the side of the first barrier dam close to the opening area, and the second barrier dam is arranged in the same layer as the planarization layer and the pixel defining layer ;
  • the height of the second barrier dam is greater than the height of the first barrier dam;
  • first barrier dam and the second barrier dam are located between the first isolation column and the second isolation column.
  • the structure of the second isolation pillar is the same as the structure of the first isolation pillar.
  • FIG. 1 is a schematic structural diagram of a part of a display panel between a display area and an isolation area according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an enlarged structure of part A shown in FIG. 1;
  • FIG. 3 is a schematic diagram of the structure of the isolation column shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of a display panel described in another embodiment of the present disclosure.
  • FIG. 5 is a schematic cross-sectional view of the display panel along the line B-B in the embodiment shown in FIG. 4;
  • FIG. 6 is a schematic cross-sectional view of the display panel along the line C-C in the embodiment shown in FIG. 4;
  • FIG. 7 is a schematic cross-sectional view of the display panel along the line C-C in another embodiment shown in FIG. 4;
  • FIG. 8 is a schematic cross-sectional view of the display panel along the line C-C in another embodiment shown in FIG. 4;
  • FIG. 9 is a schematic diagram of the structure of the first isolation column or the second isolation column in the display area of the display panel shown in FIG. 6;
  • FIG. 10 is a schematic diagram of the structure of the first isolation column or the second isolation column in the display area of the display panel shown in FIG. 7;
  • FIG. 11 is a schematic diagram of the structure of the first isolation column or the second isolation column in the display area of the display panel shown in FIG. 8.
  • Display panel; 20a display area; 20b, opening area; 20c, isolation area; 21, base substrate; 22, buffer layer; 23, first isolation column; 230, first metal layer; 231, first Insulating layer; 232, second insulating layer; 232a, first part; 232b, second part; 232c, first inclined part; 233, second metal layer; 233a, notch; 234, third insulating layer; 235, first Four insulating layers; 236, third metal layer; 24, thin film transistors; 240, semiconductor layer; 241, second gate insulating layer; 242, gate; 243, first gate insulating layer; 244, interlayer dielectric layer; 245 , Source; 246, drain; 25, storage capacitor; 250, the first plate; 251, the second plate; 26, the planarization layer; 27, the pixel defining layer; 28, the first barrier dam; 29, the first Two barrier dam; 290, the first barrier portion; 291, the second barrier portion; 30, the pixel unit; 300, the anode; 301, the organic light-emitting material;
  • the "on”, “formed on” and “disposed on” in this article can mean that one layer is directly formed or disposed on another layer, or it can mean a layer A layer is formed indirectly or arranged on another layer, that is, there are other layers between the two layers.
  • first may be used herein to describe various components, components, elements, regions, layers and/or parts, these components, components, elements, regions, and layers And/or part should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and/or section from another.
  • the term “same layer arrangement” used means that two layers, parts, components, elements or parts can be formed by the same patterning process, and the two layers, parts, components The components or parts are generally formed of the same material, and are located on the same film layer and directly contact the film layer.
  • patterning process generally includes the steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • one-time patterning process means a process of forming patterned layers, parts, components, etc., using one mask.
  • a structure such as an isolation column 12 and an isolation groove 13 are arranged between the display area 10 and the opening area 11 to block the organic light-emitting material 15, thereby isolating water and oxygen.
  • the function of the passage can also play the role of blocking the cathode layer 16.
  • the method for manufacturing the isolation pillar 12 is: separately depositing a buffer layer (buffer), a gate insulating layer (Gate Insulator, GI) and an interlayer dielectric layer (Interlayer Dielectric, ILD) on the substrate 14, and then A specific pattern is obtained by exposing and developing the ILD+GI+buffer layer 120, EBA (Etch Bending A)/EBB (Etch Bending B) etching, and then forming an SD (source drain) metal layer 121 on the specific pattern, and The SD metal layer 121 is etched to form an undercut structure, which can isolate the organic light-emitting material 15; specifically, as shown in FIGS. 2 to 3, this isolation column is made by EBA/EBB etching. 12 can be referred to as EBA/EBB isolation column for short. This EBA/EBB isolation column can share a mask with the bending process.
  • the EBA/EBB isolation column has two characteristics: one is that the formed slope angle ⁇ 1 is large, and the other is that the formed step difference h1 is large; this makes the use of chemical vapor deposition (Chemical Vapor Deposition, abbreviation: CVD)
  • CVD chemical Vapor Deposition
  • the inorganic encapsulation layer 17 formed by the technology is deposited very steeply at the slope of the ILD+GI+buffer layer 120, which is not conducive to releasing external stress. Cracks are prone to occur under the action of external stress, leading to package failure, and water and oxygen invade. , It will cause the device to display abnormality.
  • an embodiment of the present disclosure provides a display panel 2 which can be an OLED display.
  • the display panel 2 may include a display area 20a, an opening area 20b, and an isolation area 20c located between the display area 20a and the opening area 20b, and the isolation area 20c is at least partially arranged around the opening area 20b.
  • the display panel 2 may include a base substrate 21, a driving circuit layer and a first isolation pillar 23; wherein:
  • the provided base substrate 21 may be a flexible substrate such as polyimide (PI), and when the display panel 2 is a rigid substrate, the base substrate 21 may be a rigid substrate such as glass or quartz. .
  • PI polyimide
  • each area may be defined on the base substrate 21.
  • the display area 20a, The isolation region 20c and the opening region 20b are defined on the base substrate 21.
  • the driving circuit layer is formed on the base substrate 21.
  • the driving circuit layer may include a thin film transistor 24 and a storage capacitor 25 formed on the base substrate 21 and located in the display area 20a.
  • the thin film transistor 24 may include a gate electrode 242, a first gate insulating layer 243, an interlayer dielectric layer 244, and source and drain electrodes that are sequentially formed; that is, the gate electrode may be formed on the base substrate 21 first. Pole 242; After that, a first gate insulating layer 243 is formed on the side of the gate 242 away from the base substrate 21, and an interlayer dielectric layer is formed on the side of the first gate insulating layer 243 away from the base substrate 21.
  • the interlayer dielectric The side of the layer 244 away from the base substrate 21 forms source and drain electrodes; and the thin film transistor 24 may also include a semiconductor layer 240.
  • the semiconductor layer 240 may be located on the side of the gate 242 close to the base substrate 21, so that the thin film transistor 24 It is a top gate type; it should be understood that when the thin film transistor 24 is a top gate type, the thin film transistor 24 may further include a second gate insulating layer 241, which is located between the gate 242 and the semiconductor layer 240 between.
  • the semiconductor layer 240 may also be located on the side of the gate 242 away from the base substrate 21 and between the first gate insulating layer 243 and the interlayer dielectric layer 244, so that the thin film transistor 24 is of a bottom gate type. It should be understood that the thin film transistor 24 of the embodiment of the present disclosure is not limited to the top gate type shown in the figure, and may also be a bottom gate type.
  • the aforementioned source and drain electrodes include a source 245 and a drain 246 arranged in the same layer.
  • the source 245 and the drain 246 can pass through the interlayer dielectric layer 244 and the first gate.
  • the via hole on the insulating layer 243 is connected to both ends of the semiconductor layer 240 respectively.
  • the storage capacitor 25 includes a first electrode plate 250 and a second electrode plate 251.
  • the first electrode plate 250 and the gate electrode 242 are arranged in the same layer.
  • the first gate insulating layer 243, the second gate insulating layer 241, and the interlayer dielectric layer 244 mentioned in the embodiments of the present disclosure may be made of inorganic insulating materials, such as silicon oxide, silicon nitride and other inorganic materials.
  • the semiconductor layer 240 can be made of materials such as polysilicon and metal oxide; the gate 242, the first electrode plate 250 and the second electrode plate 251 can be made of aluminum, titanium, cobalt and other metals or alloy materials;
  • the source electrode 245 and the drain electrode 246 can be made of metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium; among them, the source electrode 245 and the drain electrode 246 have a multi-layer structure At this time, the multi-layer structure may be a multi-metal laminate, such as a three-layer metal laminate of titanium, aluminum, and titanium (Ti/Al/Ti).
  • a buffer layer 22 can also be provided between the base substrate 21 and the driving circuit layer.
  • the buffer layer 22 can be made of silicon nitride, silicon oxide, etc., to block water, oxygen, and alkali. While the ionic effect, it can also protect other structures on the base substrate 21; it should be noted that not only a buffer layer 22 can be provided between the base substrate 21 and the drive circuit layer, but other layers can also be provided. ,As the case may be. Wherein, when the thin film transistor 24 is of a top gate type, the semiconductor layer 240 thereof may be located on the buffer layer 22.
  • the first isolation pillar 23 is formed on the base substrate 21 and is located in the isolation region 20c; the first isolation pillar 23 is arranged around the opening region 20b, and includes a first metal layer 230 formed sequentially , The first insulating layer 231, the second insulating layer 232, and the second metal layer 233, that is, the first metal layer 230 can be formed on the base substrate 21 first, and then, the first metal layer 230 is away from the base substrate 21 A first insulating layer 231 is formed on one side, a second insulating layer 232 is formed on the side of the first insulating layer 231 away from the base substrate 21, and a second metal layer 233 is formed on the side of the second insulating layer 232 away from the base substrate 21 .
  • the first metal layer 230 and the first electrode plate 250 or the second electrode plate 251 are provided in the same layer; the first insulating layer 231 and the first gate insulating layer 243 are provided in the same layer; the second insulating layer 232 and the interlayer dielectric layer 244
  • the second insulating layer 232 includes a first portion 232a, a second portion 232b, and a first inclined portion 232c connecting the first portion 232a and the second portion 232b. As shown in FIGS.
  • the first inclined portion The slope angle ⁇ 2 of 232c is less than 90°; the second metal layer 233 is arranged in the same layer as the source and drain electrodes and is located on the side of the second portion 232b away from the base substrate 21, and it faces the side of the display area 20a and/or opens.
  • One side of the hole region 20b is provided with a notch 233a surrounding the hole region 20b; wherein the first inclined portion 232c cooperates with the second metal layer 233 to block the organic light-emitting material, thereby isolating the water and oxygen path.
  • the first spacer 23 can not only block the organic light-emitting material 301, but also block other materials, such as the cathode 302 and so on.
  • the area of the second insulating layer 232 opposite to the first metal layer 230 is heightened with respect to other areas of the second insulating layer 232 to naturally form a slope angle ⁇ 2 smaller than 90°; because the second insulating layer 232 naturally The first inclined portion 232c having a slope angle ⁇ 2 is formed. Therefore, in the process of manufacturing the first isolation column 23 in the embodiment of the present disclosure, compared to the process of manufacturing the EBA/EBB isolation column 12 shown in FIGS.
  • the steps of "exposing, developing, EBA (Etch Bending A)/EBB (Etch Bending B) etching to the ILD+GI+buffer layer 120 to obtain a specific pattern" can be omitted, that is: to block the organic light emission
  • one step of masking process can be omitted, so that the cost can be reduced.
  • the embodiment of the present disclosure adds the first metal layer 230 to heighten the portion of the second insulating layer 232 opposite to the first metal layer 230, thereby forming the first inclined portion 232c with the slope angle ⁇ 2; therefore, Compared with the slope angle ⁇ 1 formed by exposure, development, and EBA (Etch Bending A)/EBB (Etch Bending B) etching of the ILD+GI+buffer layer 120 shown in FIGS. 1 to 3, the present disclosure implements In the example, the gradient angle ⁇ 2 is relatively small, and the level difference h2 formed at the gradient angle ⁇ 2 is also relatively small. For details, referring to FIGS. 9 to 11, the gradient angle ⁇ 2 and the level difference h2 of the embodiment of the present disclosure are respectively smaller than those shown in FIG. 3 The gradient angle ⁇ 1 and the step difference h1 in the EBA/EBB isolation column 12.
  • the slope angle ⁇ 2 of the first inclined portion 232c of the first isolation column 23 in the embodiment of the present disclosure may be 10° to 45°, such as 10°, 20°, 30°, 45°, etc.
  • the slope angle ⁇ 1 of the slope surface at the ILD+GI+buffer layer 120 of the EBA/EBB isolation column 12 shown in 3 may be 50° to 70°, such as 50°, 60°, 70°, and so on.
  • the slope angle ⁇ 2 of the first inclined portion 232c of the first isolation column 23 in the embodiment of the present disclosure is smaller than the slope angle ⁇ 1 at the slope of the EBA/EBB isolation column 12, when the inorganic packaging layer is subsequently deposited, the present disclosure
  • the inorganic encapsulation layer (the first inorganic encapsulation layer 320 shown in FIGS. 6 to 8) of the embodiment is compared with the inorganic encapsulation layer 320 shown in FIGS. 1 and 2 at the first inclined portion 232c of the first spacer 23.
  • the encapsulation layer 17 is deposited more smoothly on the slope of the EBA/EBB isolation column 12 to help release external stress, so that the inorganic encapsulation layer is not prone to cracks under the condition of external stress, thereby further blocking the intrusion of water and oxygen , To ensure the display effect.
  • first insulating layer 231 and the second insulating layer 232 of the embodiment of the present disclosure may be an integral structure, as long as the first inclined portion 232c can be formed.
  • the first isolation pillar 23 further includes a third insulating layer 234 and a fourth insulating layer 235, and the third insulating layer 234 may be the same layer as the second gate insulating layer 241
  • the fourth insulating layer 235 can be provided in the same layer as the buffer layer 22.
  • the first metal layer 230 of the first isolation pillar 23 and the first electrode plate 250 may be provided in the same layer.
  • the orthographic projection of the second metal layer 233 on the base substrate 21 in the first isolation pillar 23 is located within the orthographic projection of the first metal layer 230 on the base substrate 21, so that it is located at the first isolation pillar 23
  • the inorganic encapsulation layer is more helpful to release external stress and prevent the inorganic encapsulation layer from cracking under the condition of external stress.
  • the first metal layer 230 may also form a slope with a certain angle during the manufacturing process.
  • the ratio of the cross-sectional width of the second metal layer 233 to the cross-sectional width of the first metal layer 230 is greater than or equal to 0.4 and less than or equal to 0.7.
  • the cross-sectional width of the first metal layer 230 may be 6.5 ⁇ m to 8.5 ⁇ m, such as: 6.5 ⁇ m, 7 ⁇ m, 7.5 ⁇ m, 8 ⁇ m, 8.5 ⁇ m, etc.; the cross-sectional width of the second metal layer 233 may be 3.5 ⁇ m to 8.5 ⁇ m.
  • 4.5 ⁇ m such as: 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m and so on.
  • the level difference h2 in the embodiment of the present disclosure may be the thickness of the first metal layer 230.
  • the cross-sectional plane mentioned in the embodiment of the present disclosure is a plane extending in the radial direction of the first isolation column 23; and the cross-sectional width can be the maximum width of the cross-section, but is not limited to this, and the width of other positions of the cross-section can also be in the above-mentioned Within the value range.
  • the first metal layer 230 of the first isolation pillar 23 and the second electrode plate 251 may be provided in the same layer.
  • the orthographic projection of the second metal layer 233 on the base substrate 21 in the first isolation pillar 23 is located within the orthographic projection of the first metal layer 230 on the base substrate 21, so that it is located at the first isolation pillar 23
  • the inorganic encapsulation layer is more helpful to release external stress and prevent the inorganic encapsulation layer from cracking under the condition of external stress.
  • the first metal layer 230 may also form a slope with a certain angle during the manufacturing process.
  • the ratio of the cross-sectional width of the second metal layer 233 to the cross-sectional width of the first metal layer 230 is greater than or equal to 0.4 and less than or equal to 0.7.
  • the cross-sectional width of the first metal layer 230 may be 6.5 ⁇ m to 8.5 ⁇ m, such as: 6.5 ⁇ m, 7 ⁇ m, 7.5 ⁇ m, 8 ⁇ m, 8.5 ⁇ m, etc.; the cross-sectional width of the second metal layer 233 may be 3.5 ⁇ m to 8.5 ⁇ m.
  • 4.5 ⁇ m such as: 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m and so on.
  • the level difference h2 in the embodiment of the present disclosure may be the thickness of the first metal layer 230.
  • the cross-sectional plane mentioned in the embodiment of the present disclosure is a plane extending in the radial direction of the first isolation column 23; and the cross-sectional width can be the maximum width of the cross-section, but is not limited to this, and the width of other positions of the cross-section can also be in the above-mentioned Within the value range.
  • the first metal layer 230 of the first isolation pillar 23 may be provided in the same layer as the first electrode plate 250, and the first isolation pillar 23 may further include a third metal layer 236.
  • the third metal layer 236 and the second electrode plate 251 are provided in the same layer.
  • the orthographic projection of the second metal layer 233 on the base substrate 21 is located within the orthographic projection of the third metal layer 236 on the base substrate 21; the orthographic projection of the third metal layer 236 on the base substrate 21 is located
  • the first metal layer 230 is in the orthographic projection on the base substrate 21, so that the inorganic encapsulation layer located at the first isolation pillar 23 is more helpful to release external stress, and prevents the inorganic encapsulation layer from being exposed to external stress. crack.
  • the first metal layer 230 and the second metal layer 233 may also form a slope with a certain angle during the manufacturing process.
  • the ratio of the cross-sectional width of the second metal layer 233 to the cross-sectional width of the first metal layer 230 is greater than or equal to 0.4 and less than or equal to 0.7; the cross-sectional width of the second metal layer 233 is greater than or equal to the third The ratio of the cross-sectional width of the metal layer 236 is greater than or equal to 0.5 and less than or equal to 0.9; the ratio of the cross-sectional width of the third metal layer 236 to the cross-sectional width of the first metal layer 230 is greater than or equal to 0.58 and less than 1.
  • the cross-sectional width of the first metal layer 230 may be 6.5 ⁇ m to 8.5 ⁇ m, such as: 6.5 ⁇ m, 7 ⁇ m, 7.5 ⁇ m, 8 ⁇ m, 8.5 ⁇ m, etc.; the cross-sectional width of the second metal layer 233 may be 3.5 ⁇ m to 8.5 ⁇ m. 4.5 ⁇ m, such as: 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, etc.; the maximum width of the third metal layer 236 is 5 ⁇ m to 7 ⁇ m, such as: 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m, 6.5 ⁇ m, 7 ⁇ m, etc.
  • the level difference h2 in the embodiment of the present disclosure may be the sum of the thicknesses of the first metal layer 230 and the third metal layer 236.
  • the cross-sectional plane mentioned in the embodiment of the present disclosure is a plane extending in the radial direction of the first isolation column 23; and the cross-sectional width can be the maximum width of the cross-section, but is not limited to this, and the width of other positions of the cross-section can also be in the above-mentioned Within the value range.
  • first metal layer 230, the second metal layer 233, and the third metal layer 236 in the first isolation pillar 23 mentioned in the foregoing embodiment are generally manufactured by an etching process, so that the manufactured
  • the first metal layer 230, the second metal layer 233, and the third metal layer 236 usually have a certain slope angle. Specifically, the first metal layer 230, the second metal layer 233, and the third metal layer 236 are far away from the base substrate 21.
  • the orthographic projection of the surface on the base substrate 21 is the orthographic projection of the surface close to the base substrate 21 on the base substrate 21; based on this, in order to ensure that the inorganic encapsulation layer can further release external stress, in the embodiments of the present disclosure
  • the maximum cross-sectional width of the second metal layer 233 may be less than the minimum cross-sectional width of the first metal layer 230; the maximum cross-sectional width of the second metal layer 233 may be less than the minimum cross-sectional width of the third metal layer 236; The maximum width of the third metal layer 236 may be smaller than the minimum cross-sectional width of the first metal layer 230.
  • first insulating layer 231, the second insulating layer 232, the third insulating layer 234, and the fourth insulating layer 235 in the first isolation pillar 23 of the embodiment of the present disclosure are designed to be the same as those in the related art EBA/EBB isolation pillar.
  • the maximum cross-sectional width and minimum cross-sectional width of the second insulating layer 232 with a slope angle ⁇ 2 in the first isolation column 23 are designed to be the same as those of the ILD in the EBA/EBB isolation column.
  • the main factor affecting the slope angle ⁇ 2 of the first spacer 23 in the embodiment of the present disclosure is the thickness of the first metal layer 230 and the second metal layer 233;
  • the thickness of the first metal layer 230 and the third metal layer 236 may be to for example: And so on, it should be understood that the thickness of the first metal layer 230 and the thickness of the third metal layer 236 may be the same or different, depending on the specific situation.
  • the thickness of the second metal layer 233 in the first isolation pillar 23 may be to for example: and many more.
  • the ratio of the thickness of the notch 233a on the second metal layer 233 to the thickness of the second metal layer 233 may be 0.5 to 0.8, for example: 0.5, 0.6, 0.7 , 0.8 and so on.
  • the second metal layer 233 has a Ti/Al/Ti multilayer structure
  • a specific etching solution can be used to etch the Ti/Al/Ti multilayer structure.
  • the etching solution only has an etching effect on the Al layer, or the etching rate on the Al layer is greater than the etching rate on the Ti layer, so that a notch 233a can be formed on the second metal layer 233, so that the second metal layer 233 has
  • the partition adopts vapor deposition to form a film layer (for example: organic light-emitting material 301, cathode 302, etc.).
  • a film layer for example: organic light-emitting material 301, cathode 302, etc.
  • the cross-sectional plane of the second metal layer 233 is "I-shaped", that is, the side of the second metal layer 233 facing the display area 20a and the side facing the opening area 20b are both provided with surrounding opening areas.
  • the notch 233a of 20b further separates the organic light-emitting material 301, the cathode 302, and the like.
  • the thickness of the first insulating layer 231 may be to for example: Etc.; the thickness of the second insulating layer 232 can be to for example: Etc.; the thickness of the third insulating layer 234 can be to for example: And so on; the thickness of the fourth insulating layer 235 can be to for example: and many more.
  • cross-sectional width mentioned in the embodiment of the present disclosure is the dimension in the X direction in FIGS. 6 to 8
  • the thickness is the dimension in the Y direction in FIGS. 6 to 8.
  • the isolation column that forms the slope angle only by adding the metal layer provided on the same layer as the first electrode plate 250 can be defined as the Gate1 isolation column; it is only formed by adding the metal layer provided on the same layer as the second electrode plate 251
  • the isolation column of the slope angle can be defined as the Gate2 isolation column; the isolation column that forms the slope angle by adding the metal layer provided in the same layer as the first electrode plate 250 and the second electrode plate 251 can be defined as the Gate1+Gate2 isolation column;
  • the first isolation column 23 of the embodiment of the present disclosure may be a Gate1 isolation column, a Gate2 isolation column or a Gate1+Gate2 isolation column.
  • the display panel 2 may further include a planarization layer 26 and a pixel defining layer 27 located in the display area 20a, and a first barrier dam 28 and a second barrier located in the isolation area 20c. Dam 29; where the planarization layer 26 covers the thin film transistor 24, and the pixel defining layer 27 is formed on the planarization layer 26, that is, after the formation of the thin film transistor 24 and the storage capacitor 25 is completed, the planarization layer 26 is sequentially formed And a pixel defining layer 27; this pixel defining layer 27 is used to define a plurality of pixel units 30.
  • the first barrier dam 28 and the second barrier dam 29 are both arranged around the perforated area 20b, and the second barrier dam 29 is located on the side of the first barrier dam 28 close to the perforated area 20b, wherein the first barrier dam 28 and the pixel define
  • the layer 27 is provided in the same layer
  • the second barrier dam 29 includes a first barrier portion 290 provided in the same layer as the planarization layer 26 and a second barrier portion 291 provided in the same layer as the pixel defining layer 27; and the height of the second barrier dam 29 Greater than the height of the first barrier dam 28, the first barrier dam 28 and the second barrier dam 29 are used to restrict the flow of the organic encapsulation layer 321 in the encapsulation film, and prevent the organic encapsulation layer 321 from flowing to the open area 20b.
  • the problem of package failure is used to restrict the flow of the organic encapsulation layer 321 in the encapsulation film, and prevent the organic encapsulation layer 321 from flowing to the open area 20b.
  • first barrier dam 28 or the second barrier dam 29 may also be separately provided, and the number of the first barrier dam 28 and the second barrier dam 29 is not limited to one, and may also be provided More.
  • the structures of the first barrier dam 28 and the second barrier dam 29 are not limited to the structures shown in FIGS. 6 to 8, depending on the specific circumstances.
  • the planarization layer 26 and the pixel defining layer 27 can be made of organic insulating materials, such as organic insulating materials such as polyimide and epoxy resin.
  • the display area may also include an inorganic protective layer (PVX), which is not shown in the figure.
  • the inorganic protective layer may be formed on the side of the source and drain electrodes away from the base substrate 21 and located on the planarization layer 26 close to the base substrate 21.
  • the inorganic protective layer can be located between the source and drain electrodes and the planarization layer, and the inorganic protective layer covers the source and drain electrodes to protect the source and drain electrodes.
  • the inorganic protective layer can be made of inorganic insulating materials such as silicon nitride and silicon oxide. It should be understood that the inorganic protective layer is not provided in the isolation region 20c to protect the isolation pillars.
  • the display panel 2 may further include a pixel unit 30 located in the display area 20a.
  • the pixel unit 30 may include an anode 300, an organic light-emitting material 301, and a cathode 302.
  • the anode 300 may precede The pixel defining layer 27 is formed on the planarizing layer 26 and is connected to the drain 246 of the thin film transistor 24 through the via hole on the planarizing layer 26; the pixel defining layer 27 is formed with a pixel opening corresponding to the anode 300 at the location where the pixel opening is exposed At least part of the anode 300 is formed; after the pixel defining layer 27 is formed, the organic light-emitting material 301 can be vapor-deposited on the entire surface, and the organic light-emitting material 301 can be separated at the first isolation column 23, as shown in FIGS.
  • the organic light-emitting material 301 is located in the pixel opening and is in contact with the anode 300; after the organic light-emitting material 301 is vapor-deposited on the entire surface, the cathode 302 material can also be vapor-deposited on the entire surface. 23 partitions, as shown in Figure 6 to Figure 8.
  • the pixel unit 30 may also include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, which are not shown in the figure. These layers are formed on the display panel 2 by evaporation. When it is in the middle, it can be cut off at the first isolation column 23.
  • the anode 300 may be made of ITO (Indium Tin Oxide), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) and other materials;
  • the organic light-emitting material 301 may include small molecular organic materials or polymer molecular organic materials. It can be a fluorescent light-emitting material or a phosphorescent light-emitting material, which can emit red light, green light, blue light, or white light, etc.;
  • the cathode 302 can be lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc. Made of metal materials.
  • the display panel 2 may further include a second isolation pillar 31 formed on the base substrate 21 and located in the isolation region 20c, and the second isolation pillar 31 surrounds the opening region. 20b setting. As shown in FIGS. 9 to 11, and the second isolation pillar 31 includes at least a fourth metal layer 310.
  • the fourth metal layer 310 and the second metal layer 233 have the same structure and are arranged in the same layer; wherein, the first barrier dam 28 and The second barrier dam 29 is located between the first isolation column 23 and the second isolation column 31; that is, one of the first isolation column 23 and the second isolation column 31 is located near the display area 20a of the first barrier dam 28 On one side, the other is located on the side of the second barrier dam 29 close to the opening area 20b.
  • the isolation column located on the side of the first barrier dam 28 close to the display area 20a can be defined as an inner isolation column
  • the isolation column located on the side of the second barrier dam 29 close to the opening area 20b can be defined as an outer isolation column, namely:
  • One of the one isolation column 23 and the second isolation column 31 may be defined as an inner isolation column, and the other may be defined as an outer isolation column.
  • FIGS. 6 to 8 only show the case where the first isolation column 23 is an inner isolation column and the second isolation column 31 is an outer isolation column, the embodiment of the present disclosure is not limited to this, and the first isolation column may also be the first isolation column.
  • the pillar 23 is an outer isolation pillar
  • the second isolation pillar 31 is an inner isolation pillar.
  • first isolation pillar 23 mentioned in the embodiment of the present disclosure may be provided with multiple, and/or the second isolation pillar 31 may be provided with multiple; that is, both the inner isolation pillar and the outer isolation pillar may be provided with multiple .
  • the structures of the multiple inner isolation columns can be the same, but not limited to this, and they can also be different; as shown in FIGS. 6 to 8, the structure of the multiple outer isolation columns can be The same, but not limited to this, and may also be different.
  • the organic light-emitting material 301 is further blocked by setting the inner isolation column and the outer isolation column, thereby further blocking the intrusion of water and oxygen, and ensuring the display effect.
  • the second isolation column 31 may be one of Gate1 isolation column, Gate2 isolation column, Gate1+Gate2 isolation column or EBA/EBB isolation column; specifically:
  • the second isolation pillar 31 may be a Gate1 isolation pillar.
  • the second isolation pillar 31 may also include a fifth metal layer 311, a fifth insulation layer 312, and The sixth insulating layer 313, the fifth metal layer 311 and the first electrode plate 250 are arranged in the same layer; the fifth insulating layer 312 and the first gate insulating layer 243 are arranged in the same layer; the sixth insulating layer 313 and the interlayer dielectric layer 244 are arranged in the same layer
  • the sixth insulating layer 313 includes a third portion 313a, a fourth portion 313b and a second inclined portion 313c connecting the third portion 313a and the fourth portion 313b, the slope angle of the second inclined portion 313c and the first inclined portion
  • the slope angles of 232c are the same, and the fourth metal layer 310 is located on the side of the fourth portion 313b away from the base substrate 21.
  • the second isolation pillar 31 may further include a seventh insulating layer 314 and an eighth insulating layer 315, the seventh insulating layer 314 and the second gate insulating layer 241 are provided in the same layer, and the eighth insulating layer 315 is the same as the buffer layer 22. Layer settings.
  • the second isolation pillar 31 may be a Gate2 isolation pillar.
  • the second isolation pillar 31 may also include a fifth metal layer 311, a fifth insulation layer 312, and The sixth insulating layer 313, the fifth metal layer 311 and the second electrode plate 251 are arranged in the same layer; the fifth insulating layer 312 and the first gate insulating layer 243 are arranged in the same layer; the sixth insulating layer 313 and the interlayer dielectric layer 244 are arranged in the same layer
  • the sixth insulating layer 313 includes a third portion 313a, a fourth portion 313b and a second inclined portion 313c connecting the third portion 313a and the fourth portion 313b, the slope angle of the second inclined portion 313c and the first inclined portion
  • the slope angles of 232c are the same, and the fourth metal layer 310 is located on the side of the fourth portion 313b away from the base substrate 21.
  • the second isolation pillar 31 may further include a seventh insulating layer 314 and an eighth insulating layer 315, the seventh insulating layer 314 and the second gate insulating layer 241 are provided in the same layer, and the eighth insulating layer 315 is the same as the buffer layer 22. Layer settings.
  • the second isolation pillar 31 may be Gate1+Gate2 isolation pillars.
  • the second isolation pillar 31 may also include a fifth metal layer 311 and a fifth insulation layer.
  • the sixth metal layer 316 and the sixth insulating layer 313, the fifth metal layer 311 and the first electrode plate 250 are arranged in the same layer;
  • the fifth insulating layer 312 and the first gate insulating layer 243 are arranged in the same layer;
  • the sixth insulating layer 313 and the interlayer dielectric layer 244 are provided on the same layer as the second electrode plate 251;
  • the sixth insulating layer 313 includes a third portion 313a, a fourth portion 313b and connecting the third portion 313a and the third portion 313a.
  • the second inclined portion 313c of the fourth portion 313b has the same gradient angle as the first inclined portion 232c, and the fourth metal layer 310 is located on the side of the fourth portion 313b away from the base substrate 21.
  • the second isolation pillar 31 may further include a seventh insulating layer 314 and an eighth insulating layer 315, the seventh insulating layer 314 and the second gate insulating layer 241 are provided in the same layer, and the eighth insulating layer 315 is the same as the buffer layer 22. Layer settings.
  • the second isolation pillar 31 also includes an insulating stack located on the fourth metal layer 310 close to the base substrate 21, the insulating stack and the buffer layer 22, the second gate insulating layer 241, the first gate insulating layer 243, and the interlayer dielectric.
  • the layer 244 is arranged in the same layer, and is disconnected from the buffer layer 22, the second gate insulating layer 241, the first gate insulating layer 243 and the interlayer dielectric layer 244; wherein the insulating stack has a slope angle of 50° to 70° Slope surface;
  • this second isolation column 31 can be the EBA/EBB isolation column shown in FIG. 2 and FIG. 3.
  • the first isolation column 23 is designed as at least one of Gate1 isolation column, Gate2 isolation column, Gate1+Gate2 isolation column
  • the second isolation column 31 is designed as Gate1 isolation column, Gate2 isolation column
  • At least one of Gate1+Gate2 isolation pillars is designed to prevent cracks from occurring at the slopes of the isolation pillars and also prevent cracks at the edges of the opening area 20b from extending into the display area 20a, thereby further ensuring the packaging effect.
  • the structure of the second isolation column 31 may be the same as or different from the structure of the first isolation column 23, depending on the specific circumstances.
  • FIGS. 6 to 8 only show the case where the structures of the first isolation column 23 and the second isolation column 31 are the same, but the embodiment of the present disclosure is not limited thereto.
  • the first isolation column 23 is at least one of the Gate1 isolation column, the Gate2 isolation column, and the Gate1+Gate2 isolation column
  • the second isolation column 31 is the gate1 isolation column, the Gate2 isolation column, and the Gate1+Gate2 isolation column.
  • the first insulating layer 231 and the fifth insulating layer 312 can be connected to the first gate insulating layer 243; the second insulating layer 232 and the sixth insulating layer 313 can be connected to the interlayer dielectric layer 244; the third insulating layer 234.
  • the seventh insulating layer 314 may be connected to the second gate insulating layer 241, and the fourth insulating layer 235 and the eighth insulating layer 315 may be connected to the buffer layer 22.
  • the inner isolation column and the outer isolation column in the embodiment of the present disclosure are not limited to the above-mentioned combination design.
  • multiple inner isolation columns can be provided, and each structure is different, etc.; as long as the isolation in the display panel 2 can be ensured At least one Gate1 isolation column, Gate2 isolation column or Gate1+Gate2 isolation column exists in the area 20c.
  • the display panel 2 may further include an encapsulation film 32.
  • the encapsulation film 32 includes at least a first inorganic encapsulation layer 320, which is located in the display area 20a and isolated from each other.
  • the area 20c covers the driving circuit layer and the first isolation pillar 23.
  • the first inorganic encapsulation layer 320 is relatively smooth at the slope of the first isolation pillar 23, and is not steep, which helps prevent cracks from occurring at the slope. It should be understood that the first inorganic encapsulation layer 320 may cover the entire structure on the display area 20a and the isolation area 20c to improve the encapsulation effect of the display panel 2.
  • the encapsulation film 32 may further include a second inorganic encapsulation layer 322 and an organic encapsulation layer 321.
  • the organic encapsulation layer 321 is located on the first inorganic encapsulation layer 320 and the second inorganic encapsulation layer 322. between.
  • the organic encapsulation layer 321 may be located in the display area 20a and the isolation area 20c, and be blocked on the side of the first barrier dam 28 close to the display area 20a; the second inorganic encapsulation layer 322 may cover the entire display area 20a and the isolation area 20c.
  • the first inorganic encapsulation layer 320 and the second inorganic encapsulation layer 322 are used to prevent water and oxygen from entering the display area 20a from the display side and the opening area 20b;
  • the first inorganic encapsulation layer 320 and the second inorganic encapsulation layer 322 can It is made of inorganic insulating materials such as silicon nitride and silicon oxide;
  • the organic encapsulation layer 321 is used to achieve planarization to facilitate the production of the second inorganic encapsulation layer 322.
  • the organic encapsulation layer 321 can be made of acrylic polymer, silicon Base polymer and other materials.
  • first inorganic encapsulation layer 320 and the second inorganic encapsulation layer 322 can be made by chemical vapor deposition process, but are not limited to this; and the organic encapsulation layer 321 can be made by inkjet printing process, but is not limited to this, and can also be made. Use spraying technology and so on.
  • the first barrier dam 28 and the second barrier dam 29 can restrict the flow of the organic encapsulation material and avoid the flow of the organic encapsulation material.
  • the opening area 20b causes the problem of package failure.
  • the opening area 20b in the display panel 2 of the embodiment of the present disclosure is used to assemble devices such as a camera, a sensor, a HOME key, an earpiece, or a speaker after the opening processing. It should be noted that, for the display panel 2 of the embodiment of the present disclosure, the opening area 20b may not be subjected to the opening treatment, and the opening treatment can be performed before the camera and other devices are assembled. In addition, in the display panel 2 of the embodiment of the present disclosure, as shown in FIG. 4, the hole-opening area 20b has been processed with holes. In this case, the display panel 2 can be directly used for subsequent assembly.
  • An embodiment of the present disclosure also provides a display device, which can include the display panel 2 described in the previous embodiment, can perform hole processing on the opening area 20b of the display panel 2, and the display device further includes Functional devices such as a camera, a sensor, a HOME button, an earpiece, or a speaker in the opening area 20b.
  • a display device which can include the display panel 2 described in the previous embodiment, can perform hole processing on the opening area 20b of the display panel 2, and the display device further includes Functional devices such as a camera, a sensor, a HOME button, an earpiece, or a speaker in the opening area 20b.
  • the specific type of the display device is not particularly limited, and the types of display devices commonly used in the field can be used, such as AMOLED display screens, mobile devices such as mobile phones and notebook computers, wearable devices such as watches, VR Any product or component with a display function, such as a device, a digital photo frame, a navigator, etc., can be selected by those skilled in the art according to the specific purpose of the display device, and will not be repeated here.
  • the display device in addition to the display panel 2 and the camera, sensor, HOME button, earpiece or speaker and other devices, the display device also includes other necessary components and components. Take the display as an example, such as the housing, power cord, and driver chip. Etc., those skilled in the art can make corresponding supplements according to the specific usage requirements of the display device, which will not be repeated here.
  • the embodiment of the present disclosure provides a method for manufacturing a display panel, which can manufacture the display panel 2 mentioned in the above-mentioned embodiments, wherein the method for manufacturing the display panel includes: providing a base substrate; on the base substrate A driving circuit layer and a first isolation pillar are formed; wherein, the driving circuit layer includes a thin film transistor and a storage capacitor located in the display area, the thin film transistor includes a gate, a first gate insulating layer formed on the side of the gate away from the base substrate, and The interlayer dielectric layer on the side of the first gate insulating layer away from the base substrate and the source and drain electrodes formed on the side of the interlayer dielectric layer away from the base substrate; the storage capacitor includes a first electrode plate and The second electrode plate is located between the first gate insulating layer and the interlayer dielectric layer; the first isolation pillar is arranged around the opening area, and it includes a first metal layer formed on the side of the first metal layer away from the base substrate The first insulating layer, the second insulating layer formed on
  • the above-mentioned manufacturing method provided by the embodiment of the present disclosure should have the same features and advantages as the display panel 2 provided by the embodiment of the present disclosure. Therefore, the above-mentioned manufacturing method provided by the embodiment of the present disclosure has the characteristics and advantages. Reference can be made to the features and advantages of the display panel 2 described above, which will not be repeated here.
  • the first inorganic insulating material layer can be formed on the base substrate 21 by a method such as deposition.
  • the first inorganic insulating material layer can be formed on the base substrate 21 on the entire surface, and the first inorganic insulating material can be divided
  • the buffer layer 22 located in the display area 20a, the fourth insulating layer 235 of the first isolation pillar 23 and the eighth insulating layer 315 of the second isolation pillar 31 in the isolation area 20c are shown.
  • a patterning process is used to form the semiconductor layer 240 of the thin film transistor 24 in the display area 20a; after that, a second inorganic insulating material layer can be formed by deposition or other methods, and the second inorganic insulating material layer can be adjusted.
  • the surface is formed on the base substrate 21, and it can divide the second gate insulating layer 241 located in the display area 20a, the third insulating layer 234 of the first isolation pillar 23 located in the isolation area 20c, and the second isolation pillar 31. Seven insulation layer 314.
  • a metal film is deposited on the second inorganic insulating material layer; then the metal film is processed by a patterning process to simultaneously form the gate 242 and the gate electrode of the thin film transistor 24 in the display area 20a.
  • the first plate 250 of the storage capacitor 25 and the first metal layer 230 of the first isolation pillar 23 and the fifth metal layer 311 of the second isolation pillar 31 are formed in the isolation region 20c; for example, this patterning process includes exposure and development , Dry etching; Afterwards, a third inorganic insulating material layer can be formed by deposition or other methods. This third inorganic insulating material layer can be formed on the entire surface of the base substrate 21, and it can be divided into the display area 20a.
  • a metal film is deposited on the third inorganic insulating material layer; the metal film is processed by a patterning process to simultaneously form the second plate 251 of the storage capacitor 25 in the display area 20a And the third metal layer 236 of the first isolation pillar 23 and the sixth metal layer 316 of the second isolation pillar 31 are formed in the isolation region 20c; for example, this patterning process includes exposure, development, and dry etching;
  • the fourth inorganic insulating material layer is formed by deposition or other methods.
  • the fourth inorganic insulating material layer can be formed on the entire surface of the base substrate 21, and it can divide the interlayer dielectric layer 244 located in the display area 20a and the isolation area 20c.
  • the interlayer dielectric layer 244 and the first gate insulating layer 243 are processed by a patterning process to expose the via holes of the semiconductor layer 240; after that, a patterning process is used to simultaneously form the display area 20a
  • the source 245 and drain 246 of the thin film transistor 24 and the second metal layer 233 of the first isolation pillar 23 and the fourth metal layer 310 of the second isolation pillar 31 are formed in the isolation region 20c.
  • the source 245 and the drain 246 pass The via holes on the interlayer dielectric layer 244 and the first gate insulating layer 243 are respectively connected to both ends of the semiconductor layer 240.
  • a titanium material layer, an aluminum material layer, and a titanium material layer can be sequentially formed by deposition, sputtering, or evaporation, and then the three material layers can be patterned by the same patterning process to form a constituent source
  • the electrode 245 and the drain electrode 246 have a titanium/aluminum/titanium three-layer metal structure, and an initial second metal layer 233 and an initial fourth metal layer 310 with flush sides are formed at the same time;
  • the initial second metal layer 233 and the initial fourth metal layer 310 are formed to form the second metal layer 233 and the fourth metal layer 310 having a notch 233a on the side surface.
  • a patterning process can be used to simultaneously form a planarization layer located in the display area 20a. 26 and the first barrier portion of the second barrier dam 29 located in the isolation region 20c; after that, the planarization layer 26 is processed by a patterning process to form a via hole exposing the drain electrode 246 of the thin film transistor 24; and then formed by a patterning process
  • the anode 300 of the pixel unit 30 is connected to the drain 246 of the thin film transistor 24 through the via hole on the planarization layer 26.
  • a patterning process is used to simultaneously form the pixel defining layer 27 located in the display area 20a and the second barrier portions of the first barrier dam 28 and the second barrier dam 29 located in the isolation area 20c; this pixel defining layer 27 has exposed The pixel opening of the anode 300; after that, the organic light-emitting material 301 is vapor-deposited on the entire surface to form an organic light-emitting material 301 located at the pixel opening and in contact with the anode 300. It should be understood that the organic light-emitting material 301 is in the first isolation column 23 It is separated from the second isolation column 31.
  • the cathode 302 material can also be vapor-deposited on the entire surface to form the cathode 302 located in the display area 20a.
  • the cathode 302 is in contact with the organic light-emitting material 301. It should be understood that the material of the cathode 302 is It is partitioned at the first isolation column 23 and the second isolation column 31.
  • the first inorganic packaging layer 320 of the packaging film 32 located in the display area 20a and the isolation area 20c is deposited by chemical vapor deposition;
  • the organic encapsulation layer 321 of the encapsulation film 32 in the isolation region 20c is intercepted at the first barrier dam 28; then, chemical vapor deposition is used to deposit the second encapsulation film 32 in the display region 20a and the isolation region 20c.
  • Two inorganic encapsulation layers 322; the first inorganic encapsulation layer 320 and the second inorganic encapsulation layer 322 cover the structures on the display area 20a and the isolation area 20c.
  • the manufacturing method of the display panel 2 in the embodiment of the present disclosure is not limited to the above-mentioned form. Specifically, the above-mentioned manufacturing method can be adjusted according to the required structure of the display panel 2.
  • the opening area 20 b can be formed by laser cutting or mechanical punching, and the opening area 20 b penetrates the base substrate 21.
  • the opening area 20b can be assembled with devices such as a camera, a sensor, a HOME button, an earpiece, or a speaker.

Abstract

一种显示面板（2）及其制作方法、显示装置，显示面板（2），包括显示区（20a）、开孔区（20b）及位于显示区（20a）与开孔区（20b）之间并环绕开孔区（20b）的隔离区（20c）；其中，显示面板（2）包括：衬底基板（21）；驱动电路层，包括形成在衬底基板（21）上并位于显示区（20a）的薄膜晶体管（24）和存储电容（25），薄膜晶体管（24）包括依次形成的栅极（242）、第一栅绝缘层（243）、层间介质层（244）和源漏电极；存储电容（25）包括与栅极（242）同层设置的第一极板（250）和位于第一栅绝缘层（243）与层间介质层（244）之间的第二极板（251）；第一隔离柱（23），形成在衬底基板（21）上并位于隔离区（20c）；第一隔离柱（23）环绕开孔区（20b）设置，且其包括依次形成的第一金属层（230）、第一绝缘层（231）、第二绝缘层（232）及第二金属层（233）；第一金属层（230）与第一极板（250）或第二极板（251）同层设置；第一绝缘层（231）与第一栅绝缘层（243）同层设置；第二绝缘层（232）与层间介质层（244）同层设置，且第二绝缘层（232）中与第一金属层（230）相对的区域相对于其他区域凸出设置以形成第一凸出部，第一凸出部具有坡度角小于90°的斜坡面；第二金属层（233）与源漏电极同层设置，且其朝向显示区（20a）的一侧和/或朝向开孔区（20b）的一侧设置有环绕开孔区（20b）的凹口（233a）。显示面板（2）具有更好的封装效果。

Description

显示面板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及其制作方法、显示装置。
背景技术
近年来移动显示技术发展迅猛，以柔性AMOLED(Active-matrix organic light-emitting diode，主动矩阵有机发光二极体)为代表的新一代显示技术正在得到越来越广泛的应用。AMOLED具有更薄更轻、主动发光(不需要背光源)、无视角问题、高清晰、高亮度、响应快速、能耗低、使用温度范围广、抗震能力强、可实现柔软显示等特点。
同时市场对于高屏占比的显示面板的需求也越来越迫切，现有的“刘海屏”、“水滴屏”等设计逐渐不能满足用户的需求，在此背景下，屏上打孔技术作为一种新的设计应运而生。
柔性AMOLED技术使用的发光材料是对水和氧气非常敏感的有机发光材料，不能暴露在有水氧的环境中，否则很容易发生腐蚀，导致有机发光材料失效，显示异常，因此，隔绝水氧必不可少。
发明内容
本公开实施例提供一种显示面板及其制作方法、显示装置，可避免水汽和氧气从开孔区的开口进入显示区，从而可延长产品的使用寿命及显示效果。
本公开第一方面提供了一种显示面板，包括显示区、开孔区及位于所述显示区与开孔区之间的隔离区，所述隔离区至少部分环绕所述开孔区设置；其中，所述显示面板包括：
衬底基板；
驱动电路层，包括形成在所述衬底基板上并位于所述显示区的薄膜 晶体管和存储电容，所述薄膜晶体管包括栅极、形成在所述栅极远离所述衬底基板一侧的第一栅绝缘层、形成在所述第一栅绝缘层远离所述衬底基板一侧的层间介质层和形成在所述层间介质层远离所述衬底基板一侧的源漏电极；所述存储电容包括与所述栅极同层设置的第一极板和位于所述第一栅绝缘层与所述层间介质层之间的第二极板；
第一隔离柱，形成在所述衬底基板上并位于所述隔离区；所述第一隔离柱环绕所述开孔区设置，且其包括第一金属层、形成在所述第一金属层远离所述衬底基板一侧的第一绝缘层、形成在所述第一绝缘层远离所述衬底基板一侧的第二绝缘层及形成在所述第二绝缘层远离所述衬底基板一侧的第二金属层；所述第一金属层与所述第一极板或所述第二极板同层设置；所述第一绝缘层与所述第一栅绝缘层同层设置；所述第二绝缘层与所述层间介质层同层设置，且所述第二绝缘层包括第一部分、第二部分和连接所述第一部分和所述第二部分的第一倾斜部分，所述第一倾斜部分的坡度角小于90°；所述第二金属层与所述源漏电极同层设置并位于所述第二部分远离所述衬底基板的一侧，且其朝向所述显示区的一侧和/或朝向所述开孔区的一侧设置有环绕所述开孔区的凹口。
在本公开的一种示例性实施例中，所述第二金属层在所述衬底基板上的正投影位于所述第一金属层在所述衬底基板的正投影内。
在本公开的一种示例性实施例中，所述第一金属层与所述第一极板同层设置；
所述第一隔离柱还包括第三金属层，所述第三金属层与所述第二极板同层设置。
在本公开的一种示例性实施例中，所述第二金属层在所述衬底基板上的正投影位于所述第三金属层在所述衬底基板上的正投影内；
所述第三金属层在所述衬底基板上的正投影位于所述第一金属层在所述衬底基板上的正投影内。
在本公开的一种示例性实施例中，在同一截平面内，所述第二金属层的截面宽度与所述第一金属层的截面宽度之比大于或等于0.4，且小于或等于0.7；
在同一截平面内，所述第二金属层的截面宽度与所述第三金属层的 截面宽度之比大于或等于0.5，且小于或等于0.9；
在同一截平面内，所述第三金属层的截面宽度与所述第一金属层的截面宽度之比为大于或等于0.58，且小于1；
其中，所述截平面为在所述第一隔离柱的径向上延伸的平面。
在本公开的一种示例性实施例中，所述第一金属层的截面宽度为6.5μm至8.5μm；
所述第二金属层的截面宽度为3.5μm至4.5μm；
所述第三金属层的截面宽度为5μm至7μm。
在本公开的一种示例性实施例中，所述第一金属层、所述第三金属层的厚度为
Figure PCTCN2020093514-appb-000001
至
Figure PCTCN2020093514-appb-000002
所述第二金属层的厚度为
Figure PCTCN2020093514-appb-000003
至
Figure PCTCN2020093514-appb-000004
在本公开的一种示例性实施例中，所述第一倾斜部分的坡度角为10°至45°。
在本公开的一种示例性实施例中，所述衬底基板与所述驱动电路层之间还设置有缓冲层；
所述薄膜晶体管还包括依次形成在所述缓冲层上的半导体层和第二栅绝缘层，所述第二栅绝缘层位于所述栅极与所述半导体层之间。
在本公开的一种示例性实施例中，所述第一隔离柱还包括第三绝缘层和第四绝缘层，所述第三绝缘层与所述第二栅绝缘层同层设置，所述第四绝缘层与所述缓冲层同层设置。
在本公开的一种示例性实施例中，所述显示面板还包括：
平坦化层，位于所述显示区，并覆盖所述薄膜晶体管；
像素界定层，位于所述显示区，并形成在所述平坦化层上，以用于界定多个像素单元；
第一阻隔坝，位于所述隔离区，并环绕所述开孔区设置，所述第一阻隔坝与所述像素界定层同层设置；
第二阻隔坝，位于所述隔离区，并环绕所述开孔区设置；所述第二阻隔坝位于所述第一阻隔坝靠近所述开孔区的一侧，并包括与所述平坦化层同层设置的第一阻隔部和与所述像素界定层同层设置的第二阻隔部；所述第二阻隔坝的高度大于所述第一阻隔坝的高度。
在本公开的一种示例性实施例中，所述显示面板还包括形成在所述 衬底基板上并位于所述隔离区的第二隔离柱，所述第二隔离柱环绕所述开孔区设置，且所述第二隔离柱至少包括第四金属层，所述第四金属层与所述第二金属层的结构相同且同层设置；
其中，所述第一阻隔坝和所述第二阻隔坝位于所述第一隔离柱和所述第二隔离柱之间。
在本公开的一种示例性实施例中，所述第二隔离柱还包括第五金属层、第五绝缘层及第六绝缘层，所述第五金属层与所述第一极板或所述第二极板同层设置；所述第五绝缘层与所述第一栅绝缘层同层设置；所述第六绝缘层与所述层间介质层同层设置；
其中，所述第六绝缘层包括第三部分、第四部分和连接所述第三部分和所述第四部分的第二倾斜部分，所述第二倾斜部分的坡度角与所述第一倾斜部分的坡度角相同，且所述第四金属层位于所述第四部分远离所述衬底基板的一侧。
在本公开的一种示例性实施例中，所述第五金属层与所述第一极板同层设置；
所述第二隔离柱还包括第六金属层，所述第六金属层与所述第二极板同层设置。
在本公开的一种示例性实施例中，所述第二隔离柱还包括第七绝缘层和第八绝缘层，所述第七绝缘层与所述第二栅绝缘层同层设置，所述第八绝缘层与所述缓冲层同层设置。
在本公开的一种示例性实施例中，所述第二隔离柱还包括位于所述第四金属层靠近所述衬底基板上的绝缘叠层，所述绝缘叠层与所述缓冲层、所述第二栅绝缘层、所述第一栅绝缘层及所述层间介质层同层设置，并与所述缓冲层、所述第二栅绝缘层、所述第一栅绝缘层及所述层间介质层相互断开；其中，所述绝缘叠层具有坡度角为50°至70°的斜坡面。
在本公开的一种示例性实施例中，所述第一隔离柱和所述第二隔离柱中的一者位于所述第一阻隔坝靠近所述显示区的一侧，另一者位于所述第二阻隔坝靠近所述开孔区的一侧；
其中，所述第一隔离柱设置有多个，和/或所述第二隔离柱设置有多个。
在本公开的一种示例性实施例中，所述显示面板还包括封装薄膜，所述封装薄膜至少包括第一无机封装层，所述第一无机封装层位于所述显示区和所述隔离区，并覆盖所述驱动电路层和所述第一隔离柱。
本公开第二方面提供了一种显示装置，其特征在于，包括上述任一项所述的显示面板。
本公开第二方面提供了一种显示面板的制作方法，所述显示面板包括显示区、开孔区及位于所述显示区与开孔区之间的隔离区，所述隔离区至少部分环绕所述开孔区设置；其中，所述制作方法包括：
提供一衬底基板；
在所述衬底基板上形成驱动电路层和第一隔离柱；其中，
所述驱动电路层包括位于所述显示区的薄膜晶体管和存储电容，所述薄膜晶体管包括栅极、形成在所述栅极远离所述衬底基板一侧的第一栅绝缘层、形成在所述第一栅绝缘层远离所述衬底基板一侧的层间介质层和形成在所述层间介质层远离所述衬底基板一侧的源漏电极；所述存储电容包括与所述栅极同层设置的第一极板和位于所述第一栅绝缘层与所述层间介质层之间的第二极板；
所述第一隔离柱环绕所述开孔区设置，且其包括第一金属层、形成在所述第一金属层远离所述衬底基板一侧的第一绝缘层、形成在所述第一绝缘层远离所述衬底基板一侧的第二绝缘层及形成在所述第二绝缘层远离所述衬底基板一侧的第二金属层；所述第一金属层与所述第一极板或所述第二极板同层设置；所述第一绝缘层与所述第一栅绝缘层同层设置；所述第二绝缘层与所述层间介质层同层设置，且所述第二绝缘层包括第一部分、第二部分和连接所述第一部分和所述第二部分的第一倾斜部分，所述第一倾斜部分的坡度角小于90°；所述第二金属层与所述源漏电极同层设置并位于所述第二部分远离所述衬底基板的一侧，且其朝向所述显示区的一侧和/或朝向所述开孔区的一侧设置有环绕所述开孔区的凹口。
在本公开的一种示例性实施例中，
所述第一金属层与所述第一极板同层设置；
所述第一隔离柱还包括第三金属层，所述第三金属层与所述第二极 板同层设置。
在本公开的一种示例性实施例中，还包括：
在所述衬底基板上形成位于所述隔离区的第二隔离柱；所述第二隔离柱环绕所述开孔区设置，且所述第二隔离柱至少包括第四金属层，所述第四金属层与所述第二金属层的结构相同且同层设置；
在所述显示区形成覆盖所述薄膜晶体管的平坦化层；
在所述显示区形成位于所述平坦化层上的像素界定层，以用于界定多个像素单元；
在所述隔离区形成第一阻隔坝和第二阻隔坝，所述第一阻隔坝环绕所述开孔区设置，且所述第一阻隔坝与所述像素界定层同层设置；所述第二阻隔坝环绕所述开孔区设置，并位于所述第一阻隔坝靠近所述开孔区的一侧，所述第二阻隔坝与所述平坦化层和所述像素界定层同层设置；且所述第二阻隔坝的高度大于所述第一阻隔坝的高度；
其中，所述第一阻隔坝和所述第二阻隔坝位于所述第一隔离柱和所述第二隔离柱之间。
在本公开的一种示例性实施例中，所述第二隔离柱的结构与所述第一隔离柱的结构相同。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为本公开一实施例所示的显示面板中位于显示区与隔离区之间的部分的结构示意图；
图2为图1中所示的A部的放大结构示意图；
图3为图2中所示的隔离柱的结构示意图；
图4为本公开另一实施例所描述的显示面板的结构示意图；
图5为图4中所示的一实施例中显示面板沿B-B线的截面示意图；
图6为图4中所示的一实施例中显示面板沿C-C线的截面示意图；
图7为图4中所示的另一实施例中显示面板沿C-C线的截面示意图；
图8为图4中所示的又一实施例中显示面板沿C-C线的截面示意图；
图9为图6中所示的显示面板中显示区的第一隔离柱或第二隔离柱的结构示意图；
图10为图7中所示的显示面板中显示区的第一隔离柱或第二隔离柱的结构示意图；
图11为图8中所示的显示面板中显示区的第一隔离柱或第二隔离柱的结构示意图。
附图标记：
10、显示区；11、开孔区；12、隔离柱；120、ILD+GI+buffer层；121、SD金属层；13、隔离槽；14、衬底；15、有机发光材料；16、阴极层；17、无机封装层；
2、显示面板；20a、显示区；20b、开孔区；20c、隔离区；21、衬底基板；22、缓冲层；23、第一隔离柱；230、第一金属层；231、第一绝缘层；232、第二绝缘层；232a、第一部分；232b、第二部分；232c、第一倾斜部分；233、第二金属层；233a、凹口；234、第三绝缘层；235、第四绝缘层；236、第三金属层；24、薄膜晶体管；240、半导体层；241、第二栅绝缘层；242、栅极；243、第一栅绝缘层；244、层间介质层；245、源极；246、漏极；25、存储电容；250、第一极板；251、第二极板；26、平坦化层；27、像素界定层；28、第一阻隔坝；29、第二阻隔坝；290、第一阻隔部；291、第二阻隔部；30、像素单元；300、阳极；301、有机发光材料；302、阴极；31、第二隔离柱；310、第四金属层；311、第五金属层；312、第五绝缘层；313、第六绝缘层；313a、第三部分；313b、第四部分；313c、 第二倾斜部分；314、第七绝缘层；315、第八绝缘层；316、第六金属层；32、封装薄膜；320、第一无机封装层；321、有机封装层；322、第二无机封装层。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成，并且位于同一膜层之上并与该膜层直接接触。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的 涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
在本公开一实施例中，如图1所示，采用在显示区10和开孔区11之间设置隔离柱12、隔离槽13等结构以阻断有机发光材料15，从而起到隔绝水氧通路的作用，也可起到阻断阴极层16的作用。其中，隔离柱12的制作方法为：在衬底14上分别沉积缓冲层(buffer)，栅极绝缘层(Gate Insulator，简称：GI)以及层间介质层(Interlayer Dielectric，简称：ILD)，然后通过对ILD+GI+buffer层120曝光、显影、EBA(Etch Bending A)/EBB(Etch Bending B)刻蚀得到特定的图案，然后在特定的图案上形成SD(源漏)金属层121，并对SD金属层121进行刻蚀，使其形成底切(undercut)结构，能够隔断有机发光材料15；具体如图2至图3所示，这种采用了EBA/EBB刻蚀方式制作的隔离柱12可简称为EBA/EBB隔离柱，此EBA/EBB隔离柱可以和bending(弯折)工艺共用mask(掩膜板)。
此外，如图3所示，EBA/EBB隔离柱有两个特点：一是形成的坡度角α1大，二是形成的段差h1大；这样使得采用化学气相沉积(Chemical Vapor Deposition，简称：CVD)技术形成的无机封装层17在ILD+GI+buffer层120斜坡处沉积得十分陡峭，不利于释放外界应力，在受到外界应力作用下容易发生裂纹crack，导致封装失效，那么水和氧气借此侵入，将会使器件显示异常。
为改善上述问题，如图4所示，本公开实施例又提供了一种显示面板2，此显示面板2可为OLED显示。且显示面板2可包括显示区20a、开孔区20b及位于显示区20a与开孔区20b之间的隔离区20c，此隔离区20c至少部分环绕开孔区20b设置。
下面结合附图对本公开实施例的显示面板2进行详细说明。
如图4至图11所示，显示面板2可包括衬底基板21、驱动电路层及第一隔离柱23；其中：
当显示面板2为柔性面板时，所提供的衬底基板21可以为聚酰亚胺(PI)等柔性基板，当显示面板2为刚性基板时，衬底基板21 可以为玻璃、石英等刚性基板。
需要说明的是，为了便于后续在显示面板2的各区域加工所需部件，可在衬底基板21先定义出各区域，举例而言，可先在衬底基板21上划分出显示区20a、隔离区20c和开孔区20b。
如图5所示，驱动电路层形成在衬底基板21上。且该驱动电路层可包括形成在衬底基板21上并位于显示区20a的薄膜晶体管24和存储电容25。
详细说明，如图5所示，薄膜晶体管24可包括依次形成的栅极242、第一栅绝缘层243、层间介质层244和源漏电极；即：可先在衬底基板21上形成栅极242；之后，在栅极242远离衬底基板21的一侧形成第一栅绝缘层243，在第一栅绝缘层243远离衬底基板21的一侧形成层间介质层，在层间介质层244远离衬底基板21的一侧形成源漏电极；且薄膜晶体管24还可包括半导体层240，此半导体层240可位于栅极242靠近衬底基板21的一侧，以使该薄膜晶体管24为顶栅型；应当理解的是，在薄膜晶体管24为顶栅型时，该薄膜晶体管24还可包括第二栅绝缘层241，该第二栅绝缘层241位于栅极242与半导体层240之间。
但不限于此，半导体层240也可位于栅极242远离衬底基板21的一侧并位于第一栅绝缘层243与层间介质层244之间，以使得薄膜晶体管24为底栅型。应当理解的是，本公开实施例的薄膜晶体管24不限于图中所示的顶栅型，也可为底栅型。
需要说明的是，如图5所示，前述提到的源漏电极包括同层设置的源极245和漏极246，该源极245和漏极246可通过层间介质层244、第一栅绝缘层243上的过孔与半导体层240的两端分别连接。
如图5所示，存储电容25包括第一极板250和第二极板251，此第一极板250与栅极242同层设置，第二极板251位于第一栅绝缘层243与层间介质层244之间的第二极板251。
举例而言，本公开实施例中提到的第一栅绝缘层243、第二栅绝缘层241和层间介质层244可采用无机绝缘材料制作而成，例如：氧 化硅、氮化硅等无机绝缘材料；半导体层240可以采用多晶硅和金属氧化物等材料制作而成；栅极242、第一极板250和第二极板251可采用铝、钛、钴等金属或者合金材料制作而成；源极245和漏极246可采用金属材料或者合金材料制作而成，例如由钼、铝及钛等形成的金属单层或多层结构；其中，在源极245和漏极246为多层结构时，该多层结构可为多金属层叠层，例如钛、铝、钛三层金属叠层(Ti/Al/Ti)等。
如图5所示，衬底基板21与驱动电路层之间还可设置有缓冲层22，缓冲层22可为氮化硅、氧化硅等材料制作而成，在达到阻水氧和阻隔碱性离子效果的同时，还可对衬底基板21上的其他结构起到保护作用；需要说明的是，衬底基板21与驱动电路层之间不仅可设置有缓冲层22，还可设置有其他层，视具体情况而定。其中，在薄膜晶体管24为顶栅型时，其半导体层240可位于缓冲层22上。
如图6至图11所示，第一隔离柱23形成在衬底基板21上并位于隔离区20c；第一隔离柱23环绕开孔区20b设置，且其包括依次形成的第一金属层230、第一绝缘层231、第二绝缘层232及第二金属层233，即：可先在衬底基板21上形成第一金属层230，之后，在第一金属层230远离衬底基板21的一侧形成第一绝缘层231，在第一绝缘层231远离衬底基板21的一侧形成第二绝缘层232，在第二绝缘层232远离衬底基板21的一侧形成第二金属层233。
其中，第一金属层230与第一极板250或第二极板251同层设置；第一绝缘层231与第一栅绝缘层243同层设置；第二绝缘层232与层间介质层244同层设置，且第二绝缘层232包括第一部分232a、第二部分232b和连接第一部分232a和第二部分232b的第一倾斜部分232c，如图9至图11所示，该第一倾斜部分232c的坡度角α2小于90°；第二金属层233与源漏电极同层设置并位于第二部分232b远离衬底基板21的一侧，且其朝向显示区20a的一侧和/或朝向开孔区20b的一侧设置有环绕开孔区20b的凹口233a；其中，通过第一倾斜部分232c与第二金属层233相配合可隔断有机发光材料，从而起到隔绝水氧通路的作用。应当理解的是，如图6至图8所示，该第一隔 离柱23不仅可隔断有机发光材料301，还可隔断其他材料，例如，阴极302等等。
在本公开的实施例中，通过在第一隔离柱23的底部增加与第一极板250或第二极板251同层设置的第一金属层230，这样在沉积第二绝缘层232的过程中，使得第二绝缘层232中与第一金属层230相对的区域相对于第二绝缘层232的其他区域被垫高，以自然形成有小于90°坡度角α2；由于第二绝缘层232自然形成具有坡度角α2的第一倾斜部分232c，因此，本公开实施例在制作第一隔离柱23的过程中，相比于在制作图1至图3中所示的EBA/EBB隔离柱12的过程中，可省略“对ILD+GI+buffer层120曝光、显影、EBA(Etch Bending A)/EBB(Etch Bending B)刻蚀得到特定的图案”这一步骤，即：在实现阻断有机发光材料的同时，可省略一步掩膜工艺，从而可降低成本。
此外，由于本公开实施例是通过增加第一金属层230以使第二绝缘层232上与第一金属层230相对的部位被垫高，从而形成具有坡度角α2的第一倾斜部分232c；因此，相比于对图1至图3中所示的ILD+GI+buffer层120曝光、显影、EBA(Etch Bending A)/EBB(Etch Bending B)刻蚀而形成的坡度角α1，本公开实施例的坡度角α2较小，且坡度角α2处形成的段差h2也比较小，具体参考图9至图11所示，本公开实施例的坡度角α2及段差h2分别小于图3中所示的EBA/EBB隔离柱12中的坡度角α1及段差h1。
举例而言，本公开实施例中第一隔离柱23的第一倾斜部分232c的坡度角α2可为10°至45°，比如：10°、20°、30°、45°等等，而图3所示的EBA/EBB隔离柱12的ILD+GI+buffer层120处斜坡面的坡度角α1可为50°至70°，比如：50°、60°、70°等等。
其中，由于本公开实施例中第一隔离柱23的第一倾斜部分232c的坡度角α2小于EBA/EBB隔离柱12的斜坡处的坡度角α1，因此，在后续沉积无机封装层时，本公开实施例的无机封装层(如图6至图8中所示的第一无机封装层320)在第一隔离柱23的第一倾斜部分232c处相比于如图1和图2所示的无机封装层17在EBA/EBB隔离 柱12的斜坡处沉积的得更加平滑，以便有助于释放外界应力，从而使无机封装层在受到外界应力的情况下不易发生裂纹，继而进一步阻隔水和氧气侵入，保证显示效果。
需要说明的是，本公开实施例的第一绝缘层231和第二绝缘层232可为一体结构，只要能形成第一倾斜部分232c即可。
在一些实施例中，如图9至图11所示，第一隔离柱23还包括第三绝缘层234和第四绝缘层235，此第三绝缘层234可与第二栅绝缘层241同层设置，此第四绝缘层235可与缓冲层22同层设置。
在一些实施例中，如图6和图9所示，第一隔离柱23的第一金属层230可与第一极板250同层设置。可选地，第一隔离柱23中第二金属层233在衬底基板21上的正投影位于第一金属层230在衬底基板21的正投影内，这样可使得位于第一隔离柱23处的无机封装层更加有助于释放外界应力，避免无机封装层在受到外界应力的情况下发生裂纹。需要说明的是，第一金属层230在制作过程中也可形成一定角度的坡面。
进一步地，在同一截平面内，第二金属层233的截面宽度与第一金属层230的截面宽度之比大于或等于0.4，且小于或等于0.7。举例而言，第一金属层230的截面宽度可为6.5μm至8.5μm，比如：6.5μm、7μm、7.5μm、8μm、8.5μm等等；第二金属层233的截面宽度可为3.5μm至4.5μm，比如：3.5μm、4μm、4.5μm等等。
需要说明的是，本公开实施例的段差h2可为第一金属层230的厚度。此外，本公开实施例中提到的截平面为在第一隔离柱23的径向上延伸的平面；而截面宽度可为截面的最大宽度，但不限于此，截面其他位置的宽度也可在上述取值范围内。
在一些实施例中，如图7和图10所示，第一隔离柱23的第一金属层230可与第二极板251同层设置。可选地，第一隔离柱23中第二金属层233在衬底基板21上的正投影位于第一金属层230在衬底基板21的正投影内，这样可使得位于第一隔离柱23处的无机封装层更加有助于释放外界应力，避免无机封装层在受到外界应力的情况下 发生裂纹。需要说明的是，第一金属层230在制作过程中也可形成一定角度的坡面。
进一步地，在同一截平面内，第二金属层233的截面宽度与第一金属层230的截面宽度之比大于或等于0.4，且小于或等于0.7。举例而言，第一金属层230的截面宽度可为6.5μm至8.5μm，比如：6.5μm、7μm、7.5μm、8μm、8.5μm等等；第二金属层233的截面宽度可为3.5μm至4.5μm，比如：3.5μm、4μm、4.5μm等等。
需要说明的是，本公开实施例的段差h2可为第一金属层230的厚度。此外，本公开实施例中提到的截平面为在第一隔离柱23的径向上延伸的平面；而截面宽度可为截面的最大宽度，但不限于此，截面其他位置的宽度也可在上述取值范围内。
在一些实施例中，如图8和图11所示，第一隔离柱23的第一金属层230可与第一极板250同层设置，且第一隔离柱23还可包括第三金属层236，第三金属层236与第二极板251同层设置。可选地，第二金属层233在衬底基板21上的正投影位于第三金属层236在衬底基板21上的正投影内；第三金属层236在衬底基板21上的正投影位于第一金属层230在衬底基板21上的正投影内，这样可使得位于第一隔离柱23处的无机封装层更加有助于释放外界应力，避免无机封装层在受到外界应力的情况下发生裂纹。需要说明的是，第一金属层230、第二金属层233在制作过程中也可形成一定角度的坡面。
进一步地，在同一截平面内，第二金属层233的截面宽度与第一金属层230的截面宽度之比大于或等于0.4，且小于或等于0.7；第二金属层233的截面宽度与第三金属层236的截面宽度之比大于或等于0.5，且小于或等于0.9；第三金属层236的截面宽度与第一金属层230的截面宽度之比为大于或等于0.58，且小于1。举例而言，第一金属层230的截面宽度可为6.5μm至8.5μm，比如：6.5μm、7μm、7.5μm、8μm、8.5μm等等；第二金属层233的截面宽度可为3.5μm至4.5μm，比如：3.5μm、4μm、4.5μm等等；第三金属层236的最大宽度为5μm至7μm，比如：5μm、5.5μm、6μm、6.5μm、7μm等等。
需要说明的是，本公开实施例的段差h2可为第一金属层230和第三金属层236的厚度之和。此外，本公开实施例中提到的截平面为在第一隔离柱23的径向上延伸的平面；而截面宽度可为截面的最大宽度，但不限于此，截面其他位置的宽度也可在上述取值范围内。
应当理解的是，前述实施例中提到的第一隔离柱23中的第一金属层230、第二金属层233、第三金属层236一般采用刻蚀工艺制作而成，这样使得制作出的第一金属层230、第二金属层233、第三金属层236通常具有一定的坡度角，具体地，第一金属层230、第二金属层233、第三金属层236中远离衬底基板21的表面在衬底基板21上的正投影位于其靠近衬底基板21的表面在衬底基板21上的正投影；基于此，为了保证无机封装层能够进一步释放外界应力，在本公开的实施例中，第一隔离柱23中第二金属层233的最大截面宽度可小于第一金属层230的最小截面宽度；第二金属层233的最大截面宽度可小于第三金属层236的最小截面宽度；第三金属层236的最大宽度可小于第一金属层230的最小截面宽度。
此外，在本公开实施例的第一隔离柱23中第一绝缘层231、第二绝缘层232、第三绝缘层234、第四绝缘层235设计为与相关技术的EBA/EBB隔离柱中GI1层、ILD层、GI2层、buffer层的厚度相同，且在第一隔离柱23中具有坡度角α2的第二绝缘层232的最大截面宽度、最小截面宽度设计为与EBA/EBB隔离柱中ILD+GI+buffer层120的最大截面宽度、最小截面宽度相同时，主要影响本公开实施例中第一隔离柱23的坡度角α2的因素为第一金属层230、第二金属层233的厚度；其中，为了使得本公开实施例的如图9至图11所示的第一隔离柱23的坡度角α2小于图3所示的EBA/EBB隔离柱12的坡度角α1，本公开实施例的第一金属层230、第三金属层236的厚度可为
Figure PCTCN2020093514-appb-000005
至
Figure PCTCN2020093514-appb-000006
比如：
Figure PCTCN2020093514-appb-000007
等等，应当理解的是，此第一金属层230的厚度、第三金属层236的厚度可相同，也可不同，视具体情况而定。
其中，第一隔离柱23中第二金属层233的厚度可为
Figure PCTCN2020093514-appb-000008
至
Figure PCTCN2020093514-appb-000009
比如：
Figure PCTCN2020093514-appb-000010
等等。为了 使得第二金属层233能够更好地隔断有机发光材料，第二金属层233上凹口233a的厚度与第二金属层233的厚度之比可为0.5至0.8，比如：0.5、0.6、0.7、0.8等等。
需要说明的是，在第二金属层233为Ti/Al/Ti多层结构时，为了制作出凹口233a，可采用特定的刻蚀液对Ti/Al/Ti多层结构进行刻蚀，该刻蚀液仅对Al层具有刻蚀效果，或对Al层的刻蚀速率大于对Ti层的刻蚀速率，从而可使第二金属层233上形成凹口233a，使得第二金属层233具有隔断采用蒸镀方式形成膜层(例如：有机发光材料301、阴极302等等)。应当理解的是，第二金属层233的结构、材料不限于上述内容，视具体情况而定。
在一实施例中，第二金属层233的截平面呈“工字形”，即：第二金属层233朝向显示区20a的一侧和朝向开孔区20b的一侧均设置有环绕开孔区20b的凹口233a，以进一步隔断有机发光材料301、阴极302等。
此外，第一绝缘层231的厚度可为
Figure PCTCN2020093514-appb-000011
至
Figure PCTCN2020093514-appb-000012
比如：
Figure PCTCN2020093514-appb-000013
等等；第二绝缘层232的厚度可为
Figure PCTCN2020093514-appb-000014
至
Figure PCTCN2020093514-appb-000015
比如：
Figure PCTCN2020093514-appb-000016
等等；第三绝缘层234的厚度可为
Figure PCTCN2020093514-appb-000017
至
Figure PCTCN2020093514-appb-000018
比如：
Figure PCTCN2020093514-appb-000019
等等；第四绝缘层235的厚度可为
Figure PCTCN2020093514-appb-000020
至
Figure PCTCN2020093514-appb-000021
比如：
Figure PCTCN2020093514-appb-000022
Figure PCTCN2020093514-appb-000023
等等。
需要说明的是，本公开实施例中提到的同层设置的各结构其厚度可相同，也可不相同。
此外，需要说明的是，本公开实施例中所提到的截面宽度为在图6至图8中X方向上的尺寸，厚度为在图6至图8中Y方向上的尺寸。
基于上述内容，仅通过增加与第一极板250同层设置的金属层来形成坡度角的隔离柱可定义为Gate1隔离柱；仅通过增加与第二极板251同层设置的金属层来形成坡度角的隔离柱可定义为Gate2隔离柱；通过增加与第一极板250和第二极板251同层设置的金属层来形成坡度角的隔离柱可定义为Gate1+Gate2隔离柱；也就是说，本公开实施 例的第一隔离柱23可为Gate1隔离柱、Gate2隔离柱或Gate1+Gate2隔离柱。
在一些实施例中，如图5至图8所示，显示面板2还可包括位于显示区20a的平坦化层26和像素界定层27及位于隔离区20c的第一阻隔坝28和第二阻隔坝29；其中，平坦化层26覆盖薄膜晶体管24，像素界定层27形成在平坦化层26上，即：在薄膜晶体管24以及存储电容25的各膜层形成完成后，依次形成平坦化层26和像素界定层27；此像素界定层27用于界定多个像素单元30。第一阻隔坝28和第二阻隔坝29均环绕开孔区20b设置，且第二阻隔坝29位于第一阻隔坝28靠近开孔区20b的一侧，其中，第一阻隔坝28与像素界定层27同层设置，第二阻隔坝29包括与平坦化层26同层设置的第一阻隔部290和与像素界定层27同层设置的第二阻隔部291；且第二阻隔坝29的高度大于第一阻隔坝28的高度，此第一阻隔坝28和第二阻隔坝29用于对封装薄膜中的有机封装层321材料流动形成限制，避免有机封装层321材料流动至开孔区20b引起封装失效的问题。
应当理解的是，在本公开的实施例中，也可单独设置第一阻隔坝28或第二阻隔坝29，且第一阻隔坝28、第二阻隔坝29的数量不限于一个，也可设置更多。此外，第一阻隔坝28和第二阻隔坝29的结构不限于此图6至图8中所示的结构，视具体情况而定。
其中，平坦化层26和像素界定层27可采用有机绝缘材料制作而成，比如：聚酰亚胺、环氧树脂等有机绝缘材料。此外，显示区还可包括无机保护层(PVX)，图中未示出，此无机保护层可形成在源漏电极远离衬底基板21的一侧，并位于平坦化层26靠近衬底基板21的一侧，即：无机保护层可位于源漏电极与平坦化层之间，该无机保护层包覆源漏电极，以对源漏电极起到保护作用。举例而言，无机保护层可采用氮化硅、氧化硅等无机绝缘材料制作而成。应当理解的是，隔离区20c处不设置有此无机保护层对隔离柱进行保护。
在一些实施例中，如图5所示，显示面板2还可包括位于显示区20a的像素单元30，该像素单元30可包括阳极300、有机发光材料 301和阴极302，此阳极300可先于像素界定层27形成在平坦化层26上并通过平坦化层26上的过孔与薄膜晶体管24的漏极246连接；像素界定层27与阳极300对应的部位形成有像素开口，此像素开口暴露出至少部分阳极300；在形成完像素界定层27后，可整面蒸镀有机发光材料301，此有机发光材料301可在第一隔离柱23处隔断，如图6至图8中所示；其中，有机发光材料301中位于像素开口中并与阳极300接触；在整面蒸镀完有机发光材料301之后，还可整面蒸镀阴极302材料，此阴极302材料也可在第一隔离柱23处隔断，如图6至图8中所示。
需要说明的是，像素单元30还可包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层，图中未示出，在这些层采用蒸镀方式形成在显示面板2中时，均可在第一隔离柱23处隔断。
举例而言，阳极300可为ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等材料制作而成；有机发光材料301可包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等；阴极302可为锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料制作而成。
在一些实施例中，如图6至图8所示，显示面板2还可包括形成在衬底基板21上并位于隔离区20c的第二隔离柱31，此第二隔离柱31环绕开孔区20b设置。如图9至图11所示，且第二隔离柱31至少包括第四金属层310，第四金属层310与第二金属层233的结构相同且同层设置；其中，第一阻隔坝28和第二阻隔坝29位于第一隔离柱23和第二隔离柱31之间；也就是说，第一隔离柱23和第二隔离柱31中的一者位于第一阻隔坝28靠近显示区20a的一侧，另一者位于第二阻隔坝29靠近开孔区20b的一侧。
其中，位于第一阻隔坝28靠近显示区20a一侧的隔离柱可定义为内隔离柱，位于第二阻隔坝29靠近开孔区20b一侧的隔离柱可定义为外隔离柱，即：第一隔离柱23和第二隔离柱31中的一者可定义为内隔离柱，另一者可定义为外隔离柱。
其中，虽然图6至图8中仅示出了第一隔离柱23为内隔离柱，第二隔离柱31为外隔离柱的情况，但本公开的实施例不限于此，也可第一隔离柱23为外隔离柱，第二隔离柱31为内隔离柱。
此外，本公开实施例中提到的第一隔离柱23可设置有多个，和/或第二隔离柱31设置有多个；也就是说，内隔离柱、外隔离柱均可设置多个。需要说明的是，如图6至图8所示，多个内隔离柱的结构可相同，但不限于此，也可不相同；如图6至图8所示，多个外隔离柱的结构可相同，但不限于此，也可不相同。
在本公开的实施例中，通过设置内隔离柱和外隔离柱进一步阻断有机发光材料301，从而进一步阻隔水和氧气侵入，保证显示效果。
在一些实施例中，第二隔离柱31可为Gate1隔离柱、Gate2隔离柱、Gate1+Gate2隔离柱或EBA/EBB隔离柱中的一种；具体地：
如图6和图9所示，第二隔离柱31可为Gate1隔离柱，此第二隔离柱31除了第四金属层310之外，还可包括第五金属层311、第五绝缘层312及第六绝缘层313，第五金属层311与第一极板250同层设置；第五绝缘层312与第一栅绝缘层243同层设置；第六绝缘层313与层间介质层244同层设置；其中，第六绝缘层313包括第三部分313a、第四部分313b和连接第三部分313a和第四部分313b的第二倾斜部分313c，第二倾斜部分313c的坡度角与第一倾斜部分232c的坡度角相同，且第四金属层310位于第四部分313b远离衬底基板21的一侧。可选地，第二隔离柱31还可包括第七绝缘层314和第八绝缘层315，第七绝缘层314与第二栅绝缘层241同层设置，第八绝缘层315与缓冲层22同层设置。
如图7和图10所示，第二隔离柱31可为Gate2隔离柱，此第二隔离柱31除了第四金属层310之外，还可包括第五金属层311、第五绝缘层312及第六绝缘层313，第五金属层311与第二极板251同层设置；第五绝缘层312与第一栅绝缘层243同层设置；第六绝缘层313与层间介质层244同层设置；其中，第六绝缘层313包括第三部分313a、第四部分313b和连接第三部分313a和第四部分313b的第二倾 斜部分313c，第二倾斜部分313c的坡度角与第一倾斜部分232c的坡度角相同，且第四金属层310位于第四部分313b远离衬底基板21的一侧。可选地，第二隔离柱31还可包括第七绝缘层314和第八绝缘层315，第七绝缘层314与第二栅绝缘层241同层设置，第八绝缘层315与缓冲层22同层设置。
如图8和图11所示，第二隔离柱31可为Gate1+Gate2隔离柱，此第二隔离柱31除了第四金属层310之外，还可包括第五金属层311、第五绝缘层312、第六金属层316及第六绝缘层313，第五金属层311与第一极板250同层设置；第五绝缘层312与第一栅绝缘层243同层设置；第六金属层316与第二极板251同层设置；第六绝缘层313与层间介质层244同层设置；其中，第六绝缘层313包括第三部分313a、第四部分313b和连接第三部分313a和第四部分313b的第二倾斜部分313c，第二倾斜部分313c的坡度角与第一倾斜部分232c的坡度角相同，且第四金属层310位于第四部分313b远离衬底基板21的一侧。可选地，第二隔离柱31还可包括第七绝缘层314和第八绝缘层315，第七绝缘层314与第二栅绝缘层241同层设置，第八绝缘层315与缓冲层22同层设置。
第二隔离柱31还包括位于第四金属层310靠近衬底基板21上的绝缘叠层，此绝缘叠层与缓冲层22、第二栅绝缘层241、第一栅绝缘层243及层间介质层244同层设置，并与缓冲层22、第二栅绝缘层241、第一栅绝缘层243及层间介质层244相互断开；其中，绝缘叠层具有坡度角为50°至70°的斜坡面；此第二隔离柱31可为图2和图3中所示的EBA/EBB隔离柱。
在一些实施例中，通过将第一隔离柱23设计为Gate1隔离柱、Gate2隔离柱、Gate1+Gate2隔离柱中的至少一种、将第二隔离柱31设计为Gate1隔离柱、Gate2隔离柱、Gate1+Gate2隔离柱中的至少一种，这样设计在防止隔离柱的斜坡处发生裂纹的同时，还可防止开孔区20b边缘处裂纹向显示区20a内延伸，从而可进一步保证封装效果。
基于前述可知，第二隔离柱31的结构可与第一隔离柱23的结构 相同或不同，视具体情况而定。其中，图6至图8中仅示出了第一隔离柱23、第二隔离柱31的结构相同的情况，但本公开的实施例不限于此。
此外，在第一隔离柱23为Gate1隔离柱、Gate2隔离柱、Gate1+Gate2隔离柱中的至少一种，且第二隔离柱31为Gate1隔离柱、Gate2隔离柱、Gate1+Gate2隔离柱中的至少一种时，第一绝缘层231、第五绝缘层312可与第一栅绝缘层243连接；第二绝缘层232、第六绝缘层313可与层间介质层244连接；第三绝缘层234、第七绝缘层314可与第二栅绝缘层241连接，第四绝缘层235、第八绝缘层315可与缓冲层22连接设置。
具体地，本公开实施例的显示面板2中内隔离柱和外隔离柱的组合方式可参见下表1所示。
表1
方案编号 内隔离柱 外隔离柱
1 Gate1隔离柱 Gate1隔离柱
2 Gate1隔离柱 Gate2隔离柱
3 Gate1隔离柱 Gate1+Gate2隔离柱
4 Gate2隔离柱 Gate1隔离柱
5 Gate2隔离柱 Gate2隔离柱
6 Gate2隔离柱 Gate1+Gate2隔离柱
7 Gate1+Gate2隔离柱 Gate1隔离柱
8 Gate1+Gate2隔离柱 Gate2隔离柱
9 Gate1+Gate2隔离柱 Gate1+Gate2隔离柱
10 EBA/EBB隔离柱 Gate1隔离柱
11 EBA/EBB隔离柱 Gate2隔离柱
12 EBA/EBB隔离柱 Gate1+Gate2隔离柱
13 Gate1隔离柱 EBA/EBB隔离柱
14 Gate2隔离柱 EBA/EBB隔离柱
15 Gate1+Gate2隔离柱 EBA/EBB隔离柱
需要说明的是，本公开实施例中内隔离柱和外隔离柱不限于上述组合方案设计，例如：内隔离柱可设置多个，且每个结构不同等等；只要能够保证显示面板2中隔离区20c至少存在一个Gate1隔离柱、Gate2隔离柱或Gate1+Gate2隔离柱即可。
在一些实施例中，如图6至图8所示，显示面板2还可包括封装薄膜32，此封装薄膜32至少包括第一无机封装层320，第一无机封装层320位于显示区20a和隔离区20c，并覆盖驱动电路层和第一隔离柱23，此第一无机封装层320在第一隔离柱23的斜坡处较平滑，不陡峭，有助于防止斜坡处发生裂缝的情况。应当理解的是，第一无机封装层320可覆盖整个显示区20a和隔离区20c上的结构，以提高显示面板2的封装效果。
可选地，如图6至图8所示，封装薄膜32还可包括第二无机封装层322和有机封装层321，此有机封装层321位于第一无机封装层320和第二无机封装层322之间。其中，有机封装层321可位于显示区20a和隔离区20c，并在第一阻隔坝28靠近显示区20a的一侧被阻挡；第二无机封装层322可覆盖整个显示区20a和隔离区20c。
其中，第一无机封装层320和第二无机封装层322用于防止水、氧从显示侧及开孔区20b进入到显示区20a中；第一无机封装层320和第二无机封装层322可采用氮化硅、氧化硅等无机绝缘材料制作而成；有机封装层321用于实现平坦化作用，以便于第二无机封装层322的制作，此有机封装层321可采用丙烯酸基聚合物、硅基聚合物等材料制作而成。
此外，第一无机封装层320和第二无机封装层322可采用化学气相沉积工艺制作而成，但不限于此；而有机封装层321可采用喷墨打印工艺制作，但不限于此，也可采用喷涂工艺等。在制作有机封装层321的过程中，由于有机封装材料具有一定的流动性，因此，通过设置第一阻隔坝28、第二阻隔坝29可对有机封装材料的流动形成限制，避免有机封装材料流动至开孔区20b引起封装失效的问题。
需要说明的是，本公开实施例的显示面板2中开孔区20b在开孔处理后，用于组装摄像头、传感器、HOME键、听筒或扬声器等器件。需要说明的是，对于本公开实施例的显示面板2，其开孔区20b可未进行开孔处理，在组装摄像头等器件前，再进行开孔处理即可。此外，本公开实施例的显示面板2，也可以如图4所示，开孔区20b已进行了开孔处理，在此情况下，该显示面板2可直接拿来进行后续组装。
本公开的一实施例中还提供了一种显示装置，可包括前述实施例中所描述的显示面板2，可对显示面板2的开孔区20b进行开孔处理，且显示装置还包括安装于开孔区20b的摄像头、传感器、HOME键、听筒或扬声器等功能器件。
根据本申请的实施例，该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如AMOLED显示屏、手机、笔记本电脑等移动装置、手表等可穿戴设备、VR装置、数码相框、导航仪等等任何具有显示功能的产品或部件，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板2及摄像头、传感器、HOME键、听筒或扬声器等器件以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电源线，驱动芯片等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
本公开实施例提供了一种显示面板的制作方法，该制作方法可以制作上述实施例提到的显示面板2，其中，该显示面板的制作方法包括：提供一衬底基板；在衬底基板上形成驱动电路层和第一隔离柱；其中，驱动电路层包括位于显示区的薄膜晶体管和存储电容，薄膜晶体管包括栅极、形成在栅极远离衬底基板一侧的第一栅绝缘层、形成在第一栅绝缘层远离衬底基板一侧的层间介质层和形成在层间介质层远离衬底基板一侧的源漏电极；存储电容包括与栅极同层设置的第一极板和位于第一栅绝缘层与层间介质层之间的第二极板；第一隔离柱环绕开孔区设置，且其包括第一金属层、形成在第一金属层远离衬底基板一侧的 第一绝缘层、形成在第一绝缘层远离衬底基板一侧的第二绝缘层及形成在第二绝缘层远离衬底基板一侧的第二金属层；第一金属层与第一极板或第二极板同层设置；第一绝缘层与第一栅绝缘层同层设置；第二绝缘层与层间介质层同层设置，且第二绝缘层包括第一部分、第二部分和连接第一部分和第二部分的第一倾斜部分，第一倾斜部分的坡度角小于90°；第二金属层与源漏电极同层设置并位于第二部分远离衬底基板的一侧，且其朝向显示区的一侧和/或朝向开孔区的一侧设置有环绕开孔区的凹口。
应当理解的是，本公开实施例的提供的上述制作方法应该具备与本公开实施例提供的显示面板2具有相同的特点和优点，所以，本公开实施例的提供的上述制作方法的特点和优点可以参照上文描述的显示面板2的特点和优点，在此不再赘述。
下面，以形成图4至图11所示的显示面板2为例，对本公开实施例提供的显示面板2的制作方法进行详细介绍。
举例而言，可以通过沉积等方法在衬底基板21上形成第一无机绝缘材料层，此第一无机绝缘材料层可整面形成在衬底基板21上，且其第一无机绝缘材料可划分出位于显示区20a的缓冲层22和位于隔离区20c的第一隔离柱23的第四绝缘层235和第二隔离柱31的第八绝缘层315。
在第一无机绝缘材料层形成之后，采用构图工艺在显示区20a形成薄膜晶体管24的半导体层240；之后，可以通过沉积等方法形成第二无机绝缘材料层，此第二无机绝缘材料层可整面形成在衬底基板21上，且其可划分出位于显示区20a的第二栅绝缘层241以及位于隔离区20c的第一隔离柱23的第三绝缘层234和第二隔离柱31的第七绝缘层314。
在第二无机绝缘材料层形成之后，在第二无机绝缘材料层上沉积一层金属薄膜；然后采用构图工艺对该金属薄膜进行处理，以同时在显示区20a形成薄膜晶体管24的栅极242和存储电容25的第一极板250以及在隔离区20c形成第一隔离柱23的第一金属层230和第二隔离柱31的第五金属层311；举例而言，此构图工艺包括曝光、显影、 干法刻蚀；之后，可以通过沉积等方法形成第三无机绝缘材料层，此第三无机绝缘材料层可整面形成在衬底基板21上，且其可划分出位于显示区20a的第一栅绝缘层243以及位于隔离区20c的第一隔离柱23的第一绝缘层231和第二隔离柱31的第五绝缘层312。
在第三无机绝缘材料层形成之后，在第三无机绝缘材料层上沉积一层金属薄膜；采用构图工艺对该金属薄膜进行处理，以同时在显示区20a形成存储电容25的第二极板251以及在隔离区20c形成第一隔离柱23的第三金属层236和第二隔离柱31的第六金属层316；举例而言，此构图工艺包括曝光、显影、干法刻蚀；之后，可以通过沉积等方法形成第四无机绝缘材料层，此第四无机绝缘材料层可整面形成在衬底基板21上，且其可划分出位于显示区20a的层间介质层244以及位于隔离区20c的第一隔离柱23的第二绝缘层232和第二隔离柱31的第六绝缘层313。
在第四无机绝缘材料层形成之后，采用构图工艺对层间介质层244和第一栅绝缘层243进行处理，以暴露出半导体层240的过孔；之后，采用构图工艺同时在显示区20a形成薄膜晶体管24的源极245和漏极246以及在隔离区20c形成第一隔离柱23的第二金属层233及第二隔离柱31的第四金属层310，此源极245和漏极246通过层间介质层244和第一栅绝缘层243上的过孔分别与半导体层240的两端连接。例如，在一个示例中，可以采用沉积、溅射或者蒸镀等方式依次形成钛材料层、铝材料层以及钛材料层，然后采用同一次构图工艺对三个材料层进行构图，从而形成构成源极245和漏极246的钛/铝/钛三层金属结构，同时形成侧面齐平的初始第二金属层233和初始第四金属层310；然后，通过一次刻蚀工艺刻蚀侧面齐平的初始第二金属层233和初始第四金属层310，以形成侧面具有凹口233a的第二金属层233和第四金属层310。
在形成显示区20a的薄膜晶体管24、存储电容25和形成隔离区20c的第一隔离柱23和第二隔离柱31各膜层结构之后，可采用构图工艺同时形成位于显示区20a的平坦化层26和位于隔离区20c的第二阻隔坝29的第一阻隔部；之后，采用构图工艺对平坦化层26进行 处理，以形成暴露薄膜晶体管24的漏极246的过孔；然后采用构图工艺形成像素单元30的阳极300，此阳极300通过平坦化层26上的过孔与薄膜晶体管24的漏极246连接。
在形成阳极300之后，采用构图工艺同时形成位于显示区20a的像素界定层27和位于隔离区20c的第一阻隔坝28和第二阻隔坝29的第二阻隔部；此像素界定层27具有暴露阳极300的像素开口；之后，整面蒸镀有机发光材料301，以形成位于像素开口处且与阳极300接触的有机发光材料301，应当理解的是，此有机发光材料301在第一隔离柱23和第二隔离柱31处被隔断。
在整面蒸镀有机发光材料301之后，还可整面蒸镀阴极302材料，以形成位于显示区20a的阴极302，此阴极302与有机发光材料301接触，应当理解的是，此阴极302材料在第一隔离柱23和第二隔离柱31处被隔断。
在整面蒸镀阴极302材料之后，采用化学气相沉积方式沉积位于显示区20a和隔离区20c的封装薄膜32的第一无机封装层320；之后，采用喷墨打印的方式形成位于显示区20a和隔离区20c的封装薄膜32的有机封装层321，此有机封装层321在第一阻隔坝28出被拦截；然后，采用化学气相沉积方式沉积位于显示区20a和隔离区20c的封装薄膜32的第二无机封装层322；此第一无机封装层320和第二无机封装层322覆盖显示区20a和隔离区20c上的各结构。
需要说明的是，本公开实施例中显示面板2的制作方法不限于上述的形式，具体可根据所需显示面板2的结构，对上述制作方法进行调整。
此外，还需说明的上，该制作方法中制作出的显示面板2的具体结构可参考前述实施例中所描述的显示面板2，在此不对显示面板2的具体结构做详细描述。
需要说明的是，在显示区20a形成后，可采用激光切割或者机械冲压的方式形成开孔区20b，此开孔区20b贯穿衬底基板21。此开孔区20b可组装摄像头、传感器、HOME键、听筒或扬声器等器件。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。

Claims (23)

  1. 一种显示面板，包括显示区、开孔区及位于所述显示区与开孔区之间的隔离区，所述隔离区至少部分环绕所述开孔区设置；其中，所述显示面板包括：
    衬底基板；
    驱动电路层，包括形成在所述衬底基板上并位于所述显示区的薄膜晶体管和存储电容，所述薄膜晶体管包括栅极、形成在所述栅极远离所述衬底基板一侧的第一栅绝缘层、形成在所述第一栅绝缘层远离所述衬底基板一侧的层间介质层和形成在所述层间介质层远离所述衬底基板一侧的源漏电极；所述存储电容包括与所述栅极同层设置的第一极板和位于所述第一栅绝缘层与所述层间介质层之间的第二极板；
    第一隔离柱，形成在所述衬底基板上并位于所述隔离区；所述第一隔离柱环绕所述开孔区设置，且其包括第一金属层、形成在所述第一金属层远离所述衬底基板一侧的第一绝缘层、形成在所述第一绝缘层远离所述衬底基板一侧的第二绝缘层及形成在所述第二绝缘层远离所述衬底基板一侧的第二金属层；所述第一金属层与所述第一极板或所述第二极板同层设置；所述第一绝缘层与所述第一栅绝缘层同层设置；所述第二绝缘层与所述层间介质层同层设置，且所述第二绝缘层包括第一部分、第二部分和连接所述第一部分和所述第二部分的第一倾斜部分，所述第一倾斜部分的坡度角小于90°；所述第二金属层与所述源漏电极同层设置并位于所述第二部分远离所述衬底基板的一侧，且其朝向所述显示区的一侧和/或朝向所述开孔区的一侧设置有环绕所述开孔区的凹口。
  2. 根据权利要求1所述的显示面板，其中，所述第二金属层在所述衬底基板上的正投影位于所述第一金属层在所述衬底基板的正投影内。
  3. 根据权利要求2所述的显示面板，其中，
    所述第一金属层与所述第一极板同层设置；
    所述第一隔离柱还包括第三金属层，所述第三金属层与所述第二极板同层设置。
  4. 根据权利要求3所述的显示面板，其中，
    所述第二金属层在所述衬底基板上的正投影位于所述第三金属层在所述衬底基板上的正投影内；
    所述第三金属层在所述衬底基板上的正投影位于所述第一金属层在所述衬底基板上的正投影内。
  5. 根据权利要求4所述的显示面板，其中，
    在同一截平面内，所述第二金属层的截面宽度与所述第一金属层的截面宽度之比大于或等于0.4，且小于或等于0.7；
    在同一截平面内，所述第二金属层的截面宽度与所述第三金属层的截面宽度之比大于或等于0.5，且小于或等于0.9；
    在同一截平面内，所述第三金属层的截面宽度与所述第一金属层的截面宽度之比为大于或等于0.58，且小于1；
    其中，所述截平面为在所述第一隔离柱的径向上延伸的平面。
  6. 根据权利要求5所述的显示面板，其中，
    所述第一金属层的截面宽度为6.5μm至8.5μm；
    所述第二金属层的截面宽度为3.5μm至4.5μm；
    所述第三金属层的截面宽度为5μm至7μm。
  7. 根据权利要求5所述的显示面板，其中，
    所述第一金属层、所述第三金属层的厚度为
    Figure PCTCN2020093514-appb-100001
    至
    Figure PCTCN2020093514-appb-100002
    所述第二金属层的厚度为
    Figure PCTCN2020093514-appb-100003
    至
    Figure PCTCN2020093514-appb-100004
  8. 根据权利要求1至7中任一项所述的显示面板，其中，所述第一倾斜部分的坡度角为10°至45°。
  9. 根据权利要求8所述的显示面板，其中，
    所述衬底基板与所述驱动电路层之间还设置有缓冲层；
    所述薄膜晶体管还包括依次形成在所述缓冲层上的半导体层和第二栅绝缘层，所述第二栅绝缘层位于所述栅极与所述半导体层之间。
  10. 根据权利要求9所述的显示面板，其中，
    所述第一隔离柱还包括第三绝缘层和第四绝缘层，所述第三绝缘层与所述第二栅绝缘层同层设置，所述第四绝缘层与所述缓冲层同层设置。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    平坦化层，位于所述显示区，并覆盖所述薄膜晶体管；
    像素界定层，位于所述显示区，并形成在所述平坦化层上，以用于界定多个像素单元；
    第一阻隔坝，位于所述隔离区，并环绕所述开孔区设置，所述第一阻隔坝与所述像素界定层同层设置；
    第二阻隔坝，位于所述隔离区，并环绕所述开孔区设置；所述第二阻隔坝位于所述第一阻隔坝靠近所述开孔区的一侧，并包括与所述平坦化层同层设置的第一阻隔部和与所述像素界定层同层设置的第二阻隔部；所述第二阻隔坝的高度大于所述第一阻隔坝的高度。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板还包括形成在所述衬底基板上并位于所述隔离区的第二隔离柱，所述第二隔离柱环绕所述开孔区设置，且所述第二隔离柱至少包括第四金属层，所述第四金属层与所述第二金属层的结构相同且同层设置；
    其中，所述第一阻隔坝和所述第二阻隔坝位于所述第一隔离柱和所述第二隔离柱之间。
  13. 根据权利要求12所述的显示面板，其中，所述第二隔离柱还包括第五金属层、第五绝缘层及第六绝缘层，所述第五金属层与所述第一极板或所述第二极板同层设置；所述第五绝缘层与所述第一栅绝缘层同层设置；所述第六绝缘层与所述层间介质层同层设置；
    其中，所述第六绝缘层包括第三部分、第四部分和连接所述第三部分和所述第四部分的第二倾斜部分，所述第二倾斜部分的坡度角与所述第一倾斜部分的坡度角相同，且所述第四金属层位于所述第四部分远离所述衬底基板的一侧。
  14. 根据权利要求13所述的显示面板，其中，
    所述第五金属层与所述第一极板同层设置；
    所述第二隔离柱还包括第六金属层，所述第六金属层与所述第二极板同层设置。
  15. 根据权利要求14所述的显示面板，其中，
    所述第二隔离柱还包括第七绝缘层和第八绝缘层，所述第七绝缘层与所述第二栅绝缘层同层设置，所述第八绝缘层与所述缓冲层同层设置。
  16. 根据权利要求12所述的显示面板，其中，所述第二隔离柱还包括位于所述第四金属层靠近所述衬底基板上的绝缘叠层，所述绝缘叠层与所述缓冲层、所述第二栅绝缘层、所述第一栅绝缘层及所述层间介质层同层设置，并与所述缓冲层、所述第二栅绝缘层、所述第一栅绝缘层及所述层间介质层相互断开；其中，所述绝缘叠层具有坡度角为50°至70°的斜坡面。
  17. 根据权利要求12所述的显示面板，其中，
    所述第一隔离柱和所述第二隔离柱中的一者位于所述第一阻隔坝靠近所述显示区的一侧，另一者位于所述第二阻隔坝靠近所述开孔区的一侧；
    其中，所述第一隔离柱设置有多个，和/或所述第二隔离柱设置有多个。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括封装薄膜，所述封装薄膜至少包括第一无机封装层，所述第一无机封装层位于所述显示区和所述隔离区，并覆盖所述驱动电路层和所述第一隔离柱。
  19. 一种显示装置，其特征在于，包括权利要求1至18中任一项所述的显示面板。
  20. 一种显示面板的制作方法，所述显示面板包括显示区、开孔区及位于所述显示区与开孔区之间的隔离区，所述隔离区至少部分环绕所述开孔区设置；其中，所述制作方法包括：
    提供一衬底基板；
    在所述衬底基板上形成驱动电路层和第一隔离柱；其中，
    所述驱动电路层包括位于所述显示区的薄膜晶体管和存储电容，所述薄膜晶体管包括栅极、形成在所述栅极远离所述衬底基板一侧的第一栅绝缘层、形成在所述第一栅绝缘层远离所述衬底基板一侧的层间介质层和形成在所述层间介质层远离所述衬底基板一侧的源漏电极；所述存储电容包括与所述栅极同层设置的第一极板和位于所述第一栅绝缘层与所述层间介质层之间的第二极板；
    所述第一隔离柱环绕所述开孔区设置，且其包括第一金属层、形成 在所述第一金属层远离所述衬底基板一侧的第一绝缘层、形成在所述第一绝缘层远离所述衬底基板一侧的第二绝缘层及形成在所述第二绝缘层远离所述衬底基板一侧的第二金属层；所述第一金属层与所述第一极板或所述第二极板同层设置；所述第一绝缘层与所述第一栅绝缘层同层设置；所述第二绝缘层与所述层间介质层同层设置，且所述第二绝缘层包括第一部分、第二部分和连接所述第一部分和所述第二部分的第一倾斜部分，所述第一倾斜部分的坡度角小于90°；所述第二金属层与所述源漏电极同层设置并位于所述第二部分远离所述衬底基板的一侧，且其朝向所述显示区的一侧和/或朝向所述开孔区的一侧设置有环绕所述开孔区的凹口。
  21. 根据权利要求20所述的制作方法，其中，
    所述第一金属层与所述第一极板同层设置；
    所述第一隔离柱还包括第三金属层，所述第三金属层与所述第二极板同层设置。
  22. 根据权利要求20所述的制作方法，其中，还包括：
    在所述衬底基板上形成位于所述隔离区的第二隔离柱；所述第二隔离柱环绕所述开孔区设置，且所述第二隔离柱至少包括第四金属层，所述第四金属层与所述第二金属层的结构相同且同层设置；
    在所述显示区形成覆盖所述薄膜晶体管的平坦化层；
    在所述显示区形成位于所述平坦化层上的像素界定层，以用于界定多个像素单元；
    在所述隔离区形成第一阻隔坝和第二阻隔坝，所述第一阻隔坝环绕所述开孔区设置，且所述第一阻隔坝与所述像素界定层同层设置；所述第二阻隔坝环绕所述开孔区设置，并位于所述第一阻隔坝靠近所述开孔区的一侧，所述第二阻隔坝与所述平坦化层和所述像素界定层同层设置；且所述第二阻隔坝的高度大于所述第一阻隔坝的高度；
    其中，所述第一阻隔坝和所述第二阻隔坝位于所述第一隔离柱和所述第二隔离柱之间。
  23. 根据权利要求22所述的制作方法，所述第二隔离柱的结构与所述第一隔离柱的结构相同。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114824128B (zh) * 2022-04-07 2023-07-04 武汉华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106887523A (zh) * 2015-11-20 2017-06-23 三星显示有限公司 有机发光显示器及其制造方法
CN206282861U (zh) * 2016-12-23 2017-06-27 上海天马微电子有限公司 一种有机发光显示面板及装置
CN107104077A (zh) * 2017-04-14 2017-08-29 深圳市华星光电技术有限公司 Tft阵列基板的制作方法
CN107546245A (zh) * 2016-06-28 2018-01-05 三星显示有限公司 有机发光显示装置及其制造方法
KR20180047281A (ko) * 2016-10-31 2018-05-10 엘지디스플레이 주식회사 표시장치와 그의 제조방법
WO2018167926A1 (ja) * 2017-03-16 2018-09-20 シャープ株式会社 表示装置およびその製造方法
CN109429571A (zh) * 2017-06-27 2019-03-05 堺显示器制品株式会社 有机el设备的制造方法
CN109920818A (zh) * 2018-11-14 2019-06-21 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN110265583A (zh) * 2019-07-26 2019-09-20 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN110416435A (zh) * 2019-08-28 2019-11-05 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN110429199A (zh) * 2018-04-30 2019-11-08 三星显示有限公司 显示面板和电子装置
CN110491913A (zh) * 2019-07-31 2019-11-22 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN111129078A (zh) * 2018-10-31 2020-05-08 乐金显示有限公司 透明有机发光显示设备及其制造方法
CN210535696U (zh) * 2019-11-29 2020-05-15 京东方科技集团股份有限公司 一种电致发光显示基板和包含其的电致发光显示装置
US20200168683A1 (en) * 2018-11-22 2020-05-28 Lg Display Co., Ltd. Display Device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102519126B1 (ko) 2018-03-30 2023-04-06 삼성디스플레이 주식회사 표시 장치
CN114144886B (zh) * 2020-05-15 2023-01-31 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106887523A (zh) * 2015-11-20 2017-06-23 三星显示有限公司 有机发光显示器及其制造方法
CN107546245A (zh) * 2016-06-28 2018-01-05 三星显示有限公司 有机发光显示装置及其制造方法
KR20180047281A (ko) * 2016-10-31 2018-05-10 엘지디스플레이 주식회사 표시장치와 그의 제조방법
CN206282861U (zh) * 2016-12-23 2017-06-27 上海天马微电子有限公司 一种有机发光显示面板及装置
WO2018167926A1 (ja) * 2017-03-16 2018-09-20 シャープ株式会社 表示装置およびその製造方法
CN107104077A (zh) * 2017-04-14 2017-08-29 深圳市华星光电技术有限公司 Tft阵列基板的制作方法
CN109429571A (zh) * 2017-06-27 2019-03-05 堺显示器制品株式会社 有机el设备的制造方法
CN110429199A (zh) * 2018-04-30 2019-11-08 三星显示有限公司 显示面板和电子装置
CN111129078A (zh) * 2018-10-31 2020-05-08 乐金显示有限公司 透明有机发光显示设备及其制造方法
CN109920818A (zh) * 2018-11-14 2019-06-21 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
US20200168683A1 (en) * 2018-11-22 2020-05-28 Lg Display Co., Ltd. Display Device
CN110265583A (zh) * 2019-07-26 2019-09-20 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN110491913A (zh) * 2019-07-31 2019-11-22 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN110416435A (zh) * 2019-08-28 2019-11-05 武汉天马微电子有限公司 有机发光显示面板和显示装置
CN210535696U (zh) * 2019-11-29 2020-05-15 京东方科技集团股份有限公司 一种电致发光显示基板和包含其的电致发光显示装置

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