WO2021233078A1 - 阵列基板母板及其检测方法、阵列基板、显示装置 - Google Patents

阵列基板母板及其检测方法、阵列基板、显示装置 Download PDF

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Publication number
WO2021233078A1
WO2021233078A1 PCT/CN2021/089693 CN2021089693W WO2021233078A1 WO 2021233078 A1 WO2021233078 A1 WO 2021233078A1 CN 2021089693 W CN2021089693 W CN 2021089693W WO 2021233078 A1 WO2021233078 A1 WO 2021233078A1
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WIPO (PCT)
Prior art keywords
terminal
array substrate
node
mother board
circuit
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PCT/CN2021/089693
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English (en)
French (fr)
Inventor
田宏伟
牛亚男
赵梦
刘明
于洋
刘政
Original Assignee
京东方科技集团股份有限公司
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Publication of WO2021233078A1 publication Critical patent/WO2021233078A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate mother board and a detection method thereof, an array substrate, and a display device.
  • the AT (Array Test) test method mainly refers to the provision of detection probe pads on each array substrate.
  • the detection probe pads can be connected to the leads and devices in the array substrate, and can be connected to the detection probe through external testing equipment.
  • the pad sends or receives detection signals to detect the working status of each device and lead in the array substrate.
  • the external inspection equipment needs to inspect each array substrate one by one.
  • each array substrate needs to be positioned and fixed, and the probes of the external inspection equipment and the array substrate need to be fixed. Detect the probe pad for docking. This detection process takes a long time.
  • an array substrate mother board which includes a detection area for external detection equipment, and the array substrate mother board further includes: a common probe pad, a plurality of array substrate units distributed in rows and columns, and a second A gate drive circuit and a second gate drive circuit.
  • the common probe pad is arranged in the detection area; each of the array substrate units includes: an array substrate, a detection signal terminal, and a switch circuit.
  • the detection signal terminal is used to send or receive a detection signal to the array substrate;
  • the switch circuit is connected to the first control signal terminal, the second control signal terminal, the common probe pad, and the detection signal terminal, and is used to simultaneously respond to the first
  • the signals of the control signal terminal and the second control signal terminal are used to conduct the common probe pad and the detection signal terminal;
  • the first gate drive circuit includes a plurality of cascaded first shift register units, and a plurality of the first shift register units The output terminals of a shift register unit are respectively connected to the first control signal terminals connected to the switch circuits in the same row;
  • the second gate drive circuit includes a plurality of cascaded second shift register units, and a plurality of the first control signal terminals The output terminals of the two shift register units are respectively connected to the second control signal terminals connected to the switch circuits in the same column.
  • the array substrate mother board further includes: a first control probe pad group and a second control probe pad group.
  • the first control probe pad group is arranged in the detection area and is used to input clock signals and input signals to the first gate drive circuit;
  • the second control probe pad group is arranged in the detection area and is used to input clock signals and input signals to the The second gate driving circuit inputs a clock signal and an input signal.
  • the switch circuit includes: a first switch transistor and a second switch transistor.
  • the first terminal of the first switch transistor is connected to the common probe pad, and the control terminal is connected to the first control signal terminal;
  • the first terminal of the second switch transistor is connected to the second terminal of the first switch transistor, and the second terminal is The detection signal terminal is connected, and the control terminal is connected to the second control signal terminal.
  • the array substrate mother board further includes: a first reset probe pad and a second reset probe pad.
  • the first reset probe pad is arranged in the detection area and is connected to the output terminal of each of the first shift register units; the second reset probe pad is arranged in the detection area and is connected to each of the second shift register units. The output terminal of the register unit.
  • the array substrate mother board further includes a sub-probe pad, and the sub-probe pad is connected to the detection signal terminal.
  • the array substrate unit further includes: a third reset probe pad, a fourth reset probe pad, and the third reset probe pad is connected to the first control device connected to the first switch transistor. Signal terminal; the fourth reset probe pad is connected to the second control signal terminal connected to the second switch transistor.
  • the array substrate mother board includes a plurality of common probe pads located in the detection area
  • the array substrate unit includes a plurality of switch circuits, a plurality of detection signal terminals, and the common
  • the probe pads, the switch circuit, and the detection signal terminal are arranged in one-to-one correspondence; among the common probe pads, the switch circuit, and the detection signal terminal that are arranged in a one-to-one correspondence, the switch circuit is connected to the first control signal terminal and the detection signal terminal.
  • the second control signal terminal, the common probe pad, and the detection signal terminal are used to simultaneously respond to the signals of the first control signal terminal and the second control signal terminal to turn on the common probe pad and the Detect the signal terminal.
  • the array substrate unit further includes a data selector, and the detection signal terminal is connected to a plurality of signal lines in the array substrate through the data selector.
  • the array substrate unit includes a detection circuit area and a substrate area located on both sides of the cutting line; the array substrate is integrated in the substrate area, the switch circuit, the sub-probe pad, The third reset probe pad and the fourth reset probe pad are integrated in the detection circuit area; wherein the cutting line is a cutting path of the array substrate mother board in the module process.
  • the array substrate unit includes a detection circuit area and a substrate area on the same side of the cutting line; the array substrate is integrated in the substrate area, the switch circuit, the sub-probe pad, The third reset probe pad and the fourth reset probe pad are integrated in the detection circuit area; wherein the cutting line is a cutting path of the array substrate mother board in the module process.
  • the array substrate mother board further includes: a plurality of first gate lines, a plurality of second gate lines, and the plurality of first gate lines extend along the row direction and are connected to the same row.
  • the first control signal terminal in the switch circuit; a plurality of second gate lines extend along the column direction and are connected to the second control signal terminals in the switch circuit in the same column;
  • the first gate drive circuit is arranged in the array One side of the mother substrate in the row direction, the output terminal of the first shift register unit is connected to one end of the first gate line;
  • the second gate drive circuit is arranged on the mother substrate of the array substrate in the column direction On one side, the output terminal of the second shift register unit is connected to one end of the second gate line.
  • the array substrate mother board further includes: a third gate drive circuit, a fourth gate drive circuit, and the third gate drive circuit is arranged on the array substrate mother board along a row direction
  • the other side includes a plurality of cascaded third shift register units, the output end of the third shift register unit is connected to the other end of the first gate line;
  • the fourth gate drive circuit is arranged in the
  • the other side of the array substrate mother board along the column direction includes a plurality of cascaded fourth shift register units, and the output end of the fourth shift register unit is connected to the other end of the second gate line.
  • the first shift register unit and the second shift register unit have the same structure, and the first shift register unit includes: a first input circuit, a second input The circuit, the first output circuit, the second output circuit, the isolation circuit, the first control circuit, and the second control circuit.
  • the first input circuit is connected to the first power terminal, the first node, and the first clock signal terminal, and is used for transmitting the signal of the first power terminal to the first node in response to the signal of the first clock signal terminal;
  • the second input The circuit is connected to the first clock signal terminal, the input signal terminal, and the second node, and is used to transmit the signal of the input signal terminal to the second node in response to the signal of the first clock signal terminal;
  • the first output circuit is connected to the second node;
  • the first node, the second power terminal, and the output terminal are used to transmit the signal of the second power terminal to the output terminal in response to the signal of the first node;
  • the second output circuit is connected to the output terminal, the second The clock signal terminal and the third node are used to transmit the signal of the second clock signal terminal to the output terminal in response to the signal of the third node;
  • the isolation circuit is connected to the second node, the first power terminal, and the third node.
  • the first control circuit is connected to the first node, the first clock signal terminal, and the second node, and is used to respond The signal of the second node transmits the signal of the first clock signal terminal to the first node;
  • the second control circuit is connected to the first node, the second node, the second power terminal, and the second clock signal terminal, The signal used for simultaneously responding to the first node and the second clock signal terminal will connect the second power terminal and the second node.
  • the first input circuit includes a third switching transistor, a first terminal of the third switching transistor is connected to the first power terminal, a second terminal is connected to the first node, and a control terminal Connect to the first clock signal terminal.
  • the second input circuit includes a fourth switch transistor, the first terminal of the fourth switch transistor is connected to the input signal terminal, the second terminal is connected to the second node, and the control terminal is connected to the first clock signal terminal.
  • the first output circuit includes a fifth switch transistor and a first capacitor. The first terminal of the fifth switch transistor is connected to the second power terminal, the second terminal is connected to the output terminal, and the control terminal is connected to the first node. The capacitor is connected between the second power terminal and the first node.
  • the second output circuit includes a sixth switch transistor and a second capacitor.
  • the first terminal of the sixth switch transistor is connected to the second clock signal terminal, the second terminal is connected to the output terminal, and the control terminal is connected to the third node. Two capacitors are connected between the third node and the output terminal.
  • the isolation circuit includes a seventh switch transistor, the first terminal of the seventh switch transistor is connected to the second node, the second terminal is connected to the third node, and the control terminal is connected to the first power terminal.
  • the first control circuit includes an eighth switch transistor, a first terminal of the eighth switch transistor is connected to the first node, a second terminal is connected to the first clock signal terminal, and a control terminal is connected to the second node.
  • the second control circuit includes a ninth switch transistor and a tenth switch transistor.
  • the first terminal of the ninth switch transistor is connected to the second power terminal, and the control terminal is connected to the first node.
  • the first terminal of the tenth switch transistor is connected to the second terminal of the ninth switch transistor, the second terminal is connected to the second node, and the control terminal is connected to the second clock signal terminal.
  • the structures of the first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit are the same.
  • the switching transistors in the first shift register unit and the second shift register unit are formed in the same layer as the switching transistors of the pixel circuit in the array substrate.
  • a method for detecting an array substrate mother board for detecting the above-mentioned array substrate mother board, which includes:
  • first gate driving circuit and the second gate driving circuit to simultaneously input a conduction signal to the target array substrate unit to connect the inspection signal terminal of the target array substrate unit and the common probe pad;
  • a detection device is used to send or receive a detection signal to the common probe pad to detect the target array substrate unit.
  • an array substrate is provided, which is cut from the above-mentioned array substrate mother board.
  • a display device including the above-mentioned array substrate.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of an array substrate motherboard of the present disclosure
  • FIG. 2 is a partial enlarged view of the array substrate unit in FIG. 1;
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of a switch circuit in a motherboard of the disclosed array substrate
  • FIG. 4 is a schematic structural diagram of a first shift register unit in an exemplary embodiment of the array substrate motherboard of the present disclosure
  • FIG. 5 is a timing diagram of each node in a driving method of the first shift register unit in FIG. 4;
  • FIG. 6 is a schematic diagram of the structure of the detection area in the motherboard of the disclosed array substrate
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of the array substrate mother board of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an array substrate unit in another exemplary embodiment of the array substrate mother board of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an array substrate unit in another exemplary embodiment of the array substrate mother board of the present disclosure.
  • FIG. 10 is a schematic diagram of the structure of the detection area in another exemplary embodiment of the array substrate motherboard of the present disclosure.
  • FIG. 11 is a timing diagram of the output terminals of the first gate driving circuit and the second gate driving circuit in an exemplary embodiment of the test method of the array substrate motherboard of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an exemplary embodiment of the array substrate mother board of the present disclosure
  • FIG. 2 is a schematic diagram of the array substrate unit in FIG. Partially enlarged view.
  • the array substrate mother board includes a detection area 1 for external testing equipment.
  • the array substrate mother board also includes a common probe pad 2, a plurality of array substrate units distributed in rows and columns, a first gate drive circuit 4, and a second gate. Pole drive circuit5.
  • the common probe pad 2 is arranged in the detection area 1; each of the array substrate units includes: an array substrate 31, a detection signal terminal 32, and a switch circuit 33.
  • the detection signal terminal 32 is used to send or receive a detection signal to the array substrate 31;
  • the switch circuit 33 is connected to the first control signal terminal 71, the second control signal terminal 72, the common probe pad 2, the detection signal terminal 32, In response to the signals of the first control signal terminal 71 and the second control signal terminal 72 at the same time to turn on the common probe pad 2 and the detection signal terminal 32;
  • the first gate drive circuit 4 includes a plurality of cascades
  • the first shift register unit 41 of the first shift register unit 41, the output terminals of the plurality of first shift register units 41 are respectively connected to the first control signal terminal 71 connected to the switch circuit 33 in the same row;
  • the second gate drive circuit 5 includes There are a plurality of cascaded second shift register units 51, and the output terminals of the plurality of second shift register units 51 are respectively connected to the second control signal terminals 72 connected to the switch circuits 33 in the same column.
  • the detection signal terminal may be connected to one or more signal lines in the array substrate, and the signal line may be
  • the array substrate mother board provided by this exemplary embodiment can position the target array substrate unit through the first gate drive circuit 4 and the second gate drive circuit 5, thereby conducting detection signals in the common probe pad and the target array substrate unit Terminal to provide detection signals to the array substrate in the target array substrate unit through the common probe pad.
  • the array substrate unit in the second row and second column The switch circuit is turned on to connect the common probe pad and the detection signal terminal in the second row and second column of the array substrate unit, so that the common probe pad provides a detection signal to the array substrate in the second row and second column of the array substrate unit.
  • the array substrate mother board provided by this exemplary embodiment only needs to connect the external detection device with the common probe pad to realize the inspection of all the array substrates, thereby greatly reducing the inspection time of the array substrate.
  • FIG. 3 it is a schematic structural diagram of an exemplary embodiment of a switch circuit in a motherboard of an array substrate of the present disclosure.
  • the switching circuit may include: a first switching transistor T1 and a second switching transistor T2.
  • the first terminal of the first switch transistor T1 is connected to the common probe pad 2, and the control terminal is connected to the first control signal terminal 71;
  • the first terminal of the second switch transistor T2 is connected to the second terminal of the first switch transistor T1.
  • the second terminal is connected to the detection signal terminal 32, and the control terminal is connected to the second control signal terminal 72.
  • the switch circuit can also have more structures to choose from, which all fall within the protection scope of the present disclosure.
  • the first shift register unit may include: a first input circuit 411, a second input circuit 412, a first output circuit 413, a second output circuit 414, an isolation circuit 415, a first control circuit 416, and a second control circuit 417 .
  • the first input circuit 411 is connected to the first power terminal VGL, the first node N1, and the first clock signal terminal CK1, and is used for transmitting the signal of the first power terminal VGL to all the signals in response to the signal of the first clock signal terminal CK1.
  • the second input circuit 412 is connected to the first clock signal terminal CK1, the input signal terminal INPUT, and the second node N2, and is used to transmit the signal of the input signal terminal INPUT to all the signals in response to the signal of the first clock signal terminal CK1.
  • the first output circuit 413 is connected to the first node N1, the second power terminal VGH, and the output terminal OUT, and is used to transmit the signal of the second power terminal VGH to the output terminal in response to the signal of the first node N1 OUT.
  • the second output circuit 414 is connected to the output terminal OUT, the second clock signal terminal CK2, and the third node N3, and is used to transmit the signal of the second clock signal terminal CK2 to the signal of the third node N3.
  • the isolation circuit 415 is connected to the second node N2, the first power terminal VGL, and the third node N3, and is used to respond to the signal of the first power terminal VGL to connect the second node N2 and the third node N3.
  • the first control circuit 416 is connected to the first node N1, the first clock signal terminal CK1, and the second node N2, and is used for transmitting the signal of the first clock signal terminal CK1 to all the signals in response to the signal of the second node N2.
  • the second control circuit 417 is connected to the first node N1, the second node N2, the second power supply terminal VGH, and the second clock signal terminal CK2, for simultaneously responding to the signals of the first node N1 and the second clock signal terminal CK2
  • the second power terminal VGH and the second node N2 will be connected.
  • the first input circuit 411 may include a third switching transistor T3, the first terminal of the third switching transistor T3 is connected to the first power terminal VGL, and the second terminal is connected to the first node N1.
  • the control terminal is connected to the first clock signal terminal CK1.
  • the second input circuit 412 may include a fourth switch transistor T4.
  • the first terminal of the fourth switch transistor T4 is connected to the input signal terminal INPUT, the second terminal is connected to the second node N2, and the control terminal is connected to the first clock signal. Terminal CK1.
  • the first output circuit 413 may include a fifth switch transistor T5 and a first capacitor C1.
  • the first terminal of the fifth switch transistor T5 is connected to the second power supply terminal VGH, the second terminal is connected to the output terminal OUT, and the control terminal is connected to the In the first node N1, the first capacitor C1 is connected between the second power terminal VGH and the first node N1.
  • the second output circuit 414 may include a sixth switching transistor T6 and a second capacitor C2.
  • the first terminal of the sixth switching transistor T6 is connected to the second clock signal terminal CK2, the second terminal is connected to the output terminal OUT, and the control terminal is connected to The third node N3 and the second capacitor C2 are connected between the third node N3 and the output terminal OUT.
  • the isolation circuit 415 may include a seventh switch transistor T7.
  • the first terminal of the seventh switch transistor T7 is connected to the second node N2, the second terminal is connected to the third node N3, and the control terminal is connected to the first power terminal VGL.
  • the first control circuit may include an eighth switch transistor T8.
  • a first terminal of the eighth switch transistor T8 is connected to the first node N1, a second terminal is connected to the first clock signal terminal CK1, and a control terminal is connected to the second node.
  • the second control circuit 417 may include a ninth switch transistor T9 and a tenth switch transistor T10.
  • the first terminal of the ninth switch transistor T9 is connected to the second power supply terminal VGH, and the control terminal is connected to the first node N1.
  • the first terminal of the tenth switch transistor T10 is connected to the second terminal of the ninth switch transistor, the second terminal is connected to the second node N2, and the control terminal is connected to the second clock signal terminal CK2.
  • the third to tenth switching transistors may be P-type transistors.
  • FIG. 5 it is a timing diagram of each node in a driving method of the first shift register unit in FIG. 4.
  • the first power supply terminal VGL is always low level
  • the second power supply terminal VGH is always high level
  • the seventh switch transistor T7 is constantly turned on.
  • the driving method of the first shift register unit includes 4 stages.
  • the input signal terminal INPUT the input signal terminal INPUT
  • the first clock signal terminal CK1 inputs a low level signal
  • the second clock signal terminal CK2 inputs a high level signal
  • the third switch transistor T3 and the fourth switch transistor T4 are turned on, and the input
  • the low-level signal of the signal terminal INPUT charges the second node N2 and is stored in the second capacitor C2
  • the low-level signal of the first power supply terminal charges the first node N1 and is stored in the first capacitor.
  • the fifth switch transistor T5 and the sixth switch transistor T6 are turned on, and the second power supply terminal VGH and the second clock signal terminal CK2 output a high-level signal to the output terminal OUT.
  • the input signal terminal INPUT the first clock signal terminal CK1 inputs a high level signal
  • the second clock signal terminal CK2 inputs a low level signal
  • the eighth switch transistor T8 is turned on
  • the first clock signal terminal CK1 The high-level signal is transmitted to the first node N1, so that the fifth switching transistor T5 is turned off, the fourth switching transistor T4 is continuously turned on, and the low-level signal of the second clock signal terminal CK2 is transmitted to the output terminal OUT.
  • the input signal terminal INPUT and the second clock signal terminal CK2 output a high level
  • the first clock signal terminal CK1 outputs a low level
  • the third switch transistor T3 is turned on
  • the first power terminal VGL is at a low level.
  • the signal is transmitted to the first node
  • the fifth switch transistor T5 is turned on
  • the second power supply terminal VGH inputs a high-level signal to the output terminal OUT
  • the fourth switch transistor T4 is turned on, and the high-level signal of the input signal terminal INPUT is transmitted To the second node.
  • the second shift register unit may have the same structure as the first shift register unit.
  • the signal duration of the output terminal OUT can be controlled by controlling the clock signal terminal (including the first clock signal terminal and the second clock signal terminal) and the signal of the input signal terminal, thereby controlling the detection duration of the array substrate.
  • the effective duration of the output of the first shift register unit may be n times the effective duration of the output of the second shift register unit, where n is the number of columns of the array substrate unit in the array substrate mother board. Therefore, the array substrate mother board can realize the detection of the array substrate units row by row.
  • first shift register unit may also have other structures, and the structures of the first shift register unit and the second shift register unit may also be different, which belong to the present disclosure.
  • FIG. 6 it is a schematic diagram of the structure of the detection area in the array substrate mother board of the present disclosure.
  • the array substrate mother board further includes: a first control probe pad group 81 and a second control probe ⁇ 82 ⁇ Pad group 82.
  • the first control probe pad group 81 is arranged in the detection area 1 for inputting clock signals and input signals to the first gate drive circuit 4; the second control probe pad group is arranged in the detection area To input a clock signal and an input signal to the second gate drive circuit.
  • the first control probe pad group 81 may include a plurality of probe pads, and the plurality of probe pads respectively input signals to the first clock signal terminal, the second clock signal terminal, and the input signal terminal in the first shift register unit.
  • the second control probe pad group 82 may include a plurality of probe pads, and the plurality of probe pads respectively input signals to the first clock signal terminal, the second clock signal terminal, and the input signal terminal in the second shift register unit.
  • the array substrate mother board may further include: a first reset probe pad 91 and a second reset probe pad 92.
  • the first reset probe pad 91 may be provided in the detection area 1 and connected to the output terminal of each of the first shift register units; the second reset probe pad 92 may be provided in the detection area 1 and connected to each The output terminal of the second shift register unit.
  • the array substrate mother board provided in this embodiment can use an external inspection device to input a reset signal to the output terminal of the first shift register unit through the first reset probe pad 91, thereby terminating the inspection of the target array substrate.
  • an external inspection device can also be used to input a reset signal to the output terminal of the second shift register unit through the second reset probe pad 92, thereby terminating the inspection of the target array substrate.
  • the array substrate mother board may further include a sub-probe pad 10, and the sub-probe pad 10 is connected to the detection signal terminal.
  • the detection device can be used to directly inspect the target array substrate through the sub-probe pad 10.
  • the array substrate unit may further include: a third reset probe pad 93, a fourth reset probe pad 94, and the third reset probe pad 93 is connected to the first reset probe pad.
  • an external inspection device can be used to terminate the inspection of the target array substrate through the third reset probe pad 93 or the fourth reset probe pad 94.
  • FIG. 8 it is a schematic structural diagram of an array substrate unit in another exemplary embodiment of an array substrate mother board of the present disclosure.
  • the detection signal terminal can be connected to a plurality of signal lines in the array substrate through the data selector 161.
  • the data selector can select any signal line to connect to the detection signal terminal. This setting can realize the selective detection of each signal line through a detection signal terminal.
  • FIG. 9 is a schematic structural diagram of an array substrate unit in another exemplary embodiment of an array substrate motherboard of the present disclosure
  • FIG. 10 is another exemplary embodiment of an array substrate motherboard of the present disclosure.
  • the array substrate unit may further include a plurality of detection signal terminals 32, and each detection signal terminal may be connected to a plurality of signal lines through a data selector 161.
  • the array substrate unit may further include a plurality of switch circuits 33
  • the array substrate mother board may also include a plurality of common probe pads 2 located in the detection area, the common probe pads, the switch circuit, and the detection signal
  • the terminals can be set in one-to-one correspondence.
  • the switch circuit 33 may be connected to the first control signal terminal, the second control signal terminal, and the common probe pad. 2.
  • the detection signal terminal 32 is used to simultaneously respond to the signals of the first control signal terminal and the second control signal terminal to conduct the common probe pad and the detection signal terminal.
  • the array substrate unit may further include a plurality of sub-probe pads 10, and the plurality of sub-probe pads 10 may be connected to a plurality of detection signal terminals in a one-to-one correspondence.
  • a plurality of common probe pads 2 can be arranged adjacent to each other.
  • the connection part between the external detection device and the array substrate mother board can include a plurality of adjacent probes. When the boards are docked, multiple probes can contact multiple common probe pads in a one-to-one correspondence.
  • multiple sub-probe pads 10 can also be arranged adjacently, so that the multiple probes in the external detection device can directly contact the multiple sub-probe pads 10 in a one-to-one correspondence.
  • the array substrate unit may include a detection circuit area 121 and a substrate area 122 located on both sides of the cutting line AA; the array substrate 31 may be integrated in the In the substrate area 122, the switch circuit 33, the sub-probe pad 10, the third reset probe pad 93, the fourth reset probe pad 94, and the data selector 161 may be integrated in the detection circuit area 121; wherein, the The cutting line is the cutting path of the array substrate mother board in the module process. After the array substrate mother board completes the detection and other processes, the array substrate mother board can be cut along the cutting line to form a single array substrate.
  • the array substrate unit may include a detection circuit area and a substrate area on the same side of the cutting line; the array substrate is integrated in the substrate area, and the switch circuit, sub The probe pad, the third reset probe pad, and the fourth reset probe pad are integrated in the detection circuit area; wherein the cutting line is a cutting path of the array substrate mother board in the module process. After the array substrate mother board has completed the detection and other processes, the array substrate mother board can be cut along the cutting line to form a single array substrate, which includes various components located in the detection circuit area.
  • the array substrate mother board may further include: a plurality of first gate lines 131 and a plurality of second gate lines 132, and the plurality of first gate lines 131 extend in the row direction , And connected to the first control signal terminal in the switch circuit in the same row; a plurality of second gate lines 132 extend along the column direction, and are connected to the second control signal terminal in the switch circuit in the same column; the first gate The pole drive circuit 4 may be arranged on one side of the array substrate mother board along the row direction, the output terminal of the first shift register unit 41 is connected to one end of the first gate line; the second gate drive circuit 5 may be arranged on one side of the array substrate mother board along the column direction, and the output terminal of the second shift register unit 51 is connected to one end of the second gate line.
  • the first gate line 131 and the second gate line 132 have a voltage drop. Therefore, the array substrate unit far away from the first gate drive circuit is compared to the array substrate unit close to the first gate drive circuit. , Its driving ability to receive the driving signal transmitted by the first gate line is weak. Compared with the array substrate unit close to the second gate driving circuit, the array substrate unit far away from the second gate driving circuit has a weaker driving ability to receive the driving signal transmitted by the second gate line. Therefore, this exemplary embodiment may cause the array substrate unit on the side far from the first gate driving circuit and the second gate driving circuit to be unable to sufficiently conduct the switching circuit therein. In this exemplary embodiment, as shown in FIG.
  • the array substrate mother board may further include: a third gate drive circuit 14 and a fourth gate drive circuit 15.
  • the third gate drive circuit 14 may be arranged on the other side of the array substrate mother board in the row direction, It includes a plurality of cascaded third shift register units 141.
  • the output terminal 41 of the third shift register unit 141 is connected to the other end of the first gate line;
  • the fourth gate driving circuit 15 may be arranged in the
  • the other side of the array substrate mother board along the column direction includes a plurality of cascaded fourth shift register units 151, and the output end of the fourth shift register unit 151 is connected to the other end of the second gate line.
  • first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit may have the same structure.
  • the first shift register unit and the third shift register unit can provide driving signals to the first gate line at the same time
  • the second shift register unit and the fourth shift register unit can provide driving signals to the second gate line at the same time
  • the switching transistors in the first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit may be the same as those of the pixel circuit in the array substrate.
  • the switching transistors are formed in the same layer. That is, the switch transistors in the first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit can be formed with the switch transistors of the pixel circuit in the array substrate through a set of patterning processes. .
  • all the probe pads in this exemplary embodiment may be conductive pads exposed on the surface of the array substrate mother board.
  • the first gate line and the second gate line may be located on the surface of the mother board of the array substrate or integrated inside the mother board of the array substrate.
  • This exemplary embodiment also provides a method for detecting an array substrate mother board, which is used to detect the above-mentioned array substrate mother board, which includes:
  • first gate driving circuit and the second gate driving circuit to simultaneously input a conduction signal to the target array substrate unit to connect the inspection signal terminal of the target array substrate unit and the common probe pad;
  • a detection device is used to send or receive a detection signal to the common probe pad to detect the target array substrate unit.
  • the target array substrate unit may include an array substrate unit, and the array substrate mother board detection method can realize the detection of the array substrate units row by row.
  • this embodiment can control the output terminal by controlling the clock signal terminal (including the first clock signal terminal and the second clock signal terminal) and the input signal terminal in the first gate drive circuit and the second gate drive circuit.
  • the signal duration of OUT controls the inspection duration of the array substrate.
  • the first gate driving circuit may include a plurality of cascaded first shift register units
  • the second gate driving circuit may include a plurality of cascaded second shift register units. In this exemplary embodiment, as shown in FIG.
  • OUT11 represents the timing of the output of the first shift register unit of the first stage
  • OUT12 represents the timing of the output of the first shift register unit of the second stage
  • OUT13 represents the timing of the output of the first shift register unit of the third stage
  • OUT21 represents the timing of the output of the first shift register unit of the third stage.
  • OUT22 represents the timing of the output terminal of the second shift register unit of the second stage
  • OUT23 indicates the timing of the output terminal of the second shift register unit of the third stage.
  • the detection method can detect an array substrate mother board with a 3-by-3 array of the array substrate unit.
  • the duration of the effective signal output by the first shift register unit may be 3 times the duration of the valid signal output by the second shift register unit.
  • the first-stage first shift register unit and the first-stage second shift register unit output effective levels.
  • the substrate unit is inspected.
  • the first-stage first shift register unit and the second-stage second shift register unit output valid levels, and the array substrate mother board can inspect the array substrate units in the first row and second column.
  • the first shift register unit of the first stage and the second shift register unit of the third stage output valid levels, and the array substrate mother board can inspect the array substrate units in the first row and third column.
  • the array substrate mother board can detect the array substrate units row by row.
  • the effective duration of the output of the first shift register unit may be n times the effective duration of the output of the second shift register unit.
  • the target array substrate unit may further include a plurality of array substrate units, and the detection method of the array substrate mother board can also simultaneously inspect a plurality of array substrate units.
  • the exemplary embodiment also provides an array substrate, which is formed by cutting the above-mentioned array substrate mother board.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned array substrate, and the display device may be a Micro LED display device.

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Abstract

一种阵列基板母板及其检测方法、阵列基板、显示装置。阵列基板母板包括公共探针垫（2）、多个行列分布的阵列基板单元、第一栅极驱动电路（4）、第二栅极驱动电路（5）。阵列基板单元包括阵列基板（31）、检测信号端（32）、开关电路（33）。检测信号端（32）用于向阵列基板（31）发送或接收检测信号；开关电路（33）用于响应第一控制信号端（71）、第二控制信号端（72）的信号以导通公共探针垫（2）和检测信号端（32）；第一栅极驱动电路（71）中第一移位寄存器单元（41）的输出端与同一行开关电路（33）中的第一控制信号端（71）连接；第二栅极驱动电路（5）中第二移位寄存器单元（51）的输出端与同一列开关电路（33）中的第二控制信号端（72）连接。该阵列基板母板能减小阵列基板（31）的AT检测时长。

Description

阵列基板母板及其检测方法、阵列基板、显示装置
相关申请的交叉引用
本申请要求于2020年05月20日递交的、名称为《阵列基板母板及其检测方法、阵列基板、显示装置》的中国专利申请第202010430056.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板母板及其检测方法、阵列基板、显示装置。
背景技术
显示面板生产制造过程中，需要不断地检测产品的质量问题，从而及时的筛选出不合格的产品，以实现高良率、低成本地生产。例如，在Micro LED显示面板在制作过程中，需要在将Micro LED发光单元转移到阵列基板之前，对阵列基板进行AT(Array Test)测试，以保证阵列基板的有良率。
相关技术中，AT(Array Test)测试方法主要指，在每个阵列基板上预留检测探针垫，检测探针垫可以与阵列基板中的引线、器件连接，通过外部检测设备向检测探针垫发送或接收检测信号，以检测阵列基板中各个器件、引线的工作状态。
相关技术中，外部检测设备需要每个阵列基板进行逐一检测，在对每一个阵列基板进行检查时，需要对每个阵列基板进行定位、固着，且需要将外部检测设备的探针与阵列基板的检测探针垫进行对接。该检测过程耗时较长。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种阵列基板母板，其包括用于外接检测设备的检测区，所述阵列基板母板还包括：公共探针垫、多个行列分布的阵列基板单元、第一栅极驱动电路、第二栅极驱动电路。公共探针垫设置于所述检测区；每个所述阵列基板单元包括：阵列基板、检测信号端、开关电路。检测信号端用于向所述阵列基板发送或接收检测信号；开关电路连接第一控制信号端、第二控制信号端、所述公共探针垫、检测信号端，用于同时响应所述第一控制信号端、第二控制信号端的信号以导通所述公共探针垫和所述检测信号端；第一栅极驱动电路包括多个级联的第一移位寄存器单元，多个所述第一移位寄存器单元的输出端分别与同一行所述开关电路连接的第一控制信号端连接；第二栅极驱动电路，括多个级联的第二移位寄存器单元，多个所述第二移位寄存器单元的输出端分别与同一列所述开关电路连接的第二控制信号端连 接。
本公开一种示例性实施例中，所述阵列基板母板还包括：第一控制探针垫组、第二控制探针垫组。第一控制探针垫组设置于所述检测区，用于向所述第一栅极驱动电路输入时钟信号、输入信号；第二控制探针垫组设置于所述检测区，用于向所述第二栅极驱动电路输入时钟信号、输入信号。
本公开一种示例性实施例中，所述开关电路包括：第一开关晶体管、第二开关晶体管。第一开关晶体管的第一端连接所述公共探针垫，控制端连接所述第一控制信号端；第二开关晶体管的第一端连接所述第一开关晶体管的第二端，第二端连接所述检测信号端，控制端连接所述第二控制信号端。
本公开一种示例性实施例中，所述阵列基板母板还包括：第一复位探针垫、第二复位探针垫。第一复位探针垫设置于所述检测区，连接每个所述第一移位寄存器单元的输出端；第二复位探针垫设置于所述检测区，连接每个所述第二移位寄存器单元的输出端。
本公开一种示例性实施例中，所述阵列基板母板还包括子探针垫，子探针垫连接所述检测信号端。
本公开一种示例性实施例中，所述阵列基板单元还包括：第三复位探针垫、第四复位探针垫，第三复位探针垫连接所述第一开关晶体管连接的第一控制信号端；第四复位探针垫连接所述第二开关晶体管连接的第二控制信号端。
本公开一种示例性实施例中，所述阵列基板母板包括多个位于所述检测区的公共探针垫，所述阵列基板单元包括多个开关电路、多个检测信号端，所述公共探针垫、开关电路、检测信号端一一对应设置；在一一对应设置的所述公共探针垫、开关电路、检测信号端中，所述开关电路连接所述第一控制信号端、所述第二控制信号端、所述公共探针垫、所述检测信号端，用于同时响应所述第一控制信号端、第二控制信号端的信号以导通所述公共探针垫和所述检测信号端。
本公开一种示例性实施例中，所述阵列基板单元还包括数据选择器，所述检测信号端通过所述数据选择器与所述阵列基板中的多条信号线连接。
本公开一种示例性实施例中，所述阵列基板单元包括位于切割线两侧的检测电路区和基板区；所述阵列基板集成于所述基板区，所述开关电路、子探针垫、第三复位探针垫、第四复位探针垫集成于所述检测电路区；其中，所述切割线为在模组工艺中所述阵列基板母板的切割路径。
本公开一种示例性实施例中，所述阵列基板单元包括位于切割线同一侧的检测电路区和基板区；所述阵列基板集成于所述基板区，所述开关电路、子探针垫、第三复位探针垫、第四复位探针垫集成于所述检测电路区；其中，所述切割线为在模组工艺中所述阵列基板母板的切割路径。
本公开一种示例性实施例中，所述阵列基板母板还包括：多条第一栅线、多条第二栅线，多条第一栅线沿行方向延伸，且连接同一行所述开关电路中的第一控制信号端；多条第二栅线沿列方向延伸，且连接同一列所述开关电路中的第二控制信号端；所述第一栅极驱动电路设置于所述阵列基板母板沿行方向的一侧，所述第一移位寄存器单元的输出端连接所述第一栅线的一端；所述第二栅极驱动电路设置于所述阵列基板母板沿列方向的一侧，所述第二移位寄存器单元的输出端连接所述第二栅线的一端。
本公开一种示例性实施例中，所述阵列基板母板还包括：第三栅极驱动电路、第四栅极驱动电路，第三栅极驱动电路设置于所述阵列基板母板沿行方向的另一侧，包括多个级联的第三移位寄存器单元，所述第三移位寄存器单元的输出端连接所述第一栅线的另一端；第四栅极驱动电路设置于所述阵列基板母板沿列方向的另一侧，包括多个级联的第四移位寄存器单元，所述第四移位寄存器单元的输出端连接所述第二栅线的另一端。
本公开一种示例性实施例中，所述第一移位寄存器单元和所述第二移位寄存器单元具有相同的结构，所述第一移位寄存器单元包括：第一输入电路、第二输入电路、第一输出电路、第二输出电路、隔离电路、第一控制电路、第二控制电路。第一输入电路连接第一电源端、第一节点、第一时钟信号端，用于响应所述第一时钟信号端的信号将所述第一电源端的信号传输到所述第一节点；第二输入电路连接所述第一时钟信号端、输入信号端、第二节点，用于响应所述第一时钟信号端的信号将所述输入信号端的信号传输到所述第二节点；第一输出电路连接所述第一节点、第二电源端、输出端，用于响应所述第一节点的信号将所述第二电源端的信号传输到所述输出端；第二输出电路连接所述输出端、第二时钟信号端、第三节点，用于响应所述第三节点的信号将所述第二时钟信号端的信号传输到所述输出端；隔离电路连接所述第二节点、第一电源端、第三节点，用于响应所述第一电源端的信号以连通所述第二节点和所述第三节点；第一控制电路连接所述第一节点、第一时钟信号端、第二节点，用于响应所述第二节点的信号将所述第一时钟信号端的信号传输到所述第一节点；第二控制电路连接所述第一节点、第二节点、第二电源端、第二时钟信号端，用于同时响应所述第一节点、第二时钟信号端的信号将连通所述第二电源端和所述第二节点。
本公开一种示例性实施例中，所述第一输入电路包括第三开关晶体管，第三开关晶体管的第一端连接所述第一电源端，第二端连接所述第一节点，控制端连接所述第一时钟信号端。第二输入电路包括第四开关晶体管，第四开关晶体管的第一端连接所述输入信号端，第二端连接所述第二节点，控制端连接所述第一时钟信号端。第一输出电路包括第五开关晶体管、第一电容，第五开关晶体管的第一端连接所述第二电源端，第二端连接所述输出端，控制端连接所述第一节点，第一电容连接于所述第二电源端和所述第一节点之间。第二输出电路包括第六开关晶体管、第二电容，第六开关晶体管的第一端连接所述第二时钟信号端，第二端连接所述输出端，控制端连接所述 第三节点，第二电容连接于所述第三节点和所述输出端之间。隔离电路包括第七开关晶体管，第七开关晶体管的第一端连接所述第二节点，第二端连接所述第三节点，控制端连接所述第一电源端。第一控制电路包括第八开关晶体管，第八开关晶体管的第一端连接所述第一节点，第二端连接所述第一时钟信号端，控制端连接所述第二节点。第二控制电路包括第九开关晶体管、第十开关晶体管，第九开关晶体管的第一端连接所述第二电源端，控制端连接所述第一节点。第十开关晶体管的第一端连接所述第九开关晶体管的第二端，第二端连接所述第二节点，控制端连接所述第二时钟信号端。
本公开一种示例性实施例中，所述第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元、第四移位寄存器单元的结构相同。
本公开一种示例性实施例中，所述第一移位寄存器单元、第二移位寄存器单元中的开关晶体管与所述阵列基板中像素电路的开关晶体管同层成型。
根据本公开的一个方面，提供一种阵列基板母板检测方法，用于检测上述的阵列基板母板，其包括：
利用所述第一栅极驱动电路和所述第二栅极驱动电路同时向目标阵列基板单元输入导通信号，以连接目标阵列基板单元的检查信号端和所述公共探针垫；
利用检测设备向所述公共探针垫发送或接收检测信号，以检测目标阵列基板单元。
根据本公开的一个方面，提供一种阵列基板，其由上述的阵列基板母板切割而成。
根据本公开的一个方面，提供一种显示装置，其包括上述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开阵列基板母板一种示例性实施例的结构示意图；
图2为图1中阵列基板单元的局部放大图；
图3为本公开阵列基板母板中开关电路一种示例性实施例的结构示意图；
图4为本公开阵列基板母板一种示例性实施例中第一移位寄存器单元的结构示意图；
图5为图4中第一移位寄存器单元一种驱动方法中各节点的时序图；
图6为本公开阵列基板母板中检测区的结构示意图；
图7为本公开阵列基板母板另一种示例性实施例的结构示意图；
图8为本公开阵列基板母板另一种示例性实施例中阵列基板单元的结构示意图；
图9为本公开阵列基板母板另一种示例性实施例中阵列基板单元的结构示意图；
图10为本公开阵列基板母板另一种示例性实施例中检测区的结构示意图；
图11为本公开阵列基板母板测试方法一种示例性实施例中第一栅极驱动电路和第二栅极驱动电路输出端的时序图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本示例性实施例提供一种阵列基板母板，如图1、2所示，图1为本公开阵列基板母板一种示例性实施例的结构示意图，图2为图1中阵列基板单元的局部放大图。该阵列基板母板包括用于外接检测设备的检测区1，所述阵列基板母板还包括公共探针垫2、多个行列分布的阵列基板单元、第一栅极驱动电路4、第二栅极驱动电路5。公共探针垫2设置于所述检测区1；每个所述阵列基板单元包括：阵列基板31、检测信号端32、开关电路33。检测信号端32用于向所述阵列基板31发送或接收检测信号；开关电路33连接第一控制信号端71、第二控制信号端72、所述公共探针垫2、检测信号端32，用于同时响应所述第一控制信号端71、第二控制信号端72的信号以导通所述公共探针垫2和所述检测信号端32；第一栅极驱动电路4包括多个级联的第一移位寄存器单元41，多个所述第一移位寄存器单元41的输出端分别与同一行所述开关电路33连接的第一控制信号端71连接；第二栅极驱动电路5括多个级联的第二移位寄存器单元51，多个所述第二移位寄存器单元51的输出端分别与同一列所述开关电路33连接的第二控制信号端72连接。其中，检测信号端可以与阵列基板中一条或多条信号线连接，该信号线可以为数据线。
本示例性实施例提供的阵列基板母板可以通过第一栅极驱动电路4和第二栅极驱动电路5定位目标阵列基板单元，从而导通公共探针垫和目标阵列基板单元中的检测信号端，以通过公共探针垫向目标阵列基板单元中的阵列基板提供检测信号。例如， 当第一栅极驱动电路向第二行开关电路提供导通信号，第二栅极驱动电路向第二列开关电路提供导通信号时，第二行第二列的阵列基板单元中的开关电路导通以连接公共探针垫和第二行第二列阵列基板单元中的检测信号端，从而使得公共探针垫向第二行第二列阵列基板单元中的阵列基板提供检测信号。本示例性实施例提供的阵列基板母板只需要将外部检测设备与公共探针垫对接，即可实现所有阵列基板的检查，从而极大的降低的阵列基板的检查时间。
本示例性实施例中，如图3所示，为本公开阵列基板母板中开关电路一种示例性实施例的结构示意图。所述开关电路可以包括：第一开关晶体管T1、第二开关晶体管T2。第一开关晶体管T1的第一端连接所述公共探针垫2，控制端连接所述第一控制信号端71；第二开关晶体管T2的第一端连接所述第一开关晶体管T1的第二端，第二端连接所述检测信号端32，控制端连接所述第二控制信号端72。应该理解的是，开关电路还可以有更多的结构可供选择，这些都属于本公开的保护范围。
本示例性实施例中，如图4所示，为本公开阵列基板母板一种示例性实施例中第一移位寄存器单元的结构示意图。所述第一移位寄存器单元可以包括：第一输入电路411、第二输入电路412、第一输出电路413、第二输出电路414、隔离电路415、第一控制电路416、第二控制电路417。第一输入电路411连接第一电源端VGL、第一节点N1、第一时钟信号端CK1，用于响应所述第一时钟信号端CK1的信号将所述第一电源端VGL的信号传输到所述第一节点N1。第二输入电路412连接所述第一时钟信号端CK1、输入信号端INPUT、第二节点N2，用于响应所述第一时钟信号端CK1的信号将所述输入信号端INPUT的信号传输到所述第二节点N2。第一输出电路413连接所述第一节点N1、第二电源端VGH、输出端OUT，用于响应所述第一节点N1的信号将所述第二电源端VGH的信号传输到所述输出端OUT。第二输出电路414连接所述输出端OUT、第二时钟信号端CK2、第三节点N3，用于响应所述第三节点N3的信号将所述第二时钟信号端CK2的信号传输到所述输出端OUT。隔离电路415连接所述第二节点N2、第一电源端VGL、第三节点N3，用于响应所述第一电源端VGL的信号以连通所述第二节点N2和所述第三节点N3。第一控制电路416连接所述第一节点N1、第一时钟信号端CK1、第二节点N2，用于响应所述第二节点N2的信号将所述第一时钟信号端CK1的信号传输到所述第一节点N1。第二控制电路417连接所述第一节点N1、第二节点N2、第二电源端VGH、第二时钟信号端CK2，用于同时响应所述第一节点N1、第二时钟信号端CK2的信号将连通所述第二电源端VGH和所述第二节点N2。
本示例性实施例中，所述第一输入电路411可以包括第三开关晶体管T3，第三开关晶体管T3的第一端连接所述第一电源端VGL，第二端连接所述第一节点N1，控制端连接所述第一时钟信号端CK1。第二输入电路412可以包括第四开关晶体管T4，第四开关晶体管T4的第一端连接所述输入信号端INPUT，第二端连接所述第二节点N2， 控制端连接所述第一时钟信号端CK1。第一输出电路413可以包括第五开关晶体管T5、第一电容C1，第五开关晶体管T5的第一端连接所述第二电源端VGH，第二端连接所述输出端OUT，控制端连接所述第一节点N1，第一电容C1连接于所述第二电源端VGH和所述第一节点N1之间。第二输出电路414可以包括第六开关晶体管T6、第二电容C2，第六开关晶体管T6的第一端连接所述第二时钟信号端CK2，第二端连接所述输出端OUT，控制端连接所述第三节点N3，第二电容C2连接于所述第三节点N3和所述输出端OUT之间。隔离电路415可以包括第七开关晶体管T7，第七开关晶体管T7的第一端连接所述第二节点N2，第二端连接所述第三节点N3，控制端连接所述第一电源端VGL。第一控制电路可以包括第八开关晶体管T8，第八开关晶体管T8的第一端连接所述第一节点N1，第二端连接所述第一时钟信号端CK1，控制端连接所述第二节点N2。第二控制电路417可以包括第九开关晶体管T9、第十开关晶体管T10，第九开关晶体管T9的第一端连接所述第二电源端VGH，控制端连接所述第一节点N1。第十开关晶体管T10的第一端连接所述第九开关晶体管的第二端，第二端连接所述第二节点N2，控制端连接所述第二时钟信号端CK2。本示例性实施例中，第三到第十开关晶体管可以为P型晶体管。
如图5所示，为图4中第一移位寄存器单元一种驱动方法中各节点的时序图。其中，第一电源端VGL恒为低电平，第二电源端VGH恒为高电平，第七开关晶体管T7恒导通。该第一移位寄存器单元的驱动方法包括4个阶段。在第一阶段T1：输入信号端INPUT、第一时钟信号端CK1输入低电平信号，第二时钟信号端CK2输入高电平信号，第三开关晶体管T3、第四开关晶体管T4导通，输入信号端INPUT的低电平信号向第二节点N2充电，并存储在第二电容C2中，第一电源端的低电平信号向第一节点N1充电，并存储在第一电容中，同时，第五开关晶体管T5、第六开关晶体管T6导通，第二电源端VGH、第二时钟信号端CK2向输出端OUT输出高电平信号。在第二阶段T2：输入信号端INPUT、第一时钟信号端CK1输入高电平信号，第二时钟信号端CK2输入低电平信号，第八开关晶体管T8导通，第一时钟信号端CK1的高电平信号传输到第一节点N1，从而第五开关晶体管T5关断，第四开关晶体管T4持续导通，第二时钟信号端CK2的低电平信号传输到输出端OUT。在第三阶段T3，输入信号端INPUT、第二时钟信号端CK2输出高电平，第一时钟信号端CK1输出低电平，第三开关晶体管T3导通，第一电源端VGL的低电平信号传输到第一节点，第五开关晶体管T5导通，第二电源端VGH向输出端OUT输入高电平信号，同时，第四开关晶体管T4导通，输入信号端INPUT的高电平信号传输到第二节点。在第四阶段T4，输入信号端INPUT、第一时钟信号端CK1输出高电平、第二时钟信号端CK2输出低电平，第十开关晶体管T10导通，第九开关晶体管T9导通，第二电源端VGH向第二节点输入高电平信号，第六开关晶体管T6关断，从而避免第二时钟信号端CK2的低电平信号传输到输出端OUT。
本示例性实施例中，第二移位寄存器单元可以与第一移位寄存器单元具有相同的结构。本实施例可以通过控制时钟信号端(包括第一时钟信号端、第二时钟信号端)、输入信号端的信号控制输出端OUT的信号时长，从而控制阵列基板的检测时长。本示例性实施例中，第一移位寄存器单元输出的有效时长可以是第二移位寄存器单元输出的有效时长的n倍，其中，n为阵列基板母板中阵列基板单元的列数。从而，该阵列基板母板可以实现阵列基板单元逐行逐个检测。
应该理解的是，在其他示例性实施例中，第一移位寄存器单元还可以有其他的结构，第一移位寄存器单元和第二移位寄存器单元的结构也可以不同，这些都属于本公开的保护范围。
本示例性实施例中，如图6所示，为本公开阵列基板母板中检测区的结构示意图，所述阵列基板母板还包括：第一控制探针垫组81、第二控制探针垫组82。第一控制探针垫组81设置于所述检测区1，用于向所述第一栅极驱动电路4输入时钟信号、输入信号；第二控制探针垫组设置于所述检测区，用于向所述第二栅极驱动电路输入时钟信号、输入信号。其中，第一控制探针垫组81可以包括多个探针垫，多个探针垫分别向第一移位寄存器单元中的第一时钟信号端、第二时钟信号端、输入信号端输入信号。第二控制探针垫组82可以包括多个探针垫，多个探针垫分别向第二移位寄存器单元中的第一时钟信号端、第二时钟信号端、输入信号端输入信号。
本示例性实施例中，如图6所示，所述阵列基板母板还可以包括：第一复位探针垫91、第二复位探针垫92。第一复位探针垫91可以设置于所述检测区1，连接每个所述第一移位寄存器单元的输出端；第二复位探针垫92可以设置于所述检测区1，连接每个所述第二移位寄存器单元的输出端。本实施例提供的阵列基板母板可以利用外部检测设备通过第一复位探针垫91向第一移位寄存器单元的输出端输入复位信号，从而终止目标阵列基板的检查。同理，本实施例还可以利用外部检测设备通过第二复位探针垫92向第二移位寄存器单元的输出端输入复位信号，从而终止目标阵列基板的检查。
本示例性实施例中，如图2所示，所述阵列基板母板还可以包括子探针垫10，子探针垫10连接所述检测信号端。本实施例可以利用检测设备通过子探针垫10直接对目标阵列基板进行检查。
本示例性实施例中，如图2所示，所述阵列基板单元还可以包括：第三复位探针垫93、第四复位探针垫94，第三复位探针垫93连接所述第一开关晶体管的第一控制信号端；第四复位探针垫94连接所述第二开关晶体管的第二控制信号端。本实施例可以利用外部检测设备通过第三复位探针垫93或第四复位探针垫94终止目标阵列基板的检查。
本示例性实施例中，如图8所示，为本公开阵列基板母板另一种示例性实施例中阵列基板单元的结构示意图。检测信号端可以通过数据选择器161连接阵列基板中的 多条信号线。数据选择器能够选择任意一条信号线与检测信号端连接。该设置能够通过一个检测信号端实现对每一条信号线的选择检测。
本示例性实施例中，如图9、10所示，图9为本公开阵列基板母板另一种示例性实施例中阵列基板单元的结构示意图，图10为本公开阵列基板母板另一种示例性实施例中检测区的结构示意图。所述阵列基板单元还可以包括多个检测信号端32，每个检测信号端可以通过数据选择器161与多条信号线连接。相应的，阵列基板单元还可以包括多个开关电路33，所述阵列基板母板还可以包括多个位于所述检测区的公共探针垫2，所述公共探针垫、开关电路、检测信号端可以一一对应设置。在一一对应设置的所述公共探针垫、开关电路、检测信号端中，所述开关电路33可以连接所述第一控制信号端、所述第二控制信号端、所述公共探针垫2、所述检测信号端32，用于同时响应所述第一控制信号端、第二控制信号端的信号以导通所述公共探针垫和所述检测信号端。此外，如图9所示，阵列基板单元还可以包括多个子探针垫10，多个子探针垫10可以与多个检测信号端一一对应连接。其中，在检测区内，多个公共探针垫2可以相邻设置，相应的，外部检测设备与阵列基板母板的连接部可以包括多个相邻的探针，外部检测设备与阵列基板母板对接时，多个探针可以与多个公共探针垫一一对应接触。同理，多个子探针垫10也可以相邻设置，从而使得外部检测设备中的多个探针可以直接与多个子探针垫10一一对应接触。
本示例性实施例中，如图2、8、9所示，所述阵列基板单元可以包括位于切割线A-A两侧的检测电路区121和基板区122；所述阵列基板31可以集成于所述基板区122，所述开关电路33、子探针垫10、第三复位探针垫93、第四复位探针垫94、数据选择器161可以集成于所述检测电路区121；其中，所述切割线为在模组工艺中所述阵列基板母板的切割路径。在阵列基板母板完成检测等工艺后，可以沿切割线切割阵列基板母板，从而形成单个阵列基板。
应该理解的是，在其他示例性实施例中，所述阵列基板单元可以包括位于切割线同一侧的检测电路区和基板区；所述阵列基板集成于所述基板区，所述开关电路、子探针垫、第三复位探针垫、第四复位探针垫集成于所述检测电路区；其中，所述切割线为在模组工艺中所述阵列基板母板的切割路径。在阵列基板母板完成检测等工艺后，可以沿切割线切割阵列基板母板，从而形成单个阵列基板，该单个阵列基板包括有位于检测电路区的各个元器件。
本示例性实施例中，如图1所示，所述阵列基板母板还可以包括：多条第一栅线131、多条第二栅线132，多条第一栅线131沿行方向延伸，且连接同一行所述开关电路中的第一控制信号端；多条第二栅线132沿列方向延伸，且连接同一列所述开关电路中的第二控制信号端；所述第一栅极驱动电路4可以设置于所述阵列基板母板沿行方向的一侧，所述第一移位寄存器单元41的输出端连接所述第一栅线的一端；所述第二栅极驱动电路5可以设置于所述阵列基板母板沿列方向的一侧，所述第二移位寄存 器单元51的输出端连接所述第二栅线的一端。
本示例性实施例中，第一栅线131和第二栅线132自身存在压降，因此，远离第一栅极驱动电路的阵列基板单元相较于接近第一栅极驱动电路的阵列基板单元，其接收到第一栅线传输的驱动信号的驱动能力较弱。远离第二栅极驱动电路的阵列基板单元相较于接近第二栅极驱动电路的阵列基板单元，其接收到第二栅线传输的驱动信号的驱动能力较弱。从而本示例性实施例可能造成远离第一栅极驱动电路、第二栅极驱动电路一侧的阵列基板单元可能无法充分导通其中的开关电路。本示例性实施例中，如图7所示，为本公开阵列基板母板另一种示例性实施例的结构示意图。所述阵列基板母板还可以包括：第三栅极驱动电路14、第四栅极驱动电路15，第三栅极驱动电路14可以设置于所述阵列基板母板沿行方向的另一侧，包括多个级联的第三移位寄存器单元141，所述第三移位寄存器单元141的41输出端连接所述第一栅线的另一端；第四栅极驱动电路15可以设置于所述阵列基板母板沿列方向的另一侧，包括多个级联的第四移位寄存器单元151，所述第四移位寄存器单元151的输出端连接所述第二栅线的另一端。其中，所述第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元、第四移位寄存器单元可以具有相同的结构。所述第一移位寄存器单元和第三移位寄存器单元可以同时向第一栅线提供驱动信号，第二移位寄存器单元和第四移位寄存器单元可以向第二栅线同时提供驱动信号，从而可以避免上述的“远离第一栅极驱动电路、第二栅极驱动电路一侧的阵列基板单元可以无法充分导通其中的开关电路”的技术问题。
本示例性实施例中，所述第一移位寄存器单元、第二移位寄存器单元以及第三移位寄存器单元、第四移位寄存器单元中的开关晶体管可以与所述阵列基板中像素电路的开关晶体管同层成型。即所述第一移位寄存器单元、第二移位寄存器单元以及第三移位寄存器单元、第四移位寄存器单元中的开关晶体管可以与阵列基板中像素电路的开关晶体管通过一组构图工艺形成。此外，需要说明的是，本示例性实施例中的探针垫均可以为暴露于阵列基板母板表面的导电垫。第一栅线、第二栅线可以位于阵列基板母板的表面也可以集成于阵列基板母板的内部。
本示例性实施例还提供一种阵列基板母板检测方法，用于检测上述的阵列基板母板，其包括：
利用所述第一栅极驱动电路和所述第二栅极驱动电路同时向目标阵列基板单元输入导通信号，以连接目标阵列基板单元的检查信号端和所述公共探针垫；
利用检测设备向所述公共探针垫发送或接收检测信号，以检测目标阵列基板单元。
本示例性实施例中，目标阵列基板单元可以包括一个阵列基板单元，该阵列基板母板检测方法可以实现阵列基板单元逐行逐个检测。根据上述内容可知，本实施例可以通过控制第一栅极驱动电路、第二栅极驱动电路中时钟信号端(包括第一时钟信号端、第二时钟信号端)、输入信号端的信号控制输出端OUT的信号时长，从而控制阵 列基板的检测时长。其中第一栅极驱动电路可以包括多个级联的第一移位寄存器单元，第二栅极驱动电路可以包括多个级联的第二移位寄存器单元。本示例性实施例中，如图11所示，为本公开阵列基板母板测试方法一种示例性实施例中第一栅极驱动电路和第二栅极驱动电路输出端的时序图。其中，OUT11表示第一级第一移位寄存器单元输出端的时序，OUT12表示第二级第一移位寄存器单元输出端的时序，OUT13表示第三级第一移位寄存器单元输出端的时序，OUT21表示第一级第二移位寄存器单元输出端的时序，OUT22表示第二级第二移位寄存器单元输出端的时序，OUT23表示第三级第二移位寄存器单元输出端的时序。该检测方法可以检测阵列基板单元为3乘3阵列的阵列基板母板。其中，第一移位寄存器单元输出有效信号的时长可以是第二移位寄存器单元输出信号有效时长的3倍。如图11所示，在T1时间段，第一级第一移位寄存器单元和第一级第二移位寄存器单元输出有效电平，该阵列基板母板可以对第一行第一列的阵列基板单元进行检查。在T2时间段，第一级第一移位寄存器单元和第二级第二移位寄存器单元输出有效电平，该阵列基板母板可以对第一行第二列的阵列基板单元进行检查。在T3时间段，第一级第一移位寄存器单元和第三级第二移位寄存器单元输出有效电平，该阵列基板母板可以对第一行第三列的阵列基板单元进行检查。依次类推，该阵列基板母板可以实现阵列基板单元逐行逐个检测。
应该理解的是，当阵列基板母板包括n列阵列基板单元时，第一移位寄存器单元输出的有效时长可以是第二移位寄存器单元输出的有效时长的n倍。目标阵列基板单元还可以包括多个阵列基板单元，该阵列基板母板检测方法还可以对多个阵列基板单元同时进行检查。
本示例性实施例提供的阵列基板母板检测方法已在上述内容中进行了详细说明，此处不再赘述。
本示例性实施例还提供一种阵列基板，其由上述的阵列基板母板切割而成。
本示例性实施例还提供一种显示装置，其包括上述的阵列基板，该显示装置可以为Micro LED显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (17)

  1. 一种阵列基板母板，其中，包括用于外接检测设备的检测区，所述阵列基板母板还包括：
    公共探针垫，设置于所述检测区；
    多个行列分布的阵列基板单元，每个所述阵列基板单元包括：
    阵列基板；
    检测信号端，用于向所述阵列基板发送或接收检测信号；
    以及开关电路，连接第一控制信号端、第二控制信号端、所述公共探针垫、检测信号端，用于同时响应所述第一控制信号端、第二控制信号端的信号以导通所述公共探针垫和所述检测信号端；
    第一栅极驱动电路，包括多个级联的第一移位寄存器单元，多个所述第一移位寄存器单元的输出端分别与同一行所述开关电路连接的第一控制信号端连接；
    以及第二栅极驱动电路，包括多个级联的第二移位寄存器单元，多个所述第二移位寄存器单元的输出端分别与同一列所述开关电路连接的第二控制信号端连接。
  2. 根据权利要求1所述的阵列基板母板，其中，所述阵列基板母板还包括：
    第一控制探针垫组，设置于所述检测区，用于向所述第一栅极驱动电路输入时钟信号、输入信号；
    第二控制探针垫组，设置于所述检测区，用于向所述第二栅极驱动电路输入时钟信号、输入信号。
  3. 根据权利要求1所述的阵列基板母板，其中，所述开关电路包括：
    第一开关晶体管，第一端连接所述公共探针垫，控制端连接所述第一控制信号端；
    第二开关晶体管，第一端连接所述第二开关晶体管的第二端，第二端连接所述检测信号端，控制端连接所述第二控制信号端。
  4. 根据权利要求1所述的阵列基板母板，其中，所述阵列基板母板还包括：
    第一复位探针垫，设置于所述检测区，连接每个所述第一移位寄存器单元的输出端；
    第二复位探针垫，设置于所述检测区，连接每个所述第二移位寄存器单元的输出端。
  5. 根据权利要求1所述的阵列基板母板，其中，所述阵列基板母板还包括：
    子探针垫，连接所述检测信号端。
  6. 根据权利要求3所述的阵列基板母板，其中，所述阵列基板单元还包括：
    第三复位探针垫，连接所述第一开关晶体管连接的第一控制信号端；
    第四复位探针垫，连接所述第二开关晶体管连接的第二控制信号端。
  7. 根据权利要求6所述的阵列基板母板，其中，所述阵列基板单元包括位于切割线两侧的检测电路区和基板区；
    所述阵列基板集成于所述基板区，所述开关电路、子探针垫、第三复位探针垫、第四复位探针垫集成于所述检测电路区；
    其中，所述切割线为在模组工艺中所述阵列基板母板的切割路径。
  8. 根据权利要求1所述的阵列基板母板，其中，所述阵列基板母板包括多个位于所述检测区的公共探针垫，所述阵列基板单元包括多个开关电路、多个检测信号端，所述公共探针垫、开关电路、检测信号端一一对应设置；
    在一一对应设置的所述公共探针垫、开关电路、检测信号端中，所述开关电路连接所述第一控制信号端、所述第二控制信号端、所述公共探针垫、所述检测信号端，用于同时响应所述第一控制信号端、第二控制信号端的信号以导通所述公共探针垫和所述检测信号端。
  9. 根据权利要求1所述的阵列基板母板，其中，所述阵列基板单元还包括数据选择器，所述检测信号端通过所述数据选择器与所述阵列基板中的多条信号线连接。
  10. 根据权利要求1所述的阵列基板母板，其中，所述阵列基板母板还包括：
    多条第一栅线，沿行方向延伸，且连接同一行所述开关电路中的第一控制信号端；
    多条第二栅线，沿列方向延伸，且连接同一列所述开关电路中的第二控制信号端；
    所述第一栅极驱动电路设置于所述阵列基板母板沿行方向的一侧，所述第一移位寄存器单元的输出端连接所述第一栅线的一端；
    所述第二栅极驱动电路设置于所述阵列基板母板沿列方向的一侧，所述第二移位寄存器单元的输出端连接所述第二栅线的一端。
  11. 根据权利要求10所述的阵列基板母板，其中，所述阵列基板母板还包括：
    第三栅极驱动电路，设置于所述阵列基板母板沿行方向的另一侧，包括多个级联的第三移位寄存器单元，所述第三移位寄存器单元的输出端连接所述第一栅线的另一端；
    第四栅极驱动电路，设置于所述阵列基板母板沿列方向的另一侧，包括多个级联的第四移位寄存器单元，所述第四移位寄存器单元的输出端连接所述第二栅线的另一 端；
    所述第一移位寄存器单元、第二移位寄存器单元、第三移位寄存器单元、第四移位寄存器单元的结构相同。
  12. 根据权利要求1所述的阵列基板母板，其中，所述第一移位寄存器单元和所述第二移位寄存器单元具有相同的结构，所述第一移位寄存器单元包括：
    第一输入电路，连接第一电源端、第一节点、第一时钟信号端，用于响应所述第一时钟信号端的信号将所述第一电源端的信号传输到所述第一节点；
    第二输入电路，连接所述第一时钟信号端、输入信号端、第二节点，用于响应所述第一时钟信号端的信号将所述输入信号端的信号传输到所述第二节点；
    第一输出电路，连接所述第一节点、第二电源端、输出端，用于响应所述第一节点的信号将所述第二电源端的信号传输到所述输出端；
    第二输出电路，连接所述输出端、第二时钟信号端、第三节点，用于响应所述第三节点的信号将所述第二时钟信号端的信号传输到所述输出端；
    隔离电路，连接所述第二节点、第一电源端、第三节点，用于响应所述第一电源端的信号以连通所述第二节点和所述第三节点；
    第一控制电路，连接所述第一节点、第一时钟信号端、第二节点，用于响应所述第二节点的信号将所述第一时钟信号端的信号传输到所述第一节点；
    第二控制电路，连接所述第一节点、第二节点、第二电源端、第二时钟信号端，用于同时响应所述第一节点、第二时钟信号端的信号将连通所述第二电源端和所述第二节点；
    所述第一输入电路包括：
    第三开关晶体管，第一端连接所述第一电源端，第二端连接所述第一节点，控制端连接所述第一时钟信号端；
    第二输入电路，包括：
    第四开关晶体管，第一端连接所述输入信号端，第二端连接所述第二节点，控制端连接所述第一时钟信号端；
    第一输出电路，包括：
    第五开关晶体管，第一端连接所述第二电源端，第二端连接所述输出端，控制端连接所述第一节点；
    第一电容，连接于所述第二电源端和所述第一节点之间；
    第二输出电路，包括：
    第六开关晶体管，第一端连接所述第二时钟信号端，第二端连接所述输出端，控制端连接所述第三节点；
    第二电容，连接于所述第三节点和所述输出端之间；
    隔离电路，包括：
    第七开关晶体管，第一端连接所述第二节点，第二端连接所述第三节点，控制端连接所述第一电源端；
    第一控制电路，包括：
    第八开关晶体管，第一端连接所述第一节点，第二端连接所述第一时钟信号端，控制端连接所述第二节点；
    第二控制电路，包括：
    第九开关晶体管，第一端连接所述第二电源端，控制端连接所述第一节点；
    第十开关晶体管，第一端连接所述第九开关晶体管的第二端，第二端连接所述第二节点，控制端连接所述第二时钟信号端。
  13. 根据权利要求6所述的阵列基板母板，其中，所述阵列基板单元包括位于切割线同一侧的检测电路区和基板区；
    所述阵列基板集成于所述基板区，所述开关电路、子探针垫、第三复位探针垫、第四复位探针垫集成于所述检测电路区；
    其中，所述切割线为在模组工艺中所述阵列基板母板的切割路径。
  14. 根据权利要求1所述的阵列基板母板，其中，所述第一移位寄存器单元、第二移位寄存器单元中的开关晶体管与所述阵列基板中像素电路的开关晶体管同层成型。
  15. 一种阵列基板母板检测方法，用于检测权利要求1-14任一项所述的阵列基板母板，其中，包括：
    利用所述第一栅极驱动电路和所述第二栅极驱动电路同时向目标阵列基板单元输入导通信号，以连接目标阵列基板单元的检查信号端和所述公共探针垫；
    利用检测设备向所述公共探针垫发送或接收检测信号，以检测目标阵列基板单元。
  16. 一种阵列基板，其中，由权利要求1-14任一项所述的阵列基板母板切割而成。
  17. 一种显示装置，其中，包括权利要求16所述的阵列基板。
PCT/CN2021/089693 2020-05-20 2021-04-25 阵列基板母板及其检测方法、阵列基板、显示装置 WO2021233078A1 (zh)

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