WO2022116371A1 - 显示面板及其检测方法和显示装置 - Google Patents

显示面板及其检测方法和显示装置 Download PDF

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Publication number
WO2022116371A1
WO2022116371A1 PCT/CN2021/072426 CN2021072426W WO2022116371A1 WO 2022116371 A1 WO2022116371 A1 WO 2022116371A1 CN 2021072426 W CN2021072426 W CN 2021072426W WO 2022116371 A1 WO2022116371 A1 WO 2022116371A1
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WIPO (PCT)
Prior art keywords
signal
scan
type transistor
detection
level
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PCT/CN2021/072426
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English (en)
French (fr)
Inventor
邹宗骏
孙莹
许育民
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厦门天马微电子有限公司
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Application filed by 厦门天马微电子有限公司 filed Critical 厦门天马微电子有限公司
Priority to US17/631,472 priority Critical patent/US11749179B2/en
Publication of WO2022116371A1 publication Critical patent/WO2022116371A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present application relates to the field of display technology, for example, to a display panel, a detection method thereof, and a display device.
  • the Thin Film Transistor (TFT) gate switch circuit is integrated on the array substrate of the display panel by adopting the Gate Driver on Array (GOA) technology of the array substrate to form the scanning drive for the display panel, so that the gate can be omitted. part of the pole driver chip.
  • GOA Gate Driver on Array
  • the GOA circuit is composed of a plurality of cascaded shift registers (Shift Registers), and can realize the bidirectional scanning function, that is, forward scanning and reverse scanning.
  • the output end of each stage of the shift register of the GOA circuit is connected to each row of pixel units
  • a finished or semi-finished display panel is usually tested to determine whether the functions of multiple structures in the display panel are normal. For example, a GOA circuit in the display panel is tested to determine whether the GOA circuit can operate normally.
  • the related art can only detect one of the scanning directions of the GOA circuit with the bidirectional scanning function, and cannot respectively detect the forward scanning function and the reverse scanning function of the GOA circuit with the bidirectional scanning function.
  • Embodiments of the present application provide a display panel, a detection method thereof, and a display device, so as to adopt a simple structure, the forward scanning function and the reverse scanning function of the scanning driving circuit in the display panel can be respectively detected.
  • a display panel comprising:
  • the plurality of signal pins include at least a start signal pin and a detection signal pin;
  • a scan drive circuit and a scan signal line includes N scan drive units arranged in cascade; wherein, N is a positive integer greater than or equal to 2; the scan signal output end of each level of the scan drive unit is connected to Each of the scan signal lines is electrically connected in a one-to-one correspondence; the forward scan input end of each level of the scan drive unit is electrically connected to the shift signal output end of the scan drive unit of the previous level of the scan drive unit of each level connection, and the reverse scan input end of each level of the scan drive unit is electrically connected to the shift signal output end of the next level scan drive unit of the scan drive unit of each level; the positive scan drive unit of the first level scan drive unit is electrically connected Both the scan input terminal and the reverse scan input terminal of the Nth-level scan drive unit are electrically connected to the start-up signal pins;
  • the first gating circuit includes a first switch unit and a second switch unit; the input end of the first switch unit is electrically connected with the scan signal detection end of the Nth-stage scan driving unit; the second switch unit has an electrical connection.
  • the input terminal is electrically connected to the scan signal detection terminal of the first-stage scan driving unit; the output terminal of the first switch unit and the output terminal of the second switch unit are both electrically connected to the detection signal pin;
  • the first switch unit is set to be turned on in the forward scan detection stage, and turned off in the reverse scan detection stage; the second switch unit is set to be turned on in the reverse scan detection stage, and in the forward scan detection stage The scan detection phase is closed;
  • the scan signal detection terminal of the N-th scan driving unit is the shift signal output terminal or the scan signal output terminal of the N-th scan driving unit;
  • the scan signal detection terminal of the first-level scan driving unit is The shift signal output terminal or the scan signal output terminal of the first-stage scan driving unit.
  • a detection method for a display panel is also provided, which is applied to the above-mentioned display panel, and the detection method at least includes: a forward scanning detection stage and a reverse scanning detection stage;
  • a start-up signal is provided, so that the scan driving units of the first stage to the Nth level scan driving unit output shift signals and scan signals in sequence; and , control the first switch unit to be turned on, the second switch unit to be turned off, receive the signal of the scan signal detection terminal of the Nth level scan drive unit through the first switch unit as the forward scan detection signal, and according to the The forward scanning detection signal detects the forward scanning function of the scanning driving circuit; wherein, the forward scanning detection signal is a shift signal or a scanning signal output by the Nth-stage scanning driving unit;
  • a start-up signal is provided, so that the multi-level scan driving units from the Nth level scan driving unit to the first level scan driving unit sequentially output shift signals and scan signals; and , control the first switch unit to be turned off, the second switch unit to be turned on, receive the signal of the scan signal detection terminal of the first-stage scan drive unit through the second switch unit as the reverse scan detection signal, and according to the
  • the reverse scan detection signal detects the reverse scan function of the scan drive circuit; wherein the reverse scan detection signal is a shift signal or a scan signal output by the first-stage scan drive unit.
  • a display device comprising: the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a first gating circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a scan driving unit provided by an embodiment of the present application.
  • FIG. 7 is a detection timing diagram of a scan drive circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a film layer structure of another display panel provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • 16 is a schematic structural diagram of a second gating circuit provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • 22 is a schematic diagram of a circuit structure of a scan driving unit provided by an embodiment of the present application.
  • FIG. 23 is a detection timing diagram of another scan drive circuit provided by an embodiment of the present application.
  • 24 is a schematic flowchart of a detection method provided by an embodiment of the present application.
  • 25 is a flowchart of a reverse scan detection method provided by an embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • an embodiment of the present application provides a display panel, the display panel includes a plurality of signal pins; the plurality of signal pins at least include a start-up signal pin and a detection signal pin; a scan drive circuit and a scan signal line ;
  • the scanning driving circuit comprises N scanning driving units arranged in cascade; wherein, N is a positive integer greater than or equal to 2; the scanning signal output end of each level scanning driving unit is electrically connected with each scanning signal line in one-to-one correspondence;
  • the forward scan input end of each level of scan drive unit is electrically connected to the shift signal output end of the scan drive unit of the previous level of the scan drive unit, and the reverse scan input end of each level of scan drive unit is electrically connected to the shift signal output end of the scan drive unit of the previous level.
  • the shift signal output end of the next level scan drive unit of the scan drive unit is electrically connected; the forward scan input end of the first level scan drive unit and the reverse scan input end of the Nth level scan drive unit are both connected to the start signal pin Electrical connection; a first gating circuit, including a first switch unit and a second switch unit; the input end of the first switch unit is electrically connected to the scan signal detection end of the Nth-stage scan drive unit; the input end of the second switch unit is connected to The scan signal detection terminal of the first-stage scan driving unit is electrically connected; the output terminal of the first switch unit and the output terminal of the second switch unit are both electrically connected to the detection signal pin; the first switch unit is set in the forward scan detection stage turn on, and turn off in the reverse scanning detection stage; the second switch unit is set to be turned on in the reverse scanning detection stage, and turned off in the forward scanning detection stage; wherein, the scanning signal detection terminal of the Nth-level scanning driving unit is The shift signal output terminal or scan signal output terminal of the Nth-level scan driving unit
  • the first switching unit when the forward scanning function of the scanning driving circuit is detected, the first switching unit is controlled to be turned on, and the forward scanning detection signal output by the Nth-stage scanning driving unit is received through the detection signal pin,
  • the second switching unit When the reverse scanning function of the scanning driving circuit is detected, the second switching unit is controlled to be turned on, and the reverse scanning detection signal output by the first-stage scanning driving unit is received through the detection signal pin, so as to enable the bidirectional scanning
  • the forward scanning function and reverse scanning function of the functional scanning driving circuit are detected respectively; at the same time, by setting the first gating circuit, the same detection signal pin can be used to receive the forward scanning detection signal and the reverse scanning detection signal respectively, Therefore, the number of detection signal pins provided in the display panel can be reduced, which is beneficial to simplify the structure of the display panel and reduce the cost of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel 100 includes a plurality of signal pins 30 , and the plurality of signal pins 30 can be in one-to-one correspondence with signal terminals in a chip (not shown in the figure) for driving or detecting the display panel 100 electrical connection.
  • the plurality of signal pins 30 at least include a start signal pin 31 and a detection signal pin 32 . Wherein, the start signal pin 31 can receive the start signal provided by the chip.
  • the display panel 100 is also provided with a scan drive circuit 10 and a scan signal line 20;
  • the scan drive circuit 10 includes N scan drive units (ASG1, ASG2, ASG3, . . . , ASGn-1, ASGn) arranged in cascade, and N is greater than or a positive integer equal to 2;
  • the scan signal output terminal OUT of each level of scan drive units (ASG1, ASG2, ASG3, ..., ASGn-1, ASGn) is electrically connected to each scan signal line 20 in one-to-one correspondence;
  • the first level The forward scan input terminal IN1 of the scan drive unit ASG1 is electrically connected to the start signal pin 31, and each level of scan drive units (ASG2, ASG3, . . .
  • ASGn of the second level scan drive unit ASG2 to the Nth level scan drive unit ASGn -1.
  • the forward scan input terminal IN1 of ASGn) is electrically connected to the shift signal output terminal Next of the previous level scan drive unit (ASG1, ASG2, ASG3, ..., ASGn-1); the Nth level scan drive unit ASGn
  • the reverse scan input terminal IN2 is electrically connected to the start signal pin 31, and each level of scan driving units (ASGn-1, . . . , ASG3,
  • the reverse scan input terminal IN2 of ASG2, ASG1 is electrically connected to the shift signal output terminal Next of the next-stage scan driving unit (ASGn, ASGn-1, . . . , ASG3, ASG2).
  • the first-stage scan driving unit ASG1 can generate the scan signal Gout1 and the shift signal Vnext1 according to the start-up signal of the start-up signal pin 31 , and pass the scan signal Gout1 through the first-stage scan driving unit
  • the scanning signal output terminal OUT of ASG1 is output to the corresponding scanning signal line 20, and the shift signal Vnext1 is output to the second-stage scanning driving unit ASG2 through the shifting signal output terminal Next of the first-stage scanning driving unit ASG1; the second-stage scanning driving unit ASG2;
  • the scan driving unit ASG2 generates the scan signal Gout2 and the shift signal Vnext2 according to the shift signal Vnext1 of the first-stage scan driving unit ASG1, and outputs the scan signal Gout2 to the corresponding The scan signal line 20, and the shift signal Vnext2 is output to the third level scan drive unit ASG3 through the shift signal output terminal Next of the second level scan drive unit ASG2; and so on, the Nth level scan drive unit ASGn
  • the N-th stage scan driving unit ASGn can generate the scan signal Goutn and the shift signal Vnextn according to the start signal of the start signal pin 31 , and pass the scan signal Goutn through the N-th level scan driving unit
  • the scan signal output terminal OUT of ASGn is output to the corresponding scan signal line 20, and the shift signal Vnextn is output to the N-1th level scan driving unit ASGn-1 through the shift signal output terminal Next of the Nth level scan driving unit ASGn
  • the second-level scan drive unit ASG2 generates scan signal Gout2 and shift signal Vnext2 according to the shift signal Vnext3 of the third-level scan drive unit ASG3, and scans the scan signal Gout2 through the scan of the second-level scan drive unit ASG2
  • the signal output terminal OUT is output to the corresponding scan signal line 20, and the shift signal Vnext2 is output to the first level scan driving unit ASG1 through the shift signal output terminal Next of the second level scan driving unit ASG2;
  • the multi-level scan driving units from the second level scan driving unit to the Nth level scan driving unit generate corresponding scan signals and shift signals in turn according to the shift signals of the scan driving units of the previous level.
  • any level of scan driving unit in the scan driving circuit is faulty, it will affect the Nth level scan driving unit to generate scan signals and shift signals.
  • each level of scan driving unit from the N-1 level scan driving unit to the first level scan driving unit can generate a scan signal and a shift signal according to the shift signal of the next level scan driving unit. so that when any one-level scan-driving unit in the scan-driving circuit is faulty, it will affect the first-level scan-driving unit to generate scan signals and shift signals.
  • the display panel 100 is further provided with a first gating circuit 40, the first gating circuit 40 includes a first switch unit 41 and a second switch unit 42; the input end of the first switch unit 41 is connected to the Nth switch unit 41.
  • the scan signal detection terminal of the first-level scan driving unit ASGn is electrically connected; the input terminal of the second switch unit 42 is electrically connected to the scan signal detection terminal of the first-level scan drive unit ASG1; the output terminal of the first switch unit 41 is electrically connected to the second switch unit
  • the output ends of 42 are all electrically connected to the detection signal pin 32 .
  • the first switching unit 41 is controlled to be turned on, and the second switching unit 42 is turned off, so that the forward scanning detection signal VtestF output by the Nth stage scanning driving unit passes through the first switching unit that is turned on 41 is transmitted to the detection signal pin 32; and in the reverse scan detection stage, the first switch unit 41 is controlled to be turned off, and the second switch unit 42 is turned on, so that the reverse scan detection signal VtestB output by the first-stage scan drive unit passes through The turned-on second switch unit 42 is transmitted to the detection signal pin 32 .
  • the scan signal detection terminal of the Nth level scan driving unit ASGn may be the shift signal output terminal Next of the Nth level scan driving unit ASGn
  • the scan signal detection terminal of the first level scan driving unit ASG1 is the first level scan driving unit The shift signal output terminal Next of ASG1.
  • a start-up signal is provided to the first-stage shift register unit through the start-up signal pin, and the shift signal output from the shift signal output end of the Nth-stage shift register unit is used as a forward scan detection signal, and the detection signal leads to
  • the pin and the turned-on first switch unit receive the forward scan detection signal, so as to be able to detect the forward scan function of the scan drive circuit according to the forward scan detection signal; correspondingly, move to the Nth stage through the start signal pin
  • the bit register unit provides a start signal, uses the shift signal output from the shift signal output end of the first-stage shift register unit as a reverse scan detection signal, and receives the reverse scan through the detection signal pin and the second switch unit that is turned on.
  • the scanning detection signal is used to detect the reverse scanning function of the scanning driving circuit according to the reverse scanning detection signal, so that the forward scanning function and the reverse scanning function of the display panel can be respectively realized through the same detection signal pin.
  • the detection is beneficial to reduce the number of signal pins set in the display panel, so that the number of signal terminals in the chip electrically connected to the signal pins of the display panel can be correspondingly reduced. Since the number of signal terminals of a chip is greater, the cost of the chip is higher, so the cost of the chip used in the display panel can be reduced, thereby helping to reduce the cost of the display panel using the chip.
  • FIG. 1 is only an exemplary drawing of an embodiment of the present application, and FIG. 1 only exemplarily shows that the shift signal output terminal Next of the N-th stage scan driving circuit ASGn is used as the output terminal Next of the N-th stage scan driving circuit ASGn
  • the scan signal detection terminal, and the shift signal output terminal Next of the first-level scan drive circuit ASG1 is used as the scan signal detection terminal of the first-level scan drive circuit ASG1; and in the embodiment of the present application, the Nth level scan can also be used.
  • the scan signal output end of the drive circuit is used as the scan signal detection end of the Nth level scan drive circuit; similarly, the scan signal output end OUT of the first level scan drive circuit ASG1 can be used as the scan signal of the first level scan drive circuit ASG1 detection end.
  • FIG. 2 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the input terminal of the first switching unit 41 of the first gating circuit 40 is electrically connected to the scan signal output terminal OUT of the N-th scan driving unit ASGn, that is, the scan signal output of the N-th scan driving unit ASGn
  • the terminal OUT is the scan signal detection terminal of the Nth-level scan driving unit ASGn, and uses the scan signal Goutn output by the scan signal output terminal OUT of the Nth-level scan driving unit ASGn as the forward scan detection signal to detect the scan signal Goutn of the scan driving circuit 10.
  • Forward scan function is the input terminal of the first switching unit 41 of the first gating circuit 40 .
  • the input terminal of the second switch unit 42 of the first gating circuit 10 is electrically connected to the scan signal output terminal OUT of the first-stage scan driving unit ASG1, that is, the scan signal output terminal OUT of the first-stage scan driving unit ASG1 is the first scan signal output terminal OUT.
  • the scanning signal detection terminal of the first-stage scanning driving unit ASG1 uses the scanning signal Gout1 output from the scanning signal output terminal OUT of the first-stage scanning driving unit ASG1 as the reverse scanning detection signal VnextB to detect the reverse scanning function of the scanning driving circuit 10 .
  • the shift signal output terminal of the Nth level scan driving unit is used as the scan signal detection terminal of the Nth level scan driving unit, and the first level scan driving unit
  • the output terminal of the shift signal is the scan signal detection terminal of the first-stage scan driving unit as an example to illustrate the technical solutions of the embodiments of the present application.
  • FIG. 1 only exemplarily shows that the scan drive circuit 10 is disposed in the non-display area 102 of the display area 101 side of the display panel 100 ; and in the embodiment of the present application, the scan drive circuit of the display panel may also be disposed in the The opposite sides of the display area are not limited in this embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the scan driving circuit of the display panel 100 includes a first scan driving circuit 110 and a second scan driving circuit 120 , and the first scan driving circuit 110 and the second scan driving circuit 120 are disposed at two opposite sides of the display area 101 . side.
  • the plurality of signal pins may include two enable signal pins 311 and 312 .
  • the forward scan input terminal IN1 of the first-level scan driving unit ASG1 of the first scan driving circuit 110 and the reverse scan input terminal IN2 of the N-th level scan driving unit ASGn are both electrically connected to the start signal pin 311, and the second The forward scan input terminal IN1 of the first stage scan driving unit ASG1 and the reverse scan input terminal IN2 of the Nth stage scan driving unit ASGn of the scan driving circuit 120 are both electrically connected to the enable signal pin 312 .
  • the display panel 100 may be provided with two first gating circuits 401 and 402 , and the plurality of signal pins may include two detection signal pins 321 and 322 .
  • the input terminal of the first switching unit 411 of the first gating circuit 401 is electrically connected to the scanning signal detection terminal of the Nth-stage scanning driving unit ASGn of the first scanning driving circuit 110
  • the second The input end of the switch unit 412 is electrically connected to the scan signal detection end of the first-stage scan drive unit ASG1 of the first scan drive circuit 110
  • the output terminals of the first gate circuit 402 are all electrically connected to the detection signal pin 321;
  • the input terminal of the first switch unit 421 of the first gating circuit 402 is electrically connected to the scan signal detection terminal of the Nth scan driving unit ASGn of the second scan driving circuit 120 , the input terminal of the second switching unit 422 of the first gating
  • the detection signal pin 321 is used to receive the forward scan detection signal and the reverse scan detection signal of the first scan driving circuit 110 in time
  • the pin 322 is used to receive the forward scan detection signal of the second scan driving circuit 120 in time. and the reverse scan detection signal, which is also beneficial to reduce the number of signal pins set in the display panel and reduce the cost of the display panel.
  • the embodiments of the present application all take the example that the scan driving circuit of the display panel is disposed on one side of the display area to exemplarily describe the technical solutions of the embodiments of the present application.
  • the structures of the first switch unit and the second switch unit in the first gating circuit are not limited in this embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a first gating circuit provided by an embodiment of the present application.
  • the first switch unit 41 of the first gating circuit 40 includes a first transmission gate, and the first transmission gate includes a first N-type transistor N1 and a first P-type transistor P1; the first N-type transistor N1
  • the first pole of the first P-type transistor P1 and the first pole of the first P-type transistor P1 are both the input terminals of the first switch unit 41;
  • the second pole of the first N-type transistor N1 and the second pole of the first P-type transistor P1 are the first An output terminal of the switch unit 41;
  • the gate of the first N-type transistor N1 receives the first control signal Vg1, and the gate of the first P-type transistor P1 receives the second control signal Vg2.
  • the second switch unit 42 of the first gating circuit 40 includes a second transmission gate, the second transmission gate includes a second N-type transistor N2 and a second P-type transistor P2; the first pole of the second N-type transistor N2 is connected to the second transmission gate.
  • the first poles of the two P-type transistors P2 are both the input terminals of the second switch unit 42 ; the second poles of the second N-type transistor N2 and the second poles of the second P-type transistor P2 are both the outputs of the second switch unit 42
  • the gate of the second N-type transistor N2 receives the third control signal Vg3, and the gate of the second P-type transistor P2 receives the fourth control signal Vg4.
  • the first control signal Vg1 controls the first N-type transistor N1 to turn on
  • the second control signal Vg2 controls the first P-type transistor P1 to turn on, so that the forward scanning detection output by the Nth stage scanning driving unit
  • the signal VtestF is transmitted to the detection signal pin through the first N-type transistor N1 and the first P-type transistor P1 of the first transmission gate, so that the loss of the forward scanning detection signal VtestF transmitted to the detection signal pin can be reduced, which is beneficial to improve the The accuracy when detecting the forward scan function of the scan drive circuit;
  • the third control signal Vg3 controls the second N-type transistor N2 to conduct, and the fourth control signal Vg4 controls the second P
  • the type transistor P2 is turned on, so that the reverse scan detection signal VtestB output by the first-stage scan driving unit is transmitted to the detection signal pin through the second N-type transistor N2 and the second P-type transistor P2 of the second transmission gate, thereby reducing the The loss of the reverse scan
  • the first control signal Vg1 may be multiplexed into a fourth control signal Vg4; the second control signal Vg2 may be multiplexed into a third control signal Vg3. Since the N-type transistor is turned on at a high level and turned off at a low level, and the P-type transistor is turned on at a low level and turned off at a high level; therefore, when the first control signal Vg1 is at a high level, the second control signal Vg2 is When the level is low, the first N-type transistor N1 and the first P-type transistor P1 can be controlled to be turned on, and the second N-type transistor N2 and the second P-type transistor P2 can be turned off; and when the first control signal Vg1 is at a low level, the first When the second control signal Vg2 is at a high level, the second N-type transistor N2 and the second P-type transistor P2 can be controlled to be turned on, and the first N-type transistor N1 and the first P-type transistor P1 can be turned off.
  • the first transmission gate and the second transmission gate can be time-divisionally turned on; It is beneficial to reduce the number of provided control signals, thereby reducing the number of signal pins provided in the display panel for providing control signals, simplifying the structure of the display panel, and reducing the cost of the display panel.
  • FIG. 5 is a schematic structural diagram of another display panel provided by an embodiment of the present application. 4 and 5, the plurality of signal pins 30 in the display panel 100 may further include a forward enable signal pin 33 and a reverse enable signal pin 34; the multi-level scan driving units (ASG1, ASG2, The forward scan enable terminals EN1 of ASG3,..., ASGn-1, ASGn) are all electrically connected to the forward enable signal pin 33. ) of the reverse scan enable terminal EN2 are all electrically connected to the reverse enable signal pin 34 .
  • the multi-level scan driving units ASG1, ASG2, The forward scan enable terminals EN1 of ASG3,..., ASGn-1, ASGn) are all electrically connected to the forward enable signal pin 33.
  • the reverse scan enable terminal EN2 are all electrically connected to the reverse enable signal pin 34 .
  • the gate of the first N-type transistor N1 and the gate of the second P-type transistor P2 may both be electrically connected to the forward enable signal pin 33, and the gate of the second N-type transistor N2 and the first The gates of the P-type transistors P1 are all electrically connected to the reverse enable signal pin 34 .
  • the forward enable signal U2D of the forward enable signal pin 33 will provide the positive direction of the multi-level scan drive units (ASG1, ASG2, ASG3, . . . , ASGn-1, ASGn)
  • the multi-level scan drive units ASG1, ASG2, ASG3, . . . , ASGn-1, ASGn
  • the reverse enable signal D2U of the signal pin 34 will be provided to the reverse scan enable terminal EN2 of the multi-level scan driving unit (ASG1, ASG2, ASG3, . . . , ASGn-1, ASGn), so that the multi-level scan driving unit (ASG1 , ASG2, ASG3, ..., ASGn-1, ASGn) to perform the reverse scanning process.
  • FIG. 6 is a schematic structural diagram of a scan driving unit provided by an embodiment of the present application.
  • each scan driving unit ASG may include an input module 11 , a shift module 12 and an output module 13 .
  • the input module 11 may include two transmission gates 111 and 112, and each transmission gate (111 and 112) may be composed of an N-type transistor and a P-type transistor.
  • the N-type transistor in the transmission gate 111 can be controlled by the forward enable signal U2D of the forward scan enable terminal EN1 and the reverse enable signal D2U of the reverse scan enable terminal EN2 and P-type transistors are both turned on, so that the forward scan input terminal IN1 signal is transmitted to the shift module 12, so that the shift module 12 can latch the signal, and output the shift signal through the scan drive unit of this stage
  • the terminal Next outputs the shift signal to the forward scan input terminal IN1 of the next level scan drive unit of this level of scan drive unit, and controls the output module 13 to generate a scan signal, and passes the scan signal through the scan signal of this level of scan drive unit
  • the output terminal OUT is output to the corresponding scan signal line 20 .
  • the scanning driving circuit 10 when the scanning driving circuit 10 is detected by forward scanning, a plurality of scanning driving units ASG of the scanning driving circuit 10 are required to perform the forward scanning process, and the detection signal leads to the scanning driving circuit 10 in turn.
  • the pin 32 and the conductive first switch unit 41 receive the forward scan detection signal output by the Nth-level scan drive unit ASGn; and when performing reverse scan detection on the scan drive circuit 10, multiple scans of the scan drive circuit 10 are required.
  • the driving unit ASG performs the process of reverse scanning, and sequentially receives the reverse scanning detection signal output by the first-stage scanning driving unit ASG1 through the detection signal pin 32 and the turned-on second switch unit 42; therefore, the first gating circuit
  • the gate of the first N-type transistor N1 of the first switching unit 41 of 40 may receive the same control signal as the gate of the N-type transistor of the transmission gate 111 of the input module 11 in the scan driving unit ASG, the first P-type transistor P1 can receive the same control signal as the gate of the P-type transistor of the transmission gate 111 of the input module 11 in the scan driving unit ASG; the second N-type transistor N2 of the second switch unit 42 of the first gating circuit 40
  • the gate can receive the same control signal as the gate of the N-type transistor of the transmission gate 112 of the input module 11 in the scan driving unit ASG, and the gate of the second P-type transistor P2 can be the same as the transmission gate of the input module 11 in the scan driving unit ASG.
  • the first N-type transistor, the second P-type transistor in the first gate circuit 40 and the N-type transistor of the transmission gate 111 and the P-type transistor of the transmission gate 112 of the input module 11 in the scan driving unit ASG are all connected to the same forward direction
  • the enable signal pin 33 is electrically connected to be able to be turned on or off under the control of the forward enable signal U2D of the forward enable signal pin 33; and the first P-type transistor P1 in the first gate circuit 40 , the second N-type transistor N2 and the P-type transistor of the transmission gate 111 of the input module 11 and the N-type transistor of the transmission gate 112 in the scan driving unit ASG are all electrically connected to the same reverse enable signal pin 34 to enable Turning on or off under the control of the reverse enable signal D2U to the enable signal pin 34 can reduce the number of signal pins provided in the display panel, thereby simplifying the structure of the display panel and reducing the cost of the display panel.
  • FIG. 7 is a detection timing diagram of a scan driving circuit provided by an embodiment of the present application. 4, 5 and 7, in the forward scan detection stage T1 of the scan drive circuit 10, the forward enable signal pin 33 provides a high level forward enable signal U2D to control the first N-type transistor N1 to conduct.
  • the reverse enable signal pin 34 provides a low-level reverse enable signal D2U to control the first P-type transistor P1 to turn on, the second N-type transistor N2 to turn off, and multi-level scanning
  • the driving unit ASG performs a forward scanning process, and sequentially receives the forward scanning detection signal VtestF output by the Nth-stage scanning driving unit ASGn through the detection signal pin 31, the first N-type transistor N1 and the first P-type transistor P1 that are turned on ;
  • the forward enable signal pin 33 provides a low level forward enable signal U2D to control the first N-type transistor N1 to close, the second P-type transistor P2 to lead
  • the reverse enable signal pin 34 provides a high level reverse enable signal D2U to control the first P-type transistor P1 to be turned off and the second N-type transistor N2 to be turned on, and the multi-level scan drive unit ASG performs reverse scan process, and sequentially receive the
  • FIG. 6 is only an exemplary drawing of the embodiment of the present application, and FIG. 6 exemplarily shows the structural composition of the scan driving unit ASG; and in the embodiment of the present application, in the multi-level scan driving that enables the scan driving circuit
  • the embodiment of the present application does not limit the structure of the scanning driving unit.
  • the display panel 100 further includes a reverse scan detection signal transmission line 50; the extension direction Y of the reverse scan detection signal transmission line 50 intersects with the extension direction X of the scan signal line 20; the second switch unit 42
  • the input terminal of 1 is electrically connected to the scan signal detection terminal of the first-stage scan driving unit ASG1 through the reverse scan detection signal transmission line 50 .
  • the reverse scanning detection signal output by the first-stage scanning driving unit ASG1 can be sequentially transmitted to the detection signal pin 32 through the reverse scanning detection signal transmission line 50 and the conductive second switch unit 42, In order to detect the reverse scanning function of the scanning driving circuit in the display panel.
  • FIG. 8 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the display panel is provided with a plurality of sub-pixels 60, a plurality of data signal lines 70 and a plurality of signal lines 80 arranged in an array; the plurality of sub-pixels 60 in the same row are electrically connected to the same scanning signal line 20 , so that the plurality of scanning signal lines 20 can transmit the scanning signals output by the multi-level scanning driving units ASG1, ASG2, ASG3, .
  • a plurality of sub-pixels 60 located in the same column are electrically connected to the same data signal line 70, so that the plurality of data signal lines 70 can provide data signals to the sub-pixels 60 in the corresponding row in a one-to-one correspondence when receiving valid scan signals.
  • Each sub-pixel 60 enables each sub-pixel 60 to be displayed according to the corresponding data signal; the extension direction Y of the signal line 80 intersects with the extension direction X of the scan signal line 20 , and the signal line 80 is connected to the scan signal line 20
  • Other signal lines different from the data signal lines 70 may be, for example, touch traces in the display panel 100 for transmitting touch signals to the touch electrodes 103 or receiving touch signals generated by the touch electrodes 103 .
  • the plurality of sub-pixels 60 may include a plurality of display sub-pixels 61 and a plurality of non-display sub-pixels 62 located on at least one side of the plurality of display sub-pixels 61; at this time, the data signal lines electrically connected to the same column of non-display sub-pixels 62 70 may be a dummy data signal line 72 to transmit the corresponding data signal to the corresponding non-display sub-pixel 62, and the data signal line 71 electrically connected to the display sub-pixel 61 in the same column transmits the corresponding data signal to the corresponding display sub-pixel 61 .
  • the display sub-pixels 61 emit light for display, while the non-display sub-pixels 62 do not emit light for display, so at least one dummy data signal line 72 can be multiplexed into the reverse scan detection signal transmission line 50 .
  • the dummy data signal line 72 can be directly used to transmit the reverse scanning detection signal output by the first-stage scanning driving unit ASG1, which can reduce the number of signal lines set in the display panel 100. , thereby simplifying the structure of the display panel 100 .
  • FIG. 8 is only an exemplary drawing of the embodiment of the present application, and FIG. 8 exemplarily shows that the dummy data signal line 72 is multiplexed into the reverse scan detection signal transmission line 50; and the premise of not affecting the normal display of the display panel Next, other existing signal lines can also be multiplexed into the reverse scan detection signal transmission line 50 .
  • FIG. 9 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the at least one signal line among the plurality of signal lines 80 eg, the touch electrodes 103
  • the at least one signal line can be 80 is used as a dummy signal trace 82
  • at least one dummy signal trace 82 is multiplexed into the reverse scan detection signal transmission line 50 .
  • the number of signal lines provided in the display panel 100 can also be reduced, thereby simplifying the structure of the display panel 100 .
  • the first-level scan driving unit ASG1 can also be the scan signal output terminal of the first-stage scan driving unit.
  • the dummy data signal line 72 when the dummy data signal line 72 is multiplexed into the reverse scan detection signal transmission line 50, and the scan signal output terminal OUT of the first-level scan driving unit ASG1 is used as the first-level scan drive
  • the dummy data signal line 72 can be electrically connected to the scan signal output terminal OUT of the first-stage scan driving unit ASG1 and the input terminal of the second switch unit 42 respectively.
  • the dummy signal trace 82 when the dummy signal trace 82 is multiplexed into the reverse scan detection signal transmission line 50 , and the scan signal output terminal OUT of the first-level scan driving unit ASG1 is used as the scan signal of the first-level scan driving unit ASG1
  • the dummy signal trace 82 can be electrically connected to the scan signal output terminal OUT of the first-stage scan driving unit ASG1 and the input terminal of the second switch unit 42 respectively.
  • the embodiments of the present application all take the multiplexing of dummy data signal lines into reverse scan detection signal transmission lines as an example to illustrate the technical solutions of the embodiments of the present application.
  • the above only exemplarily takes the signal wiring as the touch wiring as an example to illustrate the embodiment of the present application; and in the embodiment of the present application, the signal wiring may also be used to provide power signals to a plurality of sub-pixels
  • the type of the signal wiring is not limited in this embodiment of the present application.
  • FIG. 12 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present application.
  • the display panel includes a base substrate 1001 , and a first metal layer 1002 , a second metal layer 1003 and a third metal layer 1004 located on one side of the base substrate 1001 and provided with insulating intervals.
  • the first metal layer 1002 includes scan signal lines 20
  • the second metal layer 1003 includes data signal lines 70
  • the third metal layer 1004 includes signal lines 80 .
  • the scan signal lines 20 , the data signal lines 70 and the signal traces 80 are respectively arranged on different metal layers, and a corresponding insulating layer is arranged between any two adjacent metal layers, for example, the first metal layer 1002 and the An insulating layer 1005 is arranged between the second metal layers 1003, and an insulating layer 1006 is arranged between the second metal layer 1003 and the third metal layer 1004 to prevent signal lines of multiple metal layers from interfering with each other when transmitting signals.
  • each sub-pixel in the display panel may further include a switch transistor T, and the switch transistor T includes an active layer Tm, a gate electrode Tg, a source electrode Ts and a drain electrode Td.
  • the gate Tg of the switching transistor T in the sub-pixel and the scan signal line 20 can be set on the same metal layer, and the source Ts and drain Td of the switching transistor T in the sub-pixel can be set on the same metal layer as the data signal line 70 .
  • the display panel 100 further includes a first connection line 104 , and the extension direction of the first connection line 104 intersects with the extension direction of the reverse scan detection signal transmission line 50 ; the first connection line 104
  • the first end of the first connection line 104 is electrically connected to the input end of the second switch unit 42 through the reverse scan detection signal transmission line 50; the second end of the first connection line 104 is electrically connected to the scan signal detection end of the first-level scan driving unit ASG1.
  • the reverse scan detection signal output from the scan signal detection terminal of the first-stage scan driving unit ASG1 can be sequentially transmitted to the detection signal through the first connection line 104 , the reverse scan detection signal transmission line 50 and the turned-on second switch unit 42 .
  • the pin 32 is used to detect the reverse scan function of the scan driving circuit 10 in the display panel 100 according to the reverse scan detection signal received by the detection signal pin 32 .
  • the first connection line 104 may be disposed in the same layer as the scan signal line 20 .
  • the extension direction X of the scan signal line 20 and the extension direction X of the first connection line 104 both intersect with the extension direction Y of the data signal line 70 , the extension direction X of the first connection line 104 can be the same as that of the scan signal line.
  • the extension direction X of 20 is parallel. In this way, when the first connection lines 104 and the scan signal lines 20 are arranged in the same layer, the film layer design of the display panel can be simplified without affecting the scan signal transmission by the scan signal lines 20 , which is beneficial to the thinning of the display panel.
  • FIG. 12 is only an exemplary drawing of the embodiment of the present application, and FIG. 12 only exemplarily shows that the first connection line 104 and the scanning signal line 20 are arranged in the same layer; and in the embodiment of the present application, the first connection The line 104 may also be arranged on the same layer as the data signal line 70 (as shown in FIG. 13 ), or the first connection line 104 may be arranged on the same layer as the signal trace 80 (as shown in FIG. 14 ). In the embodiment of the present application, the first connection line 104 can be set by selecting an existing film layer with a lower impedance as much as possible, so as to ensure the accuracy of the reverse scan detection signal transmitted by the first connection line 104 .
  • the scan signal line 20 electrically connected to the scan signal output terminal OUT of the first-stage scan drive unit ASG1 of the scan drive circuit 10 is a dummy scan signal line 21 , and the dummy scan signal line 21 Not electrically connected to the display sub-pixel 61 .
  • the scan signal detection terminal of the first-level scan driving unit ASG1 is the scan signal output terminal OUT of the first-level scan driving unit ASG1
  • at least part of the dummy scan signal lines 21 are multiplexed into the first connection lines 104 .
  • At least part of the dummy scan signal lines 21 can be multiplexed into the first connection lines 104 , which can reduce the number of signal lines set in the display panel 100 and is beneficial to simplify the display The structure of the panel 100 .
  • FIG. 15 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the display panel 100 is further provided with a start-up signal transmission line 105 , the first end of the start-up signal transmission line 105 is electrically connected to the reverse scan input terminal IN2 of the N-th scan driving unit ASGn, and the start-up signal transmission line 105 The second end is electrically connected to the forward scan input terminal IN1 of the first-level scan drive unit ASG1; the start-up signal transmission line 105 is set to transmit the start-up signal of the start-up signal pin 31 to the positive direction of the first-level scan drive unit ASG1 respectively.
  • the scan input terminal IN1 and the reverse scan input terminal IN2 of the Nth-stage scan driving unit ASGn To the scan input terminal IN1 and the reverse scan input terminal IN2 of the Nth-stage scan driving unit ASGn.
  • the display panel 100 is further provided with a second gating circuit 90 and a switch module 901 ;
  • the second gating circuit 90 includes a third switching unit 91 and a fourth switching unit 92 ;
  • the terminals are also electrically connected to the output terminal of the third switch unit 91 and the input terminal of the fourth switch unit 92 respectively, and the second terminal of the start signal transmission line 105 is also electrically connected to the output terminal of the switch module 901;
  • the input end is electrically connected to the start signal pin 31;
  • the output end of the fourth switch unit 92 is electrically connected to the input end of the second switch unit 42;
  • the third switch unit 91 is configured to provide the start signal pin 31 with an effective pulse of the start signal
  • the fourth switch unit 92 is set to be turned on when the reverse scan detection signal is output;
  • the input terminal of the switch module 901 receives the fixed voltage signal VDD;
  • the control terminal of the switch module 901 scans with the first-stage scan driving unit ASG1
  • the third switch unit 91 of the second gating circuit 90 can be controlled to be turned on, so that the start signal provided by the start signal pin 31 can pass through the turned on third switch unit 91 It is transmitted to the start signal transmission line 105, and is transmitted from the start signal transmission line 105 to the forward scan input terminal IN1 of the first-stage scan driving unit ASG1, so that the multi-channel scanning from the first-stage scan driving unit ASG1 to the N-th level scan driving unit ASGn
  • the level scan driving unit generates the shift signal and the scan signal in turn; at the same time, by controlling the first switch unit 41 in the first gating circuit 40 to be turned on, the forward scan detection signal output by the Nth level scan driving unit ASGn can be It is transmitted to the detection signal pin 32 through the turned-on first switch unit 41 .
  • the third switch unit 91 of the second gate circuit 90 can be controlled to be turned on during the start time and the end time of the valid pulse of the start signal of the start signal pin 31, so that The effective pulse of the start signal of the start signal pin 31 is transmitted to the start signal transmission line 105 through the turned on third switch unit 91, and is transmitted by the start signal transmission line 105 to the reverse scan input terminal IN2 of the N-th scan drive unit ASGn,
  • the fourth switch unit 92 of the second gating circuit 90 and the second switching unit 42 of the first gating circuit 40 are controlled to be turned on, and the first switching unit 92 of the second gating circuit 90 is controlled to be turned on.
  • the three switch units 91 and the first switch unit 41 of the first gate circuit 40 are turned off, so that the switch module 901 outputs the reverse scan detection signal to the start signal transmission line 105 according to the signal of the scan signal detection terminal of the first-stage scan drive unit ASG1,
  • the signal is transmitted to the input end of the fourth switch unit 92 through the start signal transmission line 105 , and is sequentially transmitted to the detection signal pin 32 through the turned-on fourth switch unit 92 and the second switch unit 42 .
  • the second gating circuit 90 and the switch module 901 the detection of the forward scanning function and the reverse scanning function of the display panel is realized; at the same time, the start signal transmission line 105 is multiplexed as a reverse scanning signal transmitting the reverse scanning detection signal. Detecting the signal transmission lines in the scanning direction is beneficial to reduce the number of signal lines arranged in the display panel, thereby facilitating the narrow frame of the display panel and simplifying the structure of the display panel.
  • the third switch unit 91 and the fourth switch unit 92 in the second gating circuit 90 are turned on in a time-division manner, and can enable the start-up signal pin 31 in the forward scanning detection stage and the initial stage of the reverse scanning
  • the signal is transmitted to the start signal transmission line 105, and the reverse scan detection signal transmitted by the start signal transmission line 105 is transmitted to the detection signal pin in the output stage of the reverse scan detection signal.
  • the structures of the third switch unit and the fourth switch unit are not limited.
  • FIG. 16 is a schematic structural diagram of a second gating circuit provided by an embodiment of the present application.
  • the third switching unit 91 of the second gating circuit 90 includes a third transmission gate, and the third transmission gate includes a third N-type transistor N3 and a third P-type transistor P3; a third N-type transistor N3 and a third P-type transistor P3;
  • the first pole of the N-type transistor N3 and the first pole of the third P-type transistor P3 are both the input terminals of the third switch unit 91;
  • the second pole of the third N-type transistor N3 and the second pole of the third P-type transistor P3 Both are output terminals of the third switching unit 91;
  • the gate of the third N-type transistor N3 receives the fifth control signal Vg5, and the gate of the third P-type transistor P3 receives the sixth control signal Vg6.
  • the fourth switching unit 92 of the second gating circuit 90 includes a fourth transmission gate, and the fourth transmission gate includes a fourth N-type transistor N4 and a fourth P-type transistor P4; the first pole of the fourth N-type transistor N4 is connected to the The first pole of the four P-type transistor P4 is the input terminal of the fourth switch unit 92 ; the second pole of the fourth N-type transistor N4 and the second pole of the fourth P-type transistor P4 are both the output of the fourth switch unit 92
  • the gate of the fourth N-type transistor N4 receives the seventh control signal Vg7, and the gate of the fourth P-type transistor P4 receives the eighth control signal Vg8.
  • the fifth control signal Vg5 controls the third N-type transistor N3 to conduct
  • the sixth control signal Vg6 controls the third P-type transistor P3 to conduct, so that the start signal STV of the start signal pin 31 can pass through the first
  • the third N-type transistor N3 and the third P-type transistor P3 in the three transmission gates are transmitted to the start signal transmission line 105 to reduce the loss of the start signal transmitted to the start signal transmission line 105 and ensure that the first-stage scan driving unit ASG1 can receive accurate
  • the start-up signal so that the multi-level scan driving units from the first-level scan driving unit ASG1 to the N-th level scan driving unit ASGn can sequentially generate accurate shift signals and scan signals, so that the N-th level scan driving unit ASGn outputs accurate
  • the forward scan detection signal is obtained, thereby improving the detection accuracy of the forward scan function.
  • the fifth control signal Vg5 controls the third N-type transistor N3 to conduct
  • the sixth control signal Vg6 controls the third P
  • the type transistor P3 is turned on, so that the effective pulse of the start signal STV of the start signal pin 31 can be transmitted to the start signal transmission line 105 through the third N-type transistor N3 and the third P-type transistor P3 in the third transmission gate, so as to reduce the transmission to
  • the loss of the start-up signal STV of the start-up signal transmission line 105 ensures that the Nth-level scan drive unit ASGn can receive the accurate start-up signal STV, so that the multi-level scan drive from the Nth-level scan drive unit ASGn to the first-level scan drive unit ASG1
  • the unit can sequentially generate accurate shift signals and scan signals; and after the termination time of the effective pulse of the start signal STV of the start signal pin 31, the seventh control signal Vg7 controls the fourth N-type transistor N4 to conduct
  • the fourth N-type transistor N4 and the fourth P-type transistor P4 are transmitted to the second switch unit 42, so that the loss of the reverse scan detection signal can be reduced on the premise of multiplexing the start signal transmission line 105 to transmit the reverse scan detection signal, thereby reducing the loss of the reverse scan detection signal. It is beneficial to improve the detection accuracy of the reverse scan function of the scan driving circuit 10 .
  • the fifth control signal Vg5 may be multiplexed into the eighth control signal Vg8; the sixth control signal Vg6 may be multiplexed into the seventh control signal Vg7.
  • the N-type transistor is turned on at a high level and turned off at a low level, and the P-type transistor is turned on at a low level and turned off at a high level; therefore, when the fifth control signal Vg5 is at a high level, the sixth control signal Vg6 is When it is at a low level, the third N-type transistor N3 and the third P-type transistor P3 can be controlled to be turned on, and the fourth N-type transistor N4 and the fourth P-type transistor P4 can be turned off; and when the fifth control signal Vg5 is at a low level, the first When the six control signals Vg6 are at a high level, the fourth N-type transistor N4 and the fourth P-type transistor P4 can be controlled to be turned on, and the third N-type transistor N3 and the third P-type transistor P3 can be turned off
  • the third transmission gate and the fourth transmission gate can be time-divisionally turned on; at the same time,
  • the multiplexing of control signals is beneficial to reduce the number of provided control signals, thereby reducing the number of signal pins provided in the display panel for providing control signals, simplifying the structure of the display panel, and reducing the cost of the display panel.
  • FIG. 17 is a schematic structural diagram of another display panel provided by an embodiment of the present application. 16 and 17 , an inverter 902 is also provided in the display panel 100, and the plurality of signal pins 30 further include a control signal pin 35; the control signal pin 35 can be configured to provide the fifth control signal Vg5 ; The input of the inverter 902 is electrically connected to the control signal pin 35, and the output of the inverter 902 is electrically connected to the gate of the third P-type transistor P3 and the gate of the fourth N-type transistor N4; the third N The gate of the P-type transistor N3 and the gate of the fourth P-type transistor P4 are electrically connected to the control signal pin 35 .
  • the fifth control signal Vg5 can control the third N-type transistor N3 to be turned on, the fourth P-type transistor P4 to be turned off, and the high-level first
  • the fifth control signal Vg5 is converted into a low-level control signal after passing through the inverter 902 to control the third P-type transistor P3 to be turned on, and to control the fourth N-type transistor N4 to be turned off, so that the start signal pin 31 provides
  • the start signal STV can be transmitted to the start signal transmission line 105 through the third N-type transistor N3 and the third P-type transistor P3 that are turned on in the third transmission gate.
  • the four P-type transistor P4 is in an off state, so that the signal on the enable signal transmission line 105 cannot be transmitted to the detection signal pin 32 through the fourth transmission gate.
  • the fifth control signal Vg5 can control the third N-type transistor N3 to be turned off, the fourth P-type transistor P4 to be turned on, and the low-level fifth control signal Vg5
  • the fifth control signal Vg5 is converted into a high-level control signal after passing through the inverter 902 to control the third P-type transistor P3 to be turned off, and to control the fourth N-type transistor N4 to be turned on, so as to enable the signal on the signal transmission line 105 It can be transmitted to the detection signal pin 32 through the fourth N-type transistor N4 and the fourth P-type transistor P4 that are turned on in the fourth transmission gate.
  • the type transistor P3 is in an off state, so that the start signal STV provided by the start signal pin 31 cannot be transmitted to the start signal transmission line 105 through the third transmission gate.
  • control signal pin is set to control the third N-type transistor and the third P-type transistor of the third switch unit and the fourth N-type transistor and the fourth P-type transistor of the fourth switch unit in the second gating circuit.
  • the type transistor is time-divisionally turned on, thereby reducing the number of control signal pins provided in the display panel, which is beneficial to simplifying the structure of the display panel and reducing the cost of the display panel.
  • FIG. 17 is only an exemplary drawing of the embodiment of the present application, and FIG. 17 only exemplarily shows that the signal provided by the control signal pin is the fifth control signal; while in the embodiment of the present application, the signal provided by the control signal pin is the fifth control signal.
  • the control signal may also be a sixth control signal.
  • FIG. 18 is a schematic structural diagram of another display panel provided by an embodiment of the present application. 16 and 18, the input terminal of the inverter 902 is electrically connected to the control signal pin 35, and the output terminal of the inverter 902 is connected to the gate of the third N-type transistor N3 and the gate of the fourth P-type transistor P4. The gates are electrically connected; the gate of the third P-type transistor P3 and the gate of the fourth N-type transistor N4 are electrically connected to the control signal pin 35 . At this time, the control signal pin 35 is set to provide the sixth control signal Vg6.
  • the sixth control signal Vg6 can control the third P-type transistor P3 to be turned on, the fourth N-type transistor N4 to be turned off, and the low-level sixth control signal Vg6
  • the sixth control signal Vg6 is converted into a high-level control signal after passing through the inverter 902 to control the conduction of the third N-type transistor N3; and when the control signal pin 35 provides the high-level sixth control signal Vg6,
  • the sixth control signal Vg6 can control the fourth N-type transistor N4 to be turned on, the third P-type transistor P3 to be turned off, and the high-level sixth control signal Vg6 is converted into a low-level control after passing through the inverter 902 signal to control the third N-type transistor N3 to be turned off and the fourth P-type transistor P4 to be turned on.
  • the premise that the third N-type transistor and the third P-type transistor of the third switch unit in the second gating circuit can be controlled to be turned on in time division with the fourth N-type transistor and the fourth P-type transistor of the fourth switch unit Therefore, the number of control signal pins provided in the display panel can also be reduced, thereby facilitating the simplification of the structure of the display panel and reducing the cost of the display panel.
  • the scanning signal detection terminal of the first-stage scanning driving unit ASG1 may also be the scanning signal output terminal OUT of the first-stage scanning driving unit ASG1, as shown in FIG. 19 and FIG. 20 .
  • 17 and FIG. 18 reference may be made to the above description of FIG. 17 and FIG. 18 for the same points, which will not be repeated here.
  • the switch module 901 includes a switch transistor Tf; the gate of the switch transistor Tf is the control terminal of the switch module 901, the first pole of the switch transistor Tf is the input terminal of the switch module 901, and the first pole of the switch transistor Tf is the input terminal of the switch module 901.
  • the diode is the output terminal of the switch module 901 .
  • the gate of the switching transistor Tf receives the signal of the scanning detection terminal of the first-stage shift register unit ASG1, so that the switching transistor Tf can be based on the signal received by its gate and the fixed voltage signal of its first pole
  • the reverse scan detection signal is generated to the start signal transmission line 105, and is transmitted to the detection signal pin 32 by the start signal transmission line 105 through the turned-on fourth switch unit 92 and the second switch unit 42, so as to realize the reverse direction of the scan drive circuit 10 Scan function to detect.
  • the structure of the switch module shown in FIG. 17 is only an exemplary drawing of the embodiment of the present application.
  • the switch module can be made to generate a reverse scan detection signal according to the signals of the control terminal and the input terminal of the switch module.
  • the structure of the switch module is not limited in the embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • the control terminal of the switch module 901 may also be the first pole of the switch transistor Tf
  • the input terminal of the switch module 901 may be the gate of the switch transistor Tf
  • the output terminal of the switch module 901 may be the first pole of the switch transistor Tf Diode.
  • the switching transistor Tf can generate a reverse scan detection signal to the start signal transmission line 105 according to the signal output by the scan detection terminal of the first-stage scan drive unit ASG1 received by its first pole and the fixed voltage signal of its gate, and is activated by The signal transmission line 105 is transmitted to the detection signal pin 32 through the turned-on fourth switch unit 92 and the second switch unit 42 , which can also detect the reverse scan function of the scan drive circuit 10 .
  • the plurality of signal pins 30 further include a first level signal pin 36;
  • the level signal input terminals VGH are all electrically connected to the first level signal pin 36;
  • the first level signal pin 36 is set to provide the first level signal V1; wherein, the first level signal V1 can be multiplexed to provide Fixed voltage signal to the input of switch module 901 .
  • the multi-level scan driving unit may further include a first clock signal terminal, a second clock signal terminal, a second level signal input terminal, a reset signal input terminal, etc., so that in the forward scanning process, the multi-level scan driving unit can According to its forward scan enable terminal, reverse scan enable terminal, forward scan input terminal, first clock signal terminal, second clock signal terminal, first level signal input terminal, second level signal input terminal and The signal at the reset signal input terminal generates a scan signal and a shift signal in turn; and in the reverse scan process, the multi-level scan drive unit can be based on its forward scan enable terminal, reverse scan enable terminal, reverse scan input terminal, The signals of the first clock signal terminal, the second clock signal terminal, the first level signal input terminal, the second level signal input terminal and the reset signal input terminal sequentially generate the scan signal and the shift signal.
  • FIG. 22 is a schematic diagram of a circuit structure of a scan driving unit provided by an embodiment of the present application.
  • the scan driving unit ASG includes an input module 11 , a shift module 12 and an output module 13 .
  • the input module 11 is composed of two transmission gates 111 and 112 to control its forward scan input according to the forward enable signal U2D of the forward scan enable terminal EN1 and the reverse enable signal D2U of the reverse scan enable terminal EN2
  • the signal of the terminal IN1 or the reverse scan input terminal IN2 is transmitted to the shift module 12 .
  • the shift module 12 is composed of a first inverter 121 , a second inverter 124 , a first clocked inverter 122 , a second clocked inverter 123 and a reset unit 125 .
  • the input terminal of the first inverter 121 is electrically connected to the first clock signal terminal CK1, and the output terminal of the first inverter 121 is respectively connected to the control terminal of the first clocked inverter 122 and the control terminal of the second clocked inverter 123.
  • the input terminal of the first clock inverter 122 is electrically connected to the input module 11 to receive the signal from the forward scan input terminal IN1 or the reverse scan input terminal IN2 output by the input module 11 ; the first clock inverter 122
  • the output terminal of the second clocked inverter 122 is electrically connected to the input terminal of the second inverter 124, the clock terminal of the first clocked inverter 122 is electrically connected to the first clock signal terminal CK1; the input terminal of the second clocked inverter 123 is electrically connected to the second clocked inverter 123.
  • the output terminal of the inverter 124 is electrically connected, the clock terminal of the second clocked inverter 123 is electrically connected to the first clock signal terminal CK1, and the output terminal of the second clocked inverter 123 is electrically connected to the input terminal of the second clocked inverter 124. connection; the output end of the second inverter 124 is also electrically connected with the output module 13 and the shift signal output end Next.
  • the first inverter 121 is composed of a transistor M11 and a transistor M12, and outputs the first level signal terminal received by the first pole of the transistor M11 when the first clock signal CKV1 received by the first clock signal terminal CK1 is at a low level
  • the first clock inverter 122 is composed of transistors M13, M14, M15 and M16, and the first clock signal CKV1 received at the first clock signal terminal CK1 is high level and the input module 11 input is high level signal, the second level signal V2 of the second level signal terminal VGL received by the first pole of the output transistor M16, and the low level signal input to the input module 11 and the first inverter 121 to output the second level signal V2
  • the first level signal V1 of the first level signal When the level signal
  • the second level signal received by the first pole of the transistor M112 is output.
  • the second level signal V2 of the terminal VGL, and the first level signal V1 of the first level signal terminal VGH received by the first pole of the output transistor M111 when a low level signal is input to the input terminal of the second inverter 124 The control terminal of the reset unit 125 is electrically connected to the reset signal input terminal Rest, the input terminal of the reset unit 125 is electrically connected to the first level signal terminal VGH, and the output terminal of the reset unit 125 is electrically connected to the input terminal of the second inverter 124.
  • the reset unit 125 is composed of a transistor M113 to reset the signal at the input terminal of the second inverter 124 according to the reset signal Vrest of the reset signal input terminal Rest.
  • the output module 13 is composed of a NAND gate circuit 131 and a buffer circuit 132, wherein the NAND gate circuit 131 is composed of transistors M21, M22, M23 and M24, and realizes the second clock signal of the second clock signal terminal CK2 and the output of the shift module 12
  • the buffer circuit 132 is composed of three inverters composed of transistors M25, M26, M27, M28, M29 and M210 to transmit the signal output by the NAND gate circuit 131 to the scan signal output
  • the terminal OUT realizes the output of the scanning signal Gout.
  • FIG. 23 is a detection timing diagram of still another scan driving circuit provided by an embodiment of the present application. 17 , FIG. 23 and FIG. 22 , in the forward scan detection stage T1 , the fifth control signal Vg5 at the high level of the control signal pin 35 controls the third switch unit 91 in the second gating circuit 90 .
  • the three N-type transistors N3 and the third P-type transistor P3 are turned on, so that the start signal STV of the start signal pin 31 is transmitted to the positive terminal of the first-stage scan driving unit ASG1 through the turned-on third switch unit 91 and the start signal transmission line 105 To the scan input terminal IN1; the forward enable signal U2D of the high level of the forward enable signal pin 33 and the reverse enable signal D2U of the low level of the reverse enable signal pin 34 control the first strobe
  • the first N-type transistor N1 and the first P-type transistor P1 of the first switch unit 41 in the circuit 40 are turned on, and the signal of the forward scan input terminal IN1 of each stage of the scan driving unit ASG is input to the level of the scan driving unit ASG Shifting module 12, so that the shifting module 12 of each stage of the scanning driving unit ASG is selected according to the signal of the forward scanning input terminal IN1 of the scanning driving unit ASG of this stage and the first clock signal CKV1 of the first clock signal terminal CK1
  • the output module 13 of each level of scan drive unit ASG is based on the second clock signal CKV2 of the second clock signal terminal CK2 of the scan drive unit ASG of this level and the The shift signal Vnext of the shift module 12 of the level scan driving unit ASG selects the first level signal V1 of the first level signal terminal VGH or the second level of the second level signal terminal VGL of the level scan driving unit ASG
  • the signal V2 is used as its scanning signal Gout, and the scanning signals (Gout1, Gout2, Gout3, . . . , Goutn-1, Goutn ).
  • the forward scan detection signal of the scan signal detection terminal of the N-th scan driving unit ASGn is transmitted to the detection signal pin 32 through the first switch unit 41 that is turned on in the first gate circuit 40, so as to be able to lead the detection signal according to the detection signal.
  • the forward scanning detection signal received by the pin 32 detects the forward scanning function of the scanning driving circuit 10 .
  • the control signal pin 35 provides a fifth control signal with a high level during the period T21 ′ from the start time of the valid pulse of the start signal STV of the start signal pin 31 to the end time of its valid pulse T21 ′
  • Vg5 controls the third N-type transistor N3 and the third P-type transistor P3 of the third switch unit 91 in the second gating circuit 90 to be turned on, so that the start signal STV of the start signal pin 31 passes through the turned-on third switch unit 91
  • the start signal transmission line 105 is transmitted to the reverse scan input terminal IN2 of the N-th scan drive unit ASGn; and after the termination time T22' of the effective pulse of the start signal STV of the start signal pin 31, the control signal pin 35 provides a low
  • the fifth control signal Vg5 of the level controls the fourth N-type transistor and the fourth P-type transistor of the fourth switch unit 92 in the second gating circuit 90 to be turned on; at the same time, the low level of the forward enable signal pin 33
  • each level scan drive unit ASG is based on the second clock signal CKV2 of its second clock signal terminal CK2 and its shift module 12.
  • the shift signal Vnext selects the first level signal V1 of the first level signal terminal VGH or the second level signal V2 of the second level signal terminal VGL as its scan signal Gout, and scans the driving unit ASGn from the Nth stage
  • the multi-level scan driving units ASG to the first level scan driving unit ASG1 sequentially output scan signals (Goutn, Goutn-1, . . . , Gout3, Gout2, Gout1).
  • the switch module 901 generates a reverse scan detection signal according to the signal of the scan signal detection terminal of the first-stage scan driving unit ASG1 and the first level signal V1 of the first level signal pin 36, and transmits the reverse scan detection signal through the start signal transmission line 105,
  • the fourth switch unit 92 that is turned on in the second gating circuit 90 and the second switching unit 42 that is turned on in the first gating circuit 40 are transmitted to the detection signal pin 32 , so that the detection signal pin 32 can receive the reverse signal according to the detection signal pin 32 .
  • the reverse scan function of the scan drive circuit 10 is detected by the scan detection signal.
  • the reverse scanning detection signal is transmitted by multiplexing the start signal transmission line, so as to reduce the number of set in the display panel.
  • the number of signal lines is conducive to reducing the frame size of the display panel and increasing the screen ratio of the display panel; at the same time, the signal pins that provide the enable signal for the multi-level scanning driving unit are multiplexed to the first gating circuit.
  • a plurality of transistors in the second strobe circuit provide pins for control signals, and a plurality of transistors in the second gating circuit share the same signal pin to provide control signals, which can reduce the number of signal pins set in the display panel, which is conducive to simplifying the display panel. structure, reducing the cost of the display panel.
  • An embodiment of the present application further provides a detection method for a display panel, which can be used to detect the display panel provided by the embodiment of the present application, and the detection method for a display panel at least includes a forward scanning detection stage and a reverse scanning detection stage stage.
  • FIG. 24 is a schematic flowchart of a detection method provided by an embodiment of the present application. As shown in Figure 24, the detection method of the display panel includes:
  • the forward scan detection stage in the forward scan detection stage, provide a start signal, so that the multi-level scan driving units from the first level scan driving unit to the Nth level scan driving unit output the shift signal and the scan signal in sequence; and, control the first switch unit On, the second switch unit is turned off, the first switch unit receives the signal of the scan signal detection terminal of the N-th scan drive unit as the forward scan detection signal, and detects the forward scan function of the scan drive circuit according to the forward scan detection signal ; wherein, the forward scan detection signal is a shift signal or a scan signal output by the Nth-stage scan drive unit.
  • S120 in the reverse scan detection stage, provide a start signal, so that the multi-level scan drive units from the Nth level scan drive unit to the first level scan drive unit output shift signals and scan signals in sequence; and, control the first switch unit off, the second switch unit is turned on, the second switch unit receives the signal of the scan signal detection terminal of the first-stage scan drive unit as the reverse scan detection signal, and detects the reverse scan function of the scan drive circuit according to the reverse scan detection signal ; wherein, the reverse scan detection signal is a shift signal or a scan signal output by the first-stage scan drive unit.
  • a start-up signal is provided to the first-stage shift register unit through the start-up signal pin, and the shift signal output from the shift signal output end of the Nth-stage shift register unit is used as a forward scan detection signal, and the detection signal leads to
  • the pin and the turned-on first switch unit receive the forward scan detection signal, so as to be able to detect the forward scan function of the scan drive circuit according to the forward scan detection signal; correspondingly, move to the Nth stage through the start signal pin
  • the bit register unit provides a start signal, uses the shift signal output from the shift signal output end of the first-stage shift register unit as a reverse scan detection signal, and receives the reverse scan through the detection signal pin and the second switch unit that is turned on.
  • the scanning detection signal is used to detect the reverse scanning function of the scanning driving circuit according to the reverse scanning detection signal, so that the forward scanning function and the reverse scanning function of the display panel can be respectively realized through the same detection signal pin.
  • the detection is beneficial to reduce the number of signal pins set in the display panel, thereby facilitating the simplification of the structure of the display panel and reducing the cost of the display panel.
  • the first switch unit 41 of the first gating circuit 40 includes a first transmission gate, and the first transmission gate includes a first N-type transistor N1 and a first P-type transistor P1
  • the first pole of the first N-type transistor N1 and the first pole of the first P-type transistor P1 are both the input ends of the first switching unit 41; the second pole of the first N-type transistor N1 and the first P-type transistor P1
  • the second pole of each is the output end of the first switch unit 41; the gate of the first N-type transistor N1 receives the first control signal Vg1, and the gate of the first P-type transistor P1 receives the second control signal Vg2.
  • the second switch unit 42 of the first gating circuit 40 includes a second transmission gate, the second transmission gate includes a second N-type transistor N2 and a second P-type transistor P2; the first pole of the second N-type transistor N2 is connected to the second transmission gate.
  • the first poles of the two P-type transistors P2 are both the input terminals of the second switch unit 42 ; the second poles of the second N-type transistor N2 and the second poles of the second P-type transistor P2 are both the outputs of the second switch unit 42
  • the gate of the second N-type transistor N2 receives the third control signal Vg3, and the gate of the second P-type transistor P2 receives the fourth control signal Vg4.
  • the forward scan detection stage includes: providing a start-up signal, so that the multi-level scan driving units from the first level scan driving unit ASG1 to the Nth level scan driving unit ASGn sequentially output shift signals and scan signals;
  • the control signal Vg1 controls the first N-type transistor N1 to turn on
  • the second control signal Vg2 controls the first P-type transistor P1 to turn on
  • the third control signal Vg3 controls the second N-type transistor N2 to turn off
  • the fourth control signal Vg4 controls the second
  • the P-type transistor P2 is turned off, so that the first transmission gate is turned on, the second transmission gate is turned off, and the forward scanning detection signal of the scanning signal detection terminal of the N-th scan driving unit ASGn is received through the first transmission gate, and according to the forward scanning
  • the detection signal detects the forward scan function of the scan drive circuit 10 .
  • the reverse scan detection stage includes: providing a start-up signal, so that the multi-level scan driving units from the Nth level scan driving unit ASGn to the first level scan driving unit ASG1 sequentially output shift signals and scan signals; and, a first control signal Vg1 controls the first N-type transistor N1 to turn off, the second control signal Vg2 controls the first P-type transistor P1 to turn off, the third control signal Vg3 controls the second N-type transistor N2 to turn on, and the fourth control signal Vg4 controls the second P-type transistor P2 is turned on, so that the first transmission gate is turned off, the second transmission gate is turned on, and the reverse scanning detection signal of the scanning signal detection terminal of the first-stage scanning driving unit ASG1 is received through the turned-on second transmission gate, and according to the reverse scanning detection signal
  • the scan detection signal detects the reverse scan function of the scan drive circuit 10 .
  • the loss of the forward scanning detection signal during the transmission process can be reduced, so that when the forward scanning function of the display panel is detected according to the forward scanning detection signal , which can provide the detection accuracy of the forward scanning function of the display panel.
  • the second transmission gate is used to transmit the reverse scanning detection signal
  • the loss of the reverse scanning detection signal during transmission can be reduced, so that the reverse scanning function of the display panel can be detected according to the reverse scanning detection signal.
  • the detection accuracy of the reverse scanning function of the display panel can be provided.
  • the display panel 100 further includes a start-up signal transmission line 105 , a second gating circuit 90 and a switch module 901 ;
  • the second gating circuit 90 includes a third switching unit 91 and a fourth switching unit 92
  • the first end of the start-up signal transmission line 105 is electrically connected to the output end of the third switch unit 91, the input end of the fourth switch unit 92 and the reverse scan input end of the N-th scan drive unit ASGn;
  • the second terminal is respectively electrically connected to the forward scan input terminal of the first-stage scan driving unit ASG1 and the output terminal of the switch module 901;
  • the input terminal of the third switch unit 91 is electrically connected to the start signal pin 31;
  • the output terminal of the switch module 901 is electrically connected to the input terminal of the second switch unit 42; the input terminal of the switch module 901 receives a fixed voltage signal;
  • the control terminal of the switch module 901 is electrically connected to the scan signal detection terminal of the first
  • the reverse scan detection stage includes the first stage, the second stage and the third stage.
  • FIG. 25 is a flowchart of a reverse scan detection method provided by an embodiment of the present application. As shown in Figure 25, the reverse scan detection method includes:
  • the third switch unit is turned on, the fourth switch unit is turned off, and the start signal is output to the start signal transmission line through the third switch unit, so that the transmission line from the Nth level scan driving unit to the first level scan driving unit is
  • the multi-level scan driving unit sequentially outputs the scan signal and the shift signal.
  • the third switch unit of the second gating circuit is controlled to be turned on and the fourth switch unit is turned off, and the effective pulse of the start signal of the start signal pin is transmitted to the start signal transmission line through the turned on third switch unit, and The start signal transmission line is transmitted to the reverse scan input end of the Nth-level scan driving unit, so that the multi-level scan driving units from the Nth-level scan driving unit to the first-level scan driving unit sequentially generate shift signals and scan signals;
  • the start signal pin no longer provides a valid pulse of the start signal, at this time, the fourth switch unit of the second gate circuit and the second switch unit of the first gate circuit are controlled to be turned on, and the second switch unit of the second gate circuit is controlled to be turned on.
  • the third switch unit of the pass circuit and the first switch unit of the first gating circuit are closed, so that the switch module outputs the reverse scan detection signal to the start signal transmission line according to the signal of the scan signal detection terminal of the first-stage scan drive unit, and passes through the The start signal transmission line is transmitted to the input end of the fourth switch unit, and is sequentially transmitted to the detection signal pin through the turned-on fourth switch unit and the second switch unit.
  • the multiplexing start signal transmission line can transmit reverse scanning.
  • the detection signal is beneficial to reduce the number of signal lines arranged in the display panel, is beneficial to the narrow frame of the display panel, and increases the screen ratio of the display panel.
  • Embodiments of the present application further provide a display device, where the display device includes the display panel provided by the embodiments of the present application. Therefore, the display device has the technical features and effects of the display panel provided by the embodiment of the present application, and the similarities can be referred to the above description of the display panel provided by the embodiment of the present application, which will not be repeated here.
  • FIG. 26 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device 200 includes the display panel 100 provided by the embodiment of the present application.
  • the display device may be, for example, a vehicle-mounted display screen, a mobile phone, a computer display, and other known electronic devices.

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Abstract

一种显示面板及其检测方法和显示装置，显示面板（100）中设置有扫描驱动电路（10）、多个信号引脚（30）和第一选通电路（40）；多个信号引脚（30）包括检测信号引脚（32）和启动信号引脚（31）；扫描驱动电路（10）包括多个级联设置的扫描驱动单元（ASG1、ASG2、ASG3、…、ASGn-1、ASGn）；第一选通电路（40）包括第一开关单元（41）和第二开关单元（42）；第一开关单元（41）的输入端与第N级扫描驱动单元（ASGn）的扫描信号检测端电连接；第二开关单元（42）的输入端与第一级扫描驱动单元（ASG1）的扫描信号检测端电连接；第一开关单元（41）的输出端和第二开关单元（42）的输出端均与检测信号引脚（32）电连接；第一开关单元（41）设置为在正向扫描检测阶段导通，以及在反向扫描检测阶段关闭；第二开关单元（42）设置为在反向扫描检测阶段导通，以及在正向扫描检测阶段关闭。

Description

显示面板及其检测方法和显示装置
本申请要求在2020年12月04日提交中国专利局、申请号为202011409345.4的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，例如涉及一种显示面板及其检测方法和显示装置。
背景技术
采用阵列基板行驱动(Gate Driver on Array，GOA)技术将薄膜晶体管(Thin Film Transistor，TFT)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动芯片的部分。
GOA电路由多个级联的移位寄存器(Shift Register)构成，且能够实现双向扫描功能，即正向扫描和反向扫描，GOA电路的每一级移位寄存器的输出端连接每一行像素单元中的开关晶体管的栅极，以驱动对应行的像素单元。相关技术中，通常对成品或半成品的显示面板进行测试，以判断显示面板中多个结构的功能是否正常，例如对显示面板中的GOA电路进行测试，以判断GOA电路是否能够正常运行。
但是，相关技术仅能对具有双向扫描功能的GOA电路的其中一个扫描方向进行检测，而无法实现对具有双向扫描功能的GOA电路正向扫描功能和反向扫描功能分别进行检测。
发明内容
本申请实施例提供一种显示面板及其检测方法和显示装置，以采用简单的结构，能够分别对显示面板中扫描驱动电路的正向扫描功能和反向扫描功能进行检测。
提供了一种显示面板，包括：
多个信号引脚；所述多个信号引脚至少包括启动信号引脚和检测信号引脚；
扫描驱动电路和扫描信号线；所述扫描驱动电路包括N个级联设置的扫描驱动单元；其中，N为大于或等于2的正整数；每一级所述扫描驱动单元的扫描信号输出端与每条所述扫描信号线一一对应电连接；每一级所述扫描驱动单元的正向扫描输入端与所述每一级扫描驱动单元的上一级扫描驱动单元的移位 信号输出端电连接，以及每一级所述扫描驱动单元的反向扫描输入端与所述每一级扫描驱动单元的下一级扫描驱动单元的移位信号输出端电连接；第一级扫描驱动单元的正向扫描输入端和第N级扫描驱动单元的反向扫描输入端均与所述启动信号引脚电连接；
第一选通电路，包括第一开关单元和第二开关单元；所述第一开关单元的输入端与所述第N级扫描驱动单元的扫描信号检测端电连接；所述第二开关单元的输入端与所述第一级扫描驱动单元的扫描信号检测端电连接；所述第一开关单元的输出端和所述第二开关单元的输出端均与所述检测信号引脚电连接；所述第一开关单元设置为在正向扫描检测阶段导通，以及在反向扫描检测阶段关闭；所述第二开关单元设置为在所述反向扫描检测阶段导通，以及在所述正向扫描检测阶段关闭；
其中，所述第N级扫描驱动单元的扫描信号检测端为所述第N级扫描驱动单元的移位信号输出端或扫描信号输出端；所述第一级扫描驱动单元的扫描信号检测端为所述第一级扫描驱动单元的移位信号输出端或扫描信号输出端。
还提供了一种显示面板的检测方法，应用于上述显示面板，所述检测方法至少包括：正向扫描检测阶段和反向扫描检测阶段；
在所述正向扫描检测阶段，提供启动信号，以使所述第一级扫描驱动单元至所述第N级扫描驱动单元的多级所述扫描驱动单元依次输出移位信号和扫描信号；以及，控制所述第一开关单元导通，所述第二开关单元关闭，通过所述第一开关单元接收所述第N级扫描驱动单元的扫描信号检测端的信号作为正向扫描检测信号，并根据所述正向扫描检测信号检测所述扫描驱动电路的正向扫描功能；其中，所述正向扫描检测信号为所述第N级扫描驱动单元输出的移位信号或扫描信号；
在所述反向扫描检测阶段，提供启动信号，以使所述第N级扫描驱动单元至所述第一级扫描驱动单元的多级所述扫描驱动单元依次输出移位信号和扫描信号；以及，控制所述第一开关单元关闭，所述第二开关单元导通，通过所述第二开关单元接收所述第一级扫描驱动单元的扫描信号检测端的信号作为反向扫描检测信号，并根据所述反向扫描检测信号检测所述扫描驱动电路的反向扫描功能；其中，所述反向扫描检测信号为所述第一级扫描驱动单元输出的移位信号或扫描信号。
还提供一种显示装置，包括：上述显示面板。
附图说明
图1是本申请实施例提供的一种显示面板的结构示意图；
图2是本申请实施例提供的又一种显示面板的结构示意图；
图3是本申请实施例提供的又一种显示面板的结构示意图；
图4是本申请实施例提供的一种第一选通电路的结构示意图；
图5是本申请实施例提供的又一种显示面板的结构示意图；
图6是本申请实施例提供的一种扫描驱动单元的结构示意图；
图7是本申请实施例提供的一种扫描驱动电路的检测时序图；
图8是本申请实施例提供的又一种显示面板的结构示意图；
图9是本申请实施例提供的又一种显示面板的结构示意图；
图10是本申请实施例提供的又一种显示面板的结构示意图；
图11是本申请实施例提供的又一种显示面板的结构示意图；
图12是本申请实施例提供的一种显示面板的膜层结构示意图；
图13是本申请实施例提供的又一种显示面板的膜层结构示意图；
图14是本申请实施例提供的又一种显示面板的膜层结构示意图；
图15是本申请实施例提供的又一种显示面板的结构示意图；
图16是本申请实施例提供的一种第二选通电路的结构示意图；
图17是本申请实施例提供的又一种显示面板的结构示意图；
图18是本申请实施例提供的又一种显示面板的结构示意图；
图19是本申请实施例提供的又一种显示面板的结构示意图；
图20是本申请实施例提供的又一种显示面板的结构示意图；
图21是本申请实施例提供的又一种显示面板的结构示意图；
图22是本申请实施例提供的一种扫描驱动单元的电路结构示意图；
图23为本申请实施例提供的又一种扫描驱动电路的检测时序图；
图24是本申请实施例提供的一种检测方法的流程示意图；
图25是本申请实施例提供的一种反向扫描检测方法的流程图；
图26是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请进行说明。此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
当对具有双向扫描功能的扫描驱动电路进行检测时，仅设置一个检测信号引脚只能实现对该扫描驱动电路的正向扫描或反向扫描进行检测，而想要实现对扫描驱动电路的正向扫描和反向扫描的分别检测，则需要分别设置正向扫描检测引脚和反向扫描检测引脚，这样会增加显示面板中所设置的检测引脚的数量，从而相对增加对该显示面板进行检测时所使用的芯片中检测引脚的数量，这无疑将增加芯片的成本，即增加采用该芯片对显示面板进行检测时的检测成本。因此，如何在不增加检测引脚的前提下，分别对显示面板的正向扫描功能和反向扫描功能进行检测，成为当前亟待解决的问题。
为解决上述技术问题，本申请实施例提供一种显示面板，该显示面板包括多个信号引脚；多个信号引脚至少包括启动信号引脚和检测信号引脚；扫描驱动电路和扫描信号线；扫描驱动电路包括N个级联设置的扫描驱动单元；其中，N为大于或等于2的正整数；每一级扫描驱动单元的扫描信号输出端与每条扫描信号线一一对应电连接；每一级扫描驱动单元的正向扫描输入端与该级扫描驱动单元的上一级扫描驱动单元的移位信号输出端电连接，以及每一级扫描驱动单元的反向扫描输入端与该级扫描驱动单元的下一级扫描驱动单元的移位信号输出端电连接；第一级扫描驱动单元的正向扫描输入端和第N级扫描驱动单元的反向扫描输入端均与启动信号引脚电连接；第一选通电路，包括第一开关单元和第二开关单元；第一开关单元的输入端与第N级扫描驱动单元的扫描信号检测端电连接；第二开关单元的输入端与第一级扫描驱动单元的扫描信号检测端电连接；第一开关单元的输出端和第二开关单元的输出端均与检测信号引脚电连接；第一开关单元设置为在正向扫描检测阶段导通，以及在反向扫描检测阶段关闭；第二开关单元设置为在反向扫描检测阶段导通，以及在正向扫描检测阶段关闭；其中，第N级扫描驱动单元的扫描信号检测端为第N级扫描驱动单元的移位信号输出端或扫描信号输出端；第一级扫描驱动单元的扫描信号检测端为第一级扫描驱动单元的移位信号输出端或扫描信号输出端。
采用上述技术方案，通过在对扫描驱动电路的正向扫描功能进行检测时，控制第一开关单元导通，并通过检测信号引脚接收由第N级扫描驱动单元输出的正向扫描检测信号，而在对扫描驱动电路的反向扫描功能进行检测时控制第二开关单元导通，并通过检测信号引脚接收由第一级扫描驱动单元输出的反向扫描检测信号，以能够对具有双向扫描功能的扫描驱动电路的正向扫描功能和 反向扫描功能分别进行检测；同时，通过设置第一选通电路，能够采用同一检测信号引脚分别接收正向扫描检测信号和反向扫描检测信号，从而能够减少显示面板中所设置的检测信号引脚的数量，有利于简化显示面板的结构，降低显示面板的成本。
以下将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
图1是本申请实施例提供的一种显示面板的结构示意图。如图1所示，显示面板100包括多个信号引脚30，该多个信号引脚30能够与用于驱动或检测显示面板100的芯片(图中未示出)中的信号端子一一对应电连接。该多个信号引脚30中至少包括启动信号引脚31和检测信号引脚32。其中，启动信号引脚31能够接收芯片提供的启动信号。
显示面板100中还设置有扫描驱动电路10和扫描信号线20；扫描驱动电路10包括N个级联设置的扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)，N为大于或等于2的正整数；每一级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)的扫描信号输出端OUT与每条扫描信号线20一一对应电连接；第一级扫描驱动单元ASG1的正向扫描输入端IN1与启动信号引脚31电连接，第二级扫描驱动单元ASG2至第N级扫描驱动单元ASGn的每一级扫描驱动单元(ASG2、ASG3、…、ASGn-1、ASGn)的正向扫描输入端IN1与其上一级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1)的移位信号输出端Next电连接；第N级扫描驱动单元ASGn的反向扫描输入端IN2与启动信号引脚31电连接，第N-1级扫描驱动单元ASGn-1至第一级扫描驱动单元ASG1的每一级扫描驱动单元(ASGn-1、…、ASG3、ASG2、ASG1)的反向扫描输入端IN2与其下一级扫描驱动单元(ASGn、ASGn-1、…、ASG3、ASG2)的移位信号输出端Next电连接。
在扫描驱动电路10进行正向扫描时，第一级扫描驱动单元ASG1能够根据启动信号引脚31的启动信号产生扫描信号Gout1和移位信号Vnext1，并将扫描信号Gout1通过第一级扫描驱动单元ASG1的扫描信号输出端OUT输出至对应的扫描信号线20，以及将移位信号Vnext1通过第一级扫描驱动单元ASG1的移位信号输出端Next输出至第二级扫描驱动单元ASG2；第二级扫描驱动单元ASG2根据第一级扫描驱动单元ASG1的移位信号Vnext1产生扫描信号Gout2和移位信号Vnext2，并将扫描信号Gout2通过第二级扫描驱动单元ASG2的扫描信号输出端OUT输出至对应的扫描信号线20，以及将移位信号Vnext2通过第二级扫描驱动单元ASG2的移位信号输出端Next输出至第三级扫描驱动单元ASG3；以此类推，第N级扫描驱动单元ASGn根据第N-1级扫描驱动单元 ASGn-1的移位信号Vnextn-1产生扫描信号Goutn和移位信号Vnextn，并将扫描信号Goutn通过第N级扫描驱动单元ASGn的扫描信号输出端OUT输出至对应的扫描信号线20。
在扫描驱动电路10进行反向扫描时，第N级扫描驱动单元ASGn能够根据启动信号引脚31的启动信号产生扫描信号Goutn和移位信号Vnextn，并将扫描信号Goutn通过第N级扫描驱动单元ASGn的扫描信号输出端OUT输出至对应的扫描信号线20，以及将移位信号Vnextn通过第N级扫描驱动单元ASGn的移位信号输出端Next输出至第N-1级扫描驱动单元ASGn-1；以此类推，第二级扫描驱动单元ASG2根据第三级扫描驱动单元ASG3的移位信号Vnext3产生扫描信号Gout2和移位信号Vnext2，并将扫描信号Gout2通过第二级扫描驱动单元ASG2的扫描信号输出端OUT输出至对应的扫描信号线20，以及将移位信号Vnext2通过第二级扫描驱动单元ASG2的移位信号输出端Next输出至第一级扫描驱动单元ASG1；第一级扫描驱动单元ASG1根据第二级扫描驱动单元ASG2的移位信号Vnext2产生扫描信号Gout1和移位信号Vnext1，并将扫描信号Gout1通过第一级扫描驱动单元ASG1的扫描信号输出端OUT输出至对应的扫描信号线20。
由于在正向扫描时，第二级扫描驱动单元至第N级扫描驱动单元中的多级扫描驱动单元根据其上一级扫描驱动单元的移位信号，依次产生相应的扫描信号和移位信号，因此当扫描驱动电路中的任意一级扫描驱动单元存在故障时，都会影响第N级扫描驱动单元产生扫描信号和移位信号。同时，在反向扫描时，第N-1级扫描驱动单元至第一级扫描驱动单元中的每一级扫描驱动单元可根据其下一级扫描驱动单元的移位信号产生扫描信号和移位信号，使得当扫描驱动电路中的任意一级扫描驱动单元存在故障时，都会影响第一级扫描驱动单元产生扫描信号和移位信号。
继续参考图1，显示面板100中还设置有第一选通电路40，该第一选通电路40包括第一开关单元41和第二开关单元42；第一开关单元41的输入端与第N级扫描驱动单元ASGn的扫描信号检测端电连接；第二开关单元42的输入端与第一级扫描驱动单元ASG1的扫描信号检测端电连接；第一开关单元41的输出端和第二开关单元42的输出端均与检测信号引脚32电连接。此时，在正向扫描检测阶段，控制第一开关单元41导通，第二开关单元42关闭，以使第N级扫描驱动单元输出的正向扫描检测信号VtestF通过导通的第一开关单元41传输至检测信号引脚32；而在反向扫描检测阶段，控制第一开关单元41关闭，第二开关单元42导通，以使第一级扫描驱动单元输出的反向扫描检测信号VtestB通过导通的第二开关单元42传输至检测信号引脚32。其中，第N级扫描驱动单元ASGn的扫描信号检测端可以为第N级扫描驱动单元ASGn的移位信号输 出端Next，第一级扫描驱动单元ASG1的扫描信号检测端为第一级扫描驱动单元ASG1的移位信号输出端Next。
如此，通过启动信号引脚向第一级移位寄存单元提供启动信号，将第N级移位寄存单元的移位信号输出端输出的移位信号作为正向扫描检测信号，并通过检测信号引脚和导通的第一开关单元接收正向扫描检测信号，以能够根据该正向扫描检测信号对扫描驱动电路的正向扫描功能进行检测；相应的，通过启动信号引脚向第N级移位寄存单元提供启动信号，将第一级移位寄存单元的移位信号输出端输出的移位信号作为反向扫描检测信号，并通过检测信号引脚和导通的第二开关单元接收反向扫描检测信号，以能够根据该反向扫描检测信号对扫描驱动电路的反向扫描功能进行检测，从而能够通过同一检测信号引脚，分别实现对显示面板的正向扫描功能和反向扫描功能的检测，有利于减少显示面板中所设置的信号引脚数量，从而能够对应减小与该显示面板的信号引脚电连接的芯片中的信号端子的数量。由于芯片的信号端子的数量越多，该芯片的成本越高，因此能够降低该显示面板所使用的芯片的成本，从而有利于降低采用该芯片的显示面板的成本。
图1仅为本申请实施例示例性的附图，图1中仅示例性的示出了，将第N级扫描驱动电路ASGn的移位信号输出端Next作为该第N级扫描驱动电路ASGn的扫描信号检测端，以及将第一级扫描驱动电路ASG1的移位信号输出端Next作为第一级扫描驱动电路ASG1的扫描信号检测端；而在本申请实施例中，还可以将第N级扫描驱动电路的扫描信号输出端作为该第N级扫描驱动电路的扫描信号检测端；同样的，可以将第一级扫描驱动电路ASG1的扫描信号输出端OUT作为第一级扫描驱动电路ASG1的扫描信号检测端。
示例性的，图2是本申请实施例提供的又一种显示面板的结构示意图。如图2所示，第一选通电路40的第一开关单元41的输入端与第N级扫描驱动单元ASGn的扫描信号输出端OUT电连接，即第N级扫描驱动单元ASGn的扫描信号输出端OUT为该第N级扫描驱动单元ASGn的扫描信号检测端，以将第N级扫描驱动单元ASGn的扫描信号输出端OUT输出的扫描信号Goutn作为正向扫描检测信号，检测扫描驱动电路10的正向扫描功能。第一选通电路10的第二开关单元42的输入端与第一级扫描驱动单元ASG1的扫描信号输出端OUT电连接，即第一级扫描驱动单元ASG1的扫描信号输出端OUT为该第一级扫描驱动单元ASG1的扫描信号检测端，以将第一级扫描驱动单元ASG1的扫描信号输出端OUT输出的扫描信号Gout1作为反向扫描检测信号VnextB，检测扫描驱动电路10的反向扫描功能。如此，同样能够在实现对显示面板中的扫描驱动电路进行正向扫描功能和反向扫描功能的检测的前提下，采用同一检测信号引脚分时接收正向扫描检测信号和反向扫描检测信号，从而能够减少显示面板中 所设置的信号引脚的数量，降低显示面板的成本。
为便于描述，在没有特别限定的前提下，本申请实施例均以第N级扫描驱动单元的移位信号输出端为该第N级扫描驱动单元的扫描信号检测端，第一级扫描驱动单元的移位信号输出端为该第一级扫描驱动单元的扫描信号检测端为例，对本申请实施例的技术方案进行示例性的说明。
图1中仅示例性的示出了扫描驱动电路10设置于该显示面板100的显示区101一侧的非显示区102；而在本申请实施例中，显示面板的扫描驱动电路还可以设置于显示区相对的两侧，本申请实施例对此不作限定。
示例性的，图3是本申请实施例提供的又一种显示面板的结构示意图。如图3所示，显示面板100的扫描驱动电路包括第一扫描驱动电路110和第二扫描驱动电路120，且第一扫描驱动电路110和第二扫描驱动电路120设置于显示区101相对的两侧。此时，多个信号引脚中可以包括两个启动信号引脚311和312。其中，第一扫描驱动电路110的第一级扫描驱动单元ASG1的正向扫描输入端IN1和第N级扫描驱动单元ASGn的反向扫描输入端IN2均与启动信号引脚311电连接，第二扫描驱动电路120的第一级扫描驱动单元ASG1的正向扫描输入端IN1和第N级扫描驱动单元ASGn的反向扫描输入端IN2均与启动信号引脚312电连接。
显示面板100中可以设置有两个第一选通电路401和402，多个信号引脚中可以包括两个检测信号引脚321和322。此时，第一选通电路401的第一开关单元411的输入端与第一扫描驱动电路110的第N级扫描驱动单元ASGn的扫描信号检测端电连接，第一选通电路401的第二开关单元412的输入端与第一扫描驱动电路110的第一级扫描驱动单元ASG1的扫描信号检测端电连接，第一选通电路401的第一开关单元411的输出端和第二开关单元412的输出端均与检测信号引脚321电连接；第一选通电路402的第一开关单元421的输入端与第二扫描驱动电路120的第N级扫描驱动单元ASGn的扫描信号检测端电连接，第一选通电路402的第二开关单元422的输入端与第二扫描驱动电路120的第一级扫描驱动单元ASG1的扫描信号检测端电连接，第一选通电路402的第一开关单元421的输出端和第二开关单元422的输出端均与检测信号引脚322电连接。如此，采用检测信号引脚321分时接收第一扫描驱动电路110的正向扫描检测信号和反向扫描检测信号，以及采用引脚322分时接收第二扫描驱动电路120的正向扫描检测信号和反向扫描检测信号，同样有利于减少显示面板中所设置的信号引脚的数量，降低显示面板的成本。
为便于描述，本申请实施例均以显示面板的扫描驱动电路设置于显示区的一侧为例，对本申请实施例的技术方案进行示例性的说明。
在第一选通电路中的第一开关单元和第二开关单元分时导通，并能够分别将扫描驱动电路的正向扫描检测信号和反向扫描检测信号传输至检测信号引脚的前提下，本申请实施例对第一选通电路中第一开关单元和第二开关单元的结构不作限定。
可选的，图4是本申请实施例提供的一种第一选通电路的结构示意图。如图4所示，第一选通电路40的第一开关单元41包括第一传输门，该第一传输门包括第一N型晶体管N1和第一P型晶体管P1；第一N型晶体管N1的第一极与第一P型晶体管P1的第一极均为第一开关单元41的输入端；第一N型晶体管N1的第二极与第一P型晶体管P1的第二极均为第一开关单元41的输出端；第一N型晶体管N1的栅极接收第一控制信号Vg1，第一P型晶体管P1的栅极接收第二控制信号Vg2。第一选通电路40的第二开关单元42包括第二传输门，该第二传输门包括第二N型晶体管N2和第二P型晶体管P2；第二N型晶体管N2的第一极与第二P型晶体管P2的第一极均为第二开关单元42的输入端；第二N型晶体管N2的第二极与第二P型晶体管P2的第二极均为第二开关单元42的输出端；第二N型晶体管N2的栅极接收第三控制信号Vg3，第二P型晶体管P2的栅极接收第四控制信号Vg4。
在正向扫描检测阶段，第一控制信号Vg1控制第一N型晶体管N1导通，第二控制信号Vg2控制第一P型晶体管P1导通，使得第N级扫描驱动单元输出的正向扫描检测信号VtestF通过第一传输门的第一N型晶体管N1和第一P型晶体管P1传输至检测信号引脚，从而能够降低传输至检测信号引脚的正向扫描检测信号VtestF的损耗，有利于提高对扫描驱动电路的正向扫描功能进行检测时的准确性；相应的，在反向扫描检测阶段，第三控制信号Vg3控制第二N型晶体管N2导通，第四控制信号Vg4控制第二P型晶体管P2导通，使得第一级扫描驱动单元输出的反向扫描检测信号VtestB通过第二传输门的第二N型晶体管N2和第二P型晶体管P2传输至检测信号引脚，从而能够降低传输至检测信号引脚的反向扫描检测信号VtestB的损耗，有利于提高对扫描驱动电路的反向扫描功能进行检测时的准确性。
可选的，第一控制信号Vg1可以复用为第四控制信号Vg4；第二控制信号Vg2可以复用为第三控制信号Vg3。由于N型晶体管在高电平时导通、低电平时关闭，P型晶体管在低电平时导通、高电平时关闭；因此，当第一控制信号Vg1为高电平、第二控制信号Vg2为低电平时，可控制第一N型晶体管N1和第一P型晶体管P1导通，第二N型晶体管N2和第二P型晶体管P2关闭；而当第一控制信号Vg1为低电平、第二控制信号Vg2为高电平时，可控制第二N型晶体管N2和第二P型晶体管P2导通，第一N型晶体管N1和第一P型晶体管P1关闭。如此，在第一控制信号Vg1复用为第四控制信号Vg4以及第二控 制信号Vg2复用为第三控制信号Vg3时，能够实现第一传输门和第二传输门分时导通；同时有利于减少所提供的控制信号的数量，从而减少显示面板中设置的用于提供控制信号的信号引脚的数量，简化显示面板的结构，降低显示面板的成本。
可选的，图5是本申请实施例提供的又一种显示面板的结构示意图。结合图4和5所示，显示面板100中的多个信号引脚30还可包括正向使能信号引脚33和反向使能信号引脚34；多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)的正向扫描使能端EN1均与正向使能信号引脚33电连接，多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)的反向扫描使能端EN2均与反向使能信号引脚34电连接。此时，第一N型晶体管N1的栅极和第二P型晶体管P2的栅极可均与正向使能信号引脚33电连接，第二N型晶体管N2的栅极和所述第一P型晶体管P1的栅极均与反向使能信号引脚34电连接。
在扫描驱动电路10进行正向扫描时，正向使能信号引脚33的正向使能信号U2D会提供至多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)的正向扫描使能端EN1，使得多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)执行正向扫描过程；而在扫描驱动电路10进行反向扫描时，反向使能信号引脚34的反向使能信号D2U会提供至多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)的反向扫描使能端EN2，使得多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)执行反向扫描过程。
示例性的，图6是本申请实施例提供的一种扫描驱动单元的结构示意图。结合图5和图6所示，每个扫描驱动单元ASG可以包括输入模块11、移位模块12和输出模块13。输入模块11可以包括两个传输门111和112，每个传输门(111和112)可由一N型晶体管和一P型晶体管组成。在扫描驱动电路10进行正向扫描时，可由正向扫描使能端EN1的正向使能信号U2D和反向扫描使能端EN2的反向使能信号D2U控制传输门111中的N型晶体管和P型晶体管均导通，以使正向扫描输入端IN1信号传输至移位模块12，以使移位模块12能够对该信号进行锁存，并通过该级扫描驱动单元的移位信号输出端Next输出移位信号至该级扫描驱动单元的下一级扫描驱动单元的正向扫描输入端IN1，同时控制输出模块13产生扫描信号，并将该扫描信号通过该级扫描驱动单元的扫描信号输出端OUT输出至相应的扫描信号线20。
结合参考图4、图5和图6，由于在对扫描驱动电路10进行正向扫描检测时，需要扫描驱动电路10的多个扫描驱动单元ASG执行正向扫描的过程，并依次通过检测信号引脚32和导通的第一开关单元41接收第N级扫描驱动单元 ASGn输出的正向扫描检测信号；而在对扫描驱动电路10进行反向扫描检测时，需要扫描驱动电路10的多个扫描驱动单元ASG执行反向扫描的过程，并依次通过检测信号引脚32和导通的第二开关单元42接收第一级扫描驱动单元ASG1输出的反向扫描检测信号；因此，第一选通电路40的第一开关单元41的第一N型晶体管N1的栅极可与扫描驱动单元ASG中输入模块11的传输门111的N型晶体管的栅极接收相同的控制信号，第一P型晶体管P1的栅极可与扫描驱动单元ASG中输入模块11的传输门111的P型晶体管的栅极接收相同的控制信号；第一选通电路40的第二开关单元42的第二N型晶体管N2的栅极可与扫描驱动单元ASG中输入模块11的传输门112的N型晶体管的栅极接收相同的控制信号，第二P型晶体管P2的栅极可与扫描驱动单元ASG中输入模块11的传输门112的P型晶体管的栅极接收相同的控制信号。
如此，第一选通电路40中第一N型晶体管、第二P型晶体管以及扫描驱动单元ASG中输入模块11的传输门111的N型晶体管和传输门112的P型晶体管均与同一正向使能信号引脚33电连接，以能够在正向使能信号引脚33的正向使能信号U2D的控制下导通或断开；而第一选通电路40中第一P型晶体管P1、第二N型晶体管N2以及扫描驱动单元ASG中输入模块11的传输门111的P型晶体管和传输门112的N型晶体管均与同一反向使能信号引脚34电连接，以能够在反向使能信号引脚34的反向使能信号D2U的控制下导通或断开，从而能够减少显示面板中设置的信号引脚的数量，进而简化显示面板的结构，降低显示面板的成本。
图7是本申请实施例提供的一种扫描驱动电路的检测时序图。结合图4、图5和图7，在扫描驱动电路10的正向扫描检测阶段T1，正向使能信号引脚33提供高电平的正向使能信号U2D控制第一N型晶体管N1导通、第二P型晶体管P2关闭，反向使能信号引脚34提供低电平的反向使能信号D2U控制第一P型晶体管P1导通、第二N型晶体管N2关闭，多级扫描驱动单元ASG执行正向扫描过程，并依次通过检测信号引脚31、导通的第一N型晶体管N1和第一P型晶体管P1接收第N级扫描驱动单元ASGn输出的正向扫描检测信号VtestF；而在扫描驱动电路10的反向扫描检测阶段T2，正向使能信号引脚33提供低电平的正向使能信号U2D控制第一N型晶体管N1关闭、第二P型晶体管P2导通，反向使能信号引脚34提供高电平的反向使能信号D2U控制第一P型晶体管P1关闭、和第二N型晶体管N2导通，多级扫描驱动单元ASG执行反向扫描过程，并依次通过检测信号引脚31和导通的第二N型晶体管N2、第二P型晶体管P2接收第一级扫描驱动单元ASG1输出的反向扫描检测信号VtestB。如此，能够根据所接收的扫描检测信号ASIL分别检测扫描驱动电路10的正向扫描功能和反向扫描功能。
图6仅为本申请实施例示例性的附图，图6中示例性的示出了扫描驱动单元ASG的结构组成；而在本申请实施例中，在能够使扫描驱动电路的多级扫描驱动单元实现正向扫描功能和反向扫描功能的前提下，本申请实施例对扫描驱动单元的结构不作限定。
可选的，继续参考图5，显示面板100还包括反向扫描检测信号传输线50；该反向扫描检测信号传输线50的延伸方向Y与扫描信号线20的延伸方向X交叉；第二开关单元42的输入端通过反向扫描检测信号传输线50与第一级扫描驱动单元ASG1的扫描信号检测端电连接。如此，在反向扫描检测阶段，第一级扫描驱动单元ASG1输出的反向扫描检测信号能够依次通过反向扫描检测信号传输线50和导通的第二开关单元42传输至检测信号引脚32，以对显示面板中扫描驱动电路的反向扫描功能进行检测。
可选的，图8是本申请实施例提供的又一种显示面板的结构示意图。如图8所示，显示面板中设置有阵列排布的多个子像素60、多条数据信号线70以及多条信号走线80；位于同一行的多个子像素60与同一扫描信号线20电连接，以使多条扫描信号线20能够将扫描驱动电路10中多级扫描驱动单元ASG1、ASG2、ASG3、…、ASGn-1、ASGn输出的扫描信号一一对应的传输至每行子像素60；位于同一列的多个子像素60与同一数据信号线70电连接，以使多条数据信号线70能够在相应行的子像素60接收到有效的扫描信号时，将数据信号一一对应地提供至每个子像素60，并使每个子像素60能够根据相应的数据信号进行显示；信号走线80的延伸方向Y与扫描信号线20的延伸方向X交叉，该信号走线80为与扫描信号线20和数据信号线70不同的其它信号线，例如可以为显示面板100中用于向触控电极103传输触控信号或接收触控电极103产生的触控信号的触控走线。
多个子像素60中可以包括多个显示子像素61和位于多个显示子像素61至少一侧的多个非显示子像素62；此时，与同一列非显示子像素62电连接的数据信号线70可以为虚拟数据信号线72，以传输相应的数据信号至对应非显示子像素62，而与同一列显示子像素61电连接的数据信号线71传输相应的数据信号至对应的显示子像素61。由于在显示面板100显示画面时，显示子像素61会进行显示发光，而非显示子像素62不进行显示发光，因此可将至少一条虚拟数据信号线72复用为反向扫描检测信号传输线50，以能够在不影响显示面板100正常显示的前提下，直接采用虚拟数据信号线72传输第一级扫描驱动单元ASG1输出的反向扫描检测信号，能够减少显示面板100中所设置的信号线的数量，从而简化显示面板100的结构。
图8仅为本申请实施例示例性的附图，图8中示例性的示出了将虚拟数据 信号线72复用为反向扫描检测信号传输线50；而在不影响显示面板正常显示的前提下，还可以将其它已有的信号线复用为反向扫描检测信号传输线50。
示例性的，图9是本申请实施例提供的又一种显示面板的结构示意图。如图9所示，当与多条信号走线80中的至少一条信号走线电连接的结构(例如触控电极103)不影响显示面板100的正常功能时，可将该至少一条信号走线80作为虚拟信号走线82，且将至少一条虚拟信号走线82复用为反向扫描检测信号传输线50。如此，同样能够减少显示面板100中所设置的信号线的数量，从而简化显示面板100的结构。
图8和图9均是以第一级扫描驱动单元ASG1的移位信号输出端Next为该第一级扫描驱动单元ASG1的扫描信号检测端，而在本申请实施例中第一级扫描驱动单元的扫描信号检测端还可以为该第一级扫描驱动单元的扫描信号输出端。
示例性的，如图10所示，当将虚拟数据信号线72复用为反向扫描检测信号传输线50，且将第一级扫描驱动单元ASG1的扫描信号输出端OUT作为该第一级扫描驱动单元ASG1的扫描信号检测端时，可使虚拟数据信号线72分别与第一级扫描驱动单元ASG1的扫描信号输出端OUT和第二开关单元42的输入端电连接。
如图11所示，当将虚拟信号走线82复用为反向扫描检测信号传输线50，且将第一级扫描驱动单元ASG1的扫描信号输出端OUT作为该第一级扫描驱动单元ASG1的扫描信号检测端时，可使虚拟信号走线82分别与第一级扫描驱动单元ASG1的扫描信号输出端OUT和第二开关单元42的输入端电连接。
在没有特别说明的前提下，本申请实施例均以虚拟数据信号线复用为反向扫描检测信号传输线为例，对本申请实施例的技术方案进行示例性的说明。此外，上述仅示例性的以信号走线为触控走线为例对本申请实施例进行示例性的说明；而在本申请实施例中信号走线还可以为用于向多个子像素提供电源信号的电源信号线等，本申请实施例对信号走线的类型不作限定。
可选的，图12是本申请实施例提供的一种显示面板的膜层结构示意图。如图12所示，该显示面板包括衬底基板1001，以及位于衬底基板1001一侧且绝缘间隔设置的第一金属层1002、第二金属层1003和第三金属层1004。其中，第一金属层1002包括扫描信号线20，第二金属层1003包括数据信号线70，第三金属层1004包括信号走线80。如此，将扫描信号线20、数据信号线70以及信号走线80分别设置于不同的金属层，且任意相邻的两层金属层之间设置有相应的绝缘层，例如第一金属层1002与第二金属层1003之间设置有绝缘层1005，第二金属层1003与第三金属层1004之间设置有绝缘层1006，以防多个金属层 的信号线在传输信号时相互干扰。
此外，显示面板中每个子像素中还可以包括一开关晶体管T，该开关晶体管T包括有源层Tm、栅极Tg、源极Ts和漏极Td。此时，子像素中开关晶体管T的栅极Tg可与扫描信号线20设置在同一金属层，子像素中开关晶体管T的源极Ts和漏极Td可与数据信号线70设置在同一金属层。
可选的，继续参考图8所示，显示面板100还包括第一连接线104，该第一连接线104的延伸方向与反向扫描检测信号传输线50的延伸方向交叉；该第一连接线104的第一端通过反向扫描检测信号传输线50与第二开关单元42的输入端电连接；该第一连接线104的第二端与第一级扫描驱动单元ASG1的扫描信号检测端电连接。如此，第一级扫描驱动单元ASG1的扫描信号检测端输出的反向扫描检测信号能够依次通过第一连接线104、反向扫描检测信号传输线50以及导通的第二开关单元42传输至检测信号引脚32，以根据检测信号引脚32接收的反向扫描检测信号检测显示面板100中扫描驱动电路10的反向扫描功能。
可选的，结合图8和图12所示，第一连接线104可与扫描信号线20同层设置。此时，由于扫描信号线20的延伸方向X和第一连接线104的延伸方向X均与数据信号线70的延伸方向Y交叉，因此，第一连接线104的延伸方向X可与扫描信号线20的延伸方向X平行。如此，当将第一连接线104与扫描信号线20同层设置时，在不影响扫描信号线20传输扫描信号的前提下，能够简化显示面板的膜层设计，有利于显示面板的轻薄化。
图12仅为本申请实施例示例性的附图，图12中仅示例性的示出了将第一连接线104与扫描信号线20同层设置；而在本申请实施例中，第一连接线104还可以与数据信号线70同层设置(如图13所示)，或者第一连接线104与信号走线80同层设置(如图14所示)。在本申请实施例中，第一连接线104可尽量选择阻抗较小的已有膜层进行设置，以确保第一连接线104所传输的反向扫描检测信号的准确性。
可选的，继续参考图10所示，在扫描驱动电路10的第一级扫描驱动单元ASG1的扫描信号输出端OUT电连接的扫描信号线20为虚拟扫描信号线21，该虚拟扫描信号线21未与显示子像素61电连接。当第一级扫描驱动单元ASG1的扫描信号检测端为该第一级扫描驱动单元ASG1的扫描信号输出端OUT时，至少部分虚拟扫描信号线21复用为第一连接线104。如此，能够在不影响显示面板100正常显示的前提下，将至少部分虚拟扫描信号线21复用为第一连接线104，能够减少显示面板100中所设置的信号线的数量，有利于简化显示面板100的结构。
可选的，图15是本申请实施例提供的又一种显示面板的结构示意图。如图15所示，显示面板100中还设置有启动信号传输线105，该启动信号传输线105的第一端与第N级扫描驱动单元ASGn的反向扫描输入端IN2电连接，该启动信号传输线105的第二端与第一级扫描驱动单元ASG1的正向扫描输入端IN1电连接；该启动信号传输线105设置为将启动信号引脚31的启动信号分别传输至第一级扫描驱动单元ASG1的正向扫描输入端IN1和第N级扫描驱动单元ASGn的反向扫描输入端IN2。
继续参考图15，显示面板100中还设置有第二选通电路90和开关模块901；该第二选通电路90包括第三开关单元91和第四开关单元92；启动信号传输线105的第一端还分别与第三开关单元91的输出端和第四开关单元92的输入端电连接，以及启动信号传输线105的第二端还与开关模块901的输出端电连接；第三开关单元91的输入端与启动信号引脚31电连接；第四开关单元92的输出端与第二开关单元42的输入端电连接；第三开关单元91设置为在启动信号引脚31提供启动信号的有效脉冲时导通；第四开关单元92设置为在输出反向扫描检测信号时导通；开关模块901的输入端接收固定电压信号VDD；开关模块901的控制端与第一级扫描驱动单元ASG1的扫描信号检测端电连接；开关模块901设置为在反向扫描检测阶段，根据第一级扫描驱动单元ASG1的扫描信号检测端的信号，输出反向扫描检测信号。
在扫描驱动电路10的正向扫描检测阶段，可控制第二选通电路90的第三开关单元91导通，以使启动信号引脚31提供的启动信号能够通过导通的第三开关单元91传输至启动信号传输线105，并由启动信号传输线105传输至第一级扫描驱动单元ASG1的正向扫描输入端IN1，以使从第一级扫描驱动单元ASG1至第N级扫描驱动单元ASGn的多级扫描驱动单元依次生成移位信号和扫描信号；同时，通过控制第一选通电路40中的第一开关单元41导通，使得第N级扫描驱动单元ASGn输出的正向扫描检测信号，能够通过导通的第一开关单元41传输至检测信号引脚32。
在扫描驱动电路10的反向扫描检测阶段，可在启动信号引脚31的启动信号的有效脉冲的起始时刻和终止时刻期间控制第二选通电路90的第三开关单元91导通，使得启动信号引脚31的启动信号的有效脉冲通过导通的第三开关单元91传输至启动信号传输线105，并由启动信号传输线105传输至第N级扫描驱动单元ASGn的反向扫描输入端IN2，以使从第N级扫描驱动单元ASGn至第一级扫描驱动单元ASG1的多级扫描驱动单元依次生成移位信号和扫描信号；在启动信号的有效脉冲终止时刻之后以及第一级扫描驱动电路ASG1输出移位信号和/或扫描信号前，控制第二选通电路90的第四开关单元92和第一选通电路40的第二开关单元42导通，以及控制第二选通电路90的第三开关单元91 和第一选通电路40的第一开关单元41关闭，使得开关模块901根据第一级扫描驱动单元ASG1的扫描信号检测端的信号，输出反向扫描检测信号至启动信号传输线105，并通过启动信号传输线105传输至第四开关单元92的输入端，并依次通过导通的第四开关单元92和第二开关单元42传输至检测信号引脚32。
如此，通过设置第二选通电路90和开关模块901，实现对显示面板的正向扫描功能和反向扫描功能的检测；同时，将启动信号传输线105复用为传输反向扫描检测信号的反向扫描检测信号传输线，有利于减少显示面板中所设置的信号线的数量，从而有利于显示面板的窄边框，以及能够简化显示面板的结构。
在第二选通电路90中的第三开关单元91和第四开关单元92分时导通，并能够在正向扫描检测阶段和反向扫描的起始阶段将启动信号引脚31提供的启动信号传输至启动信号传输线105，并在反向扫描检测信号的输出阶段将启动信号传输线105传输的反向扫描检测信号传输至检测信号引脚的前提下，本申请实施例对第二选通电路中第三开关单元和第四开关单元的结构不作限定。
可选的，图16是本申请实施例提供的一种第二选通电路的结构示意图。结合图15和图16所示，第二选通电路90的第三开关单元91包括第三传输门，该第三传输门包括第三N型晶体管N3和第三P型晶体管P3；第三N型晶体管N3的第一极与第三P型晶体管P3的第一极均为第三开关单元91的输入端；第三N型晶体管N3的第二极与第三P型晶体管P3的第二极均为第三开关单元91的输出端；第三N型晶体管N3的栅极接收第五控制信号Vg5，第三P型晶体管P3的栅极接收第六控制信号Vg6。第二选通电路90的第四开关单元92包括第四传输门，该第四传输门包括第四N型晶体管N4和第四P型晶体管P4；第四N型晶体管N4的第一极与第四P型晶体管P4的第一极均为第四开关单元92的输入端；第四N型晶体管N4的第二极与第四P型晶体管P4的第二极均为第四开关单元92的输出端；第四N型晶体管N4的栅极接收第七控制信号Vg7，第四P型晶体管P4的栅极接收第八控制信号Vg8。
在正向扫描检测阶段，第五控制信号Vg5控制第三N型晶体管N3导通，第六控制信号Vg6控制第三P型晶体管P3导通，使得启动信号引脚31的启动信号STV能够通过第三传输门中第三N型晶体管N3和第三P型晶体管P3传输至启动信号传输线105，以降低传输至启动信号传输线105的启动信号的损耗，确保第一级扫描驱动单元ASG1能够接收到准确的启动信号，使得从第一级扫描驱动单元ASG1至第N级扫描驱动单元ASGn的多级扫描驱动单元能够依次产生准确的移位信号和扫描信号，从而使第N级扫描驱动单元ASGn输出准确的正向扫描检测信号，进而提高正向扫描功能的检测准确性。
在反向扫描检测阶段中，至少在启动信号STV的有效脉冲的起始时刻至其 终止时刻期间，第五控制信号Vg5控制第三N型晶体管N3导通，第六控制信号Vg6控制第三P型晶体管P3导通，使得启动信号引脚31的启动信号STV的有效脉冲能够通过第三传输门中第三N型晶体管N3和第三P型晶体管P3传输至启动信号传输线105，以降低传输至启动信号传输线105的启动信号STV的损耗，确保第N级扫描驱动单元ASGn能够接收到准确的启动信号STV，使得从第N级扫描驱动单元ASGn至第一级扫描驱动单元ASG1的多级扫描驱动单元能够依次产生准确的移位信号和扫描信号；而在启动信号引脚31的启动信号STV的有效脉冲的终止时刻之后，第七控制信号Vg7控制第四N型晶体管N4导通，第八控制信号Vg8控制第四P型晶体管P4导通，使得开关模块901根据第一级扫描驱动单元ASG1输出的移位信号或扫描信号生成的反向扫描检测信号通过启动信号传输线105以及第四传输门中第四N型晶体管N4和第四P型晶体管P4传输至第二开关单元42，从而能够在复用启动信号传输线105传输反向扫描检测信号的前提下，降低反向扫描检测信号的损耗，从而有利于提高扫描驱动电路10的反向扫描功能的检测准确性。
可选的，第五控制信号Vg5可以复用为第八控制信号Vg8；第六控制信号Vg6可以复用为第七控制信号Vg7。由于N型晶体管在高电平时导通、低电平时关闭，P型晶体管在低电平时导通、高电平时关闭；因此，当第五控制信号Vg5为高电平、第六控制信号Vg6为低电平时，可控制第三N型晶体管N3和第三P型晶体管P3导通，第四N型晶体管N4和第四P型晶体管P4关闭；而当第五控制信号Vg5为低电平、第六控制信号Vg6为高电平时，可控制第四N型晶体管N4和第四P型晶体管P4导通，第三N型晶体管N3和第三P型晶体管P3关闭。如此，在第五控制信号Vg5复用为第八控制信号Vg8以及第六控制信号Vg6复用为第七控制信号Vg7时，能够实现第三传输门和第四传输门分时导通；同时，通过控制信号的复用，有利于减少所提供的控制信号的数量，从而减少显示面板中设置的用于提供控制信号的信号引脚的数量，简化显示面板的结构，降低显示面板的成本。
可选的，图17是本申请实施例提供的又一种显示面板的结构示意图。结合图16和图17所示，显示面板100中还设置有反相器902，多个信号引脚30还包括控制信号引脚35；该控制信号引脚35能够设置为提供第五控制信号Vg5；反相器902的输入端与控制信号引脚35电连接，反相器902的输出端与第三P型晶体管P3的栅极和第四N型晶体管N4的栅极电连接；第三N型晶体管N3的栅极和第四P型晶体管P4的栅极与控制信号引脚35电连接。
当控制信号引脚35提供高电平的第五控制信号Vg5时，该第五控制信号Vg5能够控制第三N型晶体管N3导通，第四P型晶体管P4关闭，且该高电平的第五控制信号Vg5在通过反相器902后转换为低电平的控制信号，以控制第 三P型晶体管P3导通，以及控制第四N型晶体管N4关闭，以使启动信号引脚31提供的启动信号STV能够通过第三传输门中导通的第三N型晶体管N3和第三P型晶体管P3传输至启动信号传输线105，而此时因第四传输门的第四N型晶体管N4和第四P型晶体管P4处于关闭状态，使得启动信号传输线105上的信号无法通过第四传输门传输至检测信号引脚32。
当控制信号引脚35提供低电平的第五控制信号Vg5时，该第五控制信号Vg5能够控制第三N型晶体管N3关闭，第四P型晶体管P4导通，且该低电平的第五控制信号Vg5在通过反相器902后转换为高电平的控制信号，以控制第三P型晶体管P3关闭，以及控制第四N型晶体管N4导通，以使启动信号传输线105上的信号能够通过第四传输门中导通的第四N型晶体管N4和第四P型晶体管P4传输至检测信号引脚32，而此时因第三传输门的第三N型晶体管N3和第三P型晶体管P3处于关闭状态，使得启动信号引脚31提供的启动信号STV无法通过第三传输门传输至启动信号传输线105。
如此，仅设置一个控制信号引脚，即可控制第二选通电路中第三开关单元的第三N型晶体管和第三P型晶体管与第四开关单元的第四N型晶体管和第四P型晶体管分时导通，从而能够减少显示面板中所设置的控制信号引脚的数量，有利于简化显示面板的结构，降低显示面板的成本。
图17仅为本申请实施例示例性的附图，图17中仅示例性的示出了控制信号引脚提供的信号为第五控制信号；而在本申请实施例中控制信号引脚提供的控制信号还可以为第六控制信号。
示例性的，图18是本申请实施例提供的又一种显示面板的结构示意图。结合图16和图18所示，反相器902的输入端与控制信号引脚35电连接，反相器902的输出端与第三N型晶体管N3的栅极和第四P型晶体管P4的栅极电连接；第三P型晶体管P3的栅极和第四N型晶体管N4的栅极与控制信号引脚35电连接。此时，该控制信号引脚35设置为提供第六控制信号Vg6。当控制信号引脚35提供低电平的第六控制信号Vg6时，该第六控制信号Vg6能够控制第三P型晶体管P3导通，第四N型晶体管N4关闭，且该低电平的第六控制信号Vg6在通过反相器902后转换为高电平的控制信号，以控制第三N型晶体管N3导通；而在控制信号引脚35提供高电平的第六控制信号Vg6时，该第六控制信号Vg6能够控制第四N型晶体管N4导通，第三P型晶体管P3关闭，且该高电平的第六控制信号Vg6在通过反相器902后转换为低电平的控制信号，以控制第三N型晶体管N3关闭，第四P型晶体管P4导通。如此，在能够控制第二选通电路中第三开关单元的第三N型晶体管和第三P型晶体管与第四开关单元的第四N型晶体管和第四P型晶体管分时导通的前提下，同样能够减少显示面板中 所设置的控制信号引脚的数量，从而有利于简化显示面板的结构，降低显示面板的成本。
图17和图18均以第一级扫描器驱动单元ASG1的移位信号输出端Next为该第一级扫描驱动单元ASG1的扫描信号检测端。而在本申请实施例中，第一级扫描驱动单元ASG1的扫描信号检测端还可以为该第一级扫描驱动单元ASG1的扫描信号输出端OUT，如图19和图20所示，其技术原理与图17和图18，相同之处可参照上述对图17和图18的叙述，在此不再赘述。
可选的，继续参考图17，开关模块901包括开关晶体管Tf；该开关晶体管Tf的栅极为开关模块901的控制端，开关晶体管Tf的第一极为开关模块901的输入端，开关晶体管Tf的第二极为开关模块901的输出端。
在反向扫描检测阶段，开关晶体管Tf的栅极接收第一级移位寄存单元ASG1的扫描检测端的信号，使得该开关晶体管Tf能够根据其栅极接收的信号和其第一极的固定电压信号产生反向扫描检测信号至启动信号传输线105，并由启动信号传输线105通过导通的第四开关单元92和第二开关单元42传输至检测信号引脚32，实现对扫描驱动电路10的反向扫描功能进行检测。
图17中示出的开关模块的结构仅为本申请实施例示例性的附图，在本申请实施例中能够使该开关模块根据其控制端和输入端的信号产生反向扫描检测信号的前提下，本申请实施例对开关模块的结构不做限定。
示例性的，图21是本申请实施例提供的又一种显示面板的结构示意图。如图21所示，开关模块901的控制端还可以为开关晶体管Tf的第一极，开关模块901的输入端为开关晶体管Tf的栅极，以及开关模块901的输出端为开关晶体管Tf的第二极。如此，开关晶体管Tf能够根据其第一极接收的第一级扫描驱动单元ASG1的扫描检测端输出的信号和其栅极的固定电压信号产生反向扫描检测信号至启动信号传输线105，并由启动信号传输线105通过导通的第四开关单元92和第二开关单元42传输至检测信号引脚32，同样能够对扫描驱动电路10的反向扫描功能进行检测。
可选的，继续参考图17，多个信号引脚30还包括第一电平信号引脚36；多级扫描驱动单元(ASG1、ASG2、ASG3、…、ASGn-1、ASGn)的第一电平信号输入端VGH均与第一电平信号引脚36电连接；该第一电平信号引脚36设置为提供第一电平信号V1；其中，第一电平信号V1可以复用为提供至开关模块901的输入端的固定电压信号。如此，无需单独设置为开关模块901提供固定电压信号的引脚和传输线，从而有利于简化显示面板的结构，降低显示面板的成本。
此外，多级扫描驱动单元还可以包括第一时钟信号端、第二时钟信号端、第二电平信号输入端和复位信号输入端等，以在正向扫描过程中，多级扫描驱动单元能够根据其正向扫描使能端、反向扫描使能端、正向扫描输入端、第一时钟信号端、第二时钟信号端、第一电平信号输入端、第二电平信号输入端和复位信号输入端的信号依次产生扫描信号和移位信号；而在反向扫描过程中，多级扫描驱动单元能够根据其正向扫描使能端、反向扫描使能端、反向扫描输入端、第一时钟信号端、第二时钟信号端、第一电平信号输入端、第二电平信号输入端和复位信号输入端的信号依次产生扫描信号和移位信号。
示例性的，图22是本申请实施例提供的一种扫描驱动单元的电路结构示意图。如图22所示，扫描驱动单元ASG包括输入模块11、移位模块12和输出模块13。输入模块11由两个传输门111和112组成，以根据正向扫描使能端EN1的正向使能信号U2D和反向扫描使能端EN2的反向使能信号D2U控制其正向扫描输入端IN1或反向扫描输入端IN2的信号传输至移位模块12。
移位模块12由第一反相器121、第二反相器124、第一时钟反相器122、第二时钟反相器123以及复位单元125组成。第一反相器121的输入端与第一时钟信号端CK1电连接，第一反相器121的输出端分别与第一时钟反相器122的控制端和第二时钟反相器123的控制端电连接；第一时钟反相器122的输入端与输入模块11电连接，接收输入模块11输出的正向扫描输入端IN1或反向扫描输入端IN2的信号；第一时钟反相器122的输出端与第二反相器124的输入端电连接，第一时钟反相器122的时钟端与第一时钟信号端CK1电连接；第二时钟反相器123的输入端与第二反相器124的输出端电连接，第二时钟反相器123的时钟端与第一时钟信号端CK1电连接，第二时钟反相器123的输出端与第二反相器124的输入端电连接；第二反相器124的输出端还与输出模块13和移位信号输出端Next电连接。其中，第一反相器121由晶体管M11和晶体管M12组成，并在第一时钟信号端CK1接收的第一时钟信号CKV1为低电平时输出晶体管M11的第一极接收的第一电平信号端VGH的第一电平信号V1，而在第一时钟信号端CK1接收的第一时钟信号CKV1为高电平时输出晶体管M12的第一极接收的第二电平信号端VGL的第二电平信号V2；第一时钟反相器122由晶体管M13、M14、M15和M16组成，并在第一时钟信号端CK1接收的第一时钟信号CKV1为高电平以及输入模块11输入的为高电平的信号时，输出晶体管M16的第一极接收的第二电平信号端VGL的第二电平信号V2，而在输入模块11输入的为低电平的信号以及第一反相器121输出第二电平信号V2时输出晶体管M13的第一极接收的第一电平信号端VGH的第一电平信号V1；第二时钟反相器123由晶体管M17、M18、M19和M110组成，并在第一时钟信号端CK1接收的第一时钟信号CKV1为低电平以及第二反相器124输出低电平的 信号时输出晶体管M17的第一极接收的第一电平信号端VGH的第一电平信号V1，而在第一反相器121输出第一电平信号V1以及第二反相器124输出高电平的信号时输出晶体管M110的第一极接收的第二电平信号端VGL的第二电平信号V2；第二反相器124由晶体管M111和M112组成，在第二反相器124的输入端输入高电平信号时输出晶体管M112的第一极接收的第二电平信号端VGL的第二电平信号V2，并在第二反相器124的输入端输入低电平信号时输出晶体管M111的第一极接收的第一电平信号端VGH的第一电平信号V1；复位单元125的控制端与复位信号输入端Rest电连接，复位单元125的输入端与第一电平信号端VGH电连接，复位单元125的输出端与第二反相器124的输入端电连接，该复位单元125由晶体管M113组成，以根据复位信号输入端Rest的复位信号Vrest对第二反相器124输入端的信号进行复位。
输出模块13由与非门电路131和缓冲电路132组成，其中与非门电路131由晶体管M21、M22、M23和M24组成，实现第二时钟信号端CK2的第二时钟信号和移位模块12输出的移位信号Vnext的与非功能；缓冲电路132由晶体管M25、M26、M27、M28、M29和M210组成的三个反相器组成，以将与非门电路131输出的信号传输至扫描信号输出端OUT，实现扫描信号Gout的输出。
示例性的，图23为本申请实施例提供的又一种扫描驱动电路的检测时序图。结合图17、图23和图22所示，在正向扫描检测阶段T1，控制信号引脚35的高电平的第五控制信号Vg5控制第二选通电路90中第三开关单元91的第三N型晶体管N3和第三P型晶体管P3导通，使得启动信号引脚31的启动信号STV通过导通的第三开关单元91和启动信号传输线105传输至第一级扫描驱动单元ASG1的正向扫描输入端IN1；正向使能信号引脚33的高电平的正向使能信号U2D和反向使能信号引脚34的低电平的反向使能信号D2U控制第一选通电路40中第一开关单元41的第一N型晶体管N1和第一P型晶体管P1导通，以及使每一级扫描驱动单元ASG的正向扫描输入端IN1的信号输入该级扫描驱动单元ASG的移位模块12，以使每一级扫描驱动单元ASG的移位模块12根据该级扫描驱动单元ASG的正向扫描输入端IN1的信号和第一时钟信号端CK1的第一时钟信号CKV1选择该级扫描驱动单元ASG的第一电平信号端VGH的第一电平信号V1或第二电平信号端VGL的第二电平信号V2作为该级扫描驱动单元ASG的移位信号Vnext，并从第一级扫描驱动单元ASG1至第N级扫描驱动单元ASGn的多级扫描驱动单元ASG依次输出移位信号(Vnext1、Vnext2、Vnext3、…、Vnextn-1、Vnextn)至该级扫描驱动单元ASG的下一级扫描驱动单元的正向扫描输入端IN1；同时，每一级扫描驱动单元ASG的输出模块13根据该级扫描驱动单元ASG的第二时钟信号端CK2的第二时钟信号CKV2和该级扫描驱动单元ASG的移位模块12的移位信号Vnext选择该级扫描驱动单 元ASG的第一电平信号端VGH的第一电平信号V1或第二电平信号端VGL的第二电平信号V2作为其扫描信号Gout，并从第一级扫描驱动单元ASG1至第N级扫描驱动单元ASGn的多级扫描驱动单元ASG依次输出扫描信号(Gout1、Gout2、Gout3、…、Goutn-1、Goutn)。此时，第N级扫描驱动单元ASGn的扫描信号检测端的正向扫描检测信号通过第一选通电路40中导通的第一开关单元41传输至检测信号引脚32，以能够根据检测信号引脚32接收的正向扫描检测信号对扫描驱动电路10的正向扫描功能进行检测。
在反向扫描检测的阶段T2，控制信号引脚35在启动信号引脚31的启动信号STV的有效脉冲的起始时刻至其有效脉冲的终止时刻期间T21'提供高电平的第五控制信号Vg5控制第二选通电路90中第三开关单元91的第三N型晶体管N3和第三P型晶体管P3导通，使得启动信号引脚31的启动信号STV通过导通的第三开关单元91和启动信号传输线105传输至第N级扫描驱动单元ASGn的反向扫描输入端IN2；而在启动信号引脚31的启动信号STV的有效脉冲的终止时刻之后T22'，控制信号引脚35提供低电平的第五控制信号Vg5控制第二选通电路90中第四开关单元92的第四N型晶体管和第四P型晶体管导通；同时，正向使能信号引脚33的低电平的正向使能信号U2D和反向使能信号引脚34的高电平的反向使能信号D2U控制第一选通电路40中第二开关单元42的第二N型晶体管和第二P型晶体管导通，以及使每一级扫描驱动单元ASG的反向扫描输入端IN2的信号输入其移位模块12，以使每一级扫描驱动单元ASG的移位模块12根据其反向扫描输入端IN2的信号和第一时钟信号端CK1的第一时钟信号CKV1选择其第一电平信号端VGH的第一电平信号V1或第二电平信号端VGL的第二电平信号V2作为其移位信号Vnext，并从第N级扫描驱动单元ASGn至第一级扫描驱动单元ASG1的多级扫描驱动单元ASG依次输出移位信号(Vnextn、Vnextn-1、…、Vnext3、Vnext2、Vnext1)至其上一级扫描驱动单元的反向扫描输入端IN2；相应的，每一级扫描驱动单元ASG的输出模块13根据其第二时钟信号端CK2的第二时钟信号CKV2和其移位模块12的移位信号Vnext选择其第一电平信号端VGH的第一电平信号V1或第二电平信号端VGL的第二电平信号V2作为其扫描信号Gout，并从第N级扫描驱动单元ASGn至第一级扫描驱动单元ASG1的多级扫描驱动单元ASG依次输出扫描信号(Goutn、Goutn-1、…、Gout3、Gout2、Gout1)。此时，开关模块901根据第一级扫描驱动单元ASG1的扫描信号检测端的信号和第一电平信号引脚36的第一电平信号V1生成反向扫描检测信号，并通过启动信号传输线105、第二选通电路90中导通的第四开关单元92以及第一选通电路40中导通的第二开关单元42传输至检测信号引脚32，以能够根据检测信号引脚32接收的反向扫描检测信号对扫描驱动电路10的反向扫描功能进行检测。
本申请实施例在能够实现对显示面板中扫描驱动电路的正向扫描功能和反向扫描功能进行检测的前提下，复用启动信号传输线传输反向扫描检测信号，以减少显示面板中所设置的信号线的数量，有利于减小显示面板的边框尺寸，提高显示面板的屏占比；同时，将为多级扫描驱动单元提供使能信号的信号引脚复用为向第一选通电路中的多个晶体管提供控制信号的引脚，以及第二选通电路中的多个晶体管共用同一信号引脚提供控制信号，能够减少显示面板中所设置的信号引脚的数量，有利于简化显示面板的结构，降低显示面板的成本。
本申请实施例还提供一种显示面板的检测方法，该显示面板的检测方法可用于检测本申请实施例提供的显示面板，该显示面板的检测方法至少包括正向扫描检测阶段和反向扫描检测阶段。图24是本申请实施例提供的一种检测方法的流程示意图。如图24所示，该显示面板的检测方法包括：
S110、在正向扫描检测阶段，提供启动信号，以使第一级扫描驱动单元至第N级扫描驱动单元的多级扫描驱动单元依次输出移位信号和扫描信号；以及，控制第一开关单元导通，第二开关单元关闭，通过第一开关单元接收第N级扫描驱动单元的扫描信号检测端的信号作为正向扫描检测信号，并根据正向扫描检测信号检测扫描驱动电路的正向扫描功能；其中，正向扫描检测信号为第N级扫描驱动单元输出的移位信号或扫描信号。
S120、在反向扫描检测阶段，提供启动信号，以使第N级扫描驱动单元至第一级扫描驱动单元的多级扫描驱动单元依次输出移位信号和扫描信号；以及，控制第一开关单元关闭，第二开关单元导通，通过第二开关单元接收第一级扫描驱动单元的扫描信号检测端的信号作为反向扫描检测信号，并根据反向扫描检测信号检测扫描驱动电路的反向扫描功能；其中，反向扫描检测信号为第一级扫描驱动单元输出的移位信号或扫描信号。
如此，通过启动信号引脚向第一级移位寄存单元提供启动信号，将第N级移位寄存单元的移位信号输出端输出的移位信号作为正向扫描检测信号，并通过检测信号引脚和导通的第一开关单元接收正向扫描检测信号，以能够根据该正向扫描检测信号对扫描驱动电路的正向扫描功能进行检测；相应的，通过启动信号引脚向第N级移位寄存单元提供启动信号，将第一级移位寄存单元的移位信号输出端输出的移位信号作为反向扫描检测信号，并通过检测信号引脚和导通的第二开关单元接收反向扫描检测信号，以能够根据该反向扫描检测信号对扫描驱动电路的反向扫描功能进行检测，从而能够通过同一检测信号引脚，分别实现对显示面板的正向扫描功能和反向扫描功能的检测，有利于减少显示面板中所设置的信号引脚数量，从而有利于简化显示面板的结构，降低显示面板的成本。
可选的，结合图1和图4所示，第一选通电路40的第一开关单元41包括第一传输门，该第一传输门包括第一N型晶体管N1和第一P型晶体管P1；第一N型晶体管N1的第一极与第一P型晶体管P1的第一极均为第一开关单元41的输入端；第一N型晶体管N1的第二极与第一P型晶体管P1的第二极均为第一开关单元41的输出端；第一N型晶体管N1的栅极接收第一控制信号Vg1，第一P型晶体管P1的栅极接收第二控制信号Vg2。第一选通电路40的第二开关单元42包括第二传输门，该第二传输门包括第二N型晶体管N2和第二P型晶体管P2；第二N型晶体管N2的第一极与第二P型晶体管P2的第一极均为第二开关单元42的输入端；第二N型晶体管N2的第二极与第二P型晶体管P2的第二极均为第二开关单元42的输出端；第二N型晶体管N2的栅极接收第三控制信号Vg3，第二P型晶体管P2的栅极接收第四控制信号Vg4。
正向扫描检测阶段包括：提供启动信号，以使从第一级扫描驱动单元ASG1至所述第N级扫描驱动单元ASGn的多级扫描驱动单元依次输出移位信号和扫描信号；以及，第一控制信号Vg1控制第一N型晶体管N1导通，第二控制信号Vg2控制第一P型晶体管P1导通，第三控制信号Vg3控制第二N型晶体管N2关闭，第四控制信号Vg4控制第二P型晶体管P2关闭，以使第一传输门导通，第二传输门关闭，通过第一传输门接收第N级扫描驱动单元ASGn的扫描信号检测端的正向扫描检测信号，并根据正向扫描检测信号检测扫描驱动电路10的正向扫描功能。
反向扫描检测阶段包括：提供启动信号，以使从第N级扫描驱动单元ASGn至第一级扫描驱动单元ASG1的多级扫描驱动单元依次输出移位信号和扫描信号；以及，第一控制信号Vg1控制第一N型晶体管N1关闭，第二控制信号Vg2控制第一P型晶体管P1关闭，第三控制信号Vg3控制第二N型晶体管N2导通，第四控制信号Vg4控制第二P型晶体管P2导通，以使第一传输门关闭，第二传输门导通，通过导通的第二传输门接收第一级扫描驱动单元ASG1的扫描信号检测端的反向扫描检测信号，并根据反向扫描检测信号检测扫描驱动电路10的反向扫描功能。
如此，采用第一传输门传输正向扫描检测信号时，能够减小正向扫描检测信号在传输过程中的损耗，从而在根据该正向扫描检测信号对显示面板的正向扫描功能进行检测时，能够提供该显示面板的正向扫描功能的检测准确性。同时，在采用第二传输门传输反向扫描检测信号时，能够减小反向扫描检测信号在传输过程中的损耗，从而在根据该反向扫描检测信号对显示面板的反向扫描功能进行检测时，能够提供该显示面板的反向扫描功能的检测准确性。
可选的，如图15所示，当显示面板100还包括启动信号传输线105、第二 选通电路90和开关模块901；第二选通电路90包括第三开关单元91和第四开关单元92；启动信号传输线105的第一端分别与第三开关单元91的输出端、第四开关单元92的输入端以及第N级扫描驱动单元ASGn的反向扫描输入端电连接；启动信号传输线105的第二端分别与第一级扫描驱动单元ASG1的正向扫描输入端和开关模块901的输出端电连接；第三开关单元91的输入端与启动信号引脚31电连接；第四开关单元92的输出端与第二开关单元42的输入端电连接；开关模块901的输入端接收固定电压信号；开关模块901的控制端与第一级扫描驱动单元ASG1的扫描信号检测端电连接。
反向扫描检测阶段包括第一阶段、第二阶段和第三阶段。图25是本申请实施例提供的一种反向扫描检测方法的流程图。如图25所示，该反向扫描检测方法包括：
S121、在第一阶段，第三开关单元导通，第四开关单元关闭，启动信号通过第三开关单元输出至启动信号传输线，以使从第N级扫描驱动单元至第一级扫描驱动单元的多级扫描驱动单元依次输出扫描信号和移位信号。
S122、在第二阶段，第二开关单元和第四开关单元导通，第一开关单元和第三开关单元关闭，开关模块根据第一级扫描驱动单元的扫描信号检测端的信号，输出反向扫描检测信号。
S123、在第三阶段，通过启动信号传输线以及第四开关单元和第二开关单元接收反向扫描检测信号，并根据反向扫描检测信号检测扫描驱动电路的反向扫描功能。
在第一阶段，控制第二选通电路的第三开关单元导通、第四开关单元关闭，启动信号引脚的启动信号的有效脉冲通过导通的第三开关单元传输至启动信号传输线，并由启动信号传输线传输至第N级扫描驱动单元的反向扫描输入端，以使从第N级扫描驱动单元至第一级扫描驱动单元的多级扫描驱动单元依次生成移位信号和扫描信号；在第二阶段，启动信号引脚不再提供启动信号的有效脉冲，此时控制第二选通电路的第四开关单元和第一选通电路的第二开关单元导通，以及控制第二选通电路的第三开关单元和第一选通电路的第一开关单元关闭，使得开关模块根据第一级扫描驱动单元的扫描信号检测端的信号，输出反向扫描检测信号至启动信号传输线，并通过启动信号传输线传输至第四开关单元的输入端，并依次通过导通的第四开关单元和第二开关单元传输至检测信号引脚。如此，通过控制第二选通电路的第三开关单元和第四开关单元分时导通，能够在实现对显示面板的反向扫描功能进行检测的前提下，复用启动信号传输线传输反向扫描检测信号，有利于减少显示面板中所设置的信号线的数量，有利于显示面板的窄边框，提高显示面板的屏占比。
本申请实施例还提供一种显示装置，该显示装置包括本申请实施例提供的显示面板。因此，该显示装置具备本申请实施例提供的显示面板的技术特征和效果，相同之处可参照上述对本申请实施例提供的显示面板的描述，在此不再赘述。
示例性的，图26是本申请实施例提供的一种显示装置的结构示意图。如图26所示，该显示装置200包括本申请实施例提供的显示面板100。该显示装置例如可以为车载显示屏、手机、计算机显示器以及可知的其他电子设备。

Claims (20)

  1. 一种显示面板，包括：
    多个信号引脚；所述多个信号引脚至少包括启动信号引脚和检测信号引脚；
    扫描驱动电路和扫描信号线；所述扫描驱动电路包括N个级联设置的扫描驱动单元；其中，N为大于或等于2的正整数；每一级所述扫描驱动单元的扫描信号输出端与每条所述扫描信号线一一对应电连接；每一级所述扫描驱动单元的正向扫描输入端与所述每一级扫描驱动单元的上一级扫描驱动单元的移位信号输出端电连接，以及每一级所述扫描驱动单元的反向扫描输入端与所述每一级扫描驱动单元的下一级扫描驱动单元的移位信号输出端电连接；第一级扫描驱动单元的正向扫描输入端和第N级扫描驱动单元的反向扫描输入端均与所述启动信号引脚电连接；
    第一选通电路，包括第一开关单元和第二开关单元；所述第一开关单元的输入端与所述第N级扫描驱动单元的扫描信号检测端电连接；所述第二开关单元的输入端与所述第一级扫描驱动单元的扫描信号检测端电连接；所述第一开关单元的输出端和所述第二开关单元的输出端均与所述检测信号引脚电连接；所述第一开关单元设置为在正向扫描检测阶段导通，以及在反向扫描检测阶段关闭；所述第二开关单元设置为在所述反向扫描检测阶段导通，以及在所述正向扫描检测阶段关闭；
    其中，所述第N级扫描驱动单元的扫描信号检测端为所述第N级扫描驱动单元的移位信号输出端或扫描信号输出端；所述第一级扫描驱动单元的扫描信号检测端为所述第一级扫描驱动单元的移位信号输出端或扫描信号输出端。
  2. 根据权利要求1所述的显示面板，其中，所述第一开关单元包括第一传输门；所述第一传输门包括第一N型晶体管和第一P型晶体管；所述第一N型晶体管的第一极与所述第一P型晶体管的第一极均为所述第一开关单元的输入端；所述第一N型晶体管的第二极与所述第一P型晶体管的第二极均为所述第一开关单元的输出端；所述第一N型晶体管的栅极接收第一控制信号，所述第一P型晶体管的栅极接收第二控制信号；
    所述第二开关单元包括第二传输门；所述第二传输门包括第二N型晶体管和第二P型晶体管；所述第二N型晶体管的第一极与所述第二P型晶体管的第一极均为所述第二开关单元的输入端；所述第二N型晶体管的第二极与所述第二P型晶体管的第二极均为所述第二开关单元的输出端；所述第二N型晶体管的栅极接收第三控制信号，所述第二P型晶体管的栅极接收第四控制信号。
  3. 根据权利要求2所述的显示面板，其中，所述第一控制信号复用为所述第四控制信号；所述第二控制信号复用为所述第三控制信号。
  4. 根据权利要求3所述的显示面板，其中，所述多个信号引脚还包括正向使能信号引脚和反向使能信号引脚；
    多级所述扫描驱动单元的正向扫描使能端均与所述正向使能信号引脚电连接，多级所述扫描驱动单元的反向扫描使能端均与所述反向使能信号引脚电连接；
    所述第一N型晶体管的栅极和所述第二P型晶体管的栅极均与所述正向使能信号引脚电连接；所述第二N型晶体管的栅极和所述第一P型晶体管的栅极均与所述反向使能信号引脚电连接。
  5. 根据权利要求1所述的显示面板，还包括：反向扫描检测信号传输线；所述反向扫描检测信号传输线的延伸方向与所述扫描信号线的延伸方向交叉；
    所述第二开关单元的输入端通过所述反向扫描检测信号传输线与所述第一级扫描驱动单元的扫描信号检测端电连接。
  6. 根据权利要求5所述的显示面板，还包括：多条数据信号线、多条信号走线和阵列排布的多个子像素；
    位于同一行的多个所述子像素与同一所述扫描信号线电连接；
    位于同一列的多个所述子像素与同一所述数据信号线电连接；
    所述信号走线的延伸方向与所述扫描信号线的延伸方向交叉；
    多个所述子像素中包括多个显示子像素和位于所述多个显示子像素至少一侧的多个非显示子像素；与同一列所述非显示子像素电连接的所述数据信号线为虚拟数据信号线；至少一条所述虚拟数据信号线复用为所述反向扫描检测信号传输线；
    或者，至少一条所述信号走线为虚拟信号走线；至少一条所述虚拟信号走线复用为所述反向扫描检测信号传输线。
  7. 根据权利要求6所述的显示面板，还包括：
    衬底基板；
    位于所述衬底基板一侧且绝缘间隔设置的第一金属层、第二金属层和第三金属层；所述第一金属层包括所述扫描信号线，所述第二金属层包括所述数据信号线，所述第三金属层包括所述信号走线。
  8. 根据权利要求6所述的显示面板，还包括：第一连接线；所述第一连接线的延伸方向与所述反向扫描检测信号传输线的延伸方向交叉；
    所述第一连接线的第一端通过所述反向扫描检测信号传输线与所述第二开 关单元的输入端电连接；所述第一连接线的第二端与所述第一级扫描驱动单元的扫描信号检测端电连接。
  9. 根据权利要求8所述的显示面板，其中，所述第一连接线与所述扫描信号线同层设置；或者，所述第一连接线与所述数据信号线同层设置；或者，所述第一连接线与所述信号走线同层设置。
  10. 根据权利要求8所述的显示面板，其中，与所述第一级扫描驱动单元的扫描信号输出端电连接的所述扫描信号线为虚拟扫描信号线；所述虚拟扫描信号线未与所述显示子像素电连接；
    在所述第一级扫描驱动单元的扫描信号检测端为所述第一级扫描驱动单元的扫描信号输出端的情况下，至少部分所述虚拟扫描信号线复用为所述第一连接线。
  11. 根据权利要求1所述的显示面板，还包括：启动信号传输线、第二选通电路和开关模块；
    所述第二选通电路包括第三开关单元和第四开关单元；
    所述启动信号传输线的第一端分别与所述第三开关单元的输出端、所述第四开关单元的输入端以及所述第N级扫描驱动单元的反向扫描输入端电连接；所述启动信号传输线的第二端分别与所述第一级扫描驱动单元的正向扫描输入端和所述开关模块的输出端电连接；
    所述第三开关单元的输入端与所述启动信号引脚电连接；所述第四开关单元的输出端与所述第二开关单元的输入端电连接；所述第三开关单元设置为在所述启动信号引脚提供启动信号的有效脉冲时导通；所述第四开关单元设置为在输出反向扫描检测信号时导通；
    所述开关模块的输入端接收固定电压信号；所述开关模块的控制端与所述第一级扫描驱动单元的扫描信号检测端电连接；所述开关模块设置为在所述反向扫描检测阶段，根据所述第一级扫描驱动单元的扫描信号检测端的信号，输出所述反向扫描检测信号。
  12. 根据权利要求11所述的显示面板，其中，所述第三开关单元包括第三传输门；所述第三传输门包括第三N型晶体管和第三P型晶体管；所述第三N型晶体管的第一极与所述第三P型晶体管的第一极均为所述第三开关单元的输入端；所述第三N型晶体管的第二极与所述第三P型晶体管的第二极均为所述第三开关单元的输出端；所述第三N型晶体管的栅极接收第五控制信号，所述第三P型晶体管的栅极接收第六控制信号；
    所述第四开关单元包括第四传输门；所述第四传输门包括第四N型晶体管 和第四P型晶体管；所述第四N型晶体管的第一极与所述第四P型晶体管的第一极均为所述第四开关单元的输入端；所述第四N型晶体管的第二极与所述第四P型晶体管的第二极均为所述第四开关单元的输出端；所述第四N型晶体管的栅极接收第七控制信号，所述第四P型晶体管的栅极接收第八控制信号。
  13. 根据权利要求12所述的显示面板，其中，所述第五控制信号复用为所述第八控制信号；所述第六控制信号复用为所述第七控制信号。
  14. 根据权利要求13所述显示面板，还包括：反相器；所述多个信号引脚还包括控制信号引脚；
    所述控制信号引脚设置为提供所述第五控制信号；所述反相器的输入端与所述控制信号引脚电连接，所述反相器的输出端与所述第三P型晶体管的栅极和所述第四N型晶体管的栅极电连接；所述第三N型晶体管的栅极和所述第四P型晶体管的栅极与所述控制信号引脚电连接；
    或者，所述控制信号引脚设置为提供所述第六控制信号；所述反相器的输入端与所述控制信号引脚电连接，所述反相器的输出端与所述第三N型晶体管的栅极和所述第四P型晶体管的栅极电连接；所述第三P型晶体管的栅极和所述第四N型晶体管的栅极与所述控制信号引脚电连接。
  15. 根据权利要求11所述的显示面板，其中，所述开关模块包括开关晶体管；
    所述开关晶体管的栅极为所述开关模块的控制端，所述开关晶体管的第一极为所述开关模块的输入端，所述开关晶体管的第二极为所述开关模块的输出端；
    或者，所述开关晶体管的第一极为所述开关模块的控制端，所述开关晶体管的栅极为所述开关模块的输入端；所述开关晶体管的第二极为所述开关模块的输出端。
  16. 根据权利要求11所述的显示面板，其中，所述多个信号引脚还包括第一电平信号引脚；
    多级所述扫描驱动单元的第一电平信号输入端均与所述第一电平信号引脚电连接；所述第一电平信号引脚设置为提供第一电平信号；
    其中，所述第一电平信号复用为所述固定电压信号。
  17. 一种显示面板的检测方法，应用于权利要求1～16中任一项所述的显示面板，所述检测方法至少包括：正向扫描检测阶段和反向扫描检测阶段；
    在所述正向扫描检测阶段，提供启动信号，以使所述第一级扫描驱动单元 至所述第N级扫描驱动单元的多级所述扫描驱动单元依次输出移位信号和扫描信号；以及，控制所述第一开关单元导通，所述第二开关单元关闭，通过所述第一开关单元接收所述第N级扫描驱动单元的扫描信号检测端的信号作为正向扫描检测信号，并根据所述正向扫描检测信号检测所述扫描驱动电路的正向扫描功能；其中，所述正向扫描检测信号为所述第N级扫描驱动单元输出的移位信号或扫描信号；
    在所述反向扫描检测阶段，提供启动信号，以使所述第N级扫描驱动单元至所述第一级扫描驱动单元的多级所述扫描驱动单元依次输出移位信号和扫描信号；以及，控制所述第一开关单元关闭，所述第二开关单元导通，通过所述第二开关单元接收所述第一级扫描驱动单元的扫描信号检测端的信号作为反向扫描检测信号，并根据所述反向扫描检测信号检测所述扫描驱动电路的反向扫描功能；其中，所述反向扫描检测信号为所述第一级扫描驱动单元输出的移位信号或扫描信号。
  18. 根据权利要求17所述的检测方法，其中，所述第一开关单元包括第一传输门；所述第一传输门包括第一N型晶体管和第一P型晶体管；所述第一N型晶体管的第一极与所述第一P型晶体管的第一极均为所述第一开关单元的输入端；所述第一N型晶体管的第二极与所述第一P型晶体管的第二极均为所述第一开关单元的输出端；所述第一N型晶体管的栅极接收第一控制信号，所述第一P型晶体管的栅极接收第二控制信号；所述第二开关单元包括第二传输门；所述第二传输门包括第二N型晶体管和第二P型晶体管；所述第二N型晶体管的第一极与所述第二P型晶体管的第一极均为所述第二开关单元的输入端；所述第二N型晶体管的第二极与所述第二P型晶体管的第二极均为所述第二开关单元的输出端；所述第二N型晶体管的栅极接收第三控制信号，所述第二P型晶体管的栅极接收第四控制信号；
    所述正向扫描检测阶段包括：提供启动信号，以使从所述第一级扫描驱动单元至所述第N级扫描驱动单元的多级所述扫描驱动单元依次输出移位信号和扫描信号；以及，所述第一控制信号控制所述第一N型晶体管导通，所述第二控制信号控制所述第一P型晶体管导通，所述第三控制信号控制所述第二N型晶体管关闭，所述第四控制信号控制所述第二P型晶体管关闭，以使所述第一传输门导通，所述第二传输门关闭，通过所述第一传输门接收所述第N级扫描驱动单元的扫描信号检测端的正向扫描检测信号，并根据所述正向扫描检测信号检测所述扫描驱动电路的正向扫描功能；
    所述反向扫描检测阶段包括：提供启动信号，以使从所述第N级扫描驱动单元至所述第一级扫描驱动单元的多级所述扫描驱动单元依次输出移位信号和 扫描信号；以及，所述第一控制信号控制所述第一N型晶体管关闭，所述第二控制信号控制所述第一P型晶体管关闭，所述第三控制信号控制所述第二N型晶体管导通，所述第四控制信号控制所述第二P型晶体管导通，以使所述第一传输门关闭，所述第二传输门导通，通过导通的所述第二传输门接收所述第一级扫描驱动单元的扫描信号检测端的反向扫描检测信号，并根据所述反向扫描检测信号检测所述扫描驱动电路的反向扫描功能。
  19. 根据权利要求17所述的检测方法，其中，所述显示面板还包括启动信号传输线、第二选通电路和开关模块；所述第二选通电路包括第三开关单元和第四开关单元；所述启动信号传输线的第一端分别与所述第三开关单元的输出端、所述第四开关单元的输入端以及所述第N级扫描驱动单元的反向扫描输入端电连接；所述启动信号传输线的第二端分别与所述第一级扫描驱动单元的正向扫描输入端和所述开关模块的输出端电连接；所述第三开关单元的输入端与所述启动信号引脚电连接；所述第四开关单元的输出端与所述第二开关单元的输入端电连接；所述开关模块的输入端接收固定电压信号；所述开关模块的控制端与所述第一级扫描驱动单元的扫描信号检测端电连接；
    所述反向扫描检测阶段包括第一阶段、第二阶段和第三阶段；
    在所述第一阶段，所述第三开关单元导通，所述第四开关单元关闭，所述启动信号通过所述第三开关单元输出至所述启动信号传输线，以使从所述第N级扫描驱动单元至所述第一级扫描驱动单元的多级所述扫描驱动单元依次输出扫描信号和移位信号；
    在所述第二阶段，所述第二开关单元和所述第四开关单元导通，所述第一开关单元和所述第三开关单元关闭，所述开关模块根据所述第一级扫描驱动单元的扫描信号检测端的信号，输出所述反向扫描检测信号；
    在所述第三阶段，通过所述启动信号传输线以及所述第四开关单元和所述第二开关单元接收所述反向扫描检测信号，并根据所述反向扫描检测信号检测所述扫描驱动电路的反向扫描功能。
  20. 一种显示装置，包括：权利要求1～16中任一项所述的显示面板。
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