WO2019184253A1 - 扫描驱动电路 - Google Patents

扫描驱动电路 Download PDF

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Publication number
WO2019184253A1
WO2019184253A1 PCT/CN2018/104455 CN2018104455W WO2019184253A1 WO 2019184253 A1 WO2019184253 A1 WO 2019184253A1 CN 2018104455 W CN2018104455 W CN 2018104455W WO 2019184253 A1 WO2019184253 A1 WO 2019184253A1
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Prior art keywords
output
signal
thin film
film transistor
multiplexing module
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PCT/CN2018/104455
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English (en)
French (fr)
Inventor
徐京
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US16/089,083 priority Critical patent/US10789893B1/en
Publication of WO2019184253A1 publication Critical patent/WO2019184253A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • the organic light-emitting diode display device has the advantages of self-luminescence, no backlight, high contrast, thin thickness, wide viewing angle, fast response speed, flexible panel, wide temperature range, simple structure and simple process. It is considered to be an emerging application technology for next-generation flat panel displays.
  • An OLED display device generally includes a substrate, an anode disposed on the substrate, an organic light-emitting layer disposed on the anode, an electron transport layer disposed on the organic light-emitting layer, and a cathode disposed on the electron transport layer.
  • the holes from the anode and the electrons from the cathode are emitted to the organic light-emitting layer, and these electrons and holes are combined to generate an excited electron-hole pair, and the excited electron-hole pair is converted from the excited state to the ground state. Achieve light.
  • the frame frequency of the display panel is getting higher and higher, and the corresponding gate scanning frequency is also higher and higher, which causes the opening time of the thin film transistor to be shorter and shorter, resulting in a tight charging time of the pixel, which often occurs.
  • the prior art proposes a pre-charging method, that is, to provide the next pixel row of the currently charged pixel row, pre-charge it, and then scan to the next pixel row, The next pixel row is charged on a precharge basis to avoid undercharging.
  • the prior art also performs chamfer processing on the scan signal of the driving thin film transistor switch, specifically, the scan signal is input to the scan driving circuit (Gate IC).
  • the power supply signal (VGH) for level shifting is chamfered to generate a scan signal having a chamfer angle.
  • chamfering occurs when the pixel is precharged, resulting in a precharge effect. Reduce, affecting the charging effect of the pixel.
  • the present invention provides a scan driving circuit including an output module including a plurality of rows of output channels arranged in sequence, at least one first multiplexing module, and at least one second multiplexing Module
  • the first multiplexing module is the same number as the second multiplexing module
  • Each row of output channels includes: an input terminal, a power terminal, and an output terminal.
  • the input terminal of each row of output channels is connected to an input pulse signal corresponding to the output channel of the row, and the output terminal outputs a scan signal corresponding to the output channel of the row, 4m-
  • the power supply end of the 3-line output channel is connected to the first power supply signal, and the power supply end of the 4m-2th output channel is connected to the output end of the first multiplexing module, and the power supply end of the 4m-1th output channel is connected.
  • the output end of a second multiplexing module, the power end of the 4m line output channel is connected to the second power signal, and m is a positive integer;
  • Each of the control terminals of the first multiplexing module is connected to the selection signal, the first input terminal is connected to the first power signal, and the second input terminal is connected to the second power signal, each of the second multiplexing
  • the control end of the module is connected to the selection signal, the first input end is connected to the first power supply signal, and the second input end is connected to the second power supply signal;
  • the selection signal controls the output end of each first multiplexing module And outputting one of the first power signal and the second power signal, and each of the second multiplexing module outputs outputs another one of the first power signal and the second power signal different from the output of the first multiplexing module output .
  • the scan driving circuit further includes: a shift register and a logic control unit electrically connected to the shift register and the output module respectively;
  • the shift register receives a clock signal and a scan start signal, and is configured to generate a plurality of input pulse signals according to the clock signal and the scan start signal to be output to the logic control unit;
  • the logic control unit receives an enable signal for correspondingly inputting the plurality of input pulse signals into respective output channels of the output module according to an enable signal.
  • the first power signal and the second power signal are both chamfering signals.
  • the period in which the first power signal and the second power signal generate a chamfer are both equal to twice the period of the clock signal, respectively located on the first power signal and the second power signal and adjacent to the two chamfers
  • the time is different from the period of one clock signal, and the rising edge of each chamfer corresponds to a rising edge of the clock signal (CPV).
  • the scan driving circuit is configured to electrically connect the pixel array, and the pixel array includes a plurality of pixel driving units arranged in an array.
  • Each output channel corresponds to a row of pixel driving units, and each pixel driving unit comprises: a switching thin film transistor, a driving thin film transistor, a storage capacitor, and an organic light emitting diode;
  • the gate of the switching thin film transistor is electrically connected to the output end of the output channel corresponding to the pixel driving unit, the source is connected to the data signal, and the drain is electrically connected to the gate of the driving thin film transistor; the source of the driving thin film transistor a high potential is connected to the power source, and the drain is electrically connected to the anode of the organic light emitting diode; the first end of the storage capacitor is electrically connected to the gate of the driving thin film transistor, and the second end is electrically connected to the drain of the driving thin film transistor; The cathode of the organic light emitting diode is connected to the power source at a low potential;
  • the selection signal is low, the output of each first multiplexing module outputs a second power signal, and the output of each second multiplexing module outputs a first power signal.
  • the multi-row output channel starts from the output channel of the first row, and each of the two adjacent output channels is a group, and is divided into a plurality of output channel groups, and each output channel group corresponds to one row of pixel driving units;
  • Each of the pixel driving units includes: a switching thin film transistor, a driving thin film transistor, a sensing thin film transistor, a storage capacitor, and an organic light emitting diode;
  • the gate of the switching thin film transistor is electrically connected to an output end of one of the output channel groups corresponding to the pixel driving unit, the source is connected to the data signal, and the drain is electrically connected to the gate of the driving thin film transistor;
  • the source of the driving thin film transistor is connected to the high potential of the power source, and the drain is electrically connected to the anode of the organic light emitting diode;
  • the gate of the sensing thin film transistor is electrically connected to the output channel group corresponding to the pixel driving unit, which is different from the switch.
  • An output end of another output channel of the gate of the thin film transistor the source is electrically connected to the anode of the organic light emitting diode, and the drain outputs a sensing signal;
  • the first end of the storage capacitor is electrically connected to the gate of the driving thin film transistor, The second end is electrically connected to the drain of the driving thin film transistor;
  • the cathode of the organic light emitting diode is connected to the power source with a low potential;
  • the selection signal is high, the output of each first multiplexing module outputs a first power signal, and the output of each second multiplexing module outputs a second power signal.
  • the number of the first multiplexing module and the second multiplexing module is one.
  • the number of the first multiplexing module and the second multiplexing module are multiple, and each of the first multiplexing module and each of the second multiplexing modules is correspondingly connected to one output channel.
  • the scan signal outputted by each line of the output channel is a signal generated by the output pulse signal of the output channel of the row by the signal output of the output channel of the row.
  • the present invention also provides a scan driving circuit comprising an output module, the output module comprising a plurality of rows of output channels arranged in sequence, at least one first multiplexing module and at least one second multiplexing module;
  • the first multiplexing module is the same number as the second multiplexing module
  • Each row of output channels includes: an input terminal, a power terminal, and an output terminal.
  • the input terminal of each row of output channels is connected to an input pulse signal corresponding to the output channel of the row, and the output terminal outputs a scan signal corresponding to the output channel of the row, 4m-
  • the power supply end of the 3-line output channel is connected to the first power supply signal, and the power supply end of the 4m-2th output channel is connected to the output end of the first multiplexing module, and the power supply end of the 4m-1th output channel is connected.
  • the output end of a second multiplexing module, the power end of the 4m line output channel is connected to the second power signal, and m is a positive integer;
  • Each of the control terminals of the first multiplexing module is connected to the selection signal, the first input terminal is connected to the first power signal, and the second input terminal is connected to the second power signal, each of the second multiplexing
  • the control end of the module is connected to the selection signal, the first input end is connected to the first power supply signal, and the second input end is connected to the second power supply signal;
  • the selection signal controls the output end of each first multiplexing module And outputting one of the first power signal and the second power signal, and each of the second multiplexing module outputs outputs another one of the first power signal and the second power signal different from the output of the first multiplexing module output ;
  • the scan driving circuit further includes: a shift register and a logic control unit electrically connected to the shift register and the output module respectively;
  • the shift register receives a clock signal and a scan start signal, and is configured to generate a plurality of input pulse signals according to the clock signal and the scan start signal to be output to the logic control unit;
  • the logic control unit receives an enable signal for correspondingly inputting the plurality of input pulse signals to respective output channels of the output module according to an enable signal;
  • first power signal and the second power signal are both chamfering signals
  • the periods in which the first power signal and the second power signal are chamfered are equal to twice the period of the clock signal, and the two adjacent chamfers are respectively located on the first power signal and the second power signal.
  • the generated time is different from the period of one clock signal, and the rising edge of each chamfer corresponds to a rising edge of the clock signal;
  • the scan driving circuit is configured to electrically connect the pixel array, and the pixel array includes a plurality of pixel driving units arranged in an array.
  • the present invention provides a scan driving circuit comprising: a plurality of rows of output channels arranged in sequence, at least one first multiplexing module, and at least one second multiplexing module; each output channel of each row
  • the utility model comprises: an input end, a power supply end and an output end, wherein an input end of each line output channel is connected to an input pulse signal corresponding to the output channel of the line, and an output end outputs a scan signal corresponding to the output channel of the line, and the output channel of the 4m-3 line output channel
  • the power terminal is connected to the first power signal, the power end of the 4m-2th output channel is connected to the output end of the first multiplexing module, and the power end of the 4m-1th output channel is connected to the second multipath.
  • An output end of the multiplexing module, the power end of the 4m line output channel is connected to the second power signal; the control ends of the first multiplexing module and the second multiplexing module are respectively connected to the selection signal, and the input end Each of the first power signal and the second power signal is connected, and the first multiplexer module and the second multiplexer module are controlled to change the power signal of the output by the selection signal, thereby changing the output channel access as needed. Power signal, to ensure that the precharge effect is also applicable to multiple scanning timing requirements.
  • FIG. 1 is a structural view of a scan driving circuit of the present invention
  • FIG. 2 is a first multiplexing module in the first embodiment of the scan driving circuit of the present invention, a circuit diagram between the second multiplexing module and each of the output channels;
  • FIG. 3 is a first multiplexing module in a second embodiment of the scan driving circuit of the present invention, a circuit diagram between the second multiplexing module and each of the output channels;
  • FIG. 4 is a first embodiment of a pixel driving circuit electrically connected to a scan driving circuit of the present invention Circuit diagram
  • FIG. 5 is a timing diagram of the scan driving circuit of the present invention driving the pixel driving circuit shown in FIG. Figure
  • FIG. 6 is a first embodiment of a pixel driving circuit electrically connected to a scan driving circuit of the present invention Circuit diagram
  • FIG. 7 is a timing diagram of the scan driving circuit of the present invention driving the pixel driving circuit shown in FIG. Figure.
  • the present invention provides a scan driving circuit including an output module 1.
  • the output module 1 includes: a plurality of rows of output channels 10 arranged in sequence, at least one first multiplexing module 20, and at least A second multiplexing module 30.
  • each row of output channels 10 includes: an input end, a power end, and an output end, and an input end of each row of the output channel 10 is connected to an input pulse signal corresponding to the output channel 10 of the row.
  • the output terminal outputs a scan signal corresponding to the output channel 10 of the row, and the scan signal outputted by each row of the output channel 10 is an input pulse of the output channel of the row output channel 10 by using the signal of the power terminal of the row.
  • the signal generated after the signal is level-shifted, and the level shift is specifically boosted.
  • the input end of the output line 10 of the first row is connected to the input pulse signal O1 of the first row, and the output of the output terminal is the first.
  • Row scan signal G1 the input of the output line 10 of the second row is connected to the input pulse signal O2 of the second row, the output of the scan signal G2 of the second row is output, and the input of the output channel 10 of the third row is connected to the input pulse of the third row.
  • the output end outputs the third line scan signal G3, the input end of the fourth line output channel 10 is connected to the fourth line input pulse signal O4, the output end outputs the fourth line scan signal G4, and the n-3th line output channel 10 Input to the n-3th line
  • the pulse signal On-3 is output, the output end outputs the n-3th line scan signal Gn-3, the input end of the n-2th output channel 10 is connected to the n-2th line input pulse signal On-2, and the output end is outputted.
  • the n-2 line scan signal Gn-2 the input end of the output channel 10 of the n-1th line is connected to the input pulse signal On-1 of the n-1th line, and the output end outputs the scan signal Gn-1 of the n-1th line, the first The input end of the n-line output channel 10 is connected to the input pulse signal On of the nth line, and the output end outputs the scan signal Gn of the nth line.
  • each control end of the first multiplexing module 20 is connected to the selection signal SEL, and the first input terminal is connected to the first power signal VGHO, and the second input terminal is Accessing the second power signal VGHE
  • each control end of the second multiplexing module 30 is connected to the selection signal SEL, the first input terminal is connected to the first power signal VGHO, and the second input terminal is connected to the second Power signal VGHE.
  • the selection signal SEL controls the output end of each first multiplexing module 20 to output one of the first power signal VGHO and the second power signal VGHE, and the output of each second multiplexing module 30 The other of the output of the first power supply signal VGHO and the second power supply signal VGHE is different from the output of the output of the first multiplexing module 20.
  • the power terminal of the 4m-3th output channel 10 is connected to the first power signal VGHO, and the power terminal of the 4m-2th output channel 10 is connected to a first multiplexing module 20
  • the output end of the 4m-1th output channel 10 is connected to the output end of a second multiplexing module 30, and the power end of the 4m line output channel 10 is connected to the second power signal VGHE.
  • the number of the first multiplexing module 20 and the second multiplexing module 30 are multiple, and each of the first multiple paths is complex.
  • the module 20 and each of the second multiplexing modules 30 are respectively connected to an output channel 10, that is, each multiplex module is electrically connected to only one output channel 10, and each of the second multiplexing modules 30 Only one output channel 10 is electrically connected, and different output channels 10 are electrically connected to different multiplexing modules.
  • the output channels 10 of the second row and the n-2th row are electrically connected to each other.
  • a different first multiplexing module 20, the output channels 10 of the third row and the n-1th row are electrically connected to two different second multiplexing modules 30.
  • the number of the first multiplexing module 20 and the second multiplexing module 30 is only one, and each of the first multiplexing The module 20 and each of the second multiplexing modules 30 are respectively connected to a plurality of corresponding output channels 10.
  • the output channels 10 of the second row and the n-2th row are electrically connected to the one.
  • a multiplexing module 20, the output channels 10 of the third row and the n-1th row are electrically connected to the one second multiplexing module 30.
  • the scan driving circuit provided by the present invention further includes: a shift register 2 and a logic control unit 3 electrically connected to the shift register 2 and the output module 1 respectively;
  • the shift register 2 receives the clock signal CPV and the scan start signal DIO, for generating a plurality of input pulse signals according to the clock signal CPV and the scan start signal DIO to the logic control unit 3;
  • the logic control unit 3 receives an enable signal OE for correspondingly inputting the plurality of input pulse signals into the respective output channels 10 of the output module 1 according to the enable signal OE.
  • the first power signal VGHO and the second power signal VGHE are both chamfering signals, that is, the waveforms of the first power signal VGHO and the second power signal VGHE have periodic occurrences. angle.
  • the periods in which the first power signal VGHO and the second power signal VGHE are chamfered are equal to twice the period of the clock signal CPV, respectively located on the first power signal VGHO and the second power signal VGHE.
  • the time of the two chamfers is different from the period of one clock signal CPV, and the rising edge of each chamfer is generated simultaneously with a rising edge of the clock signal CPV.
  • the first power signal VGHO The time taken by the upper chamfer 100 and the chamfer 200 of the second power signal VGHE differs by the period of one clock signal CPV.
  • the scan driving circuit of the present invention is used for electrically connecting pixel arrays
  • the pixel array includes a plurality of pixel driving units arranged in an array
  • the pixel driving unit has various embodiments, which can be modified by changing the present invention.
  • the selection signal in the scan driving circuit is adapted to the scanning timing of different pixel driving units.
  • the typical pixel driving unit includes the 2T1C structure shown in FIG. 4 of the present invention and the 3T1C structure shown in FIG. 6 of the present invention.
  • the pixel driving unit of the 2T1C structure includes: a switching thin film transistor T1, a driving thin film transistor T2, a storage capacitor C1, and an organic light emitting diode D1; and a gate of the switching thin film transistor T1 is electrically connected.
  • the scan driving circuit and the pixel array of the pixel driving unit using the 2T1C structure are connected in a manner that the gates of the switching thin film transistors T1 in the pixel driving unit of the first row are all connected to the scan driving circuit.
  • the first row of the output signal 10 outputs the scan signal G1
  • the gate of the switching thin film transistor T1 of the pixel driving unit of the second row is connected to the scan signal G2 outputted by the second row output channel 10 of the scan driving circuit.
  • the gates of the switching thin film transistors T1 in the pixel driving unit of the third row are all connected to the scanning signal G3 outputted from the third row output channel 10 of the scan driving circuit, and are sequentially analogized to the last row of pixel driving units.
  • each first multiplexing module 20 when the scan driving circuit drives the pixel driving unit of the 2T1C structure, the selection signal SEL is low, and the output end of each first multiplexing module 20 outputs the second power signal.
  • the output end of each second multiplexing module 30 outputs the first power signal VGHO, so that the scanning signals of the pixel driving units of the odd rows are all generated by the first power signal VGHO, and the scanning signals of the pixel driving units of the even rows are Produced by the second power signal VGHE, such as the portion where the high potential pulses of the adjacent two scan signals overlap in FIG. 5, that is, the stage in which the next row of scan signals precharges the corresponding pixel row, such as the first row.
  • the portion where the scan signal G1 and the second line scan signal G2 overlap is a stage in which the second line scan signal precharges the second line of pixels, and the first line scan signal G1 and the second line scan signal G2 are respectively A power signal VGHO and a second power signal VGHE are generated, and the first line scan signal G1 and the second line scan signal G2 are simultaneously generated by one power signal, thereby effectively preventing the signal from being scanned during the precharge phase.
  • Chamfered, chamfer produces only ensure charging phase, results in a reduction chamfered to prevent the effect of the precharge.
  • the pixel driving unit of the 3T1C includes a switching thin film transistor T1', a driving thin film transistor T2', a sensing thin film transistor T3', a storage capacitor C1', and an organic light emitting diode D1'.
  • the pixel driving unit of the 3T1C needs two scanning signals to respectively control the switching thin film transistor T1' and the sensing thin film transistor T3'. Therefore, the output channel 10 needs to be grouped, specifically: the multi-row output channel 10 is from the first The row output channel 10 starts, and each two rows of adjacent output channels 10 are a group, and are divided into a plurality of output channel groups, and each output channel group corresponds to one row of pixel driving units, for example, the first row output channel 10 and the second row output.
  • the channel 10 is a group, the output line 10 of the third row and the output channel 10 of the fourth row are a group, and the output channel 10 of the fifth row and the output channel 10 of the sixth row are a group, and so on until the last row.
  • the gate of the switching thin film transistor T1' When connected, the gate of the switching thin film transistor T1' is electrically connected to the output end of one of the output channels 10 corresponding to the pixel driving unit, the source is connected to the data signal Data', and the drain is electrically connected.
  • the sensing signal SEN' is output; the first end of the storage capacitor C1' is electrically connected to the gate of the driving thin film transistor T2', and the second end is electrically connected to
  • the gate of the switching thin film transistor T1' located in the pixel driving unit of the first row is electrically connected to the output end of the output channel 10 of the first row
  • the gate of the sensing thin film transistor T3' is electrically connected to the output channel 10 of the second row.
  • the output terminal of the switching thin film transistor T1' in the second row of pixel driving units is electrically connected to the output end of the third row output channel 10
  • the gate of the sensing thin film transistor T3' is electrically connected to the fourth row output. The output of channel 10, and so on, is pushed to the last row.
  • the selection signal SEL is at a high potential, and the output end of each first multiplexing module 20 outputs a first power signal VGHO, and the output of each second multiplexing module 30 outputs a
  • the power signal VGHE is used to ensure that the output channel 10 in the same output channel group is connected to the same power signal, thereby avoiding the chamfering of the scanning signal during the pre-charging phase, ensuring that the chamfering is only generated during the charging phase, preventing the pre-preparation due to the chamfering angle.
  • the charging effect is reduced.
  • the present invention provides a scan driving circuit comprising: a plurality of rows of output channels arranged in sequence, at least one first multiplexing module, and at least one second multiplexing module; each output channel of each row includes The input end, the power end and the output end, the input end of each line output channel is connected to the input pulse signal corresponding to the output channel of the line, the output end outputs the scan signal corresponding to the output channel of the line, and the power supply of the output channel of the 4m-3 line
  • the terminal is connected to the first power signal
  • the power terminal of the 4m-2th output channel is connected to the output end of the first multiplexing module
  • the power terminal of the 4m-1th output channel is connected to the second multiplexing
  • the control ends of the first multiplexing module and the second multiplexing module are all connected to the selection signal, and the input ends are Accessing the first power signal and the second power signal, the first multiplexing module and the

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Abstract

一种扫描驱动电路。所述扫描驱动电路包括：依次排列的多行输出通道（10）、至少一个第一多路复用模块（20）及至少一个第二多路复用模块（30）；第4m-3行输出通道（10）的电源端接入第一电源信号，第4m-2行输出通道（10）的电源端接入一第一多路复用模块（20）的输出端，第4m-1行输出通道（10）的电源端接入一第二多路复用模块（30）的输出端，第4m行输出通道（10）的电源端接入第二电源信号；所述第一多路复用模块（20）和第二多路复用模块（30）的控制端均接入选择信号，输入端均接入第一电源信号和第二电源信号，能够通过选择信号控制第一多路复用模块（20）和第二多路复用模块（30）改变其输出的电源信号，从而根据需要改变输出通道（10）接入的电源信号，使得扫描驱动电路同时适用于多种扫描时序的需求。

Description

扫描驱动电路 技术领域
本发明涉及显示技术领域，尤其涉及一种扫描驱动电路。
背景技术
平面显示器件具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示器件主要包括液晶显示器件(Liquid Crystal Display，LCD)及有机发光二极管显示器件(Organic Light Emitting Display，OLED)。
有机发光二极管显示器件由于同时具备自发光，不需背光源、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。
OLED显示装置通常包括：基板、设于基板上的阳极、设于阳极上的有机发光层，设于有机发光层上的电子传输层、及设于电子传输层上的阴极。工作时向有机发光层发射来自阳极的空穴和来自阴极的电子，将这些电子和空穴组合产生激发性电子-空穴对，并将激发性电子-空穴对从受激态转换为基态实现发光。
随着显示技术的发展，显示面板的帧频率越来越高，相应的栅极扫描频率也越来越高，造成薄膜晶体管的打开时间也越来越短，造成像素的充电时间紧张，经常出现充电不足的情况，为了解决上述问题，现有技术提出了一种预充电方法，即将提供打开当前充电的像素行的下一像素行，对其进行预充电，然后扫描到下一像素行时，在预充电的基础上对下一像素行进行充电，以避免充电不足。
与此同时，为了减少薄膜晶体管在关闭时产生的电容耦合效应，现有技术还会对驱动薄膜晶体管开关的扫描信号进行削角处理，具体为，在扫描驱动电路(Gate IC)对扫描信号进电平转移时，对用于电平转移的电源信号(VGH)进行削角处理，以产生具有削角的扫描信号，此时，在对像素进行预充电时会出现削角，导致预充电效果降低，影响像素的充电效果。
发明内容
本发明的目的在于提供一种扫描驱动电路，能够根据需要改变输出通道接入的电源信号，保证预充电效果的同时还能够适用于多种扫描时序的 需求。
为实现上述目的，本发明提供了一种扫描驱动电路，包括输出模块，所述输出模块包括依次排列的多行输出通道、至少一个第一多路复用模块及至少一个第二多路复用模块；
所述第一多路复用模块与第二多路复用模块的数量相同；
每一行输出通道均包括：输入端、电源端及输出端，每一行输出通道的输入端接入该行输出通道对应的输入脉冲信号，输出端输出该行输出通道对应的扫描信号，第4m-3行输出通道的电源端接入第一电源信号，第4m-2行输出通道的电源端接入一第一多路复用模块的输出端，第4m-1行输出通道的电源端接入一第二多路复用模块的输出端，第4m行输出通道的电源端接入第二电源信号，m为正整数；
每一个第一多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号，每一个第二多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号；所述选择信号控制各个第一多路复用模块的输出端输出第一电源信号和第二电源信号中的一个，各个第二多路复用模块输出端输出第一电源信号和第二电源信号中不同于第一多路复用模块输出端输出的另一个。
所述扫描驱动电路还包括：移位寄存器以及分别与所述移位寄存器和输出模块电性连接的逻辑控制单元；
所述移位寄存器接收时钟信号及扫描起始信号，用于根据所述时钟信号及扫描起始信号产生多个输入脉冲信号输出至逻辑控制单元；
所述逻辑控制单元接收使能信号，用于根据使能信号将所述多个输入脉冲信号对应输入到所述输出模块的各个输出通道中。
所述第一电源信号和第二电源信号均为削角信号。
所述第一电源信号和第二电源信号产生削角的周期均等于时钟信号的周期的两倍，分别位于所述第一电源信号和第二电源信号上且相邻的两个削角产生的时间相差一个时钟信号的周期，且每一削角的上升沿均对应与时钟信号(CPV)的一上升沿同时产生。
所述扫描驱动电路用于电性连接像素阵列，所述像素阵列包括阵列排布的多个像素驱动单元。
每一个输出通道对应一行像素驱动单元，每一个像素驱动单元均包括：开关薄膜晶体管、驱动薄膜晶体管、存储电容及有机发光二极管；
所述开关薄膜晶体管的栅极电性连接该像素驱动单元对应的输出通道 的输出端，源极接入数据信号，漏极电性连接驱动薄膜晶体管的栅极；所述驱动薄膜晶体管的源极接入电源高电位，漏极电性连接有机发光二极管的阳极；所述存储电容的第一端电性连接驱动薄膜晶体管的栅极，第二端电性连接驱动薄膜晶体管的漏极；所述有机发光二极管的阴极接入电源低电位；
所述选择信号为低电位，各个第一多路复用模块的输出端输出第二电源信号，各个第二多路复用模块的输出端输出第一电源信号。
所述多行输出通道自第1行输出通道开始，每两行相邻输出通道为一组，分为多个输出通道组，每一个输出通道组对应一行像素驱动单元；
每一个像素驱动单元均包括：开关薄膜晶体管、驱动薄膜晶体管、感测薄膜晶体管、存储电容及有机发光二极管；
所述开关薄膜晶体管的栅极电性连接该像素驱动单元对应的一个输出通道组中的一个输出通道的输出端，源极接入数据信号，漏极电性连接驱动薄膜晶体管的栅极；所述驱动薄膜晶体管的源极接入电源高电位，漏极电性连接有机发光二极管的阳极；所述感测薄膜晶体管的栅极电性连接该像素驱动单元对应的一个输出通道组中不同于开关薄膜晶体管的栅极的另一个输出通道的输出端，源极电性连接有机发光二极管的阳极，漏极输出感测信号；所述存储电容的第一端电性连接驱动薄膜晶体管的栅极，第二端电性连接驱动薄膜晶体管的漏极；所述有机发光二极管的阴极接入电源低电位；
所述选择信号为高电位，各个第一多路复用模块输出端输出第一电源信号，各个第二多路复用模块的输出端输出第二电源信号。
所述第一多路复用模块及第二多路复用模块的数量均为一个。
所述第一多路复用模块及第二多路复用模块的数量均为多个，每一个第一多路复用模块和每一个第二多路复用模块均对应连接一个输出通道。
每一行输出通道输出的扫描信号均为所述该行输出通道利用其电源端的信号对该行输出通道的输入端接入的输入脉冲信号进行电平转移后产生的信号。
本发明还提供一种扫描驱动电路，包括输出模块，所述输出模块包括依次排列的多行输出通道、至少一个第一多路复用模块及至少一个第二多路复用模块；
所述第一多路复用模块与第二多路复用模块的数量相同；
每一行输出通道均包括：输入端、电源端及输出端，每一行输出通道的输入端接入该行输出通道对应的输入脉冲信号，输出端输出该行输出通 道对应的扫描信号，第4m-3行输出通道的电源端接入第一电源信号，第4m-2行输出通道的电源端接入一第一多路复用模块的输出端，第4m-1行输出通道的电源端接入一第二多路复用模块的输出端，第4m行输出通道的电源端接入第二电源信号，m为正整数；
每一个第一多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号，每一个第二多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号；所述选择信号控制各个第一多路复用模块的输出端输出第一电源信号和第二电源信号中的一个，各个第二多路复用模块输出端输出第一电源信号和第二电源信号中不同于第一多路复用模块输出端输出的另一个；
所述扫描驱动电路还包括：移位寄存器以及分别与所述移位寄存器和输出模块均电性连接的逻辑控制单元；
所述移位寄存器接收时钟信号及扫描起始信号，用于根据所述时钟信号及扫描起始信号产生多个输入脉冲信号输出至逻辑控制单元；
所述逻辑控制单元接收使能信号，用于根据使能信号将所述多个输入脉冲信号对应输入到所述输出模块的各个输出通道中；
其中，所述第一电源信号和第二电源信号均为削角信号；
其中，所述第一电源信号和第二电源信号产生削角的周期均等于时钟信号的周期的两倍，分别位于所述第一电源信号和第二电源信号上且相邻的两个削角产生的时间相差一个时钟信号的周期，且每一削角的上升沿均对应与时钟信号的一上升沿同时产生；
其中，所述扫描驱动电路用于电性连接像素阵列，所述像素阵列包括阵列排布的多个像素驱动单元。
本发明的有益效果：本发明提供一种扫描驱动电路，包括：依次排列的多行输出通道、至少一个第一多路复用模块及至少一个第二多路复用模块；每一行输出通道均包括：输入端、电源端及输出端，每一行输出通道的输入端接入该行输出通道对应的输入脉冲信号，输出端输出该行输出通道对应的扫描信号，第4m-3行输出通道的电源端接入第一电源信号，第4m-2行输出通道的电源端接入一第一多路复用模块的输出端，第4m-1行输出通道的电源端接入一第二多路复用模块的输出端，第4m行输出通道的电源端接入第二电源信号；所述第一多路复用模块和第二多路复用模块的控制端均接入选择信号，输入端均接入第一电源信号和第二电源信号，能够通过选择信号控制第一多路复用模块和第二多路复用模块改变其输出的 电源信号，从而根据需要改变输出通道接入的电源信号，保证预充电效果的同时还能够适用于多种扫描时序的需求。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的扫描驱动电路的结构图；
图2为本发明的扫描驱动电路中的第一实施例中第一多路复用模块、 第二多路复用模块及各个输出通道之间的电路图；
图3为本发明的扫描驱动电路中的第二实施例中第一多路复用模块、 第二多路复用模块及各个输出通道之间的电路图；
图4为与本发明扫描驱动电路电性连接的像素驱动电路的第一实施例 的电路图；
图5为本发明的扫描驱动电路驱动图4所示的像素驱动电路时的时序 图；
图6为与本发明扫描驱动电路电性连接的像素驱动电路的第一实施例 的电路图；
图7为本发明的扫描驱动电路驱动图6所示的像素驱动电路时的时序 图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图3，本发明提供一种扫描驱动电路，包括输出模块1，所述输出模块1包括：依次排列的多行输出通道10、至少一个第一多路复用模块20及至少一个第二多路复用模块30。
具体地，如图2和图3所示，每一行输出通道10均包括：输入端、电源端及输出端，每一行输出通道10的输入端接入该行输出通道10对应的输入脉冲信号，输出端输出该行输出通道10对应的扫描信号，每一行输出通道10输出的扫描信号均为所述该行输出通道10利用其电源端的信号对该行输出通道10的输入端接入的输入脉冲信号进行电平转移后产生的信号，所述电平转移具体为升压，例如图2所示，第1行输出通道10的输入 端接入第1行输入脉冲信号O1，输出端输出第1行扫描信号G1，第2行输出通道10的输入端接入第2行输入脉冲信号O2，输出端输出第2行扫描信号G2，第3行输出通道10的输入端接入第3行输入脉冲信号O3，输出端输出第3行扫描信号G3，第4行输出通道10的输入端接入第4行输入脉冲信号O4，输出端输出第4行扫描信号G4，第n-3行输出通道10的输入端接入第n-3行输入脉冲信号On-3，输出端输出第n-3行扫描信号Gn-3，第n-2行输出通道10的输入端接入第n-2行输入脉冲信号On-2，输出端输出第n-2行扫描信号Gn-2，第n-1行输出通道10的输入端接入第n-1行输入脉冲信号On-1，输出端输出第n-1行扫描信号Gn-1，第n行输出通道10的输入端接入第n行输入脉冲信号On，输出端输出第n行扫描信号Gn。
具体地，如图2和图3所示，每一个第一多路复用模块20的控制端均接入选择信号SEL，第一输入端均接入第一电源信号VGHO，第二输入端均接入第二电源信号VGHE，每一个第二多路复用模块30的控制端均接入选择信号SEL，第一输入端均接入第一电源信号VGHO，第二输入端均接入第二电源信号VGHE。需要说明的是，所述选择信号SEL控制各个第一多路复用模块20的输出端输出第一电源信号VGHO和第二电源信号VGHE中的一个，各个第二多路复用模块30输出端输出第一电源信号VGHO和第二电源信号VGHE中不同于第一多路复用模块20输出端输出的另一个。
进一步地，设m为正整数，第4m-3行输出通道10的电源端接入第一电源信号VGHO，第4m-2行输出通道10的电源端接入一第一多路复用模块20的输出端，第4m-1行输出通道10的电源端接入一第二多路复用模块30的输出端，第4m行输出通道10的电源端接入第二电源信号VGHE。
具体地，请参阅图2，在本发明的第一实施例中，所述第一多路复用模块20及第二多路复用模块30数量均为多个，每一个第一多路复用模块20和每一个第二多路复用模块30均对应连接一个输出通道10，也即每一个多路复用模块仅电性连接一个输出通道10，每一个第二多路复用模块30也仅电性连接一个输出通道10，不同的输出通道10电性连接不同的多路复用模块，例如图2所示，第2行和第n-2行的输出通道10分别电性连接两个不同的第一多路复用模块20，第3行和第n-1行的输出通道10电性连接两个不同的第二多路复用模块30。
具体地，请参阅图3，在本发明的第二实施例中，所述第一多路复用模块20及第二多路复用模块30数量仅为一个，每一个第一多路复用模块20和每一个第二多路复用模块30均对应连接多个对应的输出通道10，例如图 2所示，第2行和第n-2行的输出通道10均电性连接该一个第一多路复用模块20，第3行和第n-1行的输出通道10均电性连接该一个第二多路复用模块30。
具体地，如图1所示，本发明提供的扫描驱动电路还包括：移位寄存器2以及分别与所述移位寄存器2和输出模块1均电性连接的逻辑控制单元3；
所述移位寄存器2接收时钟信号CPV及扫描起始信号DIO，用于根据所述时钟信号CPV及扫描起始信号DIO产生多个输入脉冲信号输出至逻辑控制单元3；
所述逻辑控制单元3接收使能信号OE，用于根据使能信号OE将所述多个输入脉冲信号对应输入到所述输出模块1的各个输出通道10中。
需要说明的是，本发明中所述第一电源信号VGHO和第二电源信号VGHE均为削角信号，即所述第一电源信号VGHO和第二电源信号VGHE的波形中具有周期性出现的削角。其中，所述第一电源信号VGHO和第二电源信号VGHE产生削角的周期均等于时钟信号CPV的周期的两倍，分别位于所述第一电源信号VGHO和第二电源信号VGHE上且相邻的两个削角产生的时间相差一个时钟信号CPV的周期，且每一削角的上升沿均对应与时钟信号CPV的一上升沿同时产生，例如，如图5所示，第一电源信号VGHO上的削角100和第二电源信号VGHE的削角200产生的时间相差一个时钟信号CPV的周期。
具体应用上，本发明的扫描驱动电路用于电性连接像素阵列，所述像素阵列包括阵列排布的多个像素驱动单元，所述像素驱动单元具有多种实施方式，可通过改变本发明的扫描驱动电路中的选择信号，来适应不同的像素驱动单元的扫描时序的需要，典型的像素驱动单元包括本发明图4所示的2T1C结构和本发明的图6所示的3T1C结构。
具体地，如图4所示，所述2T1C结构的像素驱动单元包括：开关薄膜晶体管T1、驱动薄膜晶体管T2、存储电容C1及有机发光二极管D1；所述开关薄膜晶体管T1的栅极电性连接该像素驱动单元对应的输出通道10的输出端，源极接入数据信号Data，漏极电性连接驱动薄膜晶体管T2的栅极；所述驱动薄膜晶体管T2的源极接入电源高电位OVDD，漏极电性连接有机发光二极管D1的阳极；所述存储电容C1的第一端电性连接驱动薄膜晶体管T2的栅极，第二端电性连接驱动薄膜晶体管T2的漏极；所述有机发光二极管D1的阴极接入电源低电位OVSS。
具体实施时，所述扫描驱动电路和上述采用2T1C结构的像素驱动单元 的像素阵列的连接方式为：第1行的像素驱动单元中的开关薄膜晶体管T1的栅极均接入所述扫描驱动电路的第1行输出通道10输出的扫描信号G1，第2行的像素驱动单元中的开关薄膜晶体管T1的栅极均接入所述扫描驱动电路的第2行输出通道10输出的扫描信号G2，第3行的像素驱动单元中的开关薄膜晶体管T1的栅极均接入所述扫描驱动电路的第3行输出通道10输出的扫描信号G3，依次类推至最后一行像素驱动单元。
进一步地，如图5所示，所述扫描驱动电路驱动2T1C结构的像素驱动单元工作时，所述选择信号SEL为低电位，各个第一多路复用模块20的输出端输出第二电源信号VGHE，各个第二多路复用模块30的输出端输出第一电源信号VGHO，从而奇数行的像素驱动单元的扫描信号均由第一电源信号VGHO产生，偶数行的像素驱动单元的扫描信号均由第二电源信号VGHE产生，如图5中相邻的两个扫描信号的高电位脉冲交叠的部分，即为下一行扫描信号对其对应的像素行进行预充电的阶段，如第1行扫描信号G1和第2行扫描信号G2交叠的部分即为第2行扫描信号对第2行像素进行预充电的阶段，此时第1行扫描信号G1和第2行扫描信号G2分别由第一电源信号VGHO和第二电源信号VGHE产生，相比于由一条电源信号同时产生第1行扫描信号G1和第2行扫描信号G2，能够有效避免在预充电阶段扫描信号产生削角，保证削角仅产生在充电阶段，防止因削角导致预充电效果降低。
进一步地，如图6所示，所述3T1C的像素驱动单元包括：开关薄膜晶体管T1’、驱动薄膜晶体管T2’、感测薄膜晶体管T3’、存储电容C1’及有机发光二极管D1’。
该3T1C的像素驱动单元需要两条扫描信号分别控制开关薄膜晶体管T1’和感测薄膜晶体管T3’，因此，还需要对输出通道10进行分组，具体为：所述多行输出通道10自第1行输出通道10开始，每两行相邻输出通道10为一组，分为多个输出通道组，每一个输出通道组对应一行像素驱动单元，例如：第1行输出通道10和第2行输出通道10为一组，第3行输出通道10和第4行输出通道10为一组，第5行输出通道10和第6行输出通道10为一组，依次类推直至最后一行。
连接时，所述开关薄膜晶体管T1’的栅极电性连接该像素驱动单元对应的一个输出通道组中的一个输出通道10的输出端，源极接入数据信号Data’，漏极电性连接驱动薄膜晶体管T2’的栅极；所述驱动薄膜晶体管T2’的源极接入电源高电位OVDD’，漏极电性连接有机发光二极管D1’的阳极；所述感测薄膜晶体管T3’的栅极电性连接该像素驱动单元对应的一个输出 通道组中不同于开关薄膜晶体管T1’的栅极的另一个输出通道10的输出端，源极电性连接有机发光二极管D1’的阳极，漏极输出感测信号SEN’；所述存储电容C1’的第一端电性连接驱动薄膜晶体管T2’的栅极，第二端电性连接驱动薄膜晶体管T2’的漏极；所述有机发光二极管D1’的阴极接入电源低电位OVSS’。例如，位于第一行像素驱动单元中的开关薄膜晶体管T1’的栅极电性连接第1行输出通道10的输出端，感测薄膜晶体管T3’的栅极电性连接第2行输出通道10的输出端，位于第二行像素驱动单元中的开关薄膜晶体管T1’的栅极电性连接第3行输出通道10的输出端，感测薄膜晶体管T3’的栅极电性连接第4行输出通道10的输出端，依次类推直至最后一行。
请参阅图7，驱动时，所述选择信号SEL为高电位，各个第一多路复用模块20的输出端输出第一电源信号VGHO，各个第二多路复用模块30的输出端输出第二电源信号VGHE，以保证同一个输出通道组中的输出通道10接入相同的电源信号，避免在预充电阶段扫描信号产生削角，保证削角仅产生在充电阶段，防止因削角导致预充电效果降低。
综上所述，本发明提供一种扫描驱动电路，包括：依次排列的多行输出通道、至少一个第一多路复用模块及至少一个第二多路复用模块；每一行输出通道均包括：输入端、电源端及输出端，每一行输出通道的输入端接入该行输出通道对应的输入脉冲信号，输出端输出该行输出通道对应的扫描信号，第4m-3行输出通道的电源端接入第一电源信号，第4m-2行输出通道的电源端接入一第一多路复用模块的输出端，第4m-1行输出通道的电源端接入一第二多路复用模块的输出端，第4m行输出通道的电源端接入第二电源信号；所述第一多路复用模块和第二多路复用模块的控制端均接入选择信号，输入端均接入第一电源信号和第二电源信号，能够通过选择信号控制第一多路复用模块和第二多路复用模块改变其输出的电源信号，从而根据需要改变输出通道接入的电源信号，保证预充电效果的同时还能够适用于多种扫描时序的需求。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (16)

  1. 一种扫描驱动电路，包括输出模块，所述输出模块包括依次排列的多行输出通道、至少一个第一多路复用模块及至少一个第二多路复用模块；
    所述第一多路复用模块与第二多路复用模块的数量相同；
    每一行输出通道均包括：输入端、电源端及输出端，每一行输出通道的输入端接入该行输出通道对应的输入脉冲信号，输出端输出该行输出通道对应的扫描信号，第4m-3行输出通道的电源端接入第一电源信号，第4m-2行输出通道的电源端接入一第一多路复用模块的输出端，第4m-1行输出通道的电源端接入一第二多路复用模块的输出端，第4m行输出通道的电源端接入第二电源信号，m为正整数；
    每一个第一多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号，每一个第二多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号；所述选择信号控制各个第一多路复用模块的输出端输出第一电源信号和第二电源信号中的一个，各个第二多路复用模块输出端输出第一电源信号和第二电源信号中不同于第一多路复用模块输出端输出的另一个。
  2. 如权利要求1所述的扫描驱动电路，还包括：移位寄存器以及分别与所述移位寄存器和输出模块均电性连接的逻辑控制单元；
    所述移位寄存器接收时钟信号及扫描起始信号，用于根据所述时钟信号及扫描起始信号产生多个输入脉冲信号输出至逻辑控制单元；
    所述逻辑控制单元接收使能信号，用于根据使能信号将所述多个输入脉冲信号对应输入到所述输出模块的各个输出通道中。
  3. 如权利要求2所述的扫描驱动电路，其中，所述第一电源信号和第二电源信号均为削角信号。
  4. 如权利要求3所述的扫描驱动电路，其中，所述第一电源信号和第二电源信号产生削角的周期均等于时钟信号的周期的两倍，分别位于所述第一电源信号和第二电源信号上且相邻的两个削角产生的时间相差一个时钟信号的周期，且每一削角的上升沿均对应与时钟信号的一上升沿同时产生。
  5. 如权利要求1所述的扫描驱动电路，其中，所述扫描驱动电路用于电性连接像素阵列，所述像素阵列包括阵列排布的多个像素驱动单元。
  6. 如权利要求5所述的扫描驱动电路，其中，每一个输出通道对应一行像素驱动单元，每一个像素驱动单元均包括：开关薄膜晶体管、驱动薄膜晶体管、存储电容及有机发光二极管；
    所述开关薄膜晶体管的栅极电性连接该像素驱动单元对应的输出通道的输出端，源极接入数据信号，漏极电性连接驱动薄膜晶体管的栅极；所述驱动薄膜晶体管的源极接入电源高电位，漏极电性连接有机发光二极管的阳极；所述存储电容的第一端电性连接驱动薄膜晶体管的栅极，第二端电性连接驱动薄膜晶体管的漏极；所述有机发光二极管的阴极接入电源低电位；
    所述选择信号为低电位，各个第一多路复用模块的输出端输出第二电源信号，各个第二多路复用模块的输出端输出第一电源信号。
  7. 如权利要求5所述的扫描驱动电路，其中，所述多行输出通道自第1行输出通道开始，每两行相邻输出通道为一组，分为多个输出通道组，每一个输出通道组对应一行像素驱动单元；
    每一个像素驱动单元均包括：开关薄膜晶体管、驱动薄膜晶体管、感测薄膜晶体管、存储电容及有机发光二极管；
    所述开关薄膜晶体管的栅极电性连接该像素驱动单元对应的一个输出通道组中的一个输出通道的输出端，源极接入数据信号，漏极电性连接驱动薄膜晶体管的栅极；所述驱动薄膜晶体管的源极接入电源高电位，漏极电性连接有机发光二极管的阳极；所述感测薄膜晶体管的栅极电性连接该像素驱动单元对应的一个输出通道组中不同于开关薄膜晶体管的栅极的另一个输出通道的输出端，源极电性连接有机发光二极管的阳极，漏极输出感测信号；所述存储电容的第一端电性连接驱动薄膜晶体管的栅极，第二端电性连接驱动薄膜晶体管的漏极；所述有机发光二极管的阴极接入电源低电位；
    所述选择信号为高电位，各个第一多路复用模块的输出端输出第一电源信号，各个第二多路复用模块的输出端输出第二电源信号。
  8. 如权利要求1所述的扫描驱动电路，其中，所述第一多路复用模块及第二多路复用模块的数量均为一个。
  9. 如权利要求1所述的扫描驱动电路，其中，所述第一多路复用模块及第二多路复用模块的数量均为多个，每一个第一多路复用模块和每一个第二多路复用模块均对应连接一个输出通道。
  10. 如权利要求1所述的扫描驱动电路，其中，每一行输出通道输出的扫描信号均为所述该行输出通道利用其电源端的信号对该行输出通道的 输入端接入的输入脉冲信号进行电平转移后产生的信号。
  11. 一种扫描驱动电路，包括输出模块，所述输出模块包括依次排列的多行输出通道、至少一个第一多路复用模块及至少一个第二多路复用模块；
    所述第一多路复用模块与第二多路复用模块的数量相同；
    每一行输出通道均包括：输入端、电源端及输出端，每一行输出通道的输入端接入该行输出通道对应的输入脉冲信号，输出端输出该行输出通道对应的扫描信号，第4m-3行输出通道的电源端接入第一电源信号，第4m-2行输出通道的电源端接入一第一多路复用模块的输出端，第4m-1行输出通道的电源端接入一第二多路复用模块的输出端，第4m行输出通道的电源端接入第二电源信号，m为正整数；
    每一个第一多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号，每一个第二多路复用模块的控制端均接入选择信号，第一输入端均接入第一电源信号，第二输入端均接入第二电源信号；所述选择信号控制各个第一多路复用模块的输出端输出第一电源信号和第二电源信号中的一个，各个第二多路复用模块输出端输出第一电源信号和第二电源信号中不同于第一多路复用模块输出端输出的另一个；
    所述扫描驱动电路还包括：移位寄存器以及分别与所述移位寄存器和输出模块均电性连接的逻辑控制单元；
    所述移位寄存器接收时钟信号及扫描起始信号，用于根据所述时钟信号及扫描起始信号产生多个输入脉冲信号输出至逻辑控制单元；
    所述逻辑控制单元接收使能信号，用于根据使能信号将所述多个输入脉冲信号对应输入到所述输出模块的各个输出通道中；
    其中，所述第一电源信号和第二电源信号均为削角信号；
    其中，所述第一电源信号和第二电源信号产生削角的周期均等于时钟信号的周期的两倍，分别位于所述第一电源信号和第二电源信号上且相邻的两个削角产生的时间相差一个时钟信号的周期，且每一削角的上升沿均对应与时钟信号的一上升沿同时产生；
    其中，所述扫描驱动电路用于电性连接像素阵列，所述像素阵列包括阵列排布的多个像素驱动单元。
  12. 如权利要求11所述的扫描驱动电路，其中，每一个输出通道对应一行像素驱动单元，每一个像素驱动单元均包括：开关薄膜晶体管、驱动薄膜晶体管、存储电容及有机发光二极管；
    所述开关薄膜晶体管的栅极电性连接该像素驱动单元对应的输出通道的输出端，源极接入数据信号，漏极电性连接驱动薄膜晶体管的栅极；所述驱动薄膜晶体管的源极接入电源高电位，漏极电性连接有机发光二极管的阳极；所述存储电容的第一端电性连接驱动薄膜晶体管的栅极，第二端电性连接驱动薄膜晶体管的漏极；所述有机发光二极管的阴极接入电源低电位；
    所述选择信号为低电位，各个第一多路复用模块的输出端输出第二电源信号，各个第二多路复用模块的输出端输出第一电源信号。
  13. 如权利要求11所述的扫描驱动电路，其中，所述多行输出通道自第1行输出通道开始，每两行相邻输出通道为一组，分为多个输出通道组，每一个输出通道组对应一行像素驱动单元；
    每一个像素驱动单元均包括：开关薄膜晶体管、驱动薄膜晶体管、感测薄膜晶体管、存储电容及有机发光二极管；
    所述开关薄膜晶体管的栅极电性连接该像素驱动单元对应的一个输出通道组中的一个输出通道的输出端，源极接入数据信号，漏极电性连接驱动薄膜晶体管的栅极；所述驱动薄膜晶体管的源极接入电源高电位，漏极电性连接有机发光二极管的阳极；所述感测薄膜晶体管的栅极电性连接该像素驱动单元对应的一个输出通道组中不同于开关薄膜晶体管的栅极的另一个输出通道的输出端，源极电性连接有机发光二极管的阳极，漏极输出感测信号；所述存储电容的第一端电性连接驱动薄膜晶体管的栅极，第二端电性连接驱动薄膜晶体管的漏极；所述有机发光二极管的阴极接入电源低电位；
    所述选择信号为高电位，各个第一多路复用模块的输出端输出第一电源信号，各个第二多路复用模块的输出端输出第二电源信号。
  14. 如权利要求11所述的扫描驱动电路，其中，所述第一多路复用模块及第二多路复用模块的数量均为一个。
  15. 如权利要求11所述的扫描驱动电路，其中，所述第一多路复用模块及第二多路复用模块的数量均为多个，每一个第一多路复用模块和每一个第二多路复用模块均对应连接一个输出通道。
  16. 如权利要求11所述的扫描驱动电路，其中，每一行输出通道输出的扫描信号均为所述该行输出通道利用其电源端的信号对该行输出通道的输入端接入的输入脉冲信号进行电平转移后产生的信号。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108492784B (zh) 2018-03-29 2019-12-24 深圳市华星光电半导体显示技术有限公司 扫描驱动电路
KR20210116735A (ko) * 2020-03-12 2021-09-28 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130097466A1 (en) * 2003-11-04 2013-04-18 Texas Instruments Incorporated Removable and replaceable tap domain selection circuitry
CN104036747A (zh) * 2014-06-13 2014-09-10 深圳市华星光电技术有限公司 可减少驱动芯片的电子装置
CN105637578A (zh) * 2013-10-17 2016-06-01 精工爱普生株式会社 电光装置、电光装置的驱动方法及电子设备
CN106771958A (zh) * 2015-11-19 2017-05-31 飞思卡尔半导体公司 具有低功率扫描系统的集成电路
CN108492784A (zh) * 2018-03-29 2018-09-04 深圳市华星光电半导体显示技术有限公司 扫描驱动电路

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100583318B1 (ko) * 2003-12-17 2006-05-25 엘지.필립스 엘시디 주식회사 액정표시장치의 게이트 구동장치 및 방법
JP4168339B2 (ja) * 2003-12-26 2008-10-22 カシオ計算機株式会社 表示駆動装置及びその駆動制御方法並びに表示装置
JP4263153B2 (ja) * 2004-01-30 2009-05-13 Ｎｅｃエレクトロニクス株式会社 表示装置、表示装置の駆動回路およびその駆動回路用半導体デバイス
JP4594215B2 (ja) * 2004-11-26 2010-12-08 三星モバイルディスプレイ株式會社 順次走査及び飛び越し走査兼用の駆動回路
KR101274710B1 (ko) * 2008-07-10 2013-06-12 엘지디스플레이 주식회사 유기발광다이오드 표시장치
JP2010049041A (ja) * 2008-08-22 2010-03-04 Sony Corp 画像表示装置及び画像表示装置の駆動方法
WO2011045955A1 (ja) * 2009-10-16 2011-04-21 シャープ株式会社 表示駆動回路、表示装置及び表示駆動方法
KR101285541B1 (ko) * 2010-12-07 2013-07-23 엘지디스플레이 주식회사 입체 영상 표시장치
KR101857808B1 (ko) * 2011-08-29 2018-05-15 엘지디스플레이 주식회사 스캔구동부와 이를 이용한 유기전계발광표시장치
CN103187018B (zh) * 2011-12-29 2015-12-16 上海天马微电子有限公司 主动阵列显示器及其扫描线驱动电路和扫描线驱动方法
KR102080133B1 (ko) * 2013-10-15 2020-04-08 삼성디스플레이 주식회사 주사 구동부 및 그 구동 방법
CN103745685B (zh) * 2013-11-29 2015-11-04 深圳市华星光电技术有限公司 有源矩阵式有机发光二极管面板驱动电路及驱动方法
CN105096791B (zh) * 2014-05-08 2017-10-31 上海和辉光电有限公司 多路复用驱动器以及显示装置
US9659539B2 (en) * 2015-04-16 2017-05-23 Novatek Microelectronics Corp. Gate driver circuit, display apparatus having the same, and gate driving method
CN105825814B (zh) * 2016-06-07 2017-04-05 京东方科技集团股份有限公司 一种栅极驱动电路、其驱动方法、显示面板及显示装置
EP3264406A1 (en) * 2016-06-30 2018-01-03 LG Display Co., Ltd. Organic light emitting display device and driving method of the same
CN106251803B (zh) * 2016-08-17 2020-02-18 深圳市华星光电技术有限公司 用于显示面板的栅极驱动器、显示面板及显示器
CN106504702A (zh) * 2016-10-18 2017-03-15 深圳市华星光电技术有限公司 Amoled像素驱动电路及驱动方法
DE102017129795A1 (de) * 2017-06-30 2019-01-03 Lg Display Co., Ltd. Anzeigevorrichtung und gate-treiberschaltkreis davon, ansteuerungsungsverfahren und virtuelle-realität-vorrichtung
JP6658778B2 (ja) * 2018-02-16 2020-03-04 セイコーエプソン株式会社 電気光学装置及び電子機器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130097466A1 (en) * 2003-11-04 2013-04-18 Texas Instruments Incorporated Removable and replaceable tap domain selection circuitry
CN105637578A (zh) * 2013-10-17 2016-06-01 精工爱普生株式会社 电光装置、电光装置的驱动方法及电子设备
CN104036747A (zh) * 2014-06-13 2014-09-10 深圳市华星光电技术有限公司 可减少驱动芯片的电子装置
CN106771958A (zh) * 2015-11-19 2017-05-31 飞思卡尔半导体公司 具有低功率扫描系统的集成电路
CN108492784A (zh) * 2018-03-29 2018-09-04 深圳市华星光电半导体显示技术有限公司 扫描驱动电路

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