WO2021232322A1 - 电路板及其制作方法 - Google Patents

电路板及其制作方法 Download PDF

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Publication number
WO2021232322A1
WO2021232322A1 PCT/CN2020/091423 CN2020091423W WO2021232322A1 WO 2021232322 A1 WO2021232322 A1 WO 2021232322A1 CN 2020091423 W CN2020091423 W CN 2020091423W WO 2021232322 A1 WO2021232322 A1 WO 2021232322A1
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WO
WIPO (PCT)
Prior art keywords
layer
copper
plated
double
sided
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Application number
PCT/CN2020/091423
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English (en)
French (fr)
Inventor
彭超
何珂
陈志宏
Original Assignee
鹏鼎控股(深圳)股份有限公司
庆鼎精密电子（淮安）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 鹏鼎控股(深圳)股份有限公司, 庆鼎精密电子（淮安）有限公司 filed Critical 鹏鼎控股(深圳)股份有限公司
Priority to US17/780,963 priority Critical patent/US12101891B2/en
Priority to CN202080082747.XA priority patent/CN114762460B/zh
Priority to PCT/CN2020/091423 priority patent/WO2021232322A1/zh
Priority to TW109117746A priority patent/TWI737316B/zh
Publication of WO2021232322A1 publication Critical patent/WO2021232322A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout

Definitions

  • This application relates to the field of circuit board manufacturing, in particular to design a circuit board and a manufacturing method thereof.
  • the signal loss in the printed circuit board can be roughly divided into two parts, one is the conduction loss, which means the loss caused by the copper foil; the other is the dielectric loss, which means the loss caused by the dielectric layer.
  • the signal loss is related to the dielectric constant D k and the dielectric loss factor D f of the dielectric layer material. In order to reduce signal loss, dielectric materials with lower dielectric constant and dielectric loss factor need to be selected.
  • Liquid crystal polymer (LCP) and Teflon are relatively common dielectric materials. Due to the relatively low dielectric constant and dielectric loss factor, they are widely used to make the dielectric layer of printed circuit boards. However, such materials are expensive and limited in resources, which is not conducive to the mass production of circuit boards. Moreover, because such materials still have a certain dielectric constant and dielectric loss factor, as the industry has more and more control requirements for signal transmission loss The higher it is, it is difficult to meet the demand for further reducing signal loss.
  • the present application provides a method for manufacturing a circuit board, including the steps of: providing a first double-sided copper clad laminate.
  • the first double-sided copper clad laminate includes a dielectric layer and first copper formed on two opposite surfaces of the dielectric layer.
  • a foil layer and a copper-plated layer the dielectric layer is provided with a through groove, the first copper foil layer is located on one side of the groove to form the bottom wall of the groove, and the dielectric layer is The position where the groove is provided is also formed with a side wall connected to the bottom wall, and the copper-plated layer includes a first copper-plated portion formed on the bottom wall and the side wall, and the A second copper-plated part other than the copper-plated part;
  • a double-sided circuit substrate includes a base material layer and two first conductive circuit layers formed on two opposite surfaces of the base material layer, each of the first conductive circuit layers includes a signal line, In the area of the substrate layer not covered by the signal line, two conductive paste blocks are provided, and the two conductive paste blocks are located on both sides of the signal line; respectively on both sides of the double-sided circuit substrate Stacking one of the first double-sided copper clad laminates, and placing each of the signal lines in the grooves, thereby obtaining an intermediate body;
  • the intermediate is pressed together so that the conductive paste block is electrically connected to the two second copper-plated parts located on both sides of the substrate layer, wherein the second copper-plated part forms a ground wire, and the first A copper-plated part forms a shielding layer.
  • the shielding layer, the ground wire and the conductive paste block located on both sides of the base layer together form a closed shielding sleeve, and the signal wire is located on the shield Inside the sleeve;
  • the first copper foil layer of each of the first double-sided copper clad laminates is etched to obtain a second conductive circuit layer, thereby obtaining the circuit board.
  • the application also provides a circuit board, including:
  • a double-sided circuit substrate comprising a base material layer and two first conductive circuit layers formed on two opposite surfaces of the base material layer, each of the first conductive circuit layers includes a signal line, the Two conductive paste blocks are provided in the area of the substrate layer not covered by the signal line, and the two conductive paste blocks are located on both sides of the signal line;
  • a copper plating layer, a dielectric layer, and a second conductive circuit layer are sequentially formed on the surface of each of the first conductive circuit layers.
  • the dielectric layer is provided with a through trench, and the second conductive circuit layer constitutes The bottom wall of the trench, the dielectric layer is further formed with a side wall connected to the bottom wall at a position where the trench is provided, and the copper-plated layer includes a first copper-plated portion and a second copper-plated portion Part, the first copper-plated part is formed on the bottom wall and the side wall, and the second copper-plated part is an area of the copper-plated layer excluding the first copper-plated part;
  • the conductive paste block is electrically connected to the two second copper-plated parts of the copper-plated layer located on both sides of the base layer, the second copper-plated part forms a ground wire, and the first copper-plated part forms a shield Layer, the shielding layer, the ground wire and the conductive paste block located on both sides of the base layer jointly enclose a closed shielding sleeve, and the signal wire is located in the shielding sleeve.
  • the copper plating layer formed on the bottom wall and the side wall forms a shielding layer, and the shielding layer located on both sides of the base layer, the ground wire and the conductive paste block A closed shielding sleeve is enclosed together, and the signal line is located in the shielding sleeve. Since there is air in the shielding sleeve, and the dielectric constant of air is 1, in this way, the dielectric loss can be minimized. Moreover, since this application does not rely on the use of expensive dielectric materials in the prior art to minimize dielectric loss, the process is mature and simple, and the cost is low, which is conducive to mass production of circuit boards.
  • FIG. 1 is a schematic cross-sectional view of a single-sided copper clad laminate provided by an embodiment of the application.
  • FIG. 2 is a schematic cross-sectional view of the single-sided copper clad laminate shown in FIG. 1 after a trench is formed in the dielectric layer.
  • FIG. 3 is a schematic cross-sectional view of a double-sided copper clad laminate obtained after a copper plating layer is formed on the dielectric layer described in FIG. 2.
  • FIG. 4 is a schematic cross-sectional view of a double-sided copper clad laminate provided by an embodiment of the application.
  • FIG. 5 is a schematic cross-sectional view of the double-sided copper clad board shown in FIG. 4 after being covered with a patterned photoresist layer.
  • FIG. 6 is a schematic cross-sectional view after etching the second copper foil layer of the double-sided copper clad laminate through the patterned photoresist layer shown in FIG. 5.
  • FIG. 7 is a schematic cross-sectional view of a double-sided circuit board obtained after conductive paste blocks are provided in the base material layer shown in FIG. 6.
  • FIG. 8 is a schematic cross-sectional view of the double-sided copper clad laminate shown in FIG. 3 and the double-sided circuit board shown in FIG. 7 after being laminated and pressed together.
  • FIG. 9 is a schematic cross-sectional view after etching the first copper foil layer shown in FIG. 8 to obtain a second conductive circuit layer.
  • FIG. 10 is a schematic cross-sectional view of a circuit board obtained after covering a protective layer on the second conductive circuit layer shown in FIG. 9.
  • the first copper foil layer 12 is the first copper foil layer 12
  • an embodiment of the present application provides a manufacturing method of a circuit board 100, which includes the following steps:
  • a first double-sided copper clad laminate 10 is provided.
  • the first double-sided copper clad laminate 10 includes a dielectric layer 11 and a first layer formed on two opposite surfaces of the dielectric layer 11.
  • the dielectric layer 11 is provided with a through trench 110
  • the first copper foil layer 12 is located on the side of the trench 110 and forms the bottom wall 111 of the trench 110
  • the dielectric layer 11 A side wall 112 connected to the bottom wall 111 is also formed at the position where the groove 110 is provided.
  • the copper-plated layer 13 includes a first copper-plated portion 131 and a second copper-plated portion 132.
  • the first copper-plated portion 131 is formed on the bottom wall 111 and the side wall 112.
  • the second copper-plated portion 132 is the area of the copper-plated layer 13 excluding the first copper-plated portion 131, that is, the second copper-plated portion 132 is formed on the dielectric layer 11 except for the On the surface outside the trench 110.
  • the cross-sectional width of the trench 110 gradually decreases from the direction of the dielectric layer 11 to the first copper foil layer 12. More specifically, along the extending direction of the groove 110, the cross section of the groove 110 is trapezoidal.
  • the surface of the first copper-plated portion 131 away from the trench 110 is arc-shaped.
  • the surface of the second copper-plated portion 132 is flat.
  • the material of the dielectric layer 11 can be selected from epoxy resin, polypropylene (PP), BT resin, polyphenylene ether (PPO), polyimide (PI), and polyterephthalic acid. At least one of resins such as ethylene glycol ester (PET) and polyethylene naphthalate (PEN). More specifically, the material of the dielectric layer 11 is thermosetting resin.
  • the manufacturing of the first double-sided copper clad laminate 10 includes the following steps:
  • the first step referring to FIG. 1, provides a single-sided copper clad laminate 1, which includes the dielectric layer 11 and the first copper foil layer formed on the surface of the dielectric layer 11 12.
  • the trench 110 is formed in the dielectric layer 11, and the trench 110 penetrates the dielectric layer 11.
  • the groove 110 can be formed by punching, numerical control drilling or laser drilling.
  • the third step referring to FIG. 3, copper is plated on the surface of the dielectric layer 11 away from the first copper foil layer 12, the bottom wall 111 and the side wall 112 to form the copper plating layer 13 , Thereby obtaining the first double-sided copper clad laminate 10.
  • the double-sided circuit substrate 20 includes a base material layer 21 and two first conductive lines formed on opposite surfaces of the base material layer 21 Layer 22.
  • each of the first conductive circuit layer 22 includes a signal line 220.
  • the extending direction of the signal line 220 is consistent with the extending direction of the trench 110.
  • the positions of the signal lines 220 of the two first conductive circuit layers 22 may correspond to each other. That is, the projections of the signal lines 220 of the two first conductive circuit layers 22 on the base material layer 21 overlap with each other.
  • the area of the substrate layer 21 that is not covered by the signal line 220 is provided with two through holes 210, and the two through holes 210 are located on both sides of the signal line 220.
  • Each through hole 210 is provided with a conductive paste block 211.
  • the ends of the conductive paste block 211 can respectively protrude from the surface of the substrate layer 21.
  • the conductive paste block 211 includes, but is not limited to, copper paste or solder paste.
  • the material of the substrate layer 21 can be selected from epoxy resin, polypropylene, BT resin, polyphenylene ether, polyimide, polyethylene terephthalate, and polyethylene naphthalate. At least one of resins such as glycol esters. More specifically, the material of the substrate layer 21 is a thermoplastic resin.
  • the production of the double-sided circuit substrate 20 includes the following steps:
  • a second double-sided copper clad laminate 2 is provided.
  • the second double-sided copper clad laminate 2 includes the base material layer 21 and two opposite surfaces of the base material layer 21.
  • each of the second copper foil layers 23 is covered with a patterned photoresist layer 24.
  • the second copper foil layer 23 is exposed and developed through the patterned photoresist layer 24, so that the second copper foil layer 23 is etched into the first conductive circuit layer twenty two.
  • two through holes 210 are opened in the area of the first base material layer 21 not covered by the signal lines 220, and conductive paste is provided in each through hole 210.
  • Block 211 The two conductive paste blocks 211 are located on both sides of the signal line 220 to obtain the double-sided circuit substrate 20.
  • Step S3 referring to FIG. 8, stacking one of the first double-sided copper clad laminates 10 on both sides of the double-sided circuit substrate 20, and placing each of the signal lines 220 in the grooves 110, thereby An intermediate (not shown) is obtained.
  • Step S4 pressing the intermediate body so that the conductive paste block 211 is electrically connected to the second copper-plated portions 132 of the two copper-plated layers 13 located on both sides of the base layer 21.
  • the distance between the two conductive paste blocks 211 can be based on the opening width of the trench 110 (that is, the trench 110 is on the surface of the dielectric layer 11 away from the first copper foil layer 12).
  • the width of the formed opening is set.
  • the distance between the two conductive paste blocks 211 is approximately equal to the opening width of the trench 110.
  • the distance between the two conductive paste blocks 211 may also be greater than the opening width of the trench 110, as long as the conductive paste blocks 211 can be electrically connected to the grooves 110 during the pressing step.
  • the two second copper-plated portions 132 on both sides of the dielectric layer 11 are sufficient.
  • the second copper-plated portion 132 forms a ground wire
  • the first copper-plated portion 131 forms a shielding layer.
  • the shielding layer, the grounding wire and the conductive paste block 211 located on both sides of the base layer 21 collectively enclose a closed shielding sleeve 30.
  • the signal line 220 is located in the shield sleeve 30. Since the shielding sleeve 30 contains air, and the dielectric constant of the air is 1, in this way, the dielectric loss can be minimized.
  • the structure in which the signal line 220 is located in the shield sleeve 30 can avoid electromagnetic interference between the signal line 220 and other wires (not shown), and at the same time concentrate the signal transmission electromagnetic field in the shield sleeve 30 , Thereby increasing the signal transmission speed.
  • the signal line 220 is located on the central axis of the shielding sleeve 30, so as to further improve the electromagnetic shielding effect and increase the signal transmission speed.
  • the shape of the shielding sleeve 30 resembling an arch can withstand a certain vertical pressure, so that the finally formed circuit board 100 has better impact resistance.
  • the dielectric layer 11 can be made of thermosetting resin (such as epoxy resin, etc.), the impact resistance of the circuit board 100 can be further increased.
  • Step S5 referring to FIG. 9, the first copper foil layer 12 of each of the first double-sided copper clad laminates 10 is etched to obtain the second conductive circuit layer 14.
  • step S6 referring to FIG. 10, a protective layer 40 is covered on each of the second conductive circuit layers 14 to obtain the circuit board 100.
  • the protective layer 40 includes solder resist ink. In another embodiment, the protective layer 40 may also be a resin cover film (CVL).
  • CVL resin cover film
  • an embodiment of the present application also provides a circuit board 100.
  • the circuit board 100 can be manufactured by the above-mentioned manufacturing method.
  • the circuit board 100 includes a double-sided circuit substrate 20.
  • the double-sided circuit substrate 20 includes a base material layer 21 and two first conductive circuit layers 22 formed on two opposite surfaces of the base material layer 21.
  • Each of the first conductive circuit layers 22 includes a signal line 220.
  • the area of the substrate layer 21 that is not covered by the signal line 220 is provided with two through holes 210, and the two through holes 210 are located on both sides of the signal line 220.
  • Each through hole 210 is provided with a conductive paste block 211.
  • a copper plating layer 13, a dielectric layer 11 and a second conductive circuit layer 14 are sequentially formed on the surface of each of the first conductive circuit layers 22.
  • the dielectric layer 11 is provided with a penetrating trench 110
  • the second conductive circuit layer 14 forms the bottom wall 111 of the trench 110
  • the dielectric layer 11 is located at a position where the trench 110 is provided.
  • a side wall 112 connected to the bottom wall 111 is also formed.
  • the copper-plated layer 13 includes a first copper-plated portion 131 and a second copper-plated portion 132.
  • the first copper-plated portion 131 is formed on the bottom wall 111 and the side wall 112.
  • the second copper-plated portion 132 is an area of the copper-plated layer 13 excluding the first copper-plated portion 131.
  • the conductive paste block 211 is electrically connected to the second copper-plated portions 132 of the two copper-plated layers 13 on both sides of the dielectric layer 11. Wherein, the second copper-plated portion 132 forms a ground wire, and the first copper-plated portion 131 forms a shielding layer.
  • the shielding layer, the grounding wire and the conductive paste block 211 located on both sides of the base layer 21 jointly enclose a closed shielding sleeve 30.
  • the signal line 220 is located in the shield sleeve 30.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种电路板的制作方法，包括：提供第一双面覆铜板，包括介电层和形成于所述介电层相对两表面的第一铜箔层和镀铜层，所述介电层中设有沟槽，所述镀铜层包括形成于所述沟槽内的第一镀铜部分和除此之外的第二镀铜部分；提供双面电路基板，包括基材层和形成于所述基材层相对两表面的两个第一导电线路层，每一所述第一导电线路层包括信号线，所述基材层中设有两个导电膏块，两个所述导电膏块位于所述信号线的两侧；分别在所述双面电路基板的两侧层叠一个所述第一双面覆铜板，使每一所述信号线位于所述沟槽中；压合，使得所述导电膏块电连接位于所述基材层两侧的所述第二镀铜部分。本申请还提供一种电路板。

Description

电路板及其制作方法 技术领域
本申请涉及电路板制造领域，尤其设计一种电路板及其制作方法。
背景技术
印刷线路板中的信号损失大致可以分为两个部分，一种是传导损失，其意味着铜箔引起的损失；另一种是介电损失，其意味着介电层引起的损失。通常信号损失与介电层材料的介电常数D k及介电损失因子D f有关。为了减少信号损失，需要选用介电常数和介电损失因子较低的介电材料。
液晶聚合物(LCP)和铁氟龙是较为常见的介电材料，由于介电常数及介电损失因子相对较低，被广泛应用于制作印刷电路板的介电层。然而，此类材料价格较高且资源有限，不利于电路板批量制作；而且，由于该类材料仍具有一定的介电常数及介电损失因子，随着业内对信号传输损耗的控制要求越来越高，难以满足进一步降低信号损失的需求。
发明内容
为解决现有技术中的不足，有必要提供一种电路板及所述电路板的制作方法。
本申请提供一种电路板的制作方法，包括步骤：提供一第一双面覆铜板，所述第一双面覆铜板包括介电层和形成于所述介电层相对两表面的第一铜箔层和镀铜层，所述介电层中开设有贯穿的沟槽，所述第一铜箔层位于所述沟槽一侧以形成所述沟槽的底壁，所述介电层在设有所述沟槽的位置还形成有与所述底壁连接的侧壁，所述 镀铜层包括形成于所述底壁和所述侧壁上的第一镀铜部分和除所述第一镀铜部分之外的第二镀铜部分；
提供一双面电路基板，所述双面电路基板包括基材层和形成于所述基材层相对两表面的两个第一导电线路层，每一所述第一导电线路层包括信号线，所述基材层中未被所述信号线覆盖的区域设有两个导电膏块，两个所述导电膏块位于所述信号线的两侧；分别在所述双面电路基板的两侧层叠一个所述第一双面覆铜板，并使每一所述信号线位于所述沟槽中，从而得到一中间体；
压合所述中间体，使得所述导电膏块电连接位于所述基材层两侧的两个所述第二镀铜部分，其中，所述第二镀铜部分形成接地线，所述第一镀铜部分形成屏蔽层，位于所述基材层两侧的所述屏蔽层、所述接地线和所述导电膏块共同围成一闭合的屏蔽套筒，所述信号线位于所述屏蔽套筒内；及
蚀刻每一所述第一双面覆铜板的所述第一铜箔层以得到第二导电线路层，从而得到所述电路板。
本申请还提供一种电路板，包括：
双面电路基板，所述双面电路基板包括基材层和形成于所述基材层相对两表面的两个第一导电线路层，每一所述第一导电线路层包括信号线，所述基材层中未被所述信号线覆盖的区域设有两个导电膏块，两个所述导电膏块位于所述信号线的两侧；
每一所述第一导电线路层的表面依次形成有镀铜层、介电层和第二导电线路层，所述介电层中开设有贯穿的沟槽，所述第二导电线路层构成所述沟槽的底壁，所述介电层在设有所述沟槽的位置还形成有与所述底壁连接的侧壁，所述镀铜层包括第一镀铜部分和第二镀铜部分，所述第一镀铜部分形成于所述底壁和所述侧壁上，所述第二镀铜部分为所述镀铜层除所述第一镀铜部分之外的区域；
所述导电膏块电连接位于所述基材层两侧的两个所述镀铜层的第二镀铜部分，所述第二镀铜部分形成接地线，所述第一镀铜部分 形成屏蔽层，位于所述基材层两侧的所述屏蔽层、所述接地线和所述导电膏块共同围成一闭合的屏蔽套筒，所述信号线位于所述屏蔽套筒内。
在本申请中，形成于所述底壁和所述侧壁上的所述镀铜层形成一屏蔽层，位于所述基材层两侧的屏蔽层、所述接地线和所述导电膏块共同围成闭合的屏蔽套筒，所述信号线位于所述屏蔽套筒内。由于所述屏蔽套筒内具有空气，而空气的介电常数为1，如此，可以使介质损耗最小化。而且，由于本申请并不依赖使用现有技术中价格高昂的介质材料来实现介质损耗最小化，工艺成熟且简单，成本较低，利于电路板批量制作。
附图说明
图1为本申请一实施方式提供的单面覆铜板的剖面示意图。
图2为图1所示的单面覆铜板的介电层中开设沟槽后剖面示意图。
图3为在图2所述的介电层上形成镀铜层后得到的双面覆铜板的剖面示意图。
图4为本申请一实施方式提供的双面覆铜板的剖面示意图。
图5为在图4所示的双面覆铜板上覆盖图形化光阻层后的剖面示意图。
图6为通过图5所示的图形化光阻层蚀刻双面覆铜板的第二铜箔层后的剖面示意图。
图7为在图6所示的基材层中设置导电膏块后得到的双面电路基板的剖面示意图。
图8为层叠并压合图3所示的双面覆铜板和图7所示的双面电路基板后的剖面示意图。
图9为蚀刻图8所示的第一铜箔层得到第二导电线路层后的剖面示意图。
图10为在图9所示的第二导电线路层上覆盖保护层后得到的电路板的剖面示意图。
主要元件符号说明
单面覆铜板                  1
第二双面覆铜板              2
第一双面覆铜板              10
介电层                      11
第一铜箔层                  12
镀铜层                      13
第二导电线路层              14
双面电路基板                20
基材层                      21
第一导电线路层              22
第二铜箔层                  23
图形化光阻层                24
屏蔽套筒                    30
保护层                      40
电路板                      100
沟槽                        110
底壁                        111
侧壁                        112
第一镀铜部分                131
第二镀铜部分                132
通孔                        210
导电膏块                    211
信号线                      220
如下具体实施方式将结合上述附图进一步说明本申请。
具体实施方式
请参阅图1至图10，本申请一实施方式提供一种电路板100的制作方法，包括以下步骤：
步骤S1，请参阅图1至图3，提供一第一双面覆铜板10，所述第一双面覆铜板10包括介电层11和形成于所述介电层11相对两表面的第一铜箔层12和镀铜层13。
其中，所述介电层11中开设有贯穿的沟槽110，所述第一铜箔层12位于所述沟槽110一侧并构成所述沟槽110的底壁111，所述介电层11在设有所述沟槽110的位置还形成有与所述底壁111连接的侧壁112。所述镀铜层13包括第一镀铜部分131和第二镀铜部分132。所述第一镀铜部分131形成于所述底壁111和所述侧壁112上。所述第二镀铜部分132为所述镀铜层13除所述第一镀铜部分131之外的区域，即，所述第二镀铜部分132形成于所述介电层11除所述沟槽110之外的表面上。
本实施方式中，所述沟槽110的截面宽度自所述介电层11至所述第一铜箔层12的方向逐渐减小。更具体地，沿所述沟槽110的延伸方向，所述沟槽110的截面呈梯形。
进一步地，所述第一镀铜部分131远离所述沟槽110的表面为弧形。所述第二镀铜部分132的表面为平面。
在本实施方式中，所述介电层11的材质可选自环氧树脂、聚丙烯(PP)、BT树脂、聚苯醚(PPO)、聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)以及聚萘二甲酸乙二醇酯(PEN)等树脂中的至少一种。更具体地，所述介电层11的材质为热固型树脂。
在本实施方式中，所述第一双面覆铜板10的制作包括如下步骤：
第一步，请参阅图1，提供一单面覆铜板1，所述单面覆铜板1包括所述介电层11和形成于所述介电层11的表面的所述第一铜箔层12。
第二步，请参阅图2，在所述介电层11中开设所述沟槽110，所述沟槽110贯穿所述介电层11。其中，所述沟槽110可通过冲型、数控钻孔或激光打孔的方式形成。
第三步，请参阅图3，在所述介电层11远离所述第一铜箔层12的表面、所述底壁111和所述侧壁112上镀铜以形成所述镀铜层13，从而得到所述第一双面覆铜板10。
步骤S2，请参阅图4至图7，提供一双面电路基板20，所述双面电路基板20包括基材层21和形成于所述基材层21相对两表面的两个第一导电线路层22。
其中，每一所述第一导电线路层22包括信号线220。所述信号线220的延伸方向与所述沟槽110的延伸方向一致。
进一步地，两个所述第一导电线路层22的所述信号线220位置可以相对应。即，两个所述第一导电线路层22的所述信号线220在所述基材层21上的投影相互重合。
所述基材层21未被所述信号线220覆盖的区域开设有两个通孔210，两个所述通孔210位于所述信号线220的两侧。每一所述通孔210中设有导电膏块211。所述导电膏块211的端部可分别伸出所述基材层21的表面。在本实施方式中，所述导电膏块211包括，但并不限于，铜膏或锡膏。
在本实施方式中，所述基材层21的材质可选自环氧树脂、聚丙烯、BT树脂、聚苯醚、聚酰亚胺、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等树脂中的至少一种。更具体地，所述基材层21的材质为热塑型树脂。
在本实施方式中，所述双面电路基板20的制作包括如下步骤：
第一步，请参阅图4，提供一第二双面覆铜板2，所述第二双面覆铜板2包括所述基材层21和形成于所述基材层21相对两表面上的两个第二铜箔层23。
第二步，请参阅图5，在每一所述第二铜箔层23上覆盖图形化光 阻层24。
第三步，请参阅图6，通过所述图形化光阻层24对所述第二铜箔层23进行曝光显影，从而将所述第二铜箔层23蚀刻为所述第一导电线路层22。
第四步，请参阅图7，在所述第一所述基材层21未被所述信号线220覆盖的区域开设有两个通孔210并在每一所述通孔210中设置导电膏块211。两个所述导电膏块211位于所述信号线220的两侧，从而得到所述双面电路基板20。
步骤S3，请参阅图8，分别在所述双面电路基板20的两侧层叠一个所述第一双面覆铜板10，并使每一所述信号线220位于所述沟槽110中，从而得到一中间体(图未示)。
步骤S4，压合所述中间体，使得所述导电膏块211电连接位于所述基材层21两侧的两个所述镀铜层13的第二镀铜部分132。
其中，两个所述导电膏块211之间的距离可根据所述沟槽110的开口宽度(即所述沟槽110在所述介电层11远离所述第一铜箔层12的表面上形成的开口的宽度)进行设定。在本实施方式中，两个所述导电膏块211之间的距离大致等于所述沟槽110的开口宽度。在另一实施方式中，两个所述导电膏块211之间的距离也可以大于所述沟槽110的开口宽度，只要能在压合步骤中使得所述导电膏块211能够电连接位于所述介电层11两侧的两个第二镀铜部分132便可。
其中，所述第二镀铜部分132形成接地线，所述第一镀铜部分131形成屏蔽层。位于所述基材层21两侧的所述屏蔽层、所述接地线和所述导电膏块211共同围成一闭合的屏蔽套筒30。所述信号线220位于所述屏蔽套筒30内。由于所述屏蔽套筒30内具有空气，而空气的介电常数为1，如此，可以使介质损耗最小化。
其次，所述信号线220位于所述屏蔽套筒30内的结构能够避免所述信号线220与其它导线(图未示)之间的电磁干扰，同时将信号传输电磁场集中在屏蔽套筒30内，从而提高信号传输速度。在本实施 方式中，所述信号线220位于所述屏蔽套筒30的中心轴上，从而进一步提升电磁屏蔽效果及提高信号传输速度。
再次，所述屏蔽套筒30类似拱门的形状可以承受一定的垂直压力，使得最后形成的电路板100具有较好的抗冲击能力。当所述介电层11可以采用热固型树脂(如环氧树脂等)制成时能够进一步增加电路板100的抗冲击能力。
步骤S5，请参阅图9，蚀刻每一所述第一双面覆铜板10的所述第一铜箔层12以得到第二导电线路层14。
步骤S6，请参阅图10，在每一所述第二导电线路层14上覆盖保护层40，从而得到所述电路板100。
在本实施方式中，所述保护层40包括防焊油墨。在另一实施方式中，所述保护层40还可以是树脂覆盖膜(CVL)。
请参阅图10，本申请实施方式还提供一种电路板100。所述电路板100可通过上述制作方法制得。
所述电路板100包括双面电路基板20。所述双面电路基板20包括基材层21和形成于所述基材层21相对两表面的两个第一导电线路层22。每一所述第一导电线路层22包括信号线220。所述基材层21未被所述信号线220覆盖的区域开设有两个通孔210，两个所述通孔210位于所述信号线220的两侧。每一所述通孔210中设有导电膏块211。
每一所述第一导电线路层22的表面依次形成有镀铜层13、介电层11和第二导电线路层14。所述介电层11中开设有贯穿的沟槽110，所述第二导电线路层14构成所述沟槽110的底壁111，所述介电层11在设有所述沟槽110的位置还形成有与所述底壁111连接的侧壁112。所述镀铜层13包括第一镀铜部分131和第二镀铜部分132。所述第一镀铜部分131形成于所述底壁111和所述侧壁112上。所述第二镀铜部分132为所述镀铜层13除所述第一镀铜部分131之外的区域。
所述导电膏块211电连接位于所述介电层11两侧的两个所述镀铜层13的第二镀铜部分132。其中，所述第二镀铜部分132形成接地线，所述第一镀铜部分131形成屏蔽层。位于所述基材层21两侧的所述屏蔽层、所述接地线和所述导电膏块211共同围成闭合的屏蔽套筒30。所述信号线220位于所述屏蔽套筒30内。
可以理解的是，对于本领域的普通技术人员来说，可以根据本申请的技术构思做出其它各种相应的改变与变形，而所有这些改变与变形都应属于本申请权利要求的保护范围。

Claims (13)

  1. 一种电路板的制作方法，其特征在于，包括步骤：
    提供一第一双面覆铜板，所述第一双面覆铜板包括介电层和形成于所述介电层相对两表面的第一铜箔层和镀铜层，所述介电层中开设有贯穿的沟槽，所述第一铜箔层位于所述沟槽一侧以形成所述沟槽的底壁，所述介电层在设有所述沟槽的位置还形成有与所述底壁连接的侧壁，所述镀铜层包括形成于所述底壁和所述侧壁上的第一镀铜部分和除所述第一镀铜部分之外的第二镀铜部分；
    提供一双面电路基板，所述双面电路基板包括基材层和形成于所述基材层相对两表面的两个第一导电线路层，每一所述第一导电线路层包括信号线，所述基材层中未被所述信号线覆盖的区域设有两个导电膏块，两个所述导电膏块位于所述信号线的两侧；
    分别在所述双面电路基板的两侧层叠一个所述第一双面覆铜板，并使每一所述信号线位于所述沟槽中，从而得到一中间体；
    压合所述中间体，使得所述导电膏块电连接位于所述基材层两侧的两个所述第二镀铜部分，其中，所述第二镀铜部分形成接地线，所述第一镀铜部分形成屏蔽层，位于所述基材层两侧的所述屏蔽层、所述接地线和所述导电膏块共同围成一闭合的屏蔽套筒，所述信号线位于所述屏蔽套筒内；及
    蚀刻每一所述第一双面覆铜板的所述第一铜箔层以得到第二导电线路层，从而得到所述电路板。
  2. 如权利要求1所述的电路板的制作方法，其特征在于，所述沟槽的截面宽度自所述介电层至所述第一铜箔层的方向逐渐减小。
  3. 如权利要求2所述的电路板的制作方法，其特征在于，所述第一镀铜部分远离所述沟槽的表面为弧形。
  4. 如权利要求1所述的电路板的制作方法，其特征在于，所述介电层的材质为热固型树脂。
  5. 如权利要求1所述的电路板的制作方法，其特征在于，两个 所述第一导电线路层的所述信号线在所述基材层上的投影相互重合，所述信号线位于所述屏蔽套筒的中心轴上。
  6. 如权利要求1所述的电路板的制作方法，其特征在于，所述第一双面覆铜板的制作包括步骤：
    提供一单面覆铜板，所述单面覆铜板包括所述介电层和形成于所述介电层的表面的所述第一铜箔层；
    在所述介电层中开设所述沟槽；及
    在所述介电层远离所述第一铜箔层的表面、所述底壁和所述侧壁上镀铜以形成所述镀铜层，从而得到所述第一双面覆铜板。
  7. 如权利要求1所述的电路板的制作方法，其特征在于，所述双面电路基板的制作包括步骤：
    提供一第二双面覆铜板，所述第二双面覆铜板包括所述基材层和形成于所述基材层相对两表面上的两个第二铜箔层；
    在每一所述第二铜箔层上覆盖图形化光阻层；
    通过所述图形化光阻层对所述第二铜箔层进行曝光显影，从而将所述第二铜箔层蚀刻为所述第一导电线路层，从而得到所述双面电路基板。
  8. 如权利要求1所述的电路板的制作方法，其特征在于，蚀刻所述第一铜箔层后，所述制作方法还包括步骤：
    在每一所述第二导电线路层上覆盖保护层。
  9. 一种电路板，其特征在于，包括：
    双面电路基板，所述双面电路基板包括基材层和形成于所述基材层相对两表面的两个第一导电线路层，每一所述第一导电线路层包括信号线，所述基材层中未被所述信号线覆盖的区域设有两个导电膏块，两个所述导电膏块位于所述信号线的两侧；
    每一所述第一导电线路层的表面依次形成有镀铜层、介电层和第二导电线路层，所述介电层中开设有贯穿的沟槽，所述第二导电线路层构成所述沟槽的底壁，所述介电层在设有所述沟槽的位置还 形成有与所述底壁连接的侧壁，所述镀铜层包括第一镀铜部分和第二镀铜部分，所述第一镀铜部分形成于所述底壁和所述侧壁上，所述第二镀铜部分为所述镀铜层除所述第一镀铜部分之外的区域；
    所述导电膏块电连接位于所述基材层两侧的两个所述镀铜层的第二镀铜部分，所述第二镀铜部分形成接地线，所述第一镀铜部分形成屏蔽层，位于所述基材层两侧的所述屏蔽层、所述接地线和所述导电膏块共同围成一闭合的屏蔽套筒，所述信号线位于所述屏蔽套筒内。
  10. 如权利要求9所述的电路板，其特征在于，所述沟槽的截面宽度自所述介电层至所述第二导电线路层的方向逐渐减小。
  11. 如权利要求10所述的电路板，其特征在于，所述第一镀铜部分远离所述沟槽的表面为弧形。
  12. 如权利要求9所述的电路板，其特征在于，所述介电层的材质为热固型树脂。
  13. 如权利要求9所述的电路板，其特征在于，两个所述第一导电线路层的所述信号线在所述基材层上的投影相互重合，所述信号线位于所述屏蔽套筒的中心轴上。
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