WO2021227105A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2021227105A1
WO2021227105A1 PCT/CN2020/091249 CN2020091249W WO2021227105A1 WO 2021227105 A1 WO2021227105 A1 WO 2021227105A1 CN 2020091249 W CN2020091249 W CN 2020091249W WO 2021227105 A1 WO2021227105 A1 WO 2021227105A1
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Prior art keywords
channel
sub
tft
drain
source
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PCT/CN2020/091249
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English (en)
French (fr)
Inventor
江志雄
孙圣
严允晟
孙宇成
陈梦
柳吴广
李举彬
谭志威
全海燕
曲凯莉
梁楚尉
刘子琪
柳林涛
李婷
郝思坤
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Tcl华星光电技术有限公司
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Priority to US17/051,457 priority Critical patent/US11841597B2/en
Publication of WO2021227105A1 publication Critical patent/WO2021227105A1/zh

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1335Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509Filters, e.g. light shielding masks
    • G02F1/133514Colour filters
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the voltage-dividing TFT controls the brightness of the sub-pixel, and the brightness of the sub-pixel is controlled by the voltage-dividing ratio of the voltage-dividing TFT and the sub-TFT.
  • the ratio of the width of the sub-channel in the sub-TFT is controlled.
  • the gate metal layer, the insulating layer, and the source-drain metal layer are sequentially formed, and use the exposure process to pattern the source-drain metal layer, and then according to the pattern
  • the source and drain metal layers are etched to form the sub-channel in the sub-TFT and the voltage-dividing channel in the voltage-dividing TFT.
  • a Nikon machine combined with a polygon mirror 100 is commonly used for exposure. As shown in FIG.
  • the present application provides an array substrate and a display panel to solve the problem that the ratio of the width of the sub-channel in the existing sub-TFT to the width of the voltage-dividing channel in the voltage-dividing TFT is easily affected by the change of the channel width, which affects the brightness of the sub-pixel. Larger causes the technical problem of uneven display of the display panel.
  • the present application provides an array substrate, including a base substrate, and a plurality of pixel units distributed on the base substrate in an array, and any one of the pixel units at least includes a primary pixel electrode, a sub-pixel electrode, and the A first TFT electrically connected to the sub-pixel electrode, a second TFT electrically connected to the first TFT, and a third TFT electrically connected to the main pixel electrode;
  • the first TFT includes a first source, a first drain, a first channel at least partially located between the first source and the first drain, and a first channel disposed at the first channel
  • the first semiconductor layer includes a second source, a second drain, a second channel located between the second source and the second drain, and the first The second semiconductor layer at the second channel.
  • the first channel includes at least two sub-channels
  • the first semiconductor layer includes at least two semiconductor sub-layers
  • each of the sub-channels is provided with one semiconductor sub-layer.
  • the first channel includes at least a first sub-channel and a second sub-channel
  • the first semiconductor layer includes at least a first semiconductor sub-layer located in the first sub-channel And a second semiconductor sub-layer located in the second sub-channel; the first sub-channel and/or the second sub-channel are located between the first source and the first drain.
  • the first TFT and the second TFT are connected to the second source through the first source;
  • the second TFT is disposed close to the first TFT, the first sub-channel is disposed between the first TFT and the second TFT, and at least the second sub-channel in the first channel is The channel is arranged between the first source and the first drain.
  • the first sub-channel and the second sub-channel are both arranged in an I-shape between the first source electrode and the first drain electrode.
  • the first sub-channel and the second sub-channel are arranged parallel to each other, and the first channel is U-shaped and arranged on the first source and the first drain. Between the poles, the first sub-channel and the second sub-channel are respectively arranged at two parallel sides of the U-shaped first channel.
  • the first channel is arranged in an L-shape between the first source and the first drain, and the first sub-channel and the second sub-channel are They are respectively arranged at both sides of the first channel in an L-shape.
  • the first sub-channel is in communication with the second sub-channel, and the first semiconductor sub-layer and the second semiconductor sub-layer are connected as a whole.
  • the first sub-channel and the second sub-channel are arranged at intervals, and the first semiconductor sub-layer and the second semiconductor sub-layer are arranged at intervals in the first Between the source and the first drain.
  • the first sub-channel and the second sub-channel are both U-shaped and arranged between the first source electrode and the first drain electrode.
  • the present application also provides a display panel including a color filter substrate and the array substrate as described in any one of the previous embodiments, and a liquid crystal layer is arranged between the color filter substrate and the array substrate.
  • the first channel includes at least a first sub-channel and a second sub-channel
  • the first semiconductor layer includes at least a first semiconductor sub-layer located in the first sub-channel And a second semiconductor sub-layer located in the second sub-channel; the first sub-channel and/or the second sub-channel are located between the first source and the first drain.
  • the first TFT and the second TFT are connected to the second source through the first source;
  • the second TFT is disposed close to the first TFT, the first sub-channel is disposed between the first TFT and the second TFT, and at least the second sub-channel in the first channel is The channel is arranged between the first source and the first drain.
  • the first sub-channel and the second sub-channel are both arranged in an I-shape between the first source electrode and the first drain electrode.
  • the first sub-channel and the second sub-channel are arranged parallel to each other, and the first channel is U-shaped and arranged on the first source and the first drain. Between the poles, the first sub-channel and the second sub-channel are respectively arranged at two parallel sides of the U-shaped first channel.
  • the first channel is arranged in an L shape between the first source and the first drain, and the first sub-channel and the second sub-channel are They are respectively arranged at both sides of the first channel in an L-shape.
  • the first sub-channel is in communication with the second sub-channel, and the first semiconductor sub-layer and the second semiconductor sub-layer are connected as a whole.
  • the first sub-channel and the second sub-channel are arranged at intervals, and the first semiconductor sub-layer and the second semiconductor sub-layer are arranged at intervals in the first Between the source and the first drain.
  • the first sub-channel and the second sub-channel are both U-shaped and arranged between the first source electrode and the first drain electrode.
  • the beneficial effect of the present application is that the first channel is divided into at least two sub-channels in the present application, and a semiconductor sub-layer is arranged in each of the sub-channels, so that the sub-channels in the first TFT are The number is greater than the number of the second channel in the second TFT, thereby increasing the amount of change in the channel width in the first TFT.
  • the variation of the actual channel ratio between the second TFT and the first TFT caused by the influence of the exposure amount reduces the influence of the exposure amount change at the prism junction on the partial pressure ratio of the second TFT and the first TFT, thereby reducing the prism
  • the amount of change in the brightness of the sub-pixels corresponding to the connection part improves the problem of uneven display of the display panel.
  • FIG. 1 is a schematic diagram of the structure of a polygonal prism assembly in an existing exposure process
  • FIG. 2 is a schematic diagram of the first structure of an array substrate in an embodiment of the application.
  • FIG. 3 is a schematic diagram of a second structure of the array substrate in an embodiment of the application.
  • FIG. 4 is a schematic diagram of a third structure of the array substrate in an embodiment of the application.
  • FIG. 5 is a schematic diagram of a fourth structure of the array substrate in an embodiment of the application.
  • FIG. 6 is a schematic diagram of a fifth structure of the array substrate in an embodiment of the application.
  • FIG. 7 is a schematic diagram of a sixth structure of the array substrate in an embodiment of the application.
  • FIG. 8 is a schematic diagram of the structure of a display panel in an embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the present application provides an array substrate 10, as shown in FIGS. 2 to 7, including a base substrate 11 and a plurality of pixel units distributed on the base substrate 11 in an array, any of the pixel units at least It includes a main pixel electrode 12, a sub-pixel electrode 13, a first TFT 14 electrically connected to the sub-pixel electrode 13, a second TFT 15 electrically connected to the first TFT 14, and a second TFT electrically connected to the main pixel electrode 12.
  • the first TFT 14 includes a first source 141, a first drain 142, a first channel 143 at least partially located between the first source 141 and the first drain 142, and a The first semiconductor layer 144 at the first channel 143;
  • the second TFT 15 includes a second source 151, a second drain 152, and a semiconductor layer located between the second source 151 and the second drain 152
  • the second channel 153 and the second semiconductor layer 154 disposed at the second channel 153.
  • the first channel 143 includes at least two sub-channels
  • the first semiconductor layer 144 includes at least two semiconductor sub-layers
  • each of the sub-channels includes one semiconductor sub-layer.
  • the light is in The prism connecting portion 101 will have large diffraction, which causes the pattern opening on the insulating layer corresponding to the prism connecting portion 101 to increase in size, so that when the source and drain metal layer is etched, the channel The metal parts at the openings at both ends are etched too much, causing the etched channel width W to become shorter; and because in the existing structure, the sub-channel width of the sub-TFT is generally the same as the voltage-divided channel width of the voltage-dividing TFT.
  • the large difference results in a large amount of change in the voltage division ratio between the divided TFT and the sub-TFT, which affects the brightness change of the sub-pixel at the prism connection part 101.
  • the insulation at the corresponding part of the prism body 102 The size of the pattern opening on the layer has not changed, and the brightness of the sub-pixel corresponding to the prism body 102 and the sub-pixel image corresponding to the prism connecting portion 101 are different, which causes the uneven display of the display panel;
  • the amount by which the channel width becomes shorter is related to the number of openings that the channel has.
  • the channel in a general TFT structure is generally open at both ends.
  • both ends of the channel are shortened by ⁇ w, As a result, the channel width W is shortened by 2 ⁇ w as a whole; in this application, the first channel 143 is divided into at least two sub-channels, and a semiconductor sub-layer is provided in each of the sub-channels, so that the first TFT 14
  • the number of neutron channels is greater than the number of second channels 153 in the second TFT 15, and the plurality of sub-channels are provided with a plurality of openings, thereby increasing the amount of change in the channel width in the first TFT 14.
  • the existing TFT structure Compared with the existing TFT structure, it reduces the amount of variation in the actual channel ratio between the second TFT 15 and the first TFT 14 caused by the exposure amount at the prism connection part 101, and reduces the exposure due to the prism connection part 101.
  • the amount change affects the voltage division ratio of the second TFT 15 and the first TFT 14, thereby reducing the luminance change of the sub-pixel corresponding to the prism connecting portion 101, and improving the problem of uneven display of the display panel.
  • the aforementioned light will have greater diffraction at the prism connecting portion 101, causing the size of the pattern opening on the insulating layer corresponding to the prism connecting portion 101 to become larger, so that the source and drain metal
  • the metal parts at the openings at both ends of the channel are etched too much, which not only causes the channel width W to be etched to become shorter; it also causes the channel length L to become longer.
  • the length L of the channel is the distance between the source and drain.
  • the channel length of each TFT is less different. Under the condition of increasing the channel length at the same time, the difference between the voltage divider TFT and the sub-TFT The partial pressure has a small effect, so it is not considered here.
  • the number of the pixel units corresponding to the prism connecting portion 101 can be up to two hundred, and the range of influence is relatively wide, which is manifested as uneven display in the display panel.
  • the channel width W stated in this application is based on the width of the semiconductor actually filled in the channel.
  • the first TFT 14, the second TFT 15 and the third TFT 16 can be in various forms such as a top gate structure, a bottom gate structure, etc.
  • the first TFT 14, the second TFT 15 and the The third TFT 16 has a bottom gate structure, and the first TFT 14, the second TFT 15 and the third TFT 16 share a gate metal layer 17, and the first TFT 14 is connected to the sub-pixel electrode 13.
  • the second TFT 15 is connected to the first TFT 14, the first TFT 14 and the second TFT 15 are used to control the brightness of the sub-pixels, the third TFT 16 is connected to the main pixel electrode 12, and the third TFT 16 is used to The brightness of the main pixel is controlled; wherein, the second semiconductor layer 154 is covered with the second channel 153; the semiconductor sublayer is covered with the sub channel.
  • the first source 141 and the first drain 142 in the first TFT 14 can be interchanged, and the second source 151 and the second drain 152 in the second TFT 15 can also be interchanged.
  • the third source and the third drain included in the third TFT 16 can be interchanged, which will not be repeated here.
  • the first channel 143 includes at least a first sub-channel 1431 and a second sub-channel 1432
  • the first semiconductor layer 144 at least includes a first sub-channel 1431 located in the first sub-channel 1431.
  • a semiconductor sub-layer 1441 and a second semiconductor sub-layer 1442 located in the second sub-channel 1432; the first sub-channel 1431 and/or the second sub-channel 1432 are located in the first source 141 and It is understood that the first sub-channel 1431 and the second sub-channel 1432 can be located between the first source 141 and the first drain 142 at the same time. One of them can also be located between the first source 141 and the first drain 142.
  • either two sources or two drains in any two TFTs can be used One-piece structure, so as to realize that a part of the first channel 143 is located between the first source 141 and the first drain 142, that is, the first sub-channel 1431 or the second sub-channel 1432 is located where the The structure between the first source 141 and the first drain 142 is described.
  • the first TFT 14 and the second TFT 15 are connected to the second source 151 through the first source 141; or through the first drain 142 Connected to the second drain 152; the second TFT 15 is disposed close to the first TFT 14, the first sub-channel 1431 is disposed between the first TFT 14 and the second TFT 15, so At least the second sub-channel 1432 of the first channel 143 is disposed between the first source 141 and the first drain 142; in this embodiment, the first TFT 14 includes the The first sub-channel 1431 and the second sub-channel 1432 have four openings, and the variation of the overall width of the first channel 143 during the manufacturing process is 4 ⁇ w.
  • the first TFT 14 and the second TFT 15 may adopt a structure that is connected to the second drain 152 through the first drain 142; the second drain in the second TFT 15
  • the electrode 152 is arranged close to the first source 141 of the first TFT 14, and the first sub-channel 1431 is located between the second drain 152 and the first source 141.
  • the first TFT 14 and the second TFT 15 adopt a structure in which the first drain 142 and the second drain 152 are connected, which is actually similar to the common drain of the first TFT 14 and the second TFT 15 Structure, therefore, at this time, the first sub-channel 1431 is not located between the first source 141 and the first drain 142; in addition, at least the second sub-channel 143 in the first channel 143
  • the channel 1432 is arranged between the first source 141 and the first drain 142; of course, the first channel 143 may also include a third sub-channel 1433, etc., which can be simultaneously connected to the second
  • the sub-channel 1432 is arranged between the first source 141 and the first drain 142.
  • the first channel 143 is all arranged between the first source 141 and the first drain
  • the embodiment schemes between the first drain electrodes 142 are described, and will not be repeated here.
  • the first sub-channel 1431 and the second sub-channel 1432 are both I-shaped and disposed on the first source 141 and the first sub-channel 1432.
  • the first channel 143 is all provided between the first source 141 and the first drain 142; it can be understood that the first sub-channel The channel 1431 and the second sub-channel 1432 are both arranged in an I-shape between the first source 141 and the first drain 142.
  • the first sub-channel 1431 and the second sub-channel 1431 Each of the two sub-channels 1432 has two openings, and the variation of the overall width of the first channel 143 is 4 ⁇ w.
  • the first sub-channel 1431 and the second sub-channel 1432 are arranged parallel to each other, and the first channel 143 is U-shaped and arranged between the first source electrode 141 and the second sub-channel 1432. Between the first drain electrodes 142, the first sub-channel 1431 and the second sub-channel 1432 are respectively disposed at two parallel sides of the U-shaped first channel 143; specifically , The first drain 142 is disposed in the concave first source 141, so that the first channel 143 has a U-shaped structure, the first sub-channel 1431 and the second sub-channel 1431 1432 are respectively arranged at two parallel sides in the U-shaped first trench 143, that is, the first semiconductor sublayer 1441 and the second semiconductor sublayer 1442 are respectively filled in the U-shaped all At the two parallel sides of the first channel 143, there is no semiconductor filled in the connecting section of the U-shaped first channel 143 that is bent. It is worth noting that the first sub-channel 1431 and The width of the second sub
  • the first channel 143 is formed in an L shape between the first source electrode 141 and the first drain electrode 142, and the first sub-channel
  • the channel 1431 and the second sub-channel 1432 are respectively arranged at both sides of the L-shaped first channel 143; obviously, at this time, the first sub-channel 1431 and the second sub-channel 1431
  • the channel 1432 is in a non-parallel state with a certain angle. Specifically, the angle between the first sub-channel 1431 and the second sub-channel 1432 and the two sides of the L-shaped first channel 143 The angle is the same. Specifically, as shown in FIG.
  • the first sub-channel 1431 and the second sub-channel 1432 may be connected, and the first semiconductor sub-layer 1441 and the second semiconductor sub-layer 1442 are connected as a whole,
  • the first sub-channel 1431 and the second sub-channel 1432 may also be spaced apart, and the first semiconductor sub-layer 1441 and the second semiconductor sub-layer 1442 are spaced apart. It is arranged between the first source 141 and the first drain 142.
  • the first sub-channel 1431 and the second sub-channel 1432 are both U-shaped and disposed on the first source 141 and the first drain 142. It is understandable that the first channel 143 is now arranged in a double U-shaped structure between the first source 141 and the first drain 142, and the first sub Both the channel 1431 and the second sub-channel 1432 have two openings, and the variation of the overall width of the first channel 143 is 4 ⁇ w.
  • the first channel 143 may further include a third sub-channel 1433, so The third sub-channel 1433 and the second sub-channel 1432 are disposed between the first source 141 and the first drain 142.
  • the third sub-channel 1433 and the The second sub-channel 1432 is an I-shaped structure
  • the third sub-channel 1433 and the second sub-channel 1432 are arranged parallel to each other
  • the first channel 143 is U-shaped and arranged in the first source.
  • the third sub-channel 1433 and the second sub-channel 1432 are respectively disposed at two parallel sides of the U-shaped first channel 143 At this time, the first sub-channel 1431, the second sub-channel 1432, and the third sub-channel 1433 all have two openings, and the variation in the overall width of the first channel 143 is 6 ⁇ w.
  • Table 1 it is the variation of the voltage division ratio between the first TFT 14 and the second TFT 15 in the different array substrates 10 in Figs.
  • Table 1 it is the variation of the voltage division ratio between the first TFT 14 and the second TFT 15 in the different array substrates 10 in Figs.
  • the difference in the exposure amount between the overlapping connecting portion of each polygonal prism 100 and the polygonal prism body 102 there is a certain difference in the exposure amount between the prism connecting portion 101 and the prism body 102.
  • the light is in the prism connecting portion 101.
  • the ratio of the first TFT 14 The design value of W1 is 26.6um, and the design value of W2 of the second TFT15 is 6um as an example, the voltage division ratio of the second TFT15 and the first TFT14 is 22.6%, and the second TFT15 and the The amount of change in the voltage division ratio of the first TFT 14 with respect to the designed ideal voltage division ratio is zero.
  • the first TFT 14 and the first TFT 14 and the first TFT 14 in the array substrate 10 in the present application reduces the sensitivity of the voltage division ratio of the second TFT 15 and the first TFT 14 to the channel size, and reduces the voltage division of the second TFT 15 and the first TFT 14 The amount of change in the ratio further reduces the brightness change value of the sub-pixels, and solves the problem of uneven display brightness of the display panel.
  • the present application also provides a display panel. As shown in FIG. A liquid crystal layer 30 is provided between the substrate 20 and the array substrate 10.
  • the present application divides the first channel 143 into at least two sub-channels, and disposes a semiconductor sub-layer in each sub-channel, so that the number of sub-channels in the first TFT 14 is
  • the number of second channels 153 in the second TFT 15 is larger than that of the second channel 153, thereby increasing the amount of change in the channel width in the first TFT 14, and compared with the existing TFT structure, reducing the The amount of variation in the actual channel ratio between the second TFT15 and the first TFT14 caused by the amount of exposure reduces the impact of the change in the amount of exposure at the prism connection portion 101 on the partial pressure ratio of the second TFT15 to the first TFT14, thereby reducing The brightness variation of the sub-pixels corresponding to the prism connecting portion 101 is reduced, and the problem of uneven display of the display panel is improved.

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Abstract

本申请提出了一种阵列基板及显示面板,所述阵列基板包括多个像素单元,所述像素单元包括第一TFT和第二TFT;所述第一TFT包括第一沟道和设置于第一沟道处的第一半导体层;所述第二TFT包括第二沟道和设置于第二沟道处的第二半导体层;所述第一沟道包括两子沟道,所述第一半导体层包括两半导体子层,每一子沟道中均设有半导体子层。

Description

阵列基板及显示面板 技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板及显示面板。
背景技术
随着显示技术的发展,对于显示面板中TFT的结构尺寸的精确性要求越来越高,尤其在具备主像素和次像素的像素结构中,需要通过主TFT控制主像素的亮度、次TFT和分压TFT控制次像素的亮度,而次像素的亮度受到分压TFT与次TFT的分压比的控制,具体分压TFT与次TFT的分压比受到分压TFT中分压沟道宽度与次TFT中次沟道宽度的比值控制。
技术问题
目前,在次TFT和分压TFT中沟道结构的实际制作过程中,需要依次形成栅极金属层、绝缘层及源漏金属层,采用曝光工艺图案化所述源漏金属层,然后根据图案化的所述源漏金属层,蚀刻形成所述次TFT中的次沟道和分压TFT中的分压沟道,目前,在诸如曝光等工艺中普遍采用多棱镜100组合的Nikon机台来曝光,如图1所示,由于各棱镜100之间重合的连接部与棱镜100本体曝光量存在一定差异,造成棱镜连接部101与棱镜本体102处的曝光量存在一定的差异,从而影响所述绝缘层上图案化的尺寸,使得对应于棱镜连接部101处的所述次TFT中次沟道的宽度和分压TFT中分压沟道的宽度同时变长或变短;进而造成蚀刻出的分压TFT中分压沟道的宽度与次TFT中次沟道的宽度的比值发生较大变化,对分压TFT与次TFT的分压比影响较大,整体上,影响了位于棱镜连接部101处次像素的亮度变化,造成了显示面板显示不均匀的现象。
技术解决方案
本申请提供一种阵列基板及显示面板,以解决现有次TFT中次沟道的宽 度与分压TFT中分压沟道的宽度比值易受到沟道宽度变化的影响,对次像素的亮度影响较大使得显示面板显示不均的技术问题。
为解决上述问题,本申请提供的技术方案如下:
本申请提供了一种阵列基板,包括衬底基板、以及呈阵列分布于所述衬底基板上的多个像素单元,任一所述像素单元至少包括主像素电极、次像素电极、与所述次像素电极电连接的第一TFT、与所述第一TFT电连接的第二TFT、以及与所述主像素电极电连接的第三TFT;
所述第一TFT包括第一源极、第一漏极、至少部分位于所述第一源极与所述第一漏极之间的第一沟道、以及设置于所述第一沟道处的第一半导体层;所述第二TFT包括第二源极、第二漏极、位于所述第二源极与所述第二漏极之间的第二沟道、以及设置于所述第二沟道处的第二半导体层。
其中,所述第一沟道至少包括两子沟道,所述第一半导体层至少包括两半导体子层,每一所述子沟道中均设有一所述半导体子层。
在本申请的阵列基板中,所述第一沟道至少包括第一子沟道和第二子沟道,所述第一半导体层至少包括位于所述第一子沟道内的第一半导体子层和位于所述第二子沟道内的第二半导体子层;所述第一子沟道和/或第二子沟道位于所述第一源极与所述第一漏极之间。
在本申请的阵列基板中,所述第一TFT与所述第二TFT通过所述第一源极与所述第二源极连接;或
通过所述第一漏极与所述第二漏极连接;
所述第二TFT设置于靠近所述第一TFT处,所述第一子沟道设置于所述第一TFT与所述第二TFT之间,所述第一沟道中至少所述第二子沟道设置于所述第一源极与所述第一漏极之间。
在本申请的阵列基板中,所述第一子沟道和所述第二子沟道均呈I型设置于所述第一源极与所述第一漏极之间。
在本申请的阵列基板中,所述第一子沟道与所述第二子沟道相互平行设置,所述第一沟道呈U型设置于所述第一源极与所述第一漏极之间,所述第一子沟道和所述第二子沟道分别设置于呈U型的所述第一沟道中的两平行边处。
在本申请的阵列基板中,所述第一沟道呈L型设置于所述第一源极与所述第一漏极之间,所述第一子沟道与所述第二子沟道分别设置于呈L型的所述第一沟道中的两侧边处。
在本申请的阵列基板中,所述第一子沟道与所述第二子沟道连通,所述第一半导体子层与所述第二半导体子层连为一体。
在本申请的阵列基板中,所述第一子沟道与所述第二子沟道呈间隔设置,所述第一半导体子层与所述第二半导体子层呈间隔设置于所述第一源极与所述第一漏极之间。
在本申请的阵列基板中,所述第一子沟道和所述第二子沟道均呈U型设置于所述第一源极与所述第一漏极之间。
本申请还提供一种显示面板,所述显示面板包括彩膜基板和如前实施例中任一项所述的阵列基板,所述彩膜基板与所述阵列基板之间设置有液晶层。
在本申请的显示面板中,所述第一沟道至少包括第一子沟道和第二子沟道,所述第一半导体层至少包括位于所述第一子沟道内的第一半导体子层和位于所述第二子沟道内的第二半导体子层;所述第一子沟道和/或第二子沟道位于所述第一源极与所述第一漏极之间。
在本申请的显示面板中,所述第一TFT与所述第二TFT通过所述第一源极与所述第二源极连接;或
通过所述第一漏极与所述第二漏极连接;
所述第二TFT设置于靠近所述第一TFT处,所述第一子沟道设置于所述第一TFT与所述第二TFT之间,所述第一沟道中至少所述第二子沟道设置于所述第一源极与所述第一漏极之间。
在本申请的显示面板中,所述第一子沟道和所述第二子沟道均呈I型设置于所述第一源极与所述第一漏极之间。
在本申请的显示面板中,所述第一子沟道与所述第二子沟道相互平行设置,所述第一沟道呈U型设置于所述第一源极与所述第一漏极之间,所述第一子沟道和所述第二子沟道分别设置于呈U型的所述第一沟道中的两平行边处。
在本申请的显示面板中,所述第一沟道呈L型设置于所述第一源极与所述 第一漏极之间,所述第一子沟道与所述第二子沟道分别设置于呈L型的所述第一沟道中的两侧边处。
在本申请的显示面板中,所述第一子沟道与所述第二子沟道连通,所述第一半导体子层与所述第二半导体子层连为一体。
在本申请的显示面板中,所述第一子沟道与所述第二子沟道呈间隔设置,所述第一半导体子层与所述第二半导体子层呈间隔设置于所述第一源极与所述第一漏极之间。
在本申请的显示面板中,所述第一子沟道和所述第二子沟道均呈U型设置于所述第一源极与所述第一漏极之间。
有益效果
本申请的有益效果为:本申请通过将所述第一沟道划分为至少两子沟道,并在每一所述子沟道中设置半导体子层,使得所述第一TFT中子沟道的数量大于所述第二TFT中第二沟道的数量,从而增大了所述第一TFT中沟道宽度的变化量,相比于现有TFT结构,减少了对应在棱镜连接部处由于受到曝光量影响造成的第二TFT与第一TFT之间实际沟道比值的变异量,减少了由于棱镜连接部处曝光量变化对第二TFT与第一TFT分压比的影响,从而降低了棱镜连接部所对应的次像素的亮度变化量,改善了显示面板显示不均的问题。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有曝光工艺中多棱镜组合的结构示意图;
图2为本申请实施例中阵列基板的第一种结构示意图;
图3为本申请实施例中阵列基板的第二种结构示意图;
图4为本申请实施例中阵列基板的第三种结构示意图;
图5为本申请实施例中阵列基板的第四种结构示意图;
图6为本申请实施例中阵列基板的第五种结构示意图;
图7为本申请实施例中阵列基板的第六种结构示意图;及
图8为本申请一实施方式中显示面板的结构示意图。
本发明的实施方式
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语,例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等,仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。在图中,结构相似的单元是用以相同标号表示。
在本申请的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本申请的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接或可以相互通讯;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征 “之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本申请。此外,本申请可以在不同例子中重复参考数字和/或参考字母,这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施方式和/或设置之间的关系。此外,本申请提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
现结合具体实施例对本申请的技术方案进行描述。
本申请提供了一种阵列基板10,如图2至图7所示,包括衬底基板11、以及呈阵列分布于所述衬底基板11上的多个像素单元,任一所述像素单元至少包括主像素电极12、次像素电极13、与所述次像素电极13电连接的第一TFT14、与所述第一TFT14电连接的第二TFT15、以及与所述主像素电极12电连接的第三TFT16;
所述第一TFT14包括第一源极141、第一漏极142、至少部分位于所述第一源极141与所述第一漏极142之间的第一沟道143、以及设置于所述第一沟道143处的第一半导体层144;所述第二TFT15包括第二源极151、第二漏极152、位于所述第二源极151与所述第二漏极152之间的第二沟道153、以及设置于所述第二沟道153处的第二半导体层154。
其中,所述第一沟道143至少包括两子沟道,所述第一半导体层144至少包括两半导体子层,每一所述子沟道中均设有一所述半导体子层。
可以理解的是,在具体形成TFT沟道的实际制作过程中,需要依次形成栅极金属层、绝缘层及源漏金属层,采用曝光工艺图案化所述源漏金属层,然后根据图案化的所述源漏金属层,蚀刻形成所述次TFT中的次沟道和分压TFT中的分压沟道,然而,在现有的曝光等工艺中普遍采用多棱镜100组合的Nikon机台来曝光,如图1所示,由于各多棱镜100之间重合的连接部与多棱镜本体 102曝光量存在一定差异,造成棱镜连接部101与棱镜本体102处的曝光量存在一定的差异,具体的,光线在棱镜连接部101处会具备较大衍射,造成在棱镜连接部101所对应部分的所述绝缘层上的图案开口的尺寸变大,从而在所述源漏金属层上蚀刻时,使得在沟道两端开口处的金属部分被蚀刻过多,造成蚀刻出的沟道宽度W变短;又由于在现有结构中,次TFT的次沟道宽度一般与分压TFT的分压沟道宽度存在较大差异,综合导致分压TFT与次TFT与的分压比的变化量较大,影响了位于棱镜连接部101处次像素的亮度变化,其中,在棱镜本体102所对应部分的所述绝缘层上的图案开口的尺寸没有变化,所述棱镜本体102所对应的次像素与所述棱镜连接部101对应的次像素像是的亮度不同,从而造成了显示面板显示不均匀的现象;值得注意的是,沟道宽度变短的量与该沟道所具备的开口数量相关,例如,一般TFT结构中的沟道一般为两端开口,则按照前述蚀刻过程,沟道两端均缩短Δw,导致该沟道宽度W整体缩短2Δw;本申请中通过将所述第一沟道143划分为至少两子沟道,并在每一所述子沟道中设置半导体子层,使得所述第一TFT14中子沟道的数量大于所述第二TFT15中第二沟道153的数量,多个所述子沟道具备多个开口,从而增大了所述第一TFT14中沟道宽度的变化量,相比于现有TFT结构,减少了对应在棱镜连接部101处由于受到曝光量影响造成的第二TFT15与第一TFT14之间实际沟道比值的变异量,减少了由于棱镜连接部101处曝光量变化对第二TFT15与第一TFT14分压比的影响,从而降低了棱镜连接部101所对应的次像素的亮度变化量,改善了显示面板显示不均的问题。
值得注意的是,在前述光线在棱镜连接部101处会具备较大衍射,造成在棱镜连接部101所对应部分的所述绝缘层上的图案开口的尺寸变大,从而在所述源漏金属层上蚀刻时,使得在沟道两端开口处的金属部分被蚀刻过多,不仅会造成蚀刻出的沟道宽度W变短;还会造成沟道的长度L变长,其中,所述沟道的长度L为源漏极之间的间距,但在现有结构设计中,各TFT的沟道长度差异性较小,在同时增加沟道长度的条件下,对分压TFT与次TFT的分压影响较小,故在此不作考虑。在实际应用中,所述棱镜连接部101所对应的所述像素单元的数量可达两百个,影响的范围较广,从而在显示面板中体现为显示不均。此外,本申请中所表述的沟道宽度W,以实际在沟道中填充的半导 体的宽度为准。
承上,所述第一TFT14、第二TFT15和所述第三TFT16可以是诸如顶栅结构、底栅结构等多种形式,本实施例中,所述第一TFT14、第二TFT15和所述第三TFT16均为底栅结构,并且,所述第一TFT14、第二TFT15和所述第三TFT16共用一栅极金属层17,所述第一TFT14与所述次像素电极13连接,所述第二TFT15与所述第一TFT14连接,所述第一TFT14和所述第二TFT15用于控制次像素的亮度,所述第三TFT16与所述主像素电极12,所述第三TFT16用于控制主像素的亮度;其中,所述第二半导体层154布满所述第二沟道153;所述半导体子层布满所述子沟道。此外,在具体结构中,所述第一TFT14中第一源极141和第一漏极142可以互换,所述第二TFT15中第二源极151和第二漏极152也可互换,所述第三TFT16包括的第三源极和第三漏极可以互换,在此不再赘述。
在一实施例中,所述第一沟道143至少包括第一子沟道1431和第二子沟道1432,所述第一半导体层144至少包括位于所述第一子沟道1431内的第一半导体子层1441和位于所述第二子沟道1432内的第二半导体子层1442;所述第一子沟道1431和/或第二子沟道1432位于所述第一源极141与所述第一漏极142之间;可以理解的是,所述第一子沟道1431和第二子沟道1432既可以同时位于所述第一源极141与所述第一漏极142之间,也可以其中之一位于所述第一源极141与所述第一漏极142之间,在至少具备3T的结构中,任一两TFT中的两源极或两漏极均可采用一体结构,从而实现部分第一沟道143位于所述第一源极141与所述第一漏极142之间,也即是所述第一子沟道1431或第二子沟道1432位于所述第一源极141与所述第一漏极142之间的结构。
在一实施例中,如图2所示,所述第一TFT14与所述第二TFT15通过所述第一源极141与所述第二源极151连接;或通过所述第一漏极142与所述第二漏极152连接;所述第二TFT15设置于靠近所述第一TFT14处,所述第一子沟道1431设置于所述第一TFT14与所述第二TFT15之间,所述第一沟道143中至少所述第二子沟道1432设置于所述第一源极141与所述第一漏极142之间;本实施例中,所述第一TFT14中具备所述第一子沟道1431和所述第二子沟道1432,从而具备四个开口,在制作过程中的所述第一沟道143整体宽 度的变异量为4Δw。
承上,具体的,所述第一TFT14与所述第二TFT15可采用通过所述第一漏极142与所述第二漏极152连接的结构;所述第二TFT15中所述第二漏极152设置于靠近所述第一TFT14的第一源极141处,所述第一子沟道1431位于所述第二漏极152与第一源极141之间,可以理解的是,所述第一TFT14与所述第二TFT15采用通过所述第一漏极142与所述第二漏极152连接的结构,实际上类似于所述第一TFT14与所述第二TFT15采用共漏极的结构,因此,此时所述第一子沟道1431没有位于所述第一源极141与所述第一漏极142之间;此外,所述第一沟道143中至少所述第二子沟道1432设置于所述第一源极141与所述第一漏极142之间;当然,所述第一沟道143还可以包括第三子沟道1433等均可同时与所述第二子沟道1432设置于所述第一源极141与所述第一漏极142之间,具体结构可参考结合其它将所述第一沟道143全部设于所述第一源极141与所述第一漏极142之间的实施例方案,在此不再赘述。
在一实施例中,如图3-图5所示,所述第一子沟道1431和所述第二子沟道1432均呈I型设置于所述第一源极141与所述第一漏极142之间;显然,此时,所述第一沟道143全部设于所述第一源极141与所述第一漏极142之间;可以理解的是,所述第一子沟道1431与所述第二子沟道1432均呈I型设置于所述第一源极141与所述第一漏极142之间,此时,所述第一子沟道1431和所述第二子沟道1432的均具备两开口,所述第一沟道143整体宽度的变异量为4Δw。
具体的,如图3所示,所述第一子沟道1431与所述第二子沟道1432相互平行设置,所述第一沟道143呈U型设置于所述第一源极141与所述第一漏极142之间,所述第一子沟道1431和所述第二子沟道1432分别设置于呈U型的所述第一沟道143中的两平行边处;具体的,所述第一漏极142设置于呈凹型的第一源极141中,以使得所述第一沟道143呈U型结构,所述第一子沟道1431和所述第二子沟道1432分别设置于呈U型的所述第一沟道143中的两平行边处,即所述第一半导体子层1441和所述第二半导体子层1442分别填充于所述呈U型的所述第一沟道143中的两平行边处,在所述U型的所述第一沟道143中拐弯的连接段处没有填充半导体,值得注意的是,所述第一子 沟道1431和所述第二子沟道1432的宽度均大于所述第一漏极142位于呈U型的所述第一沟道143中的宽度。
在一实施例中,如图4-5所示,所述第一沟道143呈L型设置于所述第一源极141与所述第一漏极142之间,所述第一子沟道1431与所述第二子沟道1432分别设置于呈L型的所述第一沟道143中的两侧边处;显然,此时所述第一子沟道1431与所述第二子沟道1432呈一定角度的非平行状态,具体所述第一子沟道1431与所述第二子沟道1432的夹角与呈L型的所述第一沟道143中的两侧边的夹角相同。具体的,如图4所示,所述第一子沟道1431与所述第二子沟道1432可以连通,所述第一半导体子层1441与所述第二半导体子层1442连为一体,此外,如图5所示,所述第一子沟道1431与所述第二子沟道1432也可呈间隔设置,所述第一半导体子层1441与所述第二半导体子层1442呈间隔设置于所述第一源极141与所述第一漏极142之间。
在一实施例中,如图6所示,所述第一子沟道1431和所述第二子沟道1432均呈U型设置于所述第一源极141与所述第一漏极142之间;可以理解的的是,所述第一沟道143此时呈双U型结构设置于所述第一源极141与所述第一漏极142之间,并且,所述第一子沟道1431和所述第二子沟道1432均具备两开口,所述第一沟道143整体宽度的变异量为4Δw。
在一实施例中,如图7所示,在如图2所示结构的基础上,结合如图3所示的结构,所述第一沟道143还可以包括第三子沟道1433,所述第三子沟道1433与所述第二子沟道1432设置于所述第一源极141与所述第一漏极142之间,具体的,所述第三子沟道1433与所述第二子沟道1432均为I型结构,所述第三子沟道1433与所述第二子沟道1432相互平行设置,所述第一沟道143呈U型设置于所述第一源极141与所述第一漏极142之间,所述第三子沟道1433与所述第二子沟道1432分别设置于呈U型的所述第一沟道143中的两平行边处;此时,所述所述第一子沟道1431、所述第二子沟道1432和所述第三子沟道1433均具备两开口,所述第一沟道143整体宽度的变异量为6Δw。
综上,如表1所示,为图2—图7中不同所述阵列基板10中所述第一TFT14与所述第二TFT15分压比受沟道尺寸影响的变化量:显然,如前所述,由于各多棱镜100之间重合的连接部与多棱镜本体102曝光量存在一定差异,造成 棱镜连接部101与棱镜本体102处的曝光量存在一定的差异,具体的,光线在棱镜连接部101处会具备较大衍射,造成在棱镜连接部101所对应部分的所述绝缘层上的图案开口的尺寸变大,从而在所述源漏金属层上蚀刻时,使得在沟道两端开口处的金属部分被蚀刻过多,造成蚀刻出的沟道宽度W变短;导致控制次像素亮度的分压比变化量较大,影响了位于棱镜连接部101处次像素的亮度变化,造成显示面板出现亮度不均的问题。
Figure PCTCN2020091249-appb-000001
表1:不同阵列基板结构的分压变化情况
如表1所示,设有五组对照数据,分别包括理论参照、现有参照、图2-图3结构对照、图4-图6结构对照和图7结构对照,可以理解的是,理论参照即为所述第二TFT15与所述第一TFT14分压比的理论值,在理想条件下,所述第一TFT14的W1变化与所述第二TFT15的W2变化均为0,此时,所述第二TFT15与所述第一TFT14分压比即为所述第二TFT15的W2设计值与所述第一TFT14的W1设计值之比,如表1所示,以所述第一TFT14的W1设计值为26.6um,所述第二TFT15的W2设计值为6um为例,得到所述第二TFT15与所述第一TFT14分压比为22.6%,并且,所述第二TFT15与所述第一TFT14分压比相对于设计的理想分压比的变化量为0。
承上,按照上述方式计算,以Δw=0.3um为例,在现有参照中,即现有TFT结构中W1和W2的变化均为2Δw,导致在现有参照中的实际分压比为(6-2Δw)/(26.6-2Δw)=20.7%,因此,现有参照的实际分压比20.7%相比于理想分压比22.6%的变化量为1.30%;具体的,图2-图3结构对照、图4- 图6结构对照和图7结构对照的分压比变化量依次为1.30%、1.30%和0.78%,显然,本申请中所述阵列基板10中的所述第一TFT14和所述第二TFT15结构,降低了所述第二TFT15与所述第一TFT14的分压比受沟道尺寸影响的敏感度,减小了所述第二TFT15与所述第一TFT14的分压比的变化量,进而降低了次像素的亮度变化值,很好的解决了显示面板的显示亮度不均的问题。
基于上述阵列基板10,本申请还提供一种显示面板,如图8所示,所述显示面板包括彩膜基板20和如前实施例中任一项所述的阵列基板10,所述彩膜基板20与所述阵列基板10之间设置有液晶层30。
综上所述,本申请通过将所述第一沟道143划分为至少两子沟道,并在每一所述子沟道中设置半导体子层,使得所述第一TFT14中子沟道的数量大于所述第二TFT15中第二沟道153的数量,从而增大了所述第一TFT14中沟道宽度的变化量,相比于现有TFT结构,减少了对应在棱镜连接部101处由于受到曝光量影响造成的第二TFT15与第一TFT14之间实际沟道比值的变异量,减少了由于棱镜连接部101处曝光量变化对第二TFT15与第一TFT14分压比的影响,从而降低了棱镜连接部101所对应的次像素的亮度变化量,改善了显示面板显示不均的问题。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板,包括衬底基板、以及呈阵列分布于所述衬底基板上的多个像素单元,任一所述像素单元至少包括主像素电极、次像素电极、与所述次像素电极电连接的第一TFT、与所述第一TFT电连接的第二TFT、以及与所述主像素电极电连接的第三TFT;
    所述第一TFT包括第一源极、第一漏极、至少部分位于所述第一源极与所述第一漏极之间的第一沟道、以及设置于所述第一沟道处的第一半导体层;所述第二TFT包括第二源极、第二漏极、位于所述第二源极与所述第二漏极之间的第二沟道、以及设置于所述第二沟道处的第二半导体层;
    其中,所述第一沟道至少包括两子沟道,所述第一半导体层至少包括两半导体子层,每一所述子沟道中均设有一所述半导体子层。
  2. 根据权利要求1所述的阵列基板,其中,所述第一沟道至少包括第一子沟道和第二子沟道,所述第一半导体层至少包括位于所述第一子沟道内的第一半导体子层和位于所述第二子沟道内的第二半导体子层;所述第一子沟道和/或第二子沟道位于所述第一源极与所述第一漏极之间。
  3. 根据权利要求2所述的阵列基板,其中,所述第一TFT与所述第二TFT通过所述第一源极与所述第二源极连接;或
    通过所述第一漏极与所述第二漏极连接;
    所述第二TFT设置于靠近所述第一TFT处,所述第一子沟道设置于所述第一TFT与所述第二TFT之间,所述第一沟道中至少所述第二子沟道设置于所述第一源极与所述第一漏极之间。
  4. 根据权利要求2所述的阵列基板,其中,所述第一子沟道和所述第二子沟道均呈I型设置于所述第一源极与所述第一漏极之间。
  5. 根据权利要求4所述的阵列基板,其中,所述第一子沟道与所述第二子沟道相互平行设置,所述第一沟道呈U型设置于所述第一源极与所述第一漏极之间,所述第一子沟道和所述第二子沟道分别设置于呈U型的所述第一沟道中的两平行边处。
  6. 根据权利要求4所述的阵列基板,其中,所述第一沟道呈L型设置于 所述第一源极与所述第一漏极之间,所述第一子沟道与所述第二子沟道分别设置于呈L型的所述第一沟道中的两侧边处。
  7. 根据权利要求6所述的阵列基板,其中,所述第一子沟道与所述第二子沟道连通,所述第一半导体子层与所述第二半导体子层连为一体。
  8. 根据权利要求6所述的阵列基板,其中,所述第一子沟道与所述第二子沟道呈间隔设置,所述第一半导体子层与所述第二半导体子层呈间隔设置于所述第一源极与所述第一漏极之间。
  9. 根据权利要求2所述的阵列基板,其中,所述第一子沟道和所述第二子沟道均呈U型设置于所述第一源极与所述第一漏极之间。
  10. 一种显示面板,所述显示面板包括彩膜基板和如权利要求1所述的阵列基板,所述彩膜基板与所述阵列基板之间设置有液晶层。
  11. 根据权利要求10所述的显示面板,其中,所述第一沟道至少包括第一子沟道和第二子沟道,所述第一半导体层至少包括位于所述第一子沟道内的第一半导体子层和位于所述第二子沟道内的第二半导体子层;所述第一子沟道和/或第二子沟道位于所述第一源极与所述第一漏极之间。
  12. 根据权利要求11所述的显示面板,其中,所述第一TFT与所述第二TFT通过所述第一源极与所述第二源极连接;或
    通过所述第一漏极与所述第二漏极连接;
    所述第二TFT设置于靠近所述第一TFT处,所述第一子沟道设置于所述第一TFT与所述第二TFT之间,所述第一沟道中至少所述第二子沟道设置于所述第一源极与所述第一漏极之间。
  13. 根据权利要求11所述的显示面板,其中,所述第一子沟道和所述第二子沟道均呈I型设置于所述第一源极与所述第一漏极之间。
  14. 根据权利要求13所述的显示面板,其中,所述第一子沟道与所述第二子沟道相互平行设置,所述第一沟道呈U型设置于所述第一源极与所述第一漏极之间,所述第一子沟道和所述第二子沟道分别设置于呈U型的所述第一沟道中的两平行边处。
  15. 根据权利要求13所述的显示面板,其中,所述第一沟道呈L型设置于所述第一源极与所述第一漏极之间,所述第一子沟道与所述第二子沟道分别 设置于呈L型的所述第一沟道中的两侧边处。
  16. 根据权利要求15所述的显示面板,其中,所述第一子沟道与所述第二子沟道连通,所述第一半导体子层与所述第二半导体子层连为一体。
  17. 根据权利要求15所述的显示面板,其中,所述第一子沟道与所述第二子沟道呈间隔设置,所述第一半导体子层与所述第二半导体子层呈间隔设置于所述第一源极与所述第一漏极之间。
  18. 根据权利要求11所述的显示面板,其中,所述第一子沟道和所述第二子沟道均呈U型设置于所述第一源极与所述第一漏极之间。
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