WO2021212676A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021212676A1
WO2021212676A1 PCT/CN2020/103313 CN2020103313W WO2021212676A1 WO 2021212676 A1 WO2021212676 A1 WO 2021212676A1 CN 2020103313 W CN2020103313 W CN 2020103313W WO 2021212676 A1 WO2021212676 A1 WO 2021212676A1
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Prior art keywords
functional
layer
slope angle
pattern
area
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PCT/CN2020/103313
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English (en)
French (fr)
Inventor
李盼
先建波
龙春平
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020227016770A priority Critical patent/KR20230006796A/ko
Priority to US17/280,795 priority patent/US11387259B2/en
Priority to JP2021535991A priority patent/JP2023522495A/ja
Priority to EP20897670.4A priority patent/EP4141934A4/en
Publication of WO2021212676A1 publication Critical patent/WO2021212676A1/zh

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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the circuit structure generally includes thin film transistors, capacitors, electrode structures, and signal lines. At least part of the functional layers included in the thin film transistors, capacitors, electrode structures, and signal lines are patterned functional patterns. These functional patterns will be in the array. A stepped area is generated in the substrate, so that the functional layer covering the stepped area in the array substrate needs to cross the step of the stepped area, resulting in the risk of the functional layer being easily broken at the step.
  • the thickness of the functional layer is generally increased, but this processing method is not conducive to the application of the array substrate in the thin display product.
  • a first aspect of the present disclosure provides an array substrate, including: a base, and a first functional layer and a second functional layer stacked on the base; the first functional layer forms a stepped area on the base, The second functional layer covers the step area;
  • the portion of the first functional layer located in the step area has a target slope angle, and the target slope angle is the maximum slope angle under the condition that the second functional layer satisfies a preset thickness; the preset thickness is the first The thickness of the second functional layer that meets its own functional requirements and does not break in the step area.
  • the target slope angle of the first functional layer and the preset thickness of the second functional layer satisfy a relational expression:
  • N z ⁇ W ⁇ K IC , z is a constant, W is a preset value, K IC is the fracture toughness parameter of the second functional layer, x is the preset thickness of the second functional layer, and y is The thickness of the part of the first functional layer located in the step area, and a is the target slope angle of the first functional layer.
  • the first functional layer includes a first functional pattern, and the first functional pattern forms a first step area on the substrate;
  • the second functional layer includes: a first functional film layer and a second functional film layer; the first functional film layer is disposed on the side of the first functional pattern away from the substrate, and the second functional film Layer, arranged on the side of the first functional film layer away from the substrate; the first functional film layer and the second functional film layer both cover the first step area, and the first functional film layer Substantially the same as the fracture toughness parameter of the second functional film layer;
  • the thickness of the first functional film layer is uniform, and the thickness of the second functional film layer is uniform;
  • the part of the first functional graphic located in the first step area has a first target slope angle, and the first target slope angle is that the first functional film layer and the second functional film layer meet the first preset
  • the maximum slope angle under the thickness condition; the first preset thickness is when the first functional film layer and the second functional film layer meet their respective functional requirements and no fracture occurs in the first step area , The sum of the thickness of the first functional film layer and the thickness of the second functional film layer.
  • the first functional layer further includes a second functional graphic, the second functional graphic and the first functional graphic are arranged in the same layer and the same material, and the second functional graphic forms a second functional graphic on the substrate.
  • the first functional film layer covers the second step area
  • the part of the second functional graphic located in the second step area has a second target slope angle, and the second target slope angle is the maximum slope angle under the condition that the first functional film layer satisfies a second preset thickness;
  • the second predetermined thickness is the thickness at which the first functional film layer satisfies its own functional requirements and does not break in the second step area;
  • the second target slope angle is smaller than the first target slope angle.
  • the first functional layer further includes a third functional graphic, the third functional graphic is located on the side of the first functional film layer away from the substrate, and the third functional graphic is on the substrate Form the third step area;
  • the second functional film layer covers the third step area
  • the part of the third functional graphic located in the third step area has a third target slope angle, and the third target slope angle is the maximum slope angle under the condition that the second functional film layer satisfies a third preset thickness;
  • the third preset thickness is the thickness at which the second functional film layer satisfies its own functional requirements and does not break in the third step area;
  • the third target slope angle is greater than the second target slope angle and smaller than the first target slope angle.
  • the first functional layer includes a fourth functional pattern, and the fourth functional pattern forms on the substrate at least two fourth step regions arranged in sequence in a direction away from the substrate;
  • the second functional layer includes a flat layer disposed on a side of the fourth functional pattern away from the substrate, and the flat layer completely covers the fourth functional pattern;
  • the portion of the fourth functional graph located in each of the fourth step regions has a corresponding fourth target slope angle, and the fourth target slope angle is: the fourth step angle corresponding to the fourth target slope angle in the flat layer
  • the maximum slope angle of the first part of the area under the condition of meeting the fourth preset thickness; the fourth preset thickness is the thinnest thickness at which the first part meets its own functional requirements and does not break in the fourth step area .
  • the first functional layer includes a first functional pattern, and the first functional pattern forms a first step area on the substrate;
  • the second functional layer includes: a first functional film layer and a second functional film layer; the first functional film layer is disposed on the side of the first functional pattern away from the substrate, and the second functional film Layer, arranged on the side of the first functional film layer away from the substrate; both the first functional film layer and the second functional film layer cover the first step area;
  • the fourth functional pattern is located on a side of the second functional film layer away from the substrate, and the fourth functional pattern covers the first step area.
  • the flat layer includes a first flat layer and a second flat layer
  • the first functional layer further includes another fourth functional pattern
  • the other fourth functional pattern is located far away from the first flat layer.
  • the other fourth functional pattern forms another fourth stepped area on the substrate, and the portion of the other fourth functional pattern located in the other fourth stepped area has another A fourth target slope angle, and the second flat layer covers the other fourth functional pattern.
  • the first functional layer includes a fifth functional pattern and a sixth functional pattern that are sequentially stacked in a direction away from the substrate;
  • the second functional layer includes a second functional film layer arranged between the fifth functional pattern and the sixth functional pattern, and a flat layer arranged on the side of the sixth functional pattern away from the substrate Wherein, the second functional film layer is provided with a first via hole, and the second functional film layer forms a fifth step area at the edge of the first via hole;
  • the portion of the second functional film layer located in the fifth step area has a fifth target slope angle
  • the sixth functional pattern is coupled to the fifth functional pattern through the first via hole, the sixth functional pattern covers the fifth level difference area, and a sixth level difference area is formed at a position corresponding to the fifth level difference area. Step area
  • the portion of the sixth functional graph located in the sixth step area has a sixth target slope angle
  • the sixth target slope angle is: the second portion of the flat layer located in the sixth step area satisfies the sixth The maximum slope angle under a preset thickness condition; the sixth preset thickness is the thinnest thickness at which the second part meets its own functional requirements and does not break in the sixth step area;
  • the fifth target slope angle is approximately equal to the sixth target slope angle.
  • the first functional layer includes:
  • the projection overlaps the orthographic projection of the fourth part on the substrate, and the orthographic projection of the ninth step area on the substrate overlaps the orthographic projection of the fifth part on the substrate;
  • the second functional layer includes a second functional film layer and a ninth functional graphic; wherein, the second functional film layer is located between the seventh functional graphic and the eighth functional graphic, and the ninth functional graphic Located on the side of the flat layer away from the substrate and coupled to the eighth functional pattern through the second via hole; the ninth functional pattern covers the eighth step area and the ninth step area Area; the ninth functional graphic has a uniform thickness;
  • the portion of the flat layer located in the eighth step area has an eighth target slope angle, and the eighth target slope angle is: the ninth functional graphic satisfies the maximum slope angle under the condition of the eighth preset thickness; 8.
  • the preset thickness is the thickness of the ninth functional figure when it meets its own functional requirements and does not break in the eighth step area;
  • the portion of the flat layer located in the ninth step area has a ninth target slope angle, and the ninth target slope angle is: the ninth functional graphic satisfies the maximum slope angle under the condition of the ninth preset thickness;
  • the nine preset thickness is the thickness of the ninth functional figure when it meets its own functional requirements and does not break in the ninth step area.
  • the orthographic projection of the seventh functional graphic on the substrate and the orthographic projection of the eighth functional graphic on the substrate form a first overlapping area, and the first overlapping area extends along the first The direction has the first dimension;
  • the portion of the eighth functional pattern that is not located in the first overlapping area has a second size along the first direction; the ninth functional pattern and the eighth functional pattern form a first contact area along the In the first direction, the minimum distance between the boundary of the first contact area and the first end of the eighth functional pattern is a first distance, and the boundary between the first contact area and the eighth functional pattern
  • the minimum distance between the second ends is the second distance; the first end and the second end are opposite along the first direction, and the orthographic projection of the first end on the substrate is the same as the seventh
  • the functional graphics overlap, and the orthographic projection of the second end on the substrate does not overlap with the seventh functional graphics;
  • the first absolute value corresponding to the difference between the first size and the second size is proportional to the second absolute value corresponding to the difference between the first interval and the second interval.
  • the second absolute value corresponding to the difference between the first distance and the second distance is the same as the first distance between the first distance and the eighth functional graphic in the first direction.
  • the ratio of width is directly proportional.
  • the eighth target slope angle is greater than the ninth target slope angle
  • the difference between the eighth target slope angle and the ninth target slope angle is proportional to the first size.
  • the difference between the eighth target slope angle and the ninth target slope angle is smaller than the seventh target slope angle of the seventh functional graph in the seventh step difference area;
  • the seventh target gradient angle is the maximum gradient angle under the condition that the second functional film layer meets the seventh preset thickness; the seventh preset thickness is the second functional film layer meeting its own functional requirements, And the thickness at which no fracture occurs in the seventh step area.
  • the array substrate includes a capacitor structure
  • the first functional layer includes a first electrode plate of the capacitor structure, and the first electrode plate forms an electrode plate step area on the substrate;
  • the second functional layer includes a dielectric layer located on the side of the first electrode plate away from the substrate, the dielectric layer completely covers the first electrode plate;
  • the part of the area has a target slope angle of the plate, the target slope angle of the plate is the maximum slope angle under the condition that the dielectric layer meets the tenth preset thickness;
  • the tenth preset thickness is that the dielectric layer meets its The thickness required by its own function and that will not break in the region of the electrode plate section;
  • the second electrode plate of the capacitor structure is located on the side of the dielectric layer away from the substrate, and the orthographic projection of the second electrode plate on the substrate is the same as that of the first electrode plate on the substrate.
  • the projection forms a first overlapping area, and the second electrode plate covers the electrode plate level difference area.
  • the capacitor structure includes: a first capacitor structure, a second capacitor structure, and a third capacitor structure; the capacitance value of the first capacitor structure is greater than the capacitance value of the second capacitor structure, and/or the The capacitance of the first capacitor structure is greater than the capacitance of the third capacitor structure;
  • the target slope angle of the electrode plate corresponding to the first electrode plate of the first capacitor structure is greater than the target slope angle of the electrode plate corresponding to the first electrode plate of the second capacitor structure; and/or the target slope angle of the first capacitor structure
  • the target slope angle of the electrode plate corresponding to the first electrode plate is greater than the target slope angle of the electrode plate corresponding to the first electrode plate of the third capacitor structure.
  • the thickness of the first dielectric layer corresponding to the first capacitor structure is smaller than the thickness of the second dielectric layer corresponding to the second capacitor structure; and/or,
  • the thickness of the first dielectric layer corresponding to the first capacitor structure is smaller than the thickness of the third dielectric layer corresponding to the third capacitor structure.
  • the portion of the second electrode plate of the first capacitor structure that is located in the corresponding first overlapping area includes a slope angle greater than that of the second electrode plate of the second capacitor structure that is located on the corresponding first intersection.
  • the portion of the second plate of the first capacitor structure that is located in the corresponding first overlapping area includes a slope angle that is greater than the portion of the second plate of the third capacitor structure that is located in the corresponding first overlapping area. Including slope angle.
  • the first functional layer includes a composite metal pattern
  • the composite metal pattern includes a first metal sub-pattern, a second metal sub-pattern, and a third metal sub-pattern sequentially stacked in a direction away from the substrate, and
  • the material of the first metal sub-pattern is the same as that of the third metal sub-pattern;
  • the target slope angle of the first functional layer is inversely proportional to the etching rate of the third metal sub-pattern.
  • a second aspect of the present disclosure provides a display device including the above-mentioned array substrate.
  • a third aspect of the present disclosure provides a manufacturing method of an array substrate for manufacturing the above-mentioned array substrate, and the manufacturing method includes:
  • the first functional layer forms a stepped area on the substrate, and a portion of the first functional layer located in the stepped area has a target slope angle;
  • a second functional layer is formed on the side of the first functional layer away from the substrate, and the second functional layer covers the step area; the target slope angle is when the second functional layer meets the preset thickness condition The maximum slope angle of; the preset thickness is the thickness at which the second functional layer meets its own functional requirements and does not break in the step area;
  • the target slope angle of the first functional layer and the preset thickness of the second functional layer satisfy the relationship:
  • N z ⁇ W ⁇ K IC , z is a constant, W is a preset value, K IC is the fracture toughness parameter of the second functional layer, x is the preset thickness of the second functional layer, and y is The thickness of the part of the first functional layer located in the step area, and a is the target slope angle of the first functional layer.
  • FIG. 1 is a first cross-sectional schematic diagram of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a second cross-section of an array substrate provided by an embodiment of the disclosure.
  • FIG. 3 is a third schematic cross-sectional view of an array substrate provided by an embodiment of the disclosure.
  • FIG. 4 is a fourth schematic cross-sectional view of the array substrate provided by an embodiment of the disclosure.
  • FIG. 5 is a fifth schematic cross-sectional view of an array substrate provided by an embodiment of the disclosure.
  • FIG. 6 is a sixth schematic cross-sectional view of an array substrate provided by an embodiment of the disclosure.
  • FIG. 7 is a seventh schematic cross-sectional view of an array substrate provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic cross-sectional view of a first capacitor structure provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic cross-sectional view of a second capacitor structure provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic cross-sectional view of a third capacitor structure provided by an embodiment of the disclosure.
  • FIG. 11 is a first schematic diagram of a capacitor structure in a display area and a peripheral area provided by an embodiment of the disclosure.
  • FIG. 12 is a second schematic diagram of a capacitor structure in a display area and a peripheral area provided by an embodiment of the disclosure.
  • FIG. 13 is a first cross-sectional schematic diagram of a first functional layer provided by an embodiment of the disclosure.
  • FIG. 14 is a second cross-sectional schematic diagram of the first functional layer provided by an embodiment of the disclosure.
  • FIG. 16 is an eighth cross-sectional schematic diagram of an array substrate provided by an embodiment of the disclosure.
  • FIG. 17 is a schematic diagram of forming a buffer layer on a substrate according to an embodiment of the disclosure.
  • FIG. 18 is a schematic diagram of laser annealing an active thin film provided by an embodiment of the disclosure.
  • FIG. 19 is a schematic diagram of forming an active layer according to an embodiment of the disclosure.
  • FIG. 20 is a schematic diagram of forming a first gate insulating layer according to an embodiment of the disclosure.
  • FIG. 21 is a schematic diagram of forming a first gate metal pattern according to an embodiment of the disclosure.
  • FIG. 22 is a schematic diagram of performing a heavy doping process according to an embodiment of the disclosure.
  • FIG. 23 is a schematic diagram of forming a second gate insulating layer according to an embodiment of the disclosure.
  • 24 is a schematic diagram of forming a second gate metal pattern provided by an embodiment of the disclosure.
  • 25 is a schematic diagram of forming an interlayer insulating layer provided by an embodiment of the disclosure.
  • FIG. 26 is a first schematic diagram of forming a via hole according to an embodiment of the disclosure.
  • FIG. 27 is a schematic diagram of forming source and drain metal patterns according to an embodiment of the disclosure.
  • FIG. 28 is a schematic diagram of forming a flat layer provided by an embodiment of the disclosure.
  • FIG. 29 is a schematic diagram of forming an anode pattern provided by an embodiment of the disclosure.
  • FIG. 30 is a schematic diagram of forming a pixel defining layer provided by an embodiment of the disclosure.
  • a circuit structure is formed in the array substrate included in the display product.
  • the circuit structure generally includes thin film transistors, capacitors, electrode structures, and signal lines. At least part of the functional layers included in the thin film transistors, capacitors, electrode structures, and signal lines are patterns. These functional patterns will produce a stepped area in the array substrate.
  • the stepped area includes steps with a certain slope angle formed by the functional graphics, so that the functional layer covering the stepped area in the array substrate needs to cross the stepped area. Steps in the area, resulting in the risk of the functional layer being easily broken at the steps.
  • the insulating layer needs to cross the steps of the stepped area, resulting in the existence of the insulating layer easily at the step.
  • the risk of breakage, and the breakage of the insulating layer may further cause a short circuit between the conductive pattern formed on the insulating layer and the metal pattern, which affects the yield of the array substrate.
  • the thickness of the functional layer is generally increased, but this processing method is not conducive to the application of the array substrate in the thin display products.
  • an embodiment of the present disclosure provides an array substrate, including: a base 10, and a first functional layer 20 and a second functional layer 30 stacked on the base 10; the first functional layer 20 forms a level difference area 40 on the substrate 10, the second functional layer 30 covers the level difference area 40; the part of the first functional layer 20 located in the level difference area has a target slope angle a, and the target slope Angle a is the maximum slope angle under the condition that the second functional layer 30 meets the preset thickness; the preset thickness is that the second functional layer 30 meets its own functional requirements and does not occur in the step area 40 The thickness of the fracture.
  • the array substrate includes a variety of film layers, exemplarily including: a first gate metal layer, a gate insulating layer, a second gate metal layer, an interlayer insulating layer, and a first source-drain metal layer that are stacked.
  • the first flat layer, the second source and drain metal layer, the second flat layer, the anode layer, etc. but not limited to this.
  • the first gate metal layer, the second gate metal layer, the first source/drain metal layer, the second source/drain metal layer, and the anode layer all include a plurality of corresponding functional patterns, and each functional pattern forms a corresponding step area;
  • the gate insulating layer, the interlayer insulating layer, the first flat layer and the second flat layer are all layers of the entire film, but these entire layers of the film will be formed with via holes, the entire film will be in the over A corresponding step area is formed near the hole.
  • the first functional layer 20 may include: one or more of the plurality of functional patterns, and may also include the above-mentioned entire film layer formed with vias; similarly, the second functional layer 30 may also include: one or more of the plurality of functional patterns, and the above-mentioned entire film layer formed with vias, and only need to satisfy one or more of the plurality of functional patterns, and the above-mentioned formation with The entire film layer of the via can cover the step area.
  • the step area formed by the functional graphic may be located at the edge portion of the functional graphic, or may be located at the middle portion of the functional graphic surrounded by the edge portion; in more detail, the level difference area formed at the edge portion of the functional graphic
  • the level difference area is generally the level difference formed between the edge part and the plane where the edge part is located;
  • the level difference formed in the middle part of the functional graphics is generally that the middle part covers an uneven area (such as: the level difference caused by the underlying graphics Area), so that a level difference is generated in the middle part, or a level difference is formed between the middle part and the edge part.
  • the specific range of the step area can be defined according to actual needs.
  • the step area is the area where the steps generated by the functional graphics are located; or, the step area is generated by the functional graphics.
  • the step is the center, and the area within the preset range nearby.
  • the explanation is as follows: “meeting its own functional requirements” refers to the first
  • the thickness of the second functional layer 30 must be able to meet its own functional requirements.
  • the second functional layer 30 is an insulating layer, its thickness must be set to ensure that its insulating performance meets the requirements; when the insulating layer is used as a capacitor The thickness of the dielectric layer must be set to ensure that the capacitance of the capacitor meets the requirements; when the second functional layer 30 is a flat layer, the thickness of the second functional layer 30 must be set to ensure that its flatness meets the requirements.
  • the second functional layer 30 has a uniform thickness in the extending direction perpendicular to itself, and the second functional layer 30 simultaneously covers a plurality of first functional patterns with different slope angles arranged in the same layer It is necessary to ensure that the second functional layer 30 does not break in the step area generated by each first functional pattern.
  • the factors related to the risk of fracture of the second functional layer 30 include: the size of the slope angle of the steps that the second functional layer 30 needs to climb in the step area, and the thickness of the second functional layer 30; wherein, the slope of the step The larger the angle, the more conducive to the layout of compact functional graphics, which is more conducive to the application of array substrates in high-resolution display products.
  • the greater the slope angle of the steps the greater the risk of a functional layer with a certain thickness from breaking at the steps.
  • the second functional layer 30 satisfies its own functional requirements, the thicker the thickness, the less likely it is to break in the step area, but the thicker thickness is not conducive to the application of the array substrate in thin display products; therefore, Based on the above factors, the corresponding relationship between the thickness of the second functional layer 30 and the slope angle of the step across it can be found, so as to achieve the maximum slope angle and maximum slope angle without breaking the second functional layer 30. Thin second functional layer 30.
  • the part of the first functional layer 20 located in the step area has a target slope angle, and the target slope angle is that the second functional layer 30 satisfies the preset thickness condition
  • the maximum slope angle; the preset thickness is the thickness that the second functional layer 30 meets its own functional requirements and does not break in the step area; so that the array substrate realizes the first function While the layer 20 has the largest slope angle, it is ensured that the second functional layer 30 has the minimum thickness that meets its own functional requirements and does not break in the step area.
  • the array substrate provided by the embodiment of the present disclosure Under the condition of ensuring that the functional layer does not break, the largest slope angle and the thinnest second functional layer 30 are realized, so that the array substrate can be better used in thinner and high-resolution display products, and at the same time better Improve the product yield of the array substrate and reduce the cost of raw materials.
  • the target slope angle of the first functional layer 20 and the preset thickness of the second functional layer 30 satisfy the relationship:
  • N z ⁇ W ⁇ K IC , z is a constant, W is a preset value, K IC is the fracture toughness parameter of the second functional layer 30, and x is the preset thickness of the second functional layer 30, y is the thickness of the portion of the first functional layer 20 located in the step area, and a is the target slope angle of the first functional layer 20.
  • toughness is a physical concept, which represents the ability of a material to absorb energy during plastic deformation and fracture. The better the toughness, the less likely a brittle fracture will occur. Toughness is an important parameter in materials science and metallurgy. Toughness refers to the resistance of a material to breaking when subjected to the force that causes it to deform. It is defined as the ratio of the energy that the material can absorb to the volume before it breaks.
  • Fracture toughness is a measure of the ability to prevent macroscopic cracks from instability and growth, and is also a toughness parameter for materials to resist brittle failure. It has nothing to do with the size, shape and applied stress of the crack itself. It is an inherent characteristic of the material and only depends on the material itself, heat treatment and processing. Process related. Fracture toughness is usually expressed by the energy absorbed by the object before fracture or the work done by the outside world on the object, for example: the area under the stress-strain curve. Ductile materials have greater fracture toughness due to their large elongation at break, while brittle materials generally have lower fracture toughness.
  • Factors affecting the level of fracture toughness include external factors and internal factors; among them, external factors include the size of the sheet or component section, temperature and strain rate under service conditions, etc.
  • the fracture toughness of the material gradually increases with the increase of the size of the sheet or component section Decrease, and finally tend to a stable minimum value, that is, the plane strain fracture toughness K IC , which is a transformation process from a plane stress state to a plane strain state.
  • the relationship of fracture toughness with temperature is similar to that of impact toughness. With the decrease of temperature, the fracture toughness can have a sharply reduced temperature range. Below this temperature range, the fracture toughness tends to a lower plateau with a very low value. It doesn't change much if it is lowered.
  • n is the strain hardening index of the material at high temperature
  • E is the elastic modulus of the material at high temperature, in MPa
  • ⁇ S is the yield strength of the material at high temperature
  • MPa is the fracture at high temperature when uniaxially stretched Really strained.
  • strain rate on fracture toughness parameters is similar to that of temperature, and the effect of increasing strain rate and decreasing temperature is the same.
  • Internal factors include material composition and internal organization. As a combination of material composition and internal organizational factors, material strength is a macroscopic expression. From the point of view of mechanics rather than metallurgy, people always start from the strength change of the material to discuss the level of fracture toughness. As long as the strength of the material is known, the fracture toughness of the material can be roughly inferred.
  • Fracture toughness is measured in joules per cubic meter (J/m3) in the International System of Units, and pounds force per square inch in the British system.
  • the unit of toughness is MPa ⁇ m 1/2 .
  • the z in the above formula (1) is a constant, which can take a value between 1 and 1.1 (including the endpoint value), and the unit is: Mpa ⁇ -1 ⁇ m ⁇ -1/2; Tan(a) is the target slope angle The tangent function of a.
  • W is an empirical value related to the process method of forming the second functional layer, the specific interlayer structure, etc., and the value of W is between 0.4 and 2.2 (including the endpoint value).
  • the value range of the coefficient N is approximately between 0.9-1.1 (including the endpoint value); if the second functional layer 30 is an organic layer, N The value range of is roughly between 0.8-0.9 (including endpoint values).
  • the thickness of the portion of the first functional layer 20 located in the level difference region is the height of the step of the first functional layer 20 in the level difference region in a direction perpendicular to the substrate 10.
  • the second function is summarized by analyzing the material properties, formation process, thickness, and fracture toughness of the first functional layer 20 in the stepped area and the second functional layer 30 covering the stepped area.
  • the internal relationship between the thickness of the layer 30 and the slope angle formed by the first functional layer 20 in the step area, so that the first functional pattern 201 has the largest The slope angle allows the array substrate to be better used in thinner and high-resolution display products, and at the same time, it better improves the product yield of the array substrate and reduces the cost of raw materials.
  • the first functional layer 20 includes a first functional pattern 201, and the first functional pattern 201 forms a first step area 401 on the substrate 10;
  • the second functional layer 30 includes: a first functional film layer 301 and a second functional film layer 302; the first functional film layer 301 is disposed on the side of the first functional pattern 201 away from the substrate 10, The second functional film layer 302 is disposed on the side of the first functional film layer 301 away from the substrate 10; the first functional film layer 301 and the second functional film layer 302 both cover the first functional film layer 301 and the second functional film layer 302.
  • the fracture toughness parameters of the first functional film layer 301 and the second functional film layer 302 are approximately the same;
  • the thickness of the first functional film layer 301 is uniform, and in the direction perpendicular to the extension direction of the second functional film layer 302, the second functional film layer 302 The thickness is uniform;
  • the portion of the first functional graphic 201 located in the first step area 401 has a first target gradient angle a1, and the first target gradient angle a1 is the first functional film layer 301 and the second functional film layer 302 satisfies the maximum slope angle under the condition of the first preset thickness; the first preset thickness is that the first functional film layer 301 and the second functional film layer 302 meet their respective functional requirements and are in the first When none of the step regions 401 are broken, the thickness of the first functional film layer 301 and the thickness of the second functional film layer 302 are the sum of the thickness.
  • the specific structures of the first functional layer 20 and the second functional layer 30 are various.
  • the first functional layer 20 includes a first functional pattern 201, and the second functional layer 30 Including: a first functional film layer 301 disposed on the surface of the first functional pattern 201 away from the substrate 10, and a second functional film layer disposed on the surface of the first functional film 301 away from the substrate 10 302; wherein, the first functional pattern 201 may be a first gate metal pattern included in the first gate metal layer, and a first gate insulating layer 50 may be provided between the first gate metal pattern and the substrate 10
  • the first functional film layer 301 can be a second gate insulating layer
  • the second functional film layer 302 can be an interlayer insulating layer (ILD layer).
  • ILD layer interlayer insulating layer
  • Both the second gate insulating layer and the interlayer insulating layer can be formed by using silicon nitride or silicon oxide, or a combination of the two, that is, the second gate insulating layer and the interlayer insulating layer are formed by
  • the materials used are the same, and the manufacturing process is the same (for example, a plasma-enhanced chemical vapor deposition method), so the fracture toughness parameters of the first functional film layer 301 and the second functional film layer 302 are approximately the same.
  • the thickness of the first functional film 301 is uniform in the direction perpendicular to the extension direction of the first functional film 301, it is perpendicular to the second functional film 301 In the extending direction of the film layer 302, the thickness of the second functional film layer 302 is uniform. Therefore, the thickness of the first functional film layer 301 and the second functional film layer 302 may be each perpendicular to its own extending direction.
  • the thickness of the first functional film layer 301 and the second functional film layer 302 can be changed After adding the thicknesses of, it becomes the first preset thickness, that is, the value of x in the formula (1).
  • the height of the level difference formed by the first functional pattern 201 in the second level difference area 402 in the direction perpendicular to the substrate 10 is the y value in the formula (1).
  • the first target gradient angle a1 corresponding to the first functional graph 201 in the first step area 401 can be obtained; exemplary
  • the first functional pattern 201 is a first gate metal pattern
  • the first functional film layer 301 is a second gate insulating layer
  • the second functional film layer 302 is an interlayer insulating layer
  • pass the Formula (1) it can be calculated that the range of the first target slope angle a1 is between 40° and 45° (the end value can be taken).
  • the first functional film layer 301 and the second functional film layer covering the first step area 401 are formed 302, so that a thicker second functional layer 30 is formed on the first functional pattern 201.
  • the first functional film layer 301 and the second The thickness of the two functional film layers 302 is added together as the first preset thickness, and the first target slope angle a1 corresponding to the first functional graphic 201 can be determined based on the first preset thickness, so as to ensure that the second When the functional layer 30 does not break in the step area, the first functional pattern 201 has the largest slope angle, so that the array substrate can be better used in thinner and high-resolution display products, and at the same time better Improve the product yield of the array substrate and reduce the cost of raw materials.
  • the first functional layer 20 further includes a second functional graphic 202, and the second functional graphic 202 and the first functional graphic 201 are arranged in the same layer and the same material.
  • the second functional pattern 202 forms a second step area 402 on the substrate 10;
  • the first functional film layer 301 covers the second step area 402;
  • the portion of the second functional graphic 202 located in the second step area 402 has a second target gradient angle a2, and the second target gradient angle a2 is when the first functional film 301 satisfies the second preset thickness condition The maximum slope angle; the second preset thickness is when the first functional film 301 meets its own functional requirements and does not break in the second step area 402, the first functional film 301 Have the thickness
  • the second target slope angle a2 is smaller than the first target slope angle a1.
  • the first functional layer 20 may also include a second functional graphic 202, and the second functional graphic 202 and the first functional graphic 201 are set in the same layer and the same material, that is, the second functional graphic 202 and the first functional graphic 201 are set in the same layer and the same material.
  • the first functional pattern 201 can be formed at the same time through the same patterning process.
  • the first functional pattern 201 and the second functional pattern 202 are both the first gate metal pattern included in the first gate metal layer, and
  • the first functional graph 201 and the second functional graph 202 are independent of each other.
  • the first functional film layer 301 included in the second functional layer 30 can cover the second step area 402 formed by the second functional pattern 202, so that when calculating the second functional pattern 202 in the second When the second target gradient angle a2 of the level difference area 402, the first functional film layer 301 can correspond to the first functional film layer 301 when the first functional film layer 301 meets its own functional requirements and the second level difference area 402 does not break
  • the thickness of is used as the second preset thickness, that is, the value of x in the formula (1).
  • the height of the level difference formed by the second functional pattern 202 in the second level difference area 402 in the direction perpendicular to the substrate 10 is the y value in the formula (1).
  • the second target gradient angle a2 corresponding to the second functional graph 202 in the second step area 402 can be obtained; exemplary
  • the second functional pattern 202 is a first gate metal pattern and the first functional film layer 301 is a second gate insulating layer
  • the second target slope can be calculated by the formula (1)
  • the range of the angle a2 is between 26°-29° (endpoint values are acceptable).
  • the first functional film layer 301 covering the second stepped area 402 is thinner, it is smaller than the second functional layer 30 covering the first stepped area 401 (that is, the first functional layer 30).
  • the second functional pattern 202 has the largest slope angle while ensuring that the first functional film layer 301 meets its own functional requirements and that no fracture occurs in the second step area 402. Therefore, the array substrate can be better used in thinner and high-resolution display products, and at the same time, the product yield of the array substrate can be better improved and the cost of raw materials can be reduced.
  • the first functional layer 20 further includes a third functional pattern 203, and the third functional pattern 203 is located on a part of the first functional film layer 301 away from the substrate 10.
  • the third functional pattern 203 forms a third step area 403 on the substrate 10;
  • the second functional film layer 302 covers the third step area 403;
  • the portion of the third functional graphic 203 located in the third step area 403 has a third target gradient angle a3, and the third target gradient angle a3 is when the second functional film layer 302 satisfies the third preset thickness condition
  • the third preset thickness is that when the second functional film layer 302 meets its own functional requirements and does not break in the third step area 403, the second functional film layer 302 has thickness of;
  • the third target slope angle a3 is greater than the second target slope angle a2 and smaller than the first target slope angle a1.
  • the first functional layer 20 may further include a third functional pattern 203.
  • the third functional pattern 203 is a second gate metal pattern included in the second gate metal layer.
  • the third functional pattern 203 is located on the side of the first functional film layer 301 away from the substrate 10, and the third functional pattern 203 forms a third step area 403 on the substrate 10.
  • the The orthographic projection of the third step area 403 on the substrate 10 does not overlap with the orthographic projection of the first functional pattern 201 on the substrate 10, and is on the substrate 10 with the second functional pattern 202 The orthographic projections do not overlap.
  • the orthographic projection of the third functional graphic 203 on the substrate 10 and the orthographic projection of the second functional graphic 202 on the substrate 10 can be set to overlap, so that the second functional graphic 202 is overlapped with the orthographic projection of the second functional graphic 202 on the substrate 10.
  • the third functional pattern 203 can be formed as a capacitor structure.
  • the second functional film layer 302 included in the second functional layer 30 can cover the third step area 403 formed by the third functional pattern 203, so that when calculating the third functional pattern 203 in the third
  • the second functional film layer 302 can correspond to the second functional film layer 302 when the second functional film layer 302 meets its own functional requirements and the third level difference area 403 does not break.
  • the thickness of is used as the third preset thickness, that is, the value of x in the formula (1).
  • the height of the level difference formed by the third functional pattern 203 in the third level difference area 403 in the direction perpendicular to the substrate 10 is the y value in the formula (1).
  • the third target gradient angle a3 corresponding to the third functional graph 203 in the third step area 403 can be obtained; exemplary
  • the third functional pattern 203 is a second gate metal pattern and the second functional film layer 302 is an interlayer insulating layer
  • the third target gradient angle a3 can be calculated by the formula (1)
  • the range of is between 35°-39° (endpoint values are acceptable).
  • the thickness of the first functional film layer 301 covering the third level difference area 403 is greater than the thickness of the first functional film layer 301 covering the second level difference area 402, and is smaller than the thickness of the first functional film layer 301 covering the second level difference area 402.
  • the thickness of the second functional layer 30 (that is, the first functional film layer 301 and the second functional film layer 302) of the first step area 401 therefore, the calculated third target gradient angle a3 is greater than
  • the second target slope angle a2 is smaller than the first target slope angle a1.
  • the third functional pattern is made to have the largest slope angle under the condition that the second functional film layer meets its own functional requirements and does not break in the third step area, so that the array
  • the substrate can be better used in thinner and high-resolution display products, and at the same time, it can better improve the product yield of the array substrate and reduce the cost of raw materials.
  • the first functional layer 20 includes a fourth functional pattern 204, which is formed on the substrate 10 and arranged in a direction away from the substrate 10. At least two fourth-stage difference areas 404 of the cloth;
  • the second functional layer 30 includes a flat layer disposed on a side of the fourth functional pattern 204 away from the substrate 10, and the flat layer completely covers the fourth functional pattern 204;
  • the portion of the fourth functional graphic 204 located in each of the fourth step regions 404 has a corresponding fourth target slope angle a4, and the fourth target slope angle a4 is: the fourth target slope angle a4 in the flat layer
  • the corresponding maximum slope angle of the first part of the fourth step area 404 under the condition of meeting the fourth preset thickness; the fourth preset thickness means that the first part meets its own functional requirements and is not in the fourth step area 404
  • the first portion has the thinnest thickness in a direction perpendicular to the substrate 10.
  • the first functional layer 20 may further include a fourth functional pattern 204.
  • the fourth functional pattern 204 is a first source-drain metal pattern included in the first source-drain metal layer; or, the The fourth functional pattern 204 is a second source-drain metal pattern included in the second source-drain metal layer.
  • the fourth functional pattern 204 forms on the substrate 10 at least two fourth step regions 404 sequentially arranged in a direction away from the substrate 10; for example, in the at least two fourth step regions 404,
  • the fourth step area 404 closest to the substrate 10 is a step area formed by the edge portion of the fourth functional pattern 204 itself. Except for this step area, other fourth step areas 404 far from the substrate 10 are due to
  • the fourth functional pattern 204 covers the fourth level difference area 404 formed by the bottom level difference.
  • the second functional layer 30 also includes a flat layer disposed on the side of the fourth functional pattern 204 away from the substrate 10, and the flat layer can completely cover the fourth functional pattern 204, that is, it can cover all the fourth functional patterns 204.
  • the fourth step area 404 formed by the fourth functional pattern 204 because the function of the flat layer is to fill in the step below it, so that the surface of the flat layer away from the substrate 10 is flattened. In the direction of the substrate 10, the thickness of the flat layer is different in different regions, so when calculating the fourth target slope angle a4 located in the fourth difference region 404, the value of x in the formula (1) should be different Therefore, the part of the fourth functional graph 204 located in each of the fourth step regions 404 has a corresponding fourth target slope angle a4.
  • the fourth target gradient angle a4 corresponding to the fourth step area 404 is: the flat The maximum slope angle of the first part of the layer covering the fourth step area 404 under the condition of meeting the fourth preset thickness; the fourth preset thickness means that the first part meets its own functional requirements and is in the fourth step When the region 404 does not break, the first part has the thinnest thickness in the direction perpendicular to the substrate 10, that is, d1 in FIG. 2.
  • the thinnest thickness d1 of the first portion in the direction perpendicular to the base 10 may be used as the fourth preset thickness, That is, the value of x in the formula (1).
  • the height d4 of the step formed by the fourth functional pattern 204 in the fourth step area 404 in the direction perpendicular to the substrate 10 is the y value in the formula (1). Substituting the aforementioned x value, y value and the corresponding N value into the aforementioned formula (1), the fourth target gradient angle a4 corresponding to the fourth functional graph 204 in the fourth step area 404 can be obtained.
  • the fourth functional pattern 204 has the largest slope angle under the condition that the flat layer meets its own functional requirements and the fourth step area 404 does not break, so that the fourth functional pattern 204 has the largest slope angle, so that the array
  • the substrate can be better used in thinner and high-resolution display products, and at the same time, it can better improve the product yield of the array substrate and reduce the cost of raw materials.
  • the first functional layer 20 includes a first functional pattern 201, and the first functional pattern 201 forms a first step area 401 on the substrate 10;
  • the second functional layer 30 includes: a first functional film layer 301 arranged on the side of the first functional pattern 201 away from the substrate 10, and a first functional film layer 301 arranged on the first functional film layer 301 away from the substrate 10
  • the fourth functional pattern 204 is located on a side of the second functional film layer 302 away from the substrate 10, and the fourth functional pattern 204 covers the first step area 401.
  • the fourth functional pattern 204 is located on the side of the second functional film layer 302 away from the substrate 10, and the fourth functional pattern 204 covers the first One stage difference area 401, therefore, the fourth functional pattern 204 forms two fourth stage difference areas 404.
  • One fourth stage difference area 404 is located at the edge of the fourth functional pattern 204, and the other fourth stage difference area 404 is located in the fourth stage difference area 404.
  • the orthographic projection on the substrate 10 overlaps with the orthographic projection of the first step area 401 on the substrate 10.
  • the fourth functional pattern 204 when the fourth functional pattern 204 is a first source-drain metal pattern and the second functional layer 30 is a flat layer, the fourth functional pattern 204 can be calculated by the formula (1)
  • the range of the fourth target slope angle a4 corresponding to the edge portion of is between 60°-75° (the endpoint value can be taken).
  • the thickness of the flat layer is relatively thick, generally between 2um-4um, and due to the coating process, the reaction of the reaction solution (such as the developer) under a large slope angle will be affected by the metal slope angle, resulting in The reaction is insufficient, so when it is substituted into the formula (1), the value of N is smaller than that of the inorganic layer.
  • the second functional film layer 302 and the flat layer simultaneously cover the third step area 403, but since the material used for the second functional film layer 302 is generally an inorganic material, The material used for the flat layer is generally an organic material, and the manufacturing processes of the two are different, so that N in formula (1) is different.
  • the first flat layer uses a coating process
  • the second functional film layer 302 uses plasma. Volume-enhanced chemical vapor deposition method. Therefore, when calculating the third target slope angle a3 corresponding to the third step area 403, the second functional film layer 302 and the flat layer cannot be combined. The thickness is added and substituted into formula (1).
  • the flat layer includes a first flat layer PLN1 and a second flat layer PLN2, the first functional layer further includes another fourth functional pattern 204', and the other
  • the fourth functional pattern 204' is located on the side of the first flat layer PLN1 away from the substrate 10, and the other fourth functional pattern 204' forms another fourth step area 404' on the substrate 10.
  • the portion of the other fourth functional pattern 204' located in the other fourth step area 404' has another fourth target gradient angle a4', and the second flat layer PLN2 covers the other fourth functional pattern 204'.
  • the other fourth functional pattern 204' may be specifically a second source-drain metal pattern, because the underlying film structure covered by the first flat layer PLN1 may be in certain positions Not flat enough, so that the surface of the first flat layer PLN1 away from the substrate 10 has undulations, resulting in the other fourth functional pattern 204' formed on the side of the first flat layer PLN1 away from the substrate 10 A plurality of other fourth step regions 404' are formed (only one is shown in the figure).
  • the fourth functional pattern 204' is a second source-drain metal pattern
  • the second functional layer 30 is a second flat layer PLN2
  • the second functional layer 30 can be calculated by using the formula (1).
  • the range of the fourth target slope angle a4' corresponding to the edge part of the four-function graphic 204' is between 60° and 85° (the end value can be taken).
  • the first functional layer 20 includes a fifth functional pattern 205 and a sixth functional pattern 206 that are sequentially stacked in a direction away from the substrate 10;
  • the second functional layer 30 includes a second functional film layer 302 arranged between the fifth functional pattern 205 and the sixth functional pattern 206, and a second functional film layer 302 arranged on the sixth functional pattern 206 away from the substrate 10 One side of the flat layer PLN; wherein the second functional film layer 302 is provided with a first via hole, and the second functional film layer 302 forms a fifth step area 405 on the edge of the first via hole;
  • the sixth functional pattern 206 is coupled to the fifth functional pattern 205 through the first via hole, and the sixth functional pattern 206 covers the fifth step area 405, which corresponds to the fifth step area 405 The position of, forms the sixth step area 406;
  • the portion of the second functional film layer 302 located in the fifth step area 405 has a fifth target gradient angle a5;
  • the portion of the sixth functional graphic 206 located in the sixth step area 406 has a sixth target gradient angle a6, and the sixth target gradient angle a6 is: the sixth step area 406 in the flat layer
  • the two parts meet the maximum slope angle under the condition of the sixth preset thickness;
  • the sixth preset thickness is the thinnest thickness of the second part when it meets its own functional requirements and does not break in the sixth step area 406 ;
  • the gradient angle a5 of the second functional film layer 302 in the fifth step area 405 is approximately equal to the sixth target gradient angle a6.
  • the fifth function pattern 205 may be a second gate metal pattern, and a first gate metal pattern 60 may be provided between the fifth gate metal pattern and the substrate 10; the sixth function The pattern 206 may be a first source-drain metal pattern.
  • the second functional film layer 302 may include a second functional film layer 302 arranged between the fifth functional pattern 205 and the sixth functional pattern 206, and a second functional film layer 302 arranged on the sixth functional pattern 206 away from the A flat layer on one side of the substrate 10; the second functional film layer 302 can optionally be an interlayer insulating layer, the second functional film layer 302 is provided with a first via hole, and the second functional film layer 302 can A fifth step area 405 is formed on the edge of the first via hole.
  • the sixth functional pattern 206 is coupled to the fifth functional pattern 205 through the first via hole, so the sixth functional pattern 206 covers the edge of the first via hole, thereby covering the first via hole.
  • the fifth step area 405 is formed at the edge of the hole, and a sixth step area 406 is formed at a position corresponding to the fifth step area 405.
  • the sixth target gradient angle a6 corresponding to the sixth step area 406 is: the second part of the flat layer covering the sixth step area 406 satisfies the sixth preset The maximum slope angle under the thickness condition; the sixth preset thickness is the thinnest thickness of the second part when it meets its own functional requirements and does not break in the sixth step area 406, that is, d2 in FIG. 4 .
  • the thinnest thickness d2 of the second part in the direction perpendicular to the base 10 may be used as the sixth preset thickness , which is the value of x in the formula (1).
  • the height d6 of the level difference formed by the sixth functional pattern 206 in the sixth level difference area 406 in the direction perpendicular to the substrate 10 is the y value in the formula (1).
  • the sixth functional pattern 206 is the first source-drain metal pattern, because the metal has high fracture toughness, it is not easy to break at the via hole, and because the thickness of the flat layer is thick, the calculated sixth target The slope angle a6 is relatively large, and the range is about 60°-85° (including the endpoint value).
  • the sixth target gradient angle a6 is not formed by etching, but formed by covering the fifth step area 405, that is, the slope angle corresponding to the sixth functional pattern 206 in the sixth step area 406 is determined by The fifth functional graph 205 covered by it is determined by the slope angle corresponding to the fifth step area 405.
  • the sixth functional graph 206 corresponds to the slope angle of the sixth step area 406, and the fifth functional graph 205 is at the fifth step angle.
  • the gradient angle a5 corresponding to the area 405 is approximately the same.
  • the fifth functional graph 205 can be made at the gradient angle corresponding to the fifth step area 405 This angle value is such that the sixth functional pattern 206 subsequently formed can naturally have this angle value in the sixth step area 406.
  • the sixth functional pattern 206 is made to have the largest slope angle under the condition that the flat layer meets its own functional requirements and no fracture occurs in the sixth step area 406, so that the array substrate It can be better used in thinner and high-resolution display products, and at the same time, it can better improve the product yield of the array substrate and reduce the cost of raw materials.
  • the first functional layer 20 includes:
  • the orthographic projection of the step area 408 on the substrate 10 overlaps with the orthographic projection of the fourth portion 2084 on the substrate 10, and the orthographic projection of the ninth step area 409 on the substrate 10 overlaps with the orthographic projection of the ninth step area 409 on the substrate 10
  • the orthographic projections of the fifth part 2085 on the substrate 10 overlap;
  • the second functional layer 30 includes a second functional film layer 302 and a ninth functional pattern 209; wherein, the second functional film layer 302 is located between the seventh functional pattern 207 and the eighth functional pattern 208, The ninth functional pattern 209 is located on the side of the flat layer away from the substrate 10, and is coupled to the eighth functional pattern 208 through the second via hole; the ninth functional pattern 209 covers the The eighth step area 408 and the ninth step area 409; the ninth functional pattern 209 has a uniform thickness;
  • the portion of the flat layer located in the eighth step area 408 has an eighth target slope angle a8, and the eighth target slope angle a8 is: the ninth functional graphic 209 satisfies the maximum slope under the condition of the eighth preset thickness Angle; the eighth preset thickness is the thickness of the ninth functional figure 209 when it meets its own functional requirements and does not break in the eighth step area 408;
  • the portion of the flat layer located in the ninth step area 409 has a ninth target slope angle a9, and the ninth target slope angle a9 is: the ninth functional graphic 209 satisfies the maximum slope under the condition of the ninth preset thickness Angle;
  • the ninth preset thickness is the thickness of the ninth functional figure 209 when it meets its own functional requirements and does not break in the ninth step area 409.
  • the seventh functional pattern 207 may be a second gate metal pattern
  • the eighth functional pattern 208 may be a first source/drain metal pattern
  • the ninth functional pattern 209 may be an anode pattern
  • the second functional film layer 302 may optionally be an interlayer insulating layer.
  • the eighth functional graphic 208 includes a third portion 2083 covering the seventh step area 407, and covering the rest of the seventh functional graphic 207 except for the seventh step area 407.
  • the height is higher than the second height of the surface of the fifth portion 2085 away from the substrate 10
  • the surface of the third portion 2083 away from the substrate 10 includes an inclined surface in a direction perpendicular to the substrate 10
  • the third height of is between the first height and the second height.
  • the flat layer is located on the side of the eighth functional pattern 208 away from the substrate 10 and can completely cover the eighth functional pattern 208. Since different parts of the eighth functional pattern 208 have different heights, The thickness of the flat layer on different parts is different, that is, the thickness of the flat layer on the fourth part 2084 in the direction perpendicular to the substrate 10 is smaller than that of the flat layer on the fifth part 2085 in the vertical direction. The thickness in the direction of the substrate 10.
  • the second via is formed on the flat layer, and the orthographic projection of the second via on the substrate 10 is located inside the orthographic projection of the eighth functional pattern 208 on the substrate 10, for example sexually, the orthographic projection of the second via on the substrate 10 can be the same as the orthographic projection of the third portion 2083 on the substrate 10 and the orthographic projection of the fourth portion 2084 on the substrate 10 respectively.
  • the orthographic projection and the orthographic projection of the fifth portion 2085 on the substrate 10 overlap.
  • the flat layer forms an eighth step area 408 and a ninth step area 409 on the edge of the second via hole.
  • the orthographic projection of the eighth step area 408 on the substrate 10 is the same as the first
  • the orthographic projections of the four parts 2084 on the base 10 overlap, and the orthographic projections of the ninth step area 409 on the base 10 overlap with the orthographic projections of the fifth part 2085 on the base 10.
  • the ninth functional pattern 209 is located on the side of the flat layer away from the substrate 10, and can be coupled to the eighth functional pattern 208 through the second via; the ninth functional pattern 209 covers all The eighth level difference area 408 and the ninth level difference area 409; the orthographic projection of the contact area formed between the eighth functional pattern 208 and the ninth functional pattern 209 on the substrate 10, respectively The orthographic projection of the third portion 2083 on the substrate 10, the orthographic projection of the fourth portion 2084 on the substrate 10, and the orthographic projection of the fifth portion 2085 on the substrate 10 overlap.
  • the portion of the flat layer located in the eighth step area 408 has an eighth target slope angle a8, and the eighth target slope angle a8 is: the ninth functional graph 209 satisfies the eighth preset The maximum slope angle under the thickness condition; the eighth preset thickness is the thickness of the ninth functional figure 209 when it meets its own functional requirements and does not break in the eighth step area 408;
  • the eighth target gradient angle a8 corresponding to the eighth step area 408 is: the ninth functional graphic 209 satisfies the maximum gradient angle under the condition of the eighth preset thickness;
  • the eight preset thickness is the thickness of the ninth functional pattern 209 when it meets its own functional requirements and does not break in the eighth step area 408.
  • the thickness of the ninth functional pattern 209 is taken as the value of x in formula (1); the flat layer is formed in the eighth step area 408
  • the height d8 of the level difference in the direction perpendicular to the substrate 10 is used as the y value in the formula (1).
  • the eighth target gradient angle a8 corresponding to the eighth step area 408 of the flat layer can be obtained; for example, the first The value range of the eight target slope angle a8 is between 40°-50° (including the endpoint value).
  • the ninth target gradient angle a9 corresponding to the ninth step area 409 is: the ninth functional graphic 209 satisfies the maximum gradient angle under the condition of the ninth preset thickness; the ninth preset thickness is The thickness of the ninth functional pattern 209 when it meets its own functional requirements and the ninth step area 409 does not break.
  • the thickness of the ninth functional pattern 209 is taken as the value of x in formula (1); the flat layer is formed in the ninth step area 409
  • the height d9 of the level difference in the direction perpendicular to the substrate 10 is used as the y value in the formula (1).
  • the ninth target slope angle a9 corresponding to the ninth step difference area 409 of the flat layer can be obtained; for example, the first The value range of the nine target slope angle a9 is between 35°-45 (including the end point value).
  • the eighth target slope angle a8 is greater than the ninth target slope angle a9, and since d8 is smaller than d9, the ninth functional graphic 209 has a lower risk of fracture in the eighth step area 408.
  • the value range of the eighth target gradient angle a8 is positively correlated with d8
  • the value range of the ninth target gradient angle a9 is positively correlated with d9.
  • the ninth functional pattern 209 is guaranteed to meet its own functional requirements, and there is no breakage in the eighth step area 408 and the ninth step area 409, so that the flat layer is in place.
  • the edge of the second via hole has the largest slope angle, so that the array substrate can be better used in thinning and high-resolution display products, and at the same time, the product yield of the array substrate is better improved and the cost of raw materials is reduced.
  • the orthographic projection of the seventh functional pattern 207 on the substrate 10 and the orthographic projection of the eighth functional pattern 208 on the substrate 10 form a first overlap.
  • Area, the first overlapping area has a first size H1 along a first direction;
  • the portion of the eighth functional pattern 208 that is not located in the first overlapping area has a second size H2 along the first direction;
  • the ninth functional graphic 209 and the eighth functional graphic 208 form a first contact area.
  • the boundary of the first contact area (such as the position of point C) and the eighth functional graphic 208 The minimum distance between the first end (such as the position of point A) is the first distance L1, the boundary of the first contact area (such as the position of point D) and the second end of the eighth functional graphic 208 (such as B
  • the minimum distance between the point positions) is the second distance L2; the first end and the second end are opposite along the first direction, and the orthographic projection of the first end on the substrate 10 is the same as the
  • the seventh functional graphic 207 overlaps, and the orthographic projection of the second end on the substrate 10 does not overlap the seventh functional graphic 207;
  • the first absolute value corresponding to the difference between the first size H1 and the second size H2, and the second absolute value corresponding to the difference between the first distance L1 and the second distance L2 Directly proportional.
  • the first direction may optionally be: the shortest climbing direction F1 of the eighth functional graph 208 on the slope of the seventh step area 407 where the seventh functional graph 207 is located on the base 10
  • the direction after projection is as shown in Figure 7.
  • the first absolute value corresponding to the difference between the first size H1 and the second size H2, and the second absolute value corresponding to the difference between the first distance L1 and the second distance L2 It is proportional, that is
  • M ⁇ k
  • the maximum value of the absolute value of H1-H2 is the first width of the eighth functional graphic 208 along the first direction, and the maximum value of the absolute value of L1-L2 is the first width minus the first width
  • the second absolute value corresponding to the difference between the first distance L1 and the second distance L2 is different from the first distance L1 and the eighth function
  • the ratio of the first width (ie, H1+H2) of the pattern 208 along the first direction is proportional.
  • the eighth target gradient angle a8 when the first dimension H1 is greater than the first distance L1, the eighth target gradient angle a8 is greater than the ninth target gradient angle a9; or, the eighth target gradient angle a8 The difference between the ninth target gradient angle a9 and the ninth target gradient angle a9 is proportional to the first dimension H1.
  • the difference between the eighth target slope angle a8 and the ninth target slope angle a9 is smaller than the seventh target slope of the seventh functional graph 207 in the seventh step difference area 407 Angle a7; the seventh target slope angle a7 is the maximum slope angle under the condition that the second functional film 302 meets the seventh preset thickness; the seventh preset thickness is that the second functional film 302 is at A thickness that meets its own functional requirements and does not break in the seventh step area 407.
  • the thickness of the second functional film layer 302 can be substituted into x in formula (1), and the seventh functional pattern 207 can be placed in a direction perpendicular to the substrate 10
  • the above thickness is substituted into y in the formula (1), and then an appropriate value of N is selected to obtain the angle value of the seventh target slope angle a7.
  • the array substrate includes a capacitor structure
  • the first functional layer 20 includes a first electrode plate of the capacitor structure, and the first electrode plate forms an electrode plate step area on the substrate 10;
  • the second functional layer 30 includes a dielectric layer located on the side of the first electrode plate away from the substrate 10, the dielectric layer completely covers the first electrode plate; the first electrode plate is located on the electrode
  • the part of the plate-level difference area has a target slope angle of the plate, the target slope angle of the plate is the maximum slope angle under the condition that the dielectric layer meets the tenth preset thickness; the tenth preset thickness is that the dielectric layer is at A thickness that satisfies its own functional requirements and does not break in the region of the electrode plate section difference;
  • the second electrode plate of the capacitor structure is located on the side of the dielectric layer away from the substrate 10, and the orthographic projection of the second electrode plate on the substrate 10 is the same as that of the first electrode plate on the substrate 10.
  • the above orthographic projection forms a first overlapping area, and the second electrode plate covers the electrode plate level difference area.
  • the array substrate may include a plurality of capacitor structures, and these capacitor structures may be applied to the pixel driving circuit included in the array substrate, and may also be applied to the gate driving circuit in the array substrate, but are not limited to this.
  • the capacitance of the capacitor structure is not determined by Q or U.
  • the first plate of the capacitor structure may be a first gate metal pattern
  • the second plate of the capacitor structure may be a second gate metal pattern
  • the dielectric layer may be a second gate insulating layer, But it is not limited to this.
  • the first functional layer 20 is provided to include the first electrode plate of the capacitor structure, and the second functional layer 30 includes a dielectric layer located on the side of the first electrode plate away from the substrate 10.
  • the thickness of the dielectric layer can be taken as x in the formula (1), and the level difference formed by the first electrode plate
  • the height is substituted as y in the formula (1), K IC is substituted into the fracture toughness parameter of the dielectric layer, and W is substituted into the empirical value related to the process method of the dielectric layer and the specific interlayer structure.
  • the value of W is 0.4 ⁇ 2.2 (can include the endpoint value)
  • the value of z is between 1 ⁇ 1.1
  • the unit is Mpa ⁇ -1 ⁇ m ⁇ -1/2.
  • the thickness of the dielectric layer can be set to be uniform or uneven according to actual needs.
  • the thickness of the dielectric layer can be directly substituted into x.
  • the thickness of the dielectric layer is not uniform, the In the portion of the dielectric layer located in the region of the electrode plate level difference, the minimum thickness in the direction perpendicular to the substrate 10 is substituted for x.
  • the fact that the dielectric layer meets its own functional requirements means that the dielectric layer can ensure that the first electrode plate and the second electrode plate are insulated from each other, and/or the dielectric layer can satisfy the capacitance The capacitance of the structure is required.
  • the capacitance value of the capacitor structure is related to the facing area of the first electrode plate and the second electrode plate, and the facing area is the orthographic projection of the first electrode plate on the substrate and the The area of the first overlapping area formed by the orthographic projection of the second electrode plate on the substrate.
  • the part where the first electrode plate is located in the area of the electrode plate level difference described above has the target slope angle of the electrode plate, so that the first electrode plate can ensure that the dielectric layer meets its own functional requirements and is in the electrode plate.
  • the maximum slope angle is achieved without fracture in the step area.
  • the array substrate is arranged in the above structure, which increases the facing area between the first electrode plate and the second electrode plate, which helps to better improve the capacitance value of the capacitor structure.
  • the second electrode plate and the first electrode plate can be added.
  • the d3 length of the plate, or the size of the second plate in the direction perpendicular to the d3 length can also be increased.
  • the capacitor structure includes: a first capacitor structure, a second capacitor structure, and a third capacitor structure; the capacitance value of the first capacitor structure is greater than that of the second capacitor structure. The capacitance value of the capacitor structure, and/or the capacitance value of the first capacitor structure is greater than the capacitance value of the third capacitor structure;
  • the target plate slope angle b1 corresponding to the first plate C1a of the first capacitor structure is greater than the plate target slope angle b3 corresponding to the first plate C2a of the second capacitor structure; and/or, the first plate C1a of the second capacitor structure
  • the target plate slope angle b1 corresponding to the first plate C1a of a capacitor structure is greater than the target plate slope angle b5 corresponding to the first plate C3a of the third capacitor structure.
  • the specific number of capacitor structures included in the array substrate can be set according to actual needs.
  • the capacitor structure includes: a first capacitor structure, a second capacitor structure, and a third capacitor structure; the array substrate is used Taking an OLED display device as an example, when each pixel unit included in the display device includes adjacent red sub-pixels, green sub-pixels, and blue sub-pixels, the red sub-pixels may be configured to include the first Capacitor structure, the green sub-pixel includes the second capacitor structure, and the blue sub-pixel includes the third capacitor structure.
  • the first capacitor structure may also be located in the display area of the display device, and the second capacitor structure and the third capacitor structure may be located in the peripheral area of the display device; in this arrangement, It is also possible to further set the distance L3 between the adjacent first capacitor structure and the second capacitor structure to be greater than the distance L4 between the adjacent second capacitor structure and the third capacitor structure.
  • first electrode plate C1a of the first capacitor structure, the first electrode plate C2a of the second capacitor structure, and the first electrode plate C3a of the third capacitor structure can be arranged in the same layer and the same material, or Different layers are set with the same material; similarly, the second plate C1b of the first capacitor structure, the second plate C2b of the second capacitor, and the second plate C3b of the third capacitor structure can be in the same layer.
  • the material setting can also be set in different layers with the same material.
  • the first plate C1a of the first capacitor structure, the first plate C2a of the second capacitor structure, and the first plate C3a of the third capacitor structure all adopt the first plate C1a of the array substrate.
  • the second electrode plate C1b of the first capacitor structure is made of the second gate metal layer in the array substrate, and the second electrode plate C2b of the second capacitor and the second electrode plate C2b of the third capacitor structure
  • the electrode plate C3b is made of source and drain metal layers in the array substrate.
  • the capacitance value of the first capacitance structure is set to be greater than the capacitance value of the second capacitance structure, and/or the capacitance value of the first capacitance structure is larger than the capacitance value of the third capacitance structure, the following can be specifically adopted This is achieved by setting the target plate gradient angle b1 corresponding to the first plate C1a of the first capacitor structure to be greater than the target plate gradient angle b3 corresponding to the first plate C2a of the second capacitor structure; and/or It is achieved that the target plate slope angle b1 corresponding to the first plate C1a of the first capacitor structure is greater than the target plate slope angle b5 corresponding to the first plate C3a of the third capacitor structure.
  • the target plate slope angle b1 corresponding to the first plate C1a of the first capacitor structure is greater than the target plate slope angle b3 corresponding to the first plate C2a of the second capacitor structure
  • the area of the overlapping area formed by the orthographic projection of the first electrode plate C1a on the substrate and the orthographic projection of the second electrode plate C1b on the substrate in the first capacitor structure can be larger than that of the second
  • the area of the overlapping area formed by the orthographic projection of the first electrode plate C2a on the substrate and the orthographic projection of the second electrode plate C2b on the substrate in the capacitor structure thereby realizing the first capacitor structure
  • the capacitance value of is greater than the capacitance value of the second capacitor structure.
  • the thickness of the first dielectric layer 701 corresponding to the first capacitor structure in the direction perpendicular to the substrate 10 may be set to be smaller than that of the second dielectric layer 702 corresponding to the second capacitor structure.
  • the thickness in the direction perpendicular to the substrate 10; and/or, the thickness of the first dielectric layer 701 corresponding to the first capacitor structure in the direction perpendicular to the substrate 10 is smaller than the thickness corresponding to the third capacitor structure
  • the first dielectric layer corresponding to the first capacitor structure can be set
  • the thickness of 701 in the direction perpendicular to the substrate 10 is smaller than the thickness of the second dielectric layer 702 corresponding to the second capacitor structure in the direction perpendicular to the substrate 10, so as to realize the thickness of the first capacitor structure.
  • the capacitance value is greater than the capacitance value of the second capacitor structure; and/or, by setting the thickness of the first dielectric layer 701 corresponding to the first capacitor structure in the direction perpendicular to the substrate 10, it is less than that of the third capacitor structure.
  • the thickness of the third dielectric layer 703 corresponding to the capacitor structure in the direction perpendicular to the substrate 10 realizes that the capacitance value of the first capacitor structure is greater than the capacitance value of the third capacitor structure.
  • the thickness of the first dielectric layer 701 can be set to be less than the thickness of the second dielectric layer 702, and the thickness of the second dielectric layer 702 is less than that of the third dielectric layer 703. thickness. Further, the difference between the thickness of the second dielectric layer 702 and the thickness of the first dielectric layer 701 can be set to Between (can include endpoint values).
  • the portion of the second electrode plate C1b of the first capacitor structure that is located in the corresponding first overlapping area includes a slope angle b2 that is larger than the second electrode plate of the second capacitor structure
  • the slope angle b4 included in the portion of C2b located in the corresponding first overlapping area; and/or the slope angle b2 included in the portion located in the corresponding first overlapping area of the second plate C1b of the first capacitor structure Is greater than the slope angle b6 included in the portion of the second electrode plate C3b of the third capacitor structure that is located in the corresponding first overlapping area.
  • the greater the slope angle included in the portion of the second electrode plate that is located in the corresponding first overlapping area the larger the facing area formed between the second electrode plate and the corresponding first electrode plate,
  • the capacitance value of the capacitor structure formed by the second electrode plate is increased; therefore, by setting the slope angle b2 included in the portion of the second electrode plate C1b of the first capacitor structure that is located in the corresponding first overlap area, Greater than the slope angle b4 included in the portion of the second electrode plate C2b of the second capacitor structure that is located in the corresponding first overlapping area, can make the capacitance value of the first capacitor structure greater than the capacitance value of the second capacitor structure;
  • the portion of the second electrode plate C1b of the first capacitor structure that is located in the corresponding first overlapping area includes a slope angle b2 that is greater than that of the second electrode plate C3b of the third capacitor structure that is located at the corresponding first intersection.
  • the slope angle b6 included in the portion of the overlap region can make the capacitance value of the first
  • the target slope angle of the first electrode plate can be adjusted, the slope angle included in the part of the second electrode plate located in the corresponding first overlap area, and the first electrode plate
  • the thickness of the dielectric layer between and the second plate is used to adjust the capacitance of the capacitor structure.
  • the target plate gradient angle b1 corresponding to the first plate C1a in the first capacitor structure may be set between 30° and 55°, and the second plate C1b of the first capacitor structure is located in the corresponding
  • the portion of the first overlapping area includes a slope angle b2 between 35° and 85°, and the angle difference between the target slope angle b1 and the slope angle b2 of the electrode plate is 12° to 30°;
  • the target plate slope angle b3 corresponding to one plate C2a can be set between 28° and 52°;
  • the target plate slope angle b5 corresponding to the first plate C3a in the third capacitor structure can be set between 25° and 50° °between.
  • the target plate gradient angle b1 corresponding to the first plate C1a in the first capacitor structure may be set between 30° and 55°, and the second plate C1b of the first capacitor structure is located in the corresponding
  • the portion of the first overlapping area includes a slope angle b2 between 45° and 85°, and the target slope angle b1 of the electrode plate and the slope angle b2 differ by 15° to 30°;
  • the target plate gradient angle b3 corresponding to one plate C2a can be set between 20° and 45°, and the portion of the second plate C2b of the second capacitor structure that is located in the corresponding first overlap area includes the slope angle b4 is between 25° and 50°, and the angle difference between the target slope angle b3 and the slope angle b4 of the plate is 10°-25°;
  • the target slope angle b5 of the plate corresponding to the first plate C3a in the third capacitor structure It can be set between 15° and 30°, the portion of the second electrode plate C3b of the third capacitor structure located in the
  • the capacitance value of the first capacitor structure can be set to be 1.05 to 2.5 times the capacitance value of the second capacitor structure, and the capacitance value of the first capacitor structure is 1.10 to 3 times the capacitance value of the third capacitor structure.
  • the target plate slope angle of the first plate of the fourth capacitor structure C4 is greater than the plate target slope angle of the first plate of the fifth capacitor structure C5, Therefore, it is necessary to set the right end of the second plate of the fourth capacitor structure C4 to extend as far to the right as possible to prevent the second plate from falling off at the target slope angle of the first plate of the fourth capacitor structure C4 Peel off.
  • the target plate slope angle of the first plate of the sixth capacitor structure C6 is greater than the plate target slope angle of the first plate of the seventh capacitor structure C7, so it is necessary to set the sixth capacitor structure C6
  • the right end of the second electrode plate extends to the right as far as possible to prevent the second electrode plate from falling off and peeling off at the target slope angle of the first electrode plate of the sixth capacitor structure C6.
  • the right end of the second electrode plate provided with the fourth capacitor structure C4 extends as far to the right as possible, which can increase the area facing the second electrode plate and the first electrode plate of the fourth capacitor structure C4.
  • the right end of the second electrode plate provided with the sixth capacitor structure C6 extends to the right as much as possible, which can increase the area directly facing the second electrode plate and the first electrode plate of the sixth capacitor structure C6.
  • first electrode plate in each capacitor structure is located between the substrate and the second electrode plate, and the coverage of the second electrode plate to the first electrode plate in each capacitor structure can be set according to actual needs.
  • the coverage rate corresponding to the seven capacitor structure C7 is 100%, and the coverage rate corresponding to the sixth capacitor structure C6 is 40-60%.
  • the coverage ratio specifically refers to the ratio of the area covered by the second electrode plate of the first electrode plate to the entire area of the first electrode plate. It can be seen from FIG. 12 that the second electrode plate of the seventh capacitor structure C7 completely covers the first electrode plate, and the second electrode plate of the sixth capacitor structure C6 covers part of the first electrode plate.
  • the thickness of the dielectric layer 70 in the fourth capacitor structure C4 and the thickness of the dielectric layer 70 in the fifth capacitor structure C5 may be the same as the thickness of the dielectric layer 70 in the sixth capacitor structure C6. The thickness is not equal to the thickness of the dielectric layer 70 in the seventh capacitor structure C7.
  • the dielectric layer 70 located in the fourth capacitor structure C4 and the fifth capacitor structure C5 may include a second gate insulating layer and an interlayer insulating layer;
  • the dielectric layer 70 in the seven-capacitor structure C7 may include a second gate insulating layer.
  • the thickness of the first gate metal pattern and the thickness of the second gate metal pattern may both be greater than the thickness of the first source-drain metal pattern and the thickness of the second source-drain metal pattern, or, The thickness of the first gate metal pattern and the second gate metal pattern may both be smaller than the thickness of the first source-drain metal pattern and the thickness of the second source-drain metal pattern.
  • the slope angles corresponding to the first gate metal pattern and the second gate metal pattern may both be greater than the slope angles of the first source-drain metal pattern and the slope angle corresponding to the second source-drain metal pattern, or the first gate metal pattern and The slope angle corresponding to the second gate metal pattern may both be smaller than the slope angle of the first source-drain metal pattern and the slope angle corresponding to the second source-drain metal pattern.
  • the first functional layer 20 includes a composite metal pattern, and the composite metal pattern includes first metal sub-patterns stacked in sequence along a direction away from the substrate 10. 213, a second metal sub-pattern 212 and a third metal sub-pattern 211, the first metal sub-pattern 213 and the third metal sub-pattern 211 are made of the same material; when the first functional layer 20 is formed by etching, The target slope angle of the first functional layer 20 is inversely proportional to the etching rate of the third metal sub-pattern 211.
  • the material of the metal layer is different, which will cause the slope angle of the metal layer to be different under the same etching process.
  • the first metal sub-pattern 213 and the third metal sub-pattern 211 Using Ti the second metal sub-pattern 212 uses Al as an example, that is, the composite metal pattern is formed as a Ti/Al/Ti composite metal film layer.
  • Ti/Al/Ti composite metal pattern is wet-etched At this time, due to the slower corrosion rate of Ti, Ti will consume more etching solution, so that the concentration of the etching solution that Al comes into contact with is lower, and the etching rate is also slower, resulting in the etching of Ti/Al/Ti metal patterns.
  • the eroded slope angle is relatively large (such as a10), generally greater than 50 degrees.
  • the thickness of the second functional layer 30 (such as the second functional film layer 302) deposited on the Ti/Al/Ti metal pattern needs to be thicker, so that Tan(a)-1 ⁇
  • process parameters such as the concentration of the etching solution can be adjusted to ensure that the gradient angle of the composite metal pattern meets the requirements. It is worth noting that in addition to using Ti/Al/Ti composite metal patterns for the composite metal patterns, Mo/Al/Mo composite metal patterns can also be used for the composite metal patterns, but it is not limited to this.
  • the composite metal pattern is formed as Mn/ Cu/Mn composite metal film layer
  • Mn will consume less etching solution, making the etching that Cu touches
  • concentration of the etching solution the faster the etching rate, resulting in a smaller etching slope angle of the Mn/Cu/Mn metal pattern (such as a11), which is generally less than 50 degrees.
  • the thickness of the second functional layer 30 (such as the second functional film layer 302) deposited on the Mn/Cu/Mn metal pattern needs to be thin, so that Tan(a)-1 ⁇ N(xy)/y ⁇ Tan(a)+1 formula N decreases, generally the lower limit is 0.8.
  • process parameters such as the concentration of the etching solution can be adjusted to ensure that the gradient angle of the composite metal pattern meets the requirements.
  • the composite metal pattern can also be a Mo/Cu/Mo composite metal pattern, but it is not limited to this.
  • the desired target slope angle can be achieved through the selection of materials and the control of the etching process.
  • the embodiments of the present disclosure also provide a display device, including the array substrate provided in the above-mentioned embodiments.
  • the portion of the first functional layer 20 located in the step area has a target slope angle, and the target slope angle is when the second functional layer 30 satisfies the preset thickness condition
  • the maximum slope angle; the preset thickness is the thickness at which the second functional layer 30 meets its own functional requirements and does not break in the step area; so that the array substrate realizes the first While the functional layer 20 has the largest slope angle, it is ensured that the second functional layer 30 has the minimum thickness that meets its own functional requirements and does not break in the step area.
  • the array substrate provided in the above embodiment is Under the condition of ensuring that the functional layer does not break, the largest slope angle and the thinnest second functional layer 30 are realized, so that the array substrate can be better used in thinner and high-resolution display products, and at the same time better Improve the product yield of the array substrate and reduce the cost of raw materials.
  • the display device provided by the embodiment of the present disclosure includes the array substrate provided by the above-mentioned embodiment, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and so on.
  • the embodiment of the present disclosure also provides a manufacturing method of an array substrate for manufacturing the array substrate provided in the above implementation, and the manufacturing method includes:
  • a first functional layer 20 is formed on the substrate 10, the first functional layer 20 forms a stepped area on the substrate 10, and a portion of the first functional layer 20 located in the stepped area has a target slope angle;
  • a second functional layer 30 is formed on the side of the first functional layer 20 away from the substrate 10, and the second functional layer 30 covers the step area;
  • the target slope angle is such that the second functional layer 30 satisfies The maximum slope angle under a preset thickness condition;
  • the preset thickness is the thickness at which the second functional layer 30 meets its own functional requirements and does not break in the step area;
  • the target slope angle of the first functional layer and the preset thickness of the second functional layer satisfy the relationship:
  • N z ⁇ W ⁇ K IC , z is a constant, W is a preset value, K IC is the fracture toughness parameter of the second functional layer, x is the preset thickness of the second functional layer, and y is The thickness of the part of the first functional layer located in the step area, and a is the target slope angle of the first functional layer.
  • a low-temperature polysilicon thin film transistor (Low Temperature Poly-silicon Thin Film Transistor, LTPS TFT) array substrate is shown, and the array substrate may include: a base 10, a light-shielding layer LS, and a buffer layer 80 , Active layer 82, gate 81, gate insulating layer GI, interlayer insulating layer ILD, flat layer PLN, input electrode 85, output electrode 86, cathode layer 84, anode 83 and LDD lightly doped region 87; active
  • the layer can be made of P-Si.
  • the figure shows that the data signal Vdata is transmitted to the anode via the thin film transistor.
  • the first mask to make the light-shielding layer LS the specific steps include: first pre-cleaning the substrate 10, and then pre-compressing the substrate at a high temperature to prevent the substrate 10 (optionally a glass substrate) from shrinking due to high-temperature processes in the subsequent process.
  • a light-shielding material layer is deposited on the substrate, and a photoresist layer is made on the surface of the light-shielding material layer away from the substrate, and then the photoresist layer is exposed and developed, and the remaining The photoresist layer of is a mask, and the light-shielding material layer is etched using a wet etching process, and finally the remaining photoresist layer is stripped to form the light-shielding layer LS.
  • the second mask is used to fabricate the active layer 82, the specific steps include: cleaning process (D/C Clean), then multi-dep process (multi-dep), followed by dehydrogenation process (dehydrogen), hydrofluoric acid cleaning Process (D/C HF), excimer laser annealing process (ELA), and then form a photoresist layer on the surface of the polysilicon.
  • the remaining photoresist is used as a mask for the polysilicon Dry etching is performed, and the remaining photoresist layer is finally stripped, and then threshold voltage doping is performed to adjust the eigenstate of the channel region to adjust the Vth voltage (ie Vth doping), and the hydrofluoric acid cleaning process Finally, the gate insulating layer is formed by chemical vapor deposition.
  • the third mask and the fourth mask are used to make two gates 81, one of the gates 81 (corresponding to PMOS) is formed in the third mask, which specifically includes: performing a cleaning process, and then performing a sputtering process of Mo metal , Forming a Mo film, and then performing a patterning process on the Mo film.
  • the patterning process includes: photoresist layer formation, exposure, development, stripping, etc., and finally positive ion doping (P+doping) to form a P-gate;
  • a gate 81 (corresponding to NMOS) in the fourth mask specifically includes: continue the patterning process, and at the end perform negative ion doping (N+doping), ashing and dry etching processes, as well as light doping and ashing , Stripping and other processes to form N-gate.
  • the fifth mask is used to fabricate the contact layer.
  • the specific steps include: firstly perform a cleaning process, then use chemical vapor deposition to form the interlayer insulating layer ILD, then perform pre-cleaning, and then perform activation, hydrogen, and source/drain layers. S/D photo, dry etching, stripping and other processes;
  • the sixth mask is used to fabricate the input electrode 85 and the output electrode 86.
  • the specific steps include: etching (Etch), sputtering to form a Ti/Al/Ti composite metal layer, and then performing a patterning process on the composite metal layer, which in turn includes : The photoresist layer formation, exposure, development, dry etching process and the process of stripping the remaining photoresist, and finally annealing (Anneal).
  • the seventh mask is used to make a via hole for connecting the anode 83 and the output electrode 86.
  • the specific steps include: forming a flat layer PLN, which can be formed by a coating process using acrylic resin, and then forming an exposed output electrode on the PLN using a patterning process 86 through holes, and finally undergo a curing process.
  • the eighth mask is used to fabricate the cathode layer 84.
  • the specific steps include: a descum process, then a cleaning process, and then a sputtering process is used to form an indium tin oxide (ITO) film layer, and a patterning process is performed on the ITO film layer.
  • the patterning process includes: forming a photoresist layer, exposing, developing, wet etching and stripping the remaining photoresist layer, and finally forming the cathode layer 84.
  • the ninth mask is used to fabricate the passivation layer PVX.
  • the specific steps include: first performing a cleaning process, then forming a passivation layer by chemical vapor deposition, and then performing a patterning process on the passivation layer.
  • the process specifically includes: forming a photoresist layer , Exposure, development, dry etching, and finally the remaining photoresist layer is removed, and finally a passivation layer PVX with a via hole capable of exposing the output electrode 86 is formed.
  • the tenth mask is used to fabricate the anode 83.
  • the specific steps include: first performing a cleaning process, then sputtering to form an indium tin oxide (ITO) film layer, and performing a patterning process on the ITO film layer, which in turn includes: forming a photoresist layer , Exposure, development, ashing process, wet etching and stripping of the remaining photoresist layer process, and then annealing (Anneal), and finally the anode 83 is formed.
  • ITO indium tin oxide
  • the array substrate After the manufacture of the array substrate is completed, the array substrate can be tested, and after the test has no problems, the array substrate can be shipped.
  • OLED Organic Light-Emitting Diode
  • a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, PECVD) is first used to sequentially form a first buffer layer 11 and a second buffer layer 12 on the substrate 10.
  • the first buffer layer 11 can be made of SiNx material, the thickness is
  • the second buffer layer 12 can be made of SiOx material and has a thickness of
  • the steps of making the active layer perform initial clean work, and then use the PECVD method to deposit amorphous silicon on the surface of the second buffer layer 12 away from the substrate (a -Si) material to form the active film 13, and then perform pre-cleaning work, followed by excimer laser annealing (ELA) process and photolithography process to form an active layer 82 made of polysilicon (Poly-Si), the active layer 82
  • ELA excimer laser annealing
  • a Mo metal sputtering process is performed to form a Mo film, and then a patterning process is performed on the Mo film.
  • the patterning process includes: photoresist layer formation, exposure, development, stripping, etc., and finally ion doping
  • a first gate metal pattern 13 is formed, and the thickness of the first gate metal pattern 13 is
  • the Mo metal sputtering process is performed to form the Mo film, and then the Mo film is patterned.
  • the patterning process includes: photoresist layer formation, exposure, development, stripping, etc., and finally ion doping A second gate metal pattern 14 and a via hole penetrating through the second gate metal pattern 14 are formed, and the thickness of the second gate metal pattern 14 is
  • a photolithography process is used to form via holes penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD, and part of the first gate insulating layer
  • the gate metal pattern 13 is exposed.
  • a Ti/Al/Ti metal sputtering process is performed to form a stacked Ti/Al/Ti film, where the thickness of the Ti film is The thickness of the Al film is A patterning process is performed on the Ti/Al/Ti film to form a source and drain metal pattern 15 in the via hole.
  • the flat layer PLN continues to be made of organic materials, and the thickness of the flat layer PLN is The planar layer is patterned to form via holes exposing the source and drain metal patterns 15.
  • the ITO/Ag/ITO metal sputtering process is performed to form a laminated ITO/Ag/ITO film, where the thickness of ITO is The thickness of Ag is A patterning process is performed on the ITO/Ag/ITO film to form an anode pattern 15 located in the via hole.
  • the pixel defining layer PDL continues to be made of organic materials, and the thickness of the pixel defining layer PDL is A patterning process is performed on the pixel defining layer PDL to form a pixel opening capable of exposing a part of the anode pattern 15.
  • the portion of the first functional layer 20 located in the step area has a target slope angle, and the target slope angle is such that the second functional layer 30 satisfies The maximum slope angle under the preset thickness condition; the preset thickness is the thickness at which the second functional layer 30 meets its own functional requirements and does not break in the step area; so that the array substrate is While the first functional layer 20 has the largest slope angle, it is ensured that the second functional layer 30 has the minimum thickness that meets its own functional requirements and does not break in the step area. Therefore, the present invention is adopted.
  • the array substrate manufactured by the manufacturing method provided by the disclosed embodiments realizes the largest slope angle and the thinnest second functional layer 30 while ensuring that the functional layer does not break, so that the array substrate can be better applied to thinning And in high-resolution display products, at the same time, it can better improve the product yield of the array substrate and reduce the cost of raw materials.

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Abstract

本公开提供一种阵列基板及其制作方法、显示装置，所述阵列基板包括：基底，以及层叠设置在所述基底上的第一功能层和第二功能层；第一功能层在基底上形成段差区域，第二功能层覆盖段差区域；第一功能层位于段差区域的部分具有目标坡度角，目标坡度角为第二功能层满足预设厚度条件下的最大坡度角；预设厚度为第二功能层在满足其自身功能需求且在段差区域不会发生断裂的厚度。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2020年4月24日在中国提交的中国专利申请号No.202010330332.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
随着显示技术的不断发展，显示产品的种类越来越多，目前常用的显示产品包括：液晶显示(Liquid Crystal Display，LCD)产品、有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品等，这些显示产品中均包括阵列基板，阵列基板上形成有用于为显示产品的显示提供驱动信号的电路结构。
所述电路结构中一般包括薄膜晶体管、电容、电极结构和信号线等，薄膜晶体管、电容、电极结构和信号线中包括的功能层中至少部分为图形化的功能图形，这些功能图形会在阵列基板中产生段差区域，这样就使得阵列基板中覆盖段差区域的功能层需要跨越段差区域的台阶，从而导致该功能层存在容易在台阶处断裂的风险。
相关技术中为了避免该功能层在台阶处断裂，一般会增加该功能层的厚度，但是这种处理方式不利于阵列基板在薄型化显示产品中的应用。
发明内容
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种阵列基板，包括：基底，以及层叠设置在所述基底上的第一功能层和第二功能层；所述第一功能层在所述基底上形成段差区域，所述第二功能层覆盖所述段差区域；
所述第一功能层位于所述段差区域的部分具有目标坡度角，所述目标坡度角为所述第二功能层满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层在满足其自身功能需求、且在所述段差区域不会发生断裂的厚度。
可选的，所述第一功能层的所述目标坡度角和所述第二功能层的所述预设厚度满足关系式：
Tan(a)-1≤N(x-y)/y≤Tan(a)+1；
其中，N＝z×W×K IC，z为常数，W为预设值，K IC为所述第二功能层的断裂韧性参数，x为所述第二功能层的预设厚度，y为所述第一功能层位于所述段差区域的部分的厚度，a为所述第一功能层的所述目标坡度角。
可选的，所述第一功能层包括第一功能图形，所述第一功能图形在所述基底上形成第一段差区域；
所述第二功能层包括：第一功能膜层和第二功能膜层；所述第一功能膜层，设置于所述第一功能图形远离所述基底的一侧，所述第二功能膜层，设置于所述第一功能膜层远离所述基底的一侧；所述第一功能膜层和所述第二功能膜层均覆盖所述第一段差区域，所述第一功能膜层和所述第二功能膜层的断裂韧性参数大致相同；
所述第一功能膜层的厚度均匀，所述第二功能膜层的厚度均匀；
所述第一功能图形位于所述第一段差区域的部分具有第一目标坡度角，所述第一目标坡度角为所述第一功能膜层和所述第二功能膜层满足第一预设厚度条件下的最大坡度角；所述第一预设厚度为所述第一功能膜层和所述第二功能膜层在满足各自功能需求、且在所述第一段差区域均不发生断裂时，所述第一功能膜层具有的厚度与所述第二功能膜层具有的厚度之和。
可选的，所述第一功能层还包括第二功能图形，所述第二功能图形与所述第一功能图形同层同材料设置，所述第二功能图形在所述基底上形成第二段差区域；
所述第一功能膜层覆盖所述第二段差区域；
所述第二功能图形位于所述第二段差区域的部分具有第二目标坡度角，所述第二目标坡度角为所述第一功能膜层满足第二预设厚度条件下的最大坡 度角；所述第二预设厚度为所述第一功能膜层在满足其自身功能需求、且在所述第二段差区域不发生断裂的厚度；
所述第二目标坡度角小于所述第一目标坡度角。
可选的，所述第一功能层还包括第三功能图形，所述第三功能图形位于所述第一功能膜层远离所述基底的一侧，所述第三功能图形在所述基底上形成第三段差区域；
所述第二功能膜层覆盖所述第三段差区域；
所述第三功能图形位于所述第三段差区域的部分具有第三目标坡度角，所述第三目标坡度角为所述第二功能膜层满足第三预设厚度条件下的最大坡度角；所述第三预设厚度为所述第二功能膜层在满足其自身功能需求、且在所述第三段差区域不发生断裂的厚度；
所述第三目标坡度角大于所述第二目标坡度角，小于所述第一目标坡度角。
可选的，所述第一功能层包括第四功能图形，所述第四功能图形在所述基底上形成沿远离所述基底的方向依次排布的至少两个第四段差区域；
所述第二功能层包括设置于所述第四功能图形远离所述基底的一侧的平坦层，所述平坦层完全覆盖所述第四功能图形；
所述第四功能图形位于各所述第四段差区域的部分具有对应的第四目标坡度角，该第四目标坡度角为：所述平坦层中位于该第四目标坡度角对应的第四段差区域的第一部分在满足第四预设厚度条件下的最大坡度角；该第四预设厚度为所述第一部分在满足其自身功能需求、且在该第四段差区域不发生断裂的最薄厚度。
可选的，所述第一功能层包括第一功能图形，所述第一功能图形在所述基底上形成第一段差区域；
所述第二功能层包括：第一功能膜层和第二功能膜层；所述第一功能膜层，设置于所述第一功能图形远离所述基底的一侧，所述第二功能膜层，设置于所述第一功能膜层远离所述基底的一侧；所述第一功能膜层和所述第二功能膜层均覆盖所述第一段差区域；
所述第四功能图形位于所述第二功能膜层远离所述基底的一侧，所述第 四功能图形覆盖所述第一段差区域。
可选的，所述平坦层包括第一平坦层和第二平坦层，所述第一功能层还包括另一第四功能图形，所述另一第四功能图形位于所述第一平坦层远离所述基底的一侧，且所述另一第四功能图形在所述基底上形成另一第四段差区域，所述另一第四功能图形位于所述另一第四段差区域的部分具有另一第四目标坡度角，所述第二平坦层覆盖所述另一第四功能图形。
可选的，所述第一功能层包括沿远离所述基底的方向依次层叠设置的第五功能图形和第六功能图形；
所述第二功能层包括设置于所述第五功能图形和所述第六功能图形之间的第二功能膜层，以及设置于所述第六功能图形远离所述基底的一侧的平坦层；其中，所述第二功能膜层上设置有第一过孔，所述第二功能膜层在所述第一过孔的边缘形成第五段差区域；
所述第二功能膜层位于第五段差区域的部分具有第五目标坡度角；
所述第六功能图形通过所述第一过孔与所述第五功能图形耦接，所述第六功能图形覆盖所述第五段差区域，在所述第五段差区域对应的位置形成第六段差区域；
所述第六功能图形位于所述第六段差区域的部分具有第六目标坡度角，所述第六目标坡度角为：所述平坦层中位于所述第六段差区域的第二部分满足第六预设厚度条件下的最大坡度角；该第六预设厚度为所述第二部分在满足其自身功能需求、且在所述第六段差区域不发生断裂的最薄厚度；
所述第五目标坡度角，与所述第六目标坡度角大致相等。
可选的，所述第一功能层包括：
设置于所述基底上的第七功能图形，所述第七功能图形在所述基底上形成第七段差区域；
设置于所述第七功能图形远离所述基底的一侧的第八功能图形，所述第八功能图形包括：覆盖所述第七段差区域的第三部分，覆盖所述第七功能图形除位于所述第七段差区域之外的其余部分的第四部分，以及未覆盖所述第七功能图形的第五部分；
设置于所述第八功能图形远离所述基底的一侧的平坦层，所述平坦层上 设置有第二过孔，所述第二过孔在所述基底上的正投影位于所述第八功能图形在所述基底上的正投影的内部，所述平坦层在所述第二过孔的边缘形成第八段差区域和第九段差区域，所述第八段差区域在所述基底上的正投影与所述第四部分在所述基底上的正投影交叠，所述第九段差区域在所述基底上的正投影与所述第五部分在所述基底上的正投影交叠；
所述第二功能层包括第二功能膜层和第九功能图形；其中，所述第二功能膜层位于所述第七功能图形和所述第八功能图形之间，所述第九功能图形位于所述平坦层远离所述基底的一侧，且通过所述第二过孔与所述第八功能图形耦接；所述第九功能图形覆盖所述第八段差区域和所述第九段差区域；所述第九功能图形厚度均匀；
所述平坦层位于所述第八段差区域的部分具有第八目标坡度角，所述第八目标坡度角为：所述第九功能图形满足第八预设厚度条件下的最大坡度角；该第八预设厚度为所述第九功能图形在满足其自身功能需求且在所述第八段差区域不发生断裂时的厚度；
所述平坦层位于所述第九段差区域的部分具有第九目标坡度角，所述第九目标坡度角为：所述第九功能图形满足第九预设厚度条件下的最大坡度角；该第九预设厚度为所述第九功能图形在满足其自身功能需求、且在所述第九段差区域不发生断裂时的厚度。
可选的，所述第七功能图形在所述基底上的正投影与所述第八功能图形在所述基底上的正投影形成第一交叠区域，所述第一交叠区域沿第一方向具有第一尺寸；
所述第八功能图形中没有位于所述第一交叠区域的部分沿所述第一方向具有第二尺寸；所述第九功能图形与所述第八功能图形形成第一接触区域，沿所述第一方向，所述第一接触区域的边界与所述第八功能图形的第一端之间的最小距离为第一间距，所述第一接触区域的边界与所述第八功能图形的第二端之间的最小距离为第二间距；所述第一端与所述第二端沿所述第一方向相对，所述第一端在所述基底上的正投影与所述第七功能图形交叠，所述第二端在所述基底上的正投影与所述第七功能图形不交叠；
所述第一尺寸与所述第二尺寸之间的差值对应的第一绝对值，与所述第 一间距与所述第二间距之间的差值对应的第二绝对值成正比。
可选的，所述第一间距与所述第二间距之间的差值对应的第二绝对值，与所述第一间距与所述第八功能图形沿所述第一方向上的第一宽度的比值成正比。
可选的，当所述第一尺寸大于所述第一间距时，所述第八目标坡度角大于所述第九目标坡度角；或者，
所述第八目标坡度角与所述第九目标坡度角之间的差值，与所述第一尺寸成正比。
可选的，所述第八目标坡度角与所述第九目标坡度角之间的差值小于所述第七功能图形在所述第七段差区域具有的第七目标坡度角；
所述第七目标坡度角为所述第二功能膜层满足第七预设厚度条件下的最大坡度角；所述第七预设厚度为所述第二功能膜层在满足其自身功能需求、且在所述第七段差区域不会发生断裂的厚度。
可选的，所述阵列基板包括电容结构；
所述第一功能层包括所述电容结构的第一极板，所述第一极板在所述基底上形成极板段差区域；
所述第二功能层包括位于所述第一极板远离所述基底的一侧的介质层，所述介质层完全覆盖所述第一极板；所述第一极板位于所述极板段差区域的部分具有极板目标坡度角，所述极板目标坡度角为所述介质层满足第十预设厚度条件下的最大坡度角；所述第十预设厚度为所述介质层在满足其自身功能需求、且在所述极板段差区域不会发生断裂的厚度；
所述电容结构的第二极板位于所述介质层远离所述基底的一侧，所述第二极板在所述基底上的正投影与所述第一极板在所述基底上的正投影形成第一交叠区域，所述第二极板覆盖所述极板段差区域。
可选的，所述电容结构包括：第一电容结构、第二电容结构和第三电容结构；所述第一电容结构的容值大于所述第二电容结构的容值，和/或所述第一电容结构的容值大于所述第三电容结构的容值；
所述第一电容结构的第一极板对应的极板目标坡度角，大于所述第二电容结构的第一极板对应的极板目标坡度角；和/或，所述第一电容结构的第一 极板对应的极板目标坡度角，大于所述第三电容结构的第一极板对应的极板目标坡度角。
可选的，所述第一电容结构对应的第一介质层的厚度，小于所述第二电容结构对应的第二介质层的厚度；和/或，
所述第一电容结构对应的第一介质层的厚度，小于所述第三电容结构对应的第三介质层的厚度。
可选的，所述第一电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角，大于所述第二电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角；和/或，
所述第一电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角，大于所述第三电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角。
可选的，所述第一功能层包括复合金属图形，所述复合金属图形包括沿远离所述基底的方向依次层叠设置的第一金属子图形、第二金属子图形和第三金属子图形，所述第一金属子图形与所述第三金属子图形的材料相同；
在刻蚀形成所述第一功能层时，所述第一功能层具有的目标坡度角与所述第三金属子图形的刻蚀速率成反比。
基于上述阵列基板的技术方案，本公开的第二方面提供一种显示装置，包括上述阵列基板。
基于上述阵列基板的技术方案，本公开的第三方面提供一种阵列基板的制作方法，用于制作上述阵列基板，所述制作方法包括：
在基底上形成第一功能层，所述第一功能层在所述基底上形成段差区域，所述第一功能层位于所述段差区域的部分具有目标坡度角；
在所述第一功能层远离所述基底的一侧形成第二功能层，所述第二功能层覆盖所述段差区域；所述目标坡度角为所述第二功能层满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层在满足其自身功能需求、且在所述段差区域不会发生断裂的厚度；
所述第一功能层的所述目标坡度角和所述第二功能层的预设厚度满足关系式：
Tan(a)-1≤N(x-y)/y≤Tan(a)+1；
其中，N＝z×W×K IC，z为常数，W为预设值，K IC为所述第二功能层的断裂韧性参数，x为所述第二功能层的预设厚度，y为所述第一功能层位于所述段差区域的部分的厚度，a为所述第一功能层的所述目标坡度角。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的阵列基板的第一截面示意图；
图2为本公开实施例提供的阵列基板的第二截面示意图；
图3为本公开实施例提供的阵列基板的第三截面示意图；
图4为本公开实施例提供的阵列基板的第四截面示意图；
图5为本公开实施例提供的阵列基板的第五截面示意图；
图6为本公开实施例提供的阵列基板的第六截面示意图；
图7为本公开实施例提供的阵列基板的第七截面示意图；
图8为本公开实施例提供的第一电容结构的截面示意图；
图9为本公开实施例提供的第二电容结构的截面示意图；
图10为本公开实施例提供的第三电容结构的截面示意图；
图11为本公开实施例提供的显示区域和周边区域的电容结构的第一示意图；
图12为本公开实施例提供的显示区域和周边区域的电容结构的第二示意图；
图13为本公开实施例提供的第一功能层的第一截面示意图；
图14为本公开实施例提供的第一功能层的第二截面示意图；
图15为本公开实施例提供的断裂韧性与屈服强度的关系曲线图；
图16为本公开实施例提供的阵列基板的第八截面示意图；
图17为本公开实施例提供的在基底上形成缓冲层的示意图；
图18为本公开实施例提供的对有源薄膜进行激光退火的示意图；
图19为本公开实施例提供的形成有源层的示意图；
图20为本公开实施例提供的形成第一栅极绝缘层的示意图；
图21为本公开实施例提供的形成第一栅金属图形的示意图；
图22为本公开实施例提供的进行重掺杂工艺的示意图；
图23为本公开实施例提供的形成第二栅极绝缘层的示意图；
图24为本公开实施例提供的形成第二栅金属图形的示意图；
图25为本公开实施例提供的形成层间绝缘层的示意图；
图26为本公开实施例提供的形成过孔的第一示意图；
图27为本公开实施例提供的形成源漏金属图形的示意图；
图28为本公开实施例提供的形成平坦层的示意图；
图29为本公开实施例提供的形成阳极图形的示意图；
图30为本公开实施例提供的形成像素界定层的示意图。
具体实施方式
为了进一步说明本公开实施例提供的阵列基板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
显示产品包括的阵列基板中形成有电路结构，该电路结构中一般包括薄膜晶体管、电容、电极结构和信号线等，薄膜晶体管、电容、电极结构和信号线中包括的功能层中至少部分为图形化的功能图形，这些功能图形会在阵列基板中产生段差区域，段差区域中包括由所述功能图形形成的具有一定坡度角的台阶，这样就使得阵列基板中覆盖段差区域的功能层需要跨越段差区域的台阶，从而导致该功能层存在容易在台阶处断裂的风险。
以所述功能图形包括导电金属图形，覆盖该功能图形的功能层包括绝缘层为例，由于导电金属图形会形成段差区域，绝缘层需要跨越该段差区域的台阶，导致绝缘层存在容易在台阶处断裂的风险，而绝缘层发生断裂，可能进一步导致形成在绝缘层上的导电图形与该金属图形发生短路，影响阵列基板的良率。
相关技术中为了避免该功能层在台阶处断裂，一般会增加该功能层的厚度，但是这种处理方式不利于阵列基板在薄型化显示产品中的应用。
基于上述问题的存在，本公开提供如下技术方案：
如图1所示，本公开实施例提供了一种阵列基板，包括：基底10，以及层叠设置在所述基底10上的第一功能层20和第二功能层30；所述第一功能层20在所述基底10上形成段差区域40，所述第二功能层30覆盖所述段差区域40；所述第一功能层20位于所述段差区域的部分具有目标坡度角a，所述目标坡度角a为所述第二功能层30满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层30在满足其自身功能需求且在所述段差区域40不会发生断裂的厚度。
具体地，所述阵列基板中包括多种膜层，示例性的，包括：层叠设置的第一栅金属层、栅绝缘层、第二栅金属层、层间绝缘层、第一源漏金属层、第一平坦层、第二源漏金属层、第二平坦层和阳极层等，但不仅限于此。
所述第一栅金属层、第二栅金属层、第一源漏金属层、第二源漏金属层和阳极层均包括对应的多个功能图形，各功能图形会形成对应的段差区域；所述栅绝缘层、层间绝缘层、第一平坦层和第二平坦层均为整层的膜层，但这些整层的膜层上会形成有过孔，整层膜层会在所述过孔的附近形成对应的段差区域。
示例性的，所述第一功能层20可包括：所述多个功能图形中的一个或多个，也可以包括上述形成有过孔的整层膜层；同样的，所述第二功能层30也可包括：所述多个功能图形中的一个或多个，以及上述形成有过孔的整层膜层，只需满足所述多个功能图形中的一个或多个，以及上述形成有过孔的整层膜层能够覆盖段差区域即可。
需要说明，所述功能图形形成的段差区域可以位于该功能图形的边缘部分，也可以位于该功能图形被所述边缘部分包围的中间部分；更详细地说，形成在所述功能图形边缘部分的段差区域，一般为该边缘部分与该边缘部分所在平面之间形成的段差；形成在所述功能图形中间部分的段差，一般为该中间部分覆盖了不平坦的区域(如：底层图形产生的段差区域)，使得在中间部分中产生段差，或者使得中间部分与所述边缘部分之间形成段差。
另外，所述段差区域的具体范围可根据实际需要划定，示例性的，所述段差区域为所述功能图形产生的台阶所在的区域；或者，所述段差区域为以 所述功能图形产生的台阶为中心，附近预设范围内的区域。
此外，对于所述预设厚度为所述第二功能层30在满足其自身功能需求且在所述段差区域不会发生断裂的厚度，解释如下：“满足其自身功能需求”是指所述第二功能层30的厚度要能够满足其自身的功能需要，例如：当所述第二功能层30为绝缘层时，其厚度的设置要能够保证其绝缘性能满足需求；当该绝缘层作为电容中的介质层时，其厚度的设置要能够保证电容的容值满足需要；当所述第二功能层30为平坦层时，其厚度的设置要保证其平坦性满足需求。值得注意，当所述第二功能层30在垂直于其自身的延伸方向上厚度均一时，且所述第二功能层30同时覆盖同层设置的多个具有不同坡度角的第一功能图形时，要保证该第二功能层30在各第一功能图形产生的段差区域均不会发生断裂。
由于与所述第二功能层30断裂风险相关的因素包括：第二功能层30需要在段差区域爬升的台阶的坡度角的大小，以及所述第二功能层30的厚度；其中，台阶的坡度角越大，越有利于紧凑功能图形的布局，从而更有利于阵列基板在高分辨率显示产品中的应用，但是台阶的坡度角越大一定厚度的功能层的在台阶处断裂的风险越大；而所述第二功能层30在满足其自身功能需求的情况下，厚度越厚越不容易在段差区域发生断裂，但是厚度过厚不利于阵列基板在薄型化显示产品中的应用；因此，基于上述因素，可找到第二功能层30的厚度与其跨越的台阶的坡度角之间的对应关系，以实现在保证所述第二功能层30不断裂的情况下，实现最大的坡度角和最薄的第二功能层30。
本公开实施例提供的阵列基板中，通过设置所述第一功能层20位于所述段差区域的部分具有目标坡度角，所述目标坡度角为所述第二功能层30满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层30在满足其自身功能需求且在所述段差区域不会发生断裂的厚度；使得所述阵列基板在实现了所述第一功能层20具有最大的坡度角的同时，保证了所述第二功能层30具有满足其自身功能需求、且在所述段差区域不会发生断裂的最小厚度，因此，本公开实施例提供的阵列基板在保证所述功能层不断裂的情况下，实现了最大的坡度角和最薄的第二功能层30，使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降 低原材料成本。
在一些实施例中，所述第一功能层20的所述目标坡度角和所述第二功能层30的预设厚度满足关系式：
Tan(a)-1≤N(x-y)/y≤Tan(a)+1          公式(1)
其中，N＝z×W×K IC，z为常数，W为预设值，K IC为所述第二功能层30的断裂韧性参数，x为所述第二功能层30的预设厚度，y为所述第一功能层20位于所述段差区域的部分的厚度，a为所述第一功能层20的所述目标坡度角。
具体地，韧性为物理学概念，表示材料在塑性变形和破裂过程中吸收能量的能力，韧性越好，则发生脆性断裂的可能性越小。韧性是材料科学及冶金学上的重要参数，韧性是指材料受到使其发生形变的力时对折断的抵抗能力，其定义为材料在断裂前所能吸收的能量与体积的比值。
断裂韧性是阻止宏观裂纹失稳扩展能力的度量，也是材料抵抗脆性破坏的韧性参数，它和裂纹本身的大小、形状及外加应力大小无关，是材料固有的特性，只与材料本身、热处理及加工工艺有关。断裂韧性常用断裂前物体吸收的能量或外界对物体所作的功表示，例如：应力-应变曲线下的面积。韧性材料因具有大的断裂伸长值，所以有较大的断裂韧性，而脆性材料一般断裂韧性较小。
影响断裂韧性高低的因素包括外部因素和内部因素；其中，外部因素包括板材或构件截面的尺寸、服役条件下的温度和应变速率等，材料的断裂韧性随着板材或构件截面尺寸的增加而逐渐减小，最后趋于一稳定的最低值，即平面应变断裂韧性K IC，这是一个从平面应力状态向平面应变状态的转化过程。
断裂韧性随温度的变化关系和冲击韧性的变化相类似，随着温度的降低，断裂韧性可以有一急剧降低的温度范围，低于此温度范围，断裂韧性趋于一数值很低的下平台，温度再降低也不大改变了。
关于材料在高温下的断裂韧性，Hahn和Rosenfied提出了以下经验公式：
Figure PCTCN2020103313-appb-000001
式中：n为高温下材料的应变硬化指数；E为高温下材料的弹性模量，单位MPa；σ S为高温下材料的屈服强度；MPa；ε f为高温下单向拉伸时的断裂 真应变。
应变速率对断裂韧性参数的影响和温度的影响相似，增加应变速率和降低温度的影响是一致的。
内部因素包括材料成分和内部组织等。作为材料成分与内部组织因素的综合，材料强度是一宏观表现。从力学上而不是冶金学的角度，人们总是首先从材料的强度变化出发来探讨断裂韧性的高低，只要知道材料强度，就可大致推断材料的断裂韧性。
如图15所示，为AISI 4340(40CrNiMo)钢的断裂韧性和经淬火、回火热处理成不同屈服强度后的相互关系，图中横坐标代表屈服强度σ S，单位为MPa，纵坐标代表断裂韧性参数K IC，单位为MPa·m 1/2。可见，断裂韧性是随材料屈服强度的降低而不断升高的。这一试验结果是有代表性的，大多数低合金钢均有此变化规律，即使像马氏体时效钢(18Ni)也是如此，只不过同样强度下断裂韧性值较高些而已。
断裂韧性在国际单位制中是用焦耳每立方米(J/m3)来测量，在英制中是用磅力每平方英寸来测量，韧性的单位是MPa·m 1/2。
上述公式(1)中的z为常数，可取值在1～1.1之间(可包括端点值)，单位为：Mpa^-1·m^-1/2；Tan(a)为目标坡度角a的正切函数。W为与第二功能层形成的工艺方法，具体层间结构等相关的经验值，W取值在0.4～2.2之间(可包括端点值)。
示例性的，若所述第二功能层30为无机层，则系数N的取值范围大致在0.9-1.1之间(可包括端点值)；若所述第二功能层30为有机层，N的取值范围大致在0.8-0.9之间(可包括端点值)。
另外，所述第一功能层20位于所述段差区域的部分的厚度，即为：所述第一功能层20在所述段差区域具有的台阶在垂直于所述基底10的方向上的高度。
上述实施例提供的阵列基板中，通过对产生的段差区域的第一功能层20和覆盖段差区域的第二功能层30的材料特性、形成工艺、厚度以及断裂韧性的分析，总结了第二功能层30的厚度和第一功能层20在段差区域形成的坡度角的内在关系，从而在保证第二功能层30在段差区域不产生断裂的情况下， 使得所述第一功能图形201具有最大的坡度角，使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图2所示，在一些实施例中，所述第一功能层20包括第一功能图形201，所述第一功能图形201在所述基底10上形成第一段差区域401；
所述第二功能层30包括：第一功能膜层301和第二功能膜层302；所述第一功能膜层301，设置于所述第一功能图形201远离所述基底10的一侧，所述第二功能膜层302，设置于所述第一功能膜层301远离所述基底10的一侧；所述第一功能膜层301和所述第二功能膜层302均覆盖所述第一段差区域401，所述第一功能膜层301和所述第二功能膜层302的断裂韧性参数大致相同；
在垂直于所述第一功能膜层301的延伸方向，所述第一功能膜层301的厚度均匀，在垂直于所述第二功能膜层302的延伸方向，所述第二功能膜层302的厚度均匀；
所述第一功能图形201位于所述第一段差区域401的部分具有第一目标坡度角a1，所述第一目标坡度角a1为所述第一功能膜层301和所述第二功能膜层302满足第一预设厚度条件下的最大坡度角；所述第一预设厚度为所述第一功能膜层301和所述第二功能膜层302在满足各自功能需求且在所述第一段差区域401均不发生断裂时，所述第一功能膜层301具有的厚度与所述第二功能膜层302具有的厚度之和。
具体地，所述第一功能层20和所述第二功能层30的具体结构多种多样，示例性的，所述第一功能层20包括第一功能图形201，所述第二功能层30包括：设置于所述第一功能图形201远离所述基底10的表面的第一功能膜层301，以及设置于所述第一功能膜层301远离所述基底10的表面的第二功能膜层302；其中，所述第一功能图形201可选为第一栅金属层包括的第一栅金属图形，该第一栅金属图形与所述基底10之间可设置有第一栅极绝缘层50；所述第一功能膜层301可选为第二栅极绝缘层，所述第二功能膜层302可选为层间绝缘层(ILD层)。
所述第二栅极绝缘层和所述层间绝缘层均可采用氮化硅或氧化硅，或者 二者的组合来形成，即所述第二栅极绝缘层和所述层间绝缘层所采用的材料相同，制作工艺相同(如：采用等离子体增强化学的气相沉积法)，因此所述第一功能膜层301和所述第二功能膜层302的断裂韧性参数大致相同。
在计算所述第一功能图形201的坡度角时，由于在垂直于所述第一功能膜层301的延伸方向，所述第一功能膜层301的厚度均匀，在垂直于所述第二功能膜层302的延伸方向，所述第二功能膜层302的厚度均匀，因此，所述第一功能膜层301和所述第二功能膜层302的厚度可取各自在垂直于其自身延伸方向上的厚度；同时由于所述第一功能膜层301和所述第二功能膜层302的断裂韧性参数大致相同，可将所述第一功能膜层301的厚度和所述第二功能膜层302的厚度相加后，作为所述第一预设厚度，即所述公式(1)中的x值。
所述第一功能图形201在所述第二段差区域402形成的段差在垂直于所述基底10的方向上的高度，即为所述公式(1)中的y值。
将上述x值、y值以及对应的N值代入上述公式(1)中，即可得到所述第一功能图形201在所述第一段差区域401对应的第一目标坡度角a1；示例性的，当所述第一功能图形201为第一栅金属图形，所述第一功能膜层301为第二栅极绝缘层，所述第二功能膜层302为层间绝缘层时，通过所述公式(1)，可计算得到所述第一目标坡度角a1的范围在40°-45°之间(可取端点值)。
上述实施例提供的阵列基板中，由于在所述第一功能图形201上，采用了相同工艺、相同材料形成了覆盖所述第一段差区域401的第一功能膜层301和第二功能膜层302，使得所述第一功能图形201上形成了较厚的第二功能层30，因此，在计算所述第一目标坡度角a1时，可将所述第一功能膜层301和所述第二功能膜层302的厚度相加，作为所述第一预设厚度，并可基于该第一预设厚度确定所述第一功能图形201对应的第一目标坡度角a1，从而在保证第二功能层30在段差区域不产生断裂的情况下，使得所述第一功能图形201具有最大的坡度角，使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图2所示，在一些实施例中，所述第一功能层20还包括第二功能图形 202，所述第二功能图形202与所述第一功能图形201同层同材料设置，所述第二功能图形202在所述基底10上形成第二段差区域402；
所述第一功能膜层301覆盖所述第二段差区域402；
所述第二功能图形202位于所述第二段差区域402的部分具有第二目标坡度角a2，所述第二目标坡度角a2为所述第一功能膜层301满足第二预设厚度条件下的最大坡度角；所述第二预设厚度为所述第一功能膜层301在满足其自身功能需求、且在所述第二段差区域402不发生断裂时，所述第一功能膜层301具有的厚度；
所述第二目标坡度角a2小于所述第一目标坡度角a1。
具体地，所述第一功能层20还可以包括第二功能图形202，所述第二功能图形202与所述第一功能图形201同层同材料设置，即所述第二功能图形202与所述第一功能图形201能够通过同一次构图工艺同时形成，示例性的，所述第一功能图形201和所述第二功能图形202均为第一栅金属层包括的第一栅金属图形，且所述第一功能图形201和所述第二功能图形202相互独立。
所述第二功能层30中包括的所述第一功能膜层301能够覆盖所述第二功能图形202形成的第二段差区域402，这样在计算所述第二功能图形202在所述第二段差区域402的第二目标坡度角a2时，可将所述第一功能膜层301在满足其自身功能需求且在所述第二段差区域402不发生断裂时所述第一功能膜层301对应的厚度，作为所述第二预设厚度，即所述公式(1)中的x值。
所述第二功能图形202在所述第二段差区域402形成的段差在垂直于所述基底10的方向上的高度，即为所述公式(1)中的y值。
将上述x值、y值以及对应的N值代入上述公式(1)中，即可得到所述第二功能图形202在所述第二段差区域402对应的第二目标坡度角a2；示例性的，当所述第二功能图形202为第一栅金属图形，所述第一功能膜层301为第二栅极绝缘层时，通过所述公式(1)，可计算得到所述第二目标坡度角a2的范围在26°-29°之间(可取端点值)。
上述实施例提供的阵列基板中，由于覆盖所述第二段差区域402的第一功能膜层301较薄，小于覆盖所述第一段差区域401的第二功能层30(即所述第一功能膜层301与所述第二功能膜层302)的厚度，因此，计算得到的 第二目标坡度角a2小于所述第一目标坡度角a1。
上述实施例提供的阵列基板中，在保证第一功能膜层301满足其自身功能需求、且在第二段差区域402不产生断裂的情况下，使得所述第二功能图形202具有最大的坡度角，从而使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图2所示，在一些实施例中，所述第一功能层20还包括第三功能图形203，所述第三功能图形203位于所述第一功能膜层301远离所述基底10的一侧，所述第三功能图形203在所述基底10上形成第三段差区域403；
所述第二功能膜层302覆盖所述第三段差区域403；
所述第三功能图形203位于所述第三段差区域403的部分具有第三目标坡度角a3，所述第三目标坡度角a3为所述第二功能膜层302满足第三预设厚度条件下的最大坡度角；所述第三预设厚度为所述第二功能膜层302在满足其自身功能需求且在所述第三段差区域403不发生断裂时，所述第二功能膜层302具有的厚度；
所述第三目标坡度角a3大于所述第二目标坡度角a2，小于所述第一目标坡度角a1。
具体地，所述第一功能层20还可以包括第三功能图形203，示例性的，所述第三功能图形203为第二栅金属层包括的第二栅金属图形。
所述第三功能图形203位于所述第一功能膜层301远离所述基底10的一侧，所述第三功能图形203在所述基底10上形成第三段差区域403，示例性的，该第三段差区域403在所述基底10上的正投影与所述第一功能图形201在所述基底10上的正投影不交叠，且与所述第二功能图形202在所述基底10上的正投影不交叠。
另外，可设置所述第三功能图形203在所述基底10上的正投影与所述第二功能图形202在所述基底10上的正投影交叠，使得所述第二功能图形202与所述第三功能图形203能够形成为电容结构。
所述第二功能层30中包括的所述第二功能膜层302能够覆盖所述第三功能图形203形成的第三段差区域403，这样在计算所述第三功能图形203在 所述第三段差区域403的第三目标坡度角a3时，可将所述第二功能膜层302在满足其自身功能需求且在所述第三段差区域403不发生断裂时所述第二功能膜层302对应的厚度，作为所述第三预设厚度，即所述公式(1)中的x值。
所述第三功能图形203在所述第三段差区域403形成的段差在垂直于所述基底10的方向上的高度，即为所述公式(1)中的y值。
将上述x值、y值以及对应的N值代入上述公式(1)中，即可得到所述第三功能图形203在所述第三段差区域403对应的第三目标坡度角a3；示例性的，当所述第三功能图形203为第二栅金属图形，所述第二功能膜层302为层间绝缘层时，通过所述公式(1)，可计算得到所述第三目标坡度角a3的范围在35°-39°之间(可取端点值)。
上述实施例提供的阵列基板中，由于覆盖所述第三段差区域403的第一功能膜层301的厚度，大于覆盖所述第二段差区域402的第一功能膜层301的厚度，且小于覆盖所述第一段差区域401的第二功能层30(即所述第一功能膜层301与所述第二功能膜层302)的厚度，因此，计算得到的所述第三目标坡度角a3大于所述第二目标坡度角a2，小于所述第一目标坡度角a1。
上述实施例提供的阵列基板中，在保证第二功能膜层满足其自身功能需求且在第三段差区域不产生断裂的情况下，使得所述第三功能图形具有最大的坡度角，从而使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图2所示，在一些实施例中，所述第一功能层20包括第四功能图形204，所述第四功能图形204在所述基底10上形成沿远离所述基底10的方向依次排布的至少两个第四段差区域404；
所述第二功能层30包括设置于所述第四功能图形204远离所述基底10的一侧的平坦层，所述平坦层完全覆盖所述第四功能图形204；
所述第四功能图形204位于各所述第四段差区域404的部分具有对应的第四目标坡度角a4，该第四目标坡度角a4为：所述平坦层中位于该第四目标坡度角a4对应的第四段差区域404的第一部分在满足第四预设厚度条件下的最大坡度角；该第四预设厚度为所述第一部分在满足其自身功能需求且在该第四段差区域404不发生断裂时，所述第一部分在垂直于所述基底10的方 向上具有的最薄厚度。
具体地，所述第一功能层20还可以包括第四功能图形204，示例性的，所述第四功能图形204为第一源漏金属层包括的第一源漏金属图形；或者，所述第四功能图形204为第二源漏金属层包括的第二源漏金属图形。
所述第四功能图形204在所述基底10上形成沿远离所述基底10的方向依次排布的至少两个第四段差区域404；示例性的，该至少两个第四段差区域404中，最靠近所述基底10的第四段差区域404为所述第四功能图形204边缘部分自身形成的段差区域，除该段差区域外，其它远离所述基底10的第四段差区域404均为由于所述第四功能图形204覆盖了底层段差而形成的第四段差区域404。
所述第二功能层30中还包括设置于所述第四功能图形204远离所述基底10的一侧的平坦层，所述平坦层能够完全覆盖所述第四功能图形204，即能够覆盖所述第四功能图形204形成的第四段差区域404，由于所述平坦层的作用即为填平其下方的段差，使得平坦层远离所述基底10的表面平坦化，因此，在垂直于所述基底10的方向上，所述平坦层在不同区域的厚度存在不同，这样在计算位于不同第四段差区域404的第四目标坡度角a4时，对于公式(1)中的x值，应做不同的选取，从而使得所述第四功能图形204位于各所述第四段差区域404的部分具有对应的第四目标坡度角a4。
更详细地说，如图2所示，以所述第四功能图形204边缘部分形成的第四段差区域404为例，该第四段差区域404对应的第四目标坡度角a4为：所述平坦层中覆盖该第四段差区域404的第一部分在满足第四预设厚度条件下的最大坡度角；该第四预设厚度为所述第一部分在满足其自身功能需求、且在该第四段差区域404不发生断裂时，所述第一部分在垂直于所述基底10的方向上具有的最薄厚度，即图2中的d1。
在计算该第四段差区域404对应的第四目标坡度角a4时，可将所述第一部分在垂直于所述基底10的方向上具有的最薄厚度d1，作为所述第四预设厚度，即所述公式(1)中的x值。所述第四功能图形204在该第四段差区域404形成的段差在垂直于所述基底10的方向上的高度d4，即为所述公式(1)中的y值。将上述x值、y值以及对应的N值代入上述公式(1)中，即可得 到所述第四功能图形204在该第四段差区域404对应的第四目标坡度角a4。
上述实施例提供的阵列基板中，在保证平坦层满足其自身功能需求、且在第四段差区域404不产生断裂的情况下，使得所述第四功能图形204具有最大的坡度角，从而使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图2所示，在一些实施例中，所述第一功能层20包括第一功能图形201，所述第一功能图形201在所述基底10上形成第一段差区域401；
所述第二功能层30包括：设置于所述第一功能图形201远离所述基底10的一侧的第一功能膜层301，以及设置于所述第一功能膜层301远离所述基底10的一侧的第二功能膜层302；所述第一功能膜层301和所述第二功能膜层302均覆盖所述第一段差区域401；
所述第四功能图形204位于所述第二功能膜层302远离所述基底10的一侧，所述第四功能图形204覆盖所述第一段差区域401。
具体地，从图2所示的结构来看，所述第四功能图形204位于所述第二功能膜层302远离所述基底10的一侧，且所述第四功能图形204覆盖所述第一段差区域401，因此，所述第四功能图形204形成两个第四段差区域404，其中一个第四段差区域404位于第四功能图形204的边缘部分，另一个第四段差区域404在所述基底10上的正投影与所述第一段差区域401在所述基底10上的正投影交叠。
示例性的，当所述第四功能图形204为第一源漏金属图形，所述第二功能层30为平坦层时，通过所述公式(1)，可计算得到所述第四功能图形204的边缘部分对应的第四目标坡度角a4的范围在60°-75°之间(可取端点值)。
需要说明，由于平坦层的厚度较厚，一般在2um-4um之间，同时由于采用Coating工艺，反应液(如：显影液)在大坡度角下的反应会受到金属坡度角的影响，从而造成反应不充分，因此，在代入公式(1)中计算时，N的取值相比于无机层的情况小。
值得注意，图2所示的结构中，第二功能膜层302和平坦层同时覆盖所述第三段差区域403，但由于所述第二功能膜层302所采用的材料一般为无机材料，所述平坦层所采用的材料一般为有机材料，二者的制作工艺不同， 使得公式(1)中的N不同，如：所述第平坦层采用Coating工艺，所述第二功能膜层302采用等离子体增强化学的气相沉积法制作，因此，在计算所述第三目标在计算所述第三段差区域403对应的第三目标坡度角a3时，不能够将第二功能膜层302和平坦层的厚度相加代入公式(1)中。
如图3所示，在一些实施例中，所述平坦层包括第一平坦层PLN1和第二平坦层PLN2，所述第一功能层还包括另一第四功能图形204＇，所述另一第四功能图形204＇位于所述第一平坦层PLN1远离所述基底10的一侧，且所述另一第四功能图形204＇在所述基底10上形成另一第四段差区域404＇，所述另一第四功能图形204＇位于所述另一第四段差区域404＇的部分具有另一第四目标坡度角a4＇，所述第二平坦层PLN2覆盖所述另一第四功能图形204＇。
具体地，当所述阵列基板为上述结构时，所述另一第四功能图形204＇可具体为第二源漏金属图形，由于第一平坦层PLN1覆盖的下层膜层结构会在某些位置不够平整，使得所述第一平坦层PLN1远离基底10的表面存在起伏现象，从而导致形成在所述第一平坦层PLN1远离所述基底10的一侧的所述另一第四功能图形204＇形成多处另一第四段差区域404＇(图中仅示出了一处)。
示例性的，当所述第四功能图形204＇为第二源漏金属图形，所述第二功能层30为第二平坦层PLN2时，通过所述公式(1)，可计算得到所述第四功能图形204＇的边缘部分对应的第四目标坡度角a4＇的范围在60°-85°之间(可取端点值)。
如图4所示，在一些实施例中，所述第一功能层20包括沿远离所述基底10的方向依次层叠设置的第五功能图形205和第六功能图形206；
所述第二功能层30包括设置于所述第五功能图形205和所述第六功能图形206之间的第二功能膜层302，以及设置于所述第六功能图形206远离所述基底10的一侧的平坦层PLN；其中，所述第二功能膜层302上设置有第一过孔，所述第二功能膜层302在所述第一过孔的边缘形成第五段差区域405；
所述第六功能图形206通过所述第一过孔与所述第五功能图形205耦接，所述第六功能图形206覆盖所述第五段差区域405，在所述第五段差区域405对应的位置形成第六段差区域406；
所述第二功能膜层302位于所述第五段差区域405的部分具有第五目标坡度角a5；
所述第六功能图形206位于所述第六段差区域406的部分具有第六目标坡度角a6，所述第六目标坡度角a6为：所述平坦层中位于所述第六段差区域406的第二部分满足第六预设厚度条件下的最大坡度角；该第六预设厚度为所述第二部分在满足其自身功能需求且在所述第六段差区域406不发生断裂时的最薄厚度；
所述第二功能膜层302在所述第五段差区域405的坡度角a5，与所述第六目标坡度角a6大致相等。
示例性的，所述第五功能图形205可选为第二栅金属图形，在所述第五栅金属图形与所述基底10之间可设置有第一栅金属图形60；所述第六功能图形206可选为第一源漏金属图形。
所述第二功能膜层302可包括设置于所述第五功能图形205和所述第六功能图形206之间的第二功能膜层302，以及设置于所述第六功能图形206远离所述基底10的一侧的平坦层；所述第二功能膜层302可选为层间绝缘层，所述第二功能膜层302上设置有第一过孔，所述第二功能膜层302能够在所述第一过孔的边缘形成第五段差区域405。
所述第六功能图形206通过所述第一过孔与所述第五功能图形205耦接，因此所述第六功能图形206覆盖所述第一过孔的边缘，进而覆盖所述第一过孔边缘处形成的所述第五段差区域405，并在所述第五段差区域405对应的位置形成第六段差区域406。
更详细地说，如图4所示，所述第六段差区域406对应的第六目标坡度角a6为：所述平坦层中覆盖该第六段差区域406的第二部分在满足第六预设厚度条件下的最大坡度角；该第六预设厚度为所述第二部分在满足其自身功能需求、且在该第六段差区域406不发生断裂时的最薄厚度，即图4中的d2。
在计算该第六段差区域406对应的第六目标坡度角a6时，可将所述第二部分在垂直于所述基底10的方向上具有的最薄厚度d2，作为所述第六预设厚度，即所述公式(1)中的x值。所述第六功能图形206在该第六段差区域406形成的段差在垂直于所述基底10的方向上的高度d6，即为所述公式(1) 中的y值。将上述x值、y值以及对应的N值代入上述公式(1)中，即可得到所述第六功能图形206在该第六段差区域406对应的第六目标坡度角a6。
需要说明，当所述第六功能图形206为第一源漏金属图形时，由于金属断裂韧性很高，在过孔处不易断裂，而且由于平坦层厚度较厚，因此，计算得到的第六目标坡度角a6较大，范围约在60°-85°之间(可包括端点值)。
由于所述第六目标坡度角a6并非刻蚀形成，而是由于覆盖了所述第五段差区域405才形成的，即所述第六功能图形206在第六段差区域406对应的坡度角，由其覆盖的第五功能图形205在第五段差区域405对应的坡度角决定，所述第六功能图形206在第六段差区域406对应的坡度角，与所述第五功能图形205在第五段差区域405对应的坡度角a5大致相同，因此，在计算得到所述第六目标坡度角a6的角度值后，可将所述第五功能图形205在所述第五段差区域405对应的坡度角制作为该角度值，这样后续形成的第六功能图形206可自然在所述第六段差区域406具有该角度值。
上述实施例提供的阵列基板中，在保证平坦层满足其自身功能需求且在第六段差区域406不产生断裂的情况下，使得所述第六功能图形206具有最大的坡度角，从而使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图5和图6所示，在一些实施例中，所述第一功能层20包括：
设置于所述基底10上的第七功能图形207，所述第七功能图形207在所述基底10上形成第七段差区域407；
设置于所述第七功能图形207远离所述基底10的一侧的第八功能图形208，所述第八功能图形208包括：覆盖所述第七段差区域407的第三部分2083，覆盖所述第七功能图形207除位于所述第七段差区域407之外的其余部分的第四部分2084，以及未覆盖所述第七功能图形207的第五部分2085；
设置于所述第八功能图形208远离所述基底10的一侧的平坦层PLN，所述平坦层PLN上设置有第二过孔，所述第二过孔在所述基底10上的正投影位于所述第八功能图形208在所述基底10上的正投影的内部，所述平坦层在所述第二过孔的边缘形成第八段差区域408和第九段差区域409，所述第八段差区域408在所述基底10上的正投影与所述第四部分2084在所述基底10上 的正投影交叠，所述第九段差区域409在所述基底10上的正投影与所述第五部分2085在所述基底10上的正投影交叠；
所述第二功能层30包括第二功能膜层302和第九功能图形209；其中，所述第二功能膜层302位于所述第七功能图形207和所述第八功能图形208之间，所述第九功能图形209位于所述平坦层远离所述基底10的一侧，且通过所述第二过孔与所述第八功能图形208耦接；所述第九功能图形209覆盖所述第八段差区域408和所述第九段差区域409；所述第九功能图形209厚度均匀；
所述平坦层位于所述第八段差区域408的部分具有第八目标坡度角a8，所述第八目标坡度角a8为：所述第九功能图形209满足第八预设厚度条件下的最大坡度角；该第八预设厚度为所述第九功能图形209在满足其自身功能需求、且在所述第八段差区域408不发生断裂时的厚度；
所述平坦层位于所述第九段差区域409的部分具有第九目标坡度角a9，所述第九目标坡度角a9为：所述第九功能图形209满足第九预设厚度条件下的最大坡度角；该第九预设厚度为所述第九功能图形209在满足其自身功能需求、且在所述第九段差区域409不发生断裂时的厚度。
具体地，所述第七功能图形207可选为第二栅金属图形，所述第八功能图形208可选为第一源漏金属图形，所述第九功能图形209可选为阳极图形；所述第二功能膜层302可选为层间绝缘层。
如图6所示，所述第八功能图形208包括：覆盖所述第七段差区域407的第三部分2083，覆盖所述第七功能图形207除位于所述第七段差区域407之外的其余部分的第四部分2084，以及未覆盖所述第七功能图形207的第五部分2085；在垂直于所述基底10的方向上，所述第四部分2084远离所述基底10的表面的第一高度，高于所述第五部分2085远离所述基底10的表面的第二高度，所述第三部分2083远离所述基底10的表面包括斜面，该斜面在垂直于所述基底10的方向上的第三高度介于所述第一高度和所述第二高度之间。
所述平坦层位于所述第八功能图形208远离所述基底10的一侧，且能够完全覆盖所述第八功能图形208，由于所述第八功能图形208中不同部分对 应的高度不同，从而使得位于不同部分上所述平坦层具有厚度不同，即位于第四部分2084上的平坦层在垂直于所述基底10的方向上的厚度，小于位于所述第五部分2085上的平坦层在垂直于所述基底10的方向上的厚度。
所述平坦层上形成有所述第二过孔，所述第二过孔在所述基底10上的正投影位于所述第八功能图形208在所述基底10上的正投影的内部，示例性的，所述第二过孔在所述基底10上的正投影能够分别与所述第三部分2083在所述基底10上的正投影、所述第四部分2084在所述基底10上的正投影，以及所述第五部分2085在所述基底10上的正投影交叠。
所述平坦层在所述第二过孔的边缘形成第八段差区域408和第九段差区域409，示例性的，所述第八段差区域408在所述基底10上的正投影与所述第四部分2084在所述基底10上的正投影交叠，所述第九段差区域409在所述基底10上的正投影与所述第五部分2085在所述基底10上的正投影交叠。
所述第九功能图形209位于所述平坦层远离所述基底10的一侧，且能够通过所述第二过孔与所述第八功能图形208耦接；所述第九功能图形209覆盖所述第八段差区域408和所述第九段差区域409；所述第八功能图形208与所述第九功能图形209之间形成的接触区域在所述基底10上的正投影，能够分别与所述第三部分2083在所述基底10上的正投影、所述第四部分2084在所述基底10上的正投影，以及所述第五部分2085在所述基底10上的正投影交叠。
如图5所示，所述平坦层位于所述第八段差区域408的部分具有第八目标坡度角a8，所述第八目标坡度角a8为：所述第九功能图形209满足第八预设厚度条件下的最大坡度角；该第八预设厚度为所述第九功能图形209在满足其自身功能需求、且在所述第八段差区域408不发生断裂时的厚度；
更详细地说，如图5所示，所述第八段差区域408对应的第八目标坡度角a8为：所述第九功能图形209满足第八预设厚度条件下的最大坡度角；该第八预设厚度为所述第九功能图形209在满足其自身功能需求、且在所述第八段差区域408不发生断裂时的厚度。在计算该第八段差区域408对应的第八目标坡度角a8时，将所述第九功能图形209的厚度作为公式(1)中的x值；将所述平坦层在第八段差区域408形成的段差在垂直于所述基底10的方 向上的高度d8，作为所述公式(1)中的y值。将上述x值、y值以及对应的N值代入上述公式(1)中，即可得到所述平坦层在该第八段差区域408对应的第八目标坡度角a8；示例性的，所述第八目标坡度角a8的取值范围在40°-50°之间(可包括端点值)。
如图6所示，所述第九段差区域409对应的第九目标坡度角a9为：所述第九功能图形209满足第九预设厚度条件下的最大坡度角；该第九预设厚度为所述第九功能图形209在满足其自身功能需求、且在所述第九段差区域409不发生断裂时的厚度。在计算该第九段差区域409对应的第九目标坡度角a9时，将所述第九功能图形209的厚度作为公式(1)中的x值；将所述平坦层在第九段差区域409形成的段差在垂直于所述基底10的方向上的高度d9，作为所述公式(1)中的y值。将上述x值、y值以及对应的N值代入上述公式(1)中，即可得到所述平坦层在该第九段差区域409对应的第九目标坡度角a9；示例性的，所述第九目标坡度角a9的取值范围在35°-45之间(可包括端点值)。
进一步地，如图6所示，第八目标坡度角a8大于第九目标坡度角a9，而由于d8小于d9，使得所述第九功能图形209在所述第八段差区域408的断裂风险较小；另外，所述第八目标坡度角a8的取值范围与d8正相关，同时所述第九目标坡度角a9的取值范围与d9正相关。
上述实施例提供的阵列基板中，在保证第九功能图形209满足其自身功能需求、且在第八段差区域408和第九段差区域409均不产生断裂的情况下，使得所述平坦层在所述第二过孔的边缘处具有最大的坡度角，从而使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
如图7所示，在一些实施例中，所述第七功能图形207在所述基底10上的正投影与所述第八功能图形208在所述基底10上的正投影形成第一交叠区域，所述第一交叠区域沿第一方向具有第一尺寸H1；
所述第八功能图形208中没有位于所述第一交叠区域的部分沿所述第一方向具有第二尺寸H2；
所述第九功能图形209与所述第八功能图形208形成第一接触区域，沿 所述第一方向，所述第一接触区域的边界(如C点位置)与所述第八功能图形208的第一端(如A点位置)之间的最小距离为第一间距L1，所述第一接触区域的边界(如D点位置)与所述第八功能图形208的第二端(如B点位置)之间的最小距离为第二间距L2；所述第一端与所述第二端沿所述第一方向相对，所述第一端在所述基底10上的正投影与所述第七功能图形207交叠，所述第二端在所述基底10上的正投影与所述第七功能图形207不交叠；
所述第一尺寸H1与所述第二尺寸H2之间的差值对应的第一绝对值，与所述第一间距L1与所述第二间距L2之间的差值对应的第二绝对值成正比。
具体地，所述第一方向可选为：所述第八功能图形208在所述第七功能图形207位于所述第七段差区域407的斜面上的最短爬升方向F1，在所述基底10上投影后的方向，如图7中所示。
所述第一尺寸H1与所述第二尺寸H2之间的差值对应的第一绝对值，与所述第一间距L1与所述第二间距L2之间的差值对应的第二绝对值成正比，即|L1-L2|＝M·k|H1-H2|，M为所述第八功能图形208正下方功能图形(如：金属图形)的数量，k取值在0.01～10之间(可包括端点值)，k代表第七功能图形207和第八功能图形208在垂直于基底的方向上的重叠位置关系，k与第七目标坡度角a7、第八目标坡度角a8等角度，以及第七功能图形207和第八功能图形208的分布相关。
H1-H2的绝对值的最大取值是所述第八功能图形208沿所述第一方向的第一宽度，L1-L2的绝对值的最大取值是所述第一宽度减去所述第一接触区域沿所述第一方向的第二宽度；所述第二宽度取所述第一宽度的9/10时，当L2等于0时，L1-L2就等于所述第一宽度的1/10。值得注意，L1-L2最小值为0，H1-H2最小值为0。
示例性的，可设置M＝1，L1-L2＝0.01μm，H1-H2＝0.1μm，k＝0.1。
示例性的，可设置M＝1，L1-L2＝0.019μm，H1-H2＝0.2μm，k＝0.1。
示例性的，可设置M＝1，L1-L2＝0.032μm，H1-H2＝0.3μm，k＝0.11。
示例性的，可设置M＝1，L1-L2＝0.042μm，H1-H2＝0.4μm，k＝0.1。
示例性的，可设置M＝1，L1-L2＝0.05μm，H1-H2＝0.5μm，k＝0.1。
上述实施例提供的阵列基板中，通过合理的调节H1、H2、L1和L2，能 够在保证所述第九功能图形209与所述第八功能图形208良好接触性能的同时，使得所述第七目标坡度角a7、第八目标坡度角a8以及所述第九目标坡度角a9最小化，从而更利于所述阵列基板应用于薄型化、高分辨率的显示装置中。
如图7所示，在一些实施例中，所述第一间距L1与所述第二间距L2之间的差值对应的第二绝对值，与所述第一间距L1与所述第八功能图形208沿所述第一方向上的第一宽度(即H1+H2)的比值成正比。
在一些实施例中，当所述第一尺寸H1大于所述第一间距L1时，所述第八目标坡度角a8大于所述第九目标坡度角a9；或者，所述第八目标坡度角a8与所述第九目标坡度角a9之间的差值，与所述第一尺寸H1成正比。
在一些实施例中，所述第八目标坡度角a8与所述第九目标坡度角a9之间的差值小于所述第七功能图形207在所述第七段差区域407具有的第七目标坡度角a7；所述第七目标坡度角a7为所述第二功能膜层302满足第七预设厚度条件下的最大坡度角；所述第七预设厚度为所述第二功能膜层302在满足其自身功能需求、且在所述第七段差区域407不会发生断裂的厚度。
上述实施例提供的阵列基板中，通过合理的调节H1、H2、L1和L2，能够在保证所述第九功能图形209与所述第八功能图形208良好接触性能的同时，使得所述第七目标坡度角a7、第八目标坡度角a8以及所述第九目标坡度角a9最小化，从而更利于所述阵列基板应用于薄型化、高分辨率的显示装置中。
在计算所述第七目标坡度角a7时，可将所述第二功能膜层302的厚度代入公式(1)中的x，将所述第七功能图形207在垂直于所述基底10的方向上的厚度代入公式(1)中的y，再选取合适的N值，即可得到所述第七目标坡度角a7的角度值。
如图8所示，在一些实施例中，所述阵列基板包括电容结构；
所述第一功能层20包括所述电容结构的第一极板，所述第一极板在所述基底10上形成极板段差区域；
所述第二功能层30包括位于所述第一极板远离所述基底10的一侧的介质层，所述介质层完全覆盖所述第一极板；所述第一极板位于所述极板段差 区域的部分具有极板目标坡度角，所述极板目标坡度角为所述介质层满足第十预设厚度条件下的最大坡度角；所述第十预设厚度为所述介质层在满足其自身功能需求、且在所述极板段差区域不会发生断裂的厚度；
所述电容结构的第二极板位于所述介质层远离所述基底10的一侧，所述第二极板在所述基底10上的正投影与所述第一极板在所述基底10上的正投影形成第一交叠区域，所述第二极板覆盖所述极板段差区域。
具体地，所述阵列基板中可包括多个电容结构，这些电容结构可应用于阵列基板包括的像素驱动电路中，也可应用于阵列基板中的栅极驱动电路中，但不仅限于此。
需要说明，一个电容结构带1库的电量Q时，电容结构两极板间的电势差U为1伏，电容结构的电容C为1法拉，即满足关系式：C＝Q/U。但电容结构的电容大小不是由Q或U决定的，电容大小的决定式为：C＝εS/(4πkd)，其中，ε为极板间介质的介电常数，S为电容结构的第一极板和第二极板的正对面积，d为电容结构的第一极板和第二极板之间的距离，k为静电力常量。常见的平行板电容器，电容为C＝εS/d。
所述电容结构的第一极板可选为第一栅金属图形，所述电容结构的第二极板可选为第二栅金属图形，所述介质层可选为第二栅极绝缘层，但不仅限于此。
设置所述第一功能层20包括所述电容结构的第一极板，所述第二功能层30包括位于所述第一极板远离所述基底10的一侧的介质层，在计算所述第一极板位于所述极板段差区域的部分具有的极板目标坡度角时，可将所述介质层的厚度作为公式(1)中的x，将所述第一极板形成的段差的高度作为公式(1)中的y代入，K IC代入介质层的断裂韧性参数，W代入与介质层形成的工艺方法和具体层间结构等相关的经验值，示例性的，W取值在0.4～2.2之间(可以包括端点值)，z的取值在1～1.1之间，单位为Mpa^-1·m^-1/2。
需要说明，所述介质层的厚度可根据实际需要设置为均匀或者不均匀，当所述介质层的厚度均匀时，可直接将介质层的厚度代入x，当介质层的厚度不均匀时，将介质层中位于所述极板段差区域的部分，在垂直于所述基底10的方向上的最小厚度代入x。另外，所述介质层在满足其自身功能需求是 指：所述介质层能够保证所述第一极板与所述第二极板相互绝缘，和/或，所述介质层能够满足所述电容结构的容值需要。此外，所述电容结构的容值与所述第一极板和所述第二极板的正对面积相关，该正对面积即所述第一极板在所述基底上的正投影与所述第二极板在所述基底上的正投影形成的第一交叠区域的面积。
上述设置所述第一极板位于所述极板段差区域的部分具有极板目标坡度角，使得所述第一极板在保证所述介质层在满足其自身功能需求、且在所述极板段差区域不会发生断裂的情况下，实现了最大的坡度角。
而且，在设置所述第一极板的坡度角较大的情况下，当所述第二极板覆盖所述极板段差区域时，需要设置所述第二极板与所述第一极板的交叠面积更大，以保证在所述极板段差区域所述第二极板能够更好的搭在所述第一极板上，不易从所述第一极板上剥离；因此，将所述阵列基板设置为上述结构，增加了所述第一极板与所述第二极板之间的正对面积，有助于更好的提升所述电容结构的容值。
需要说明，上述“设置所述第二极板与所述第一极板的交叠面积更大”的具体方式多种多样，示例性的，如图8所示，可增加所述第二极板的d3长度，或者，也可以增加第二极板在垂直于d3长度方向上的尺寸。
如图8～图10所示，在一些实施例中，所述电容结构包括：第一电容结构、第二电容结构和第三电容结构；所述第一电容结构的容值大于所述第二电容结构的容值，和/或所述第一电容结构的容值大于所述第三电容结构的容值；
所述第一电容结构的第一极板C1a对应的极板目标坡度角b1，大于所述第二电容结构的第一极板C2a对应的极板目标坡度角b3；和/或，所述第一电容结构的第一极板C1a对应的极板目标坡度角b1，大于所述第三电容结构的第一极板C3a对应的极板目标坡度角b5。
具体地，所述阵列基板中包括的电容结构的具体数量可根据实际需要设置，示例性的，所述电容结构包括：第一电容结构、第二电容结构和第三电容结构；以阵列基板应用于OLED显示装置中为例，当显示装置中包括的每个像素单元均包括相邻的红色子像素、绿色子像素和蓝色子像素时，可设置所 述红色子像素中包括所述第一电容结构，所述绿色子像素中包括所述第二电容结构，所述蓝色子像素中包括所述第三电容结构。
另外，如图11所示，也可设置所述第一电容结构位于显示装置的显示区域，所述第二电容结构和所述第三电容结构位于显示装置的周边区域；这种设置方式下，也可以进一步设置相邻的第一电容结构与第二电容结构之间的距离L3，大于相邻的第二电容结构与第三电容结构之间的距离L4。
需要说明，所述第一电容结构的第一极板C1a、所述第二电容结构的第一极板C2a和所述第三电容结构的第一极板C3a可同层同材料设置，也可以不同层同材料设置；同样的，所述第一电容结构的第二极板C1b、所述第二电容的第二极板C2b和所述第三电容结构的第二极板C3b可同层同材料设置，也可以不同层同材料设置。示例性的，所述第一电容结构的第一极板C1a、所述第二电容结构的第一极板C2a和所述第三电容结构的第一极板C3a均采用阵列基板中的第一栅金属层制作；所述第一电容结构的第二极板C1b采用阵列基板中的第二栅金属层制作，所述第二电容的第二极板C2b和所述第三电容结构的第二极板C3b均采用阵列基板中的源漏金属层制作。
在设置所述第一电容结构的容值大于所述第二电容结构的容值，和/或所述第一电容结构的容值大于所述第三电容结构的容值时，具体可通过如下方式实现：设置所述第一电容结构的第一极板C1a对应的极板目标坡度角b1，大于所述第二电容结构的第一极板C2a对应的极板目标坡度角b3；和/或，所述第一电容结构的第一极板C1a对应的极板目标坡度角b1，大于所述第三电容结构的第一极板C3a对应的极板目标坡度角b5来实现。
更详细地说，当设置所述第一电容结构的第一极板C1a对应的极板目标坡度角b1，大于所述第二电容结构的第一极板C2a对应的极板目标坡度角b3时，能够实现所述第一电容结构中第一极板C1a在所述基底上的正投影与第二极板C1b在所述基底上的正投影形成的交叠区域的面积，大于所述第二电容结构中所述第一极板C2a在所述基底上的正投影与所述第二极板C2b在所述基底上的正投影形成的交叠区域的面积，从而实现所述第一电容结构的电容值大于所述第二电容结构的电容值。
在一些实施例中，还可以设置所述第一电容结构对应的第一介质层701 在垂直于所述基底10的方向上的厚度，小于所述第二电容结构对应的第二介质层702在垂直于所述基底10的方向上的厚度；和/或，所述第一电容结构对应的第一介质层701在垂直于所述基底10的方向上的厚度，小于所述第三电容结构对应的第三介质层703在垂直于所述基底10的方向上的厚度。
具体地，由于所述第一极板与所述第二极板之间的介质层厚度越小，电容结构的容值越大，因此可通过设置所述第一电容结构对应的第一介质层701在垂直于所述基底10的方向上的厚度，小于所述第二电容结构对应的第二介质层702在垂直于所述基底10的方向上的厚度，来实现所述第一电容结构的容值大于所述第二电容结构的容值；和/或，通过设置所述第一电容结构对应的第一介质层701在垂直于所述基底10的方向上的厚度，小于所述第三电容结构对应的第三介质层703在垂直于所述基底10的方向上的厚度，来实现所述第一电容结构的容值大于所述第三电容结构的容值。
示例性的，如图11所示，可设置所述第一介质层701的厚度小于所述第二介质层702的厚度，所述第二介质层702的厚度小于所述第三介质层703的厚度。进一步地，可设置所述第二介质层702的厚度与所述第一介质层701的厚度之间的差值在
Figure PCTCN2020103313-appb-000002
之间(可包括端点值)。
在一些实施例中，还可以设置所述第一电容结构的第二极板C1b中位于对应的第一交叠区域的部分包括的坡度角b2，大于所述第二电容结构的第二极板C2b中位于对应的第一交叠区域的部分包括的坡度角b4；和/或，所述第一电容结构的第二极板C1b中位于对应的第一交叠区域的部分包括的坡度角b2，大于所述第三电容结构的第二极板C3b中位于对应的第一交叠区域的部分包括的坡度角b6。
具体地，所述第二极板中位于对应的第一交叠区域的部分包括的坡度角越大，则该第二极板与对应的第一极板之间形成的正对面积越大，从而使得该第二极板形成的电容结构的容值越大；因此，通过设置所述第一电容结构的第二极板C1b中位于对应的第一交叠区域的部分包括的坡度角b2，大于所述第二电容结构的第二极板C2b中位于对应的第一交叠区域的部分包括的坡度角b4，可使得所述第一电容结构的电容值大于第二电容结构的电容值；通过所述第一电容结构的第二极板C1b中位于对应的第一交叠区域的部分包括 的坡度角b2，大于所述第三电容结构的第二极板C3b中位于对应的第一交叠区域的部分包括的坡度角b6，可使得所述第一电容结构的电容值大于第三电容结构的电容值。
可见，在设置电容结构的电容值时，可通过调节第一极板的极板目标坡度角，第二极板中位于对应的第一交叠区域的部分包括的坡度角，以及第一极板和第二极板之间的介质层的厚度，来实现电容结构容值的调节。
示例性的，所述第一电容结构中第一极板C1a对应的极板目标坡度角b1可设置在30°～55°之间，所述第一电容结构的第二极板C1b中位于对应的第一交叠区域的部分包括的坡度角b2在35°～85°之间，极板目标坡度角b1与坡度角b2之间角度相差12°～30°；所述第二电容结构中第一极板C2a对应的极板目标坡度角b3可设置在28°～52°之间；所述第三电容结构中第一极板C3a对应的极板目标坡度角b5可设置在25°～50°之间。
示例性的，所述第一电容结构中第一极板C1a对应的极板目标坡度角b1可设置在30°～55°之间，所述第一电容结构的第二极板C1b中位于对应的第一交叠区域的部分包括的坡度角b2在45°～85°之间，极板目标坡度角b1与坡度角b2之间角度相差15°～30°；所述第二电容结构中第一极板C2a对应的极板目标坡度角b3可设置在20°～45°之间，所述第二电容结构的第二极板C2b中位于对应的第一交叠区域的部分包括的坡度角b4在25°～50°之间，极板目标坡度角b3与坡度角b4之间角度相差10°～25°；所述第三电容结构中第一极板C3a对应的极板目标坡度角b5可设置在15°～30°之间，所述第三电容结构的第二极板C3b中位于对应的第一交叠区域的部分包括的坡度角b6在20°～40°之间，极板目标坡度角b5与坡度角b6之间角度相差5°～20°。
进一步地，可设置第一电容结构的容值为第二电容结构的容值的1.05～2.5倍，第一电容结构的容值为第三电容结构的容值的1.10～3倍。
值得注意，电容结构中，第一极板对应的极板目标坡度角越大，需要上层覆盖的第二极板的面积越大或介质层厚度越大。
如图12所示，在一些实施例中，在周边区域，第四电容结构C4的第一极板的极板目标坡度角大于第五电容结构C5的第一极板的极板目标坡度角， 因此需要设置第四电容结构C4的第二极板的右侧端部尽量向右侧延伸，以避免该第二极板在第四电容结构C4的第一极板的极板目标坡度角处脱落剥离。同样的，在显示区域，第六电容结构C6的第一极板的极板目标坡度角大于第七电容结构C7的第一极板的极板目标坡度角，因此需要设置第六电容结构C6的第二极板的右侧端部尽量向右侧延伸，以避免该第二极板在第六电容结构C6的第一极板的极板目标坡度角处脱落剥离。
需要说明，上述设置第四电容结构C4的第二极板的右侧端部尽量向右侧延伸，能够增加第四电容结构C4的第二极板与第一极板之间的正对面积。同样的，上述设置第六电容结构C6的第二极板的右侧端部尽量向右侧延伸，能够增加第六电容结构C6的第二极板与第一极板之间的正对面积。
值得注意，每个电容结构中第一极板均位于基底与第二极板之间，各电容结构中第二极板对第一极板的覆盖率可根据实际需要设置，示例性的，第七电容结构C7对应的覆盖率为100％，第六电容结构C6对应的覆盖率为40-60％。
需要说明，所述覆盖率具体指：所述第一极板被所述第二极板覆盖的面积占该第一极板整体面积的比值。从图12中能够看出第七电容结构C7的第二极板完全将第一极板覆盖，第六电容结构C6的第二极板覆盖了部分第一极板。
另外，位于所述第四电容结构C4中的介质层70的厚度和位于所述第五电容结构C5中的介质层70的厚度，可以与位于所述第六电容结构C6中的介质层70的厚度和位于所述第七电容结构C7中的介质层70的厚度不相等。示例性的，位于所述第四电容结构C4和所述第五电容结构C5中的介质层70可包括第二栅绝缘层和层间绝缘层；位于所述第六电容结构C6和所述第七电容结构C7中的介质层70可包括第二栅绝缘层。
需要说明，上述实施例提供的阵列基板中，第一栅极金属图形和第二栅极金属图形的厚度可均大于第一源漏金属图形的厚度和第二源漏金属图形的厚度，或者，第一栅极金属图形和第二栅极金属图形的厚度可均小于第一源漏金属图形的厚度和第二源漏金属图形的厚度。
第一栅极金属图形和第二栅极金属图形对应的坡度角可均大于第一源漏 金属图形的坡度角和第二源漏金属图形对应的坡度角，或者，第一栅极金属图形和第二栅极金属图形对应的坡度角可均小于第一源漏金属图形的坡度角和第二源漏金属图形对应的坡度角。
如图13和图14所示，在一些实施例中，所述第一功能层20包括复合金属图形，所述复合金属图形包括沿远离所述基底10的方向依次层叠设置的第一金属子图形213、第二金属子图形212和第三金属子图形211，所述第一金属子图形213与所述第三金属子图形211的材料相同；在刻蚀形成所述第一功能层20时，所述第一功能层20具有的目标坡度角与所述第三金属子图形211的刻蚀速率成反比。
具体地，金属层材料不同，会造成金属层坡度角在相同的刻蚀工艺下坡度角有差异，如图13所示，以所述第一金属子图形213和所述第三金属子图形211采用Ti，所述第二金属子图形212采用Al为例，即所述复合金属图形形成为Ti/Al/Ti复合金属膜层，当对Ti/Al/Ti复合金属图形进行湿法刻蚀的时候，由于Ti的腐蚀速率较慢，Ti会消耗更多的刻蚀液，使得Al接触到的刻蚀液浓度较低，刻蚀速率也变慢，从而导致Ti/Al/Ti金属图形的刻蚀坡度角较大(如：a10)，一般大于50度。在满足公式(1)的情况下，在Ti/Al/Ti金属图形之上沉积的第二功能层30(如第二功能膜层302)的厚度需要较厚，使得Tan(a)-1≤N(x-y)/y≤Tan(a)+1公式中的N增大，一般取上限0.9。
另外一方面，在第二功能层30厚度调整范围有限的情况下，可以调整刻蚀液的浓度等工艺参数，保证复合金属图形的坡度角满足要求。值得注意，除了将所述复合金属图形采用Ti/Al/Ti复合金属图形外，还可以将所述复合金属图形采用Mo/Al/Mo复合金属图形，但不仅限于此。
如图14所示，以所述第一金属子图形213和所述第三金属子图形211采用Mn，所述第二金属子图形212采用Cu为例，即所述复合金属图形形成为Mn/Cu/Mn复合金属膜层，当对Mn/Cu/Mn复合金属图形进行湿法刻蚀的时候，由于Mn的腐蚀速率较快，Mn会消耗更少的刻蚀液，使得Cu接触到的刻蚀液浓度较高，刻蚀速率加快，从而导致Mn/Cu/Mn金属图形的刻蚀坡度角较小(如：a11)，一般小于50度。在满足公式(1)的情况下，在Mn/Cu/Mn金属图形之上沉积的第二功能层30(如第二功能膜层302)的厚度需要较薄，使得 Tan(a)-1≤N(x-y)/y≤Tan(a)+1公式中的N减小，一般取下限0.8。另外一方面，在第二功能层30厚度调整范围有限的情况下，可以调整刻蚀液的浓度等工艺参数，保证复合金属图形的坡度角满足要求。值得注意，除了将所述复合金属图形采用Mn/Cu/Mn复合金属图形外，还可以将所述复合金属图形采用Mo/Cu/Mo复合金属图形，但不仅限于此。
可见，根据公式(1)确定出对应的目标坡度角后，可通过材料的选择和刻蚀工艺的控制，实现所需的目标坡度角。
本公开实施例还提供了一种显示装置，包括上述实施例提供的阵列基板。
由于上述实施例提供的阵列基板中，通过设置所述第一功能层20位于所述段差区域的部分具有目标坡度角，所述目标坡度角为所述第二功能层30满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层30在满足其自身功能需求、且在所述段差区域不会发生断裂的厚度；使得所述阵列基板在实现了所述第一功能层20具有最大的坡度角的同时，保证了所述第二功能层30具有满足其自身功能需求且在所述段差区域不会发生断裂的最小厚度，因此，上述实施例提供的阵列基板在保证所述功能层不断裂的情况下，实现了最大的坡度角和最薄的第二功能层30，使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
因此，本公开实施例提供的显示装置在包括上述实施例提供的阵列基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种阵列基板的制作方法，用于制作上述实施提供的阵列基板，所述制作方法包括：
在基底10上形成第一功能层20，所述第一功能层20在所述基底10上形成段差区域，所述第一功能层20位于所述段差区域的部分具有目标坡度角；
在所述第一功能层20远离所述基底10的一侧形成第二功能层30，所述第二功能层30覆盖所述段差区域；所述目标坡度角为所述第二功能层30满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层30在满足 其自身功能需求、且在所述段差区域不会发生断裂的厚度；
所述第一功能层的所述目标坡度角和所述第二功能层的预设厚度满足关系式：
Tan(a)-1≤N(x-y)/y≤Tan(a)+1；
其中，N＝z×W×K IC，z为常数，W为预设值，K IC为所述第二功能层的断裂韧性参数，x为所述第二功能层的预设厚度，y为所述第一功能层位于所述段差区域的部分的厚度，a为所述第一功能层的所述目标坡度角。
具体地，如图16所示，示出了低温多晶硅薄膜晶体管(Low Temperature Poly-silicon Thin Film Transistor，LTPS TFT)阵列基板，所述阵列基板中可包括：基底10、遮光层LS、缓冲层80、有源层82、栅极81、栅极绝缘层GI、层间绝缘层ILD、平坦层PLN、输入电极85、输出电极86、阴极层84、阳极83和LDD轻掺杂区域87；有源层可采用P-Si制作。图中示出了数据信号Vdata经薄膜晶体管传输至阳极。
在制作所述LTPS TFT阵列基板时，至少经过10次mask，具体说明如下：
第一次mask制作所述遮光层LS，具体步骤包括：先对基底10进行预清洗，然后对基板进行高温预压缩，以防止后续工序中高温制程造成基底10(可选为玻璃基底)收缩，进而导致出现对位偏差，然后在基板上沉积形成遮光材料层，并在该遮光材料层远离所述基底的表面制作光刻胶层，接着对该光刻胶层进行曝光、显影，并以剩余的光刻胶层为掩膜，采用湿法刻蚀工艺，对所述遮光材料层进行刻蚀，最后将剩余的光刻胶层剥离，形成所述遮光层LS。
第二次mask制作有源层82，具体步骤包括：进行清洗工艺(D/C Clean)，然后进行多层沉积工艺(multi-dep)，接着依次进行去氢化工艺(dehydrogen)、氢氟酸清洗工艺(D/C HF)、准分子激光退火工艺(ELA)、然后在多晶硅表面形成光刻胶层，对光刻胶层进行曝光、显影后，以剩余的光刻胶为掩膜，对多晶硅进行干法刻蚀，并最终将剩余的光刻胶层剥离，然后进行阈值电压掺杂，调节沟道区域本征态，从而调节Vth电压的工艺(即Vth doping)，和氢氟酸清洗工艺，最后通过化学气相沉积法形成栅极绝缘层。
第三次mask和第四次mask用于制作两个栅极81，其中一个栅极81(对 应PMOS)在第三次mask中形成，具体包括：进行清洗工艺，然后进行Mo金属的溅射工艺，形成Mo薄膜，然后对Mo薄膜进行构图工艺，该构图工艺包括：光刻胶层形成、曝光、显影、剥离等工艺，最后进行正离子掺杂(P+doping)，形成P-gate；另一个栅极81(对应NMOS)在第四次mask中，具体包括：继续进行构图工艺，并在最后进行负离子掺杂(N+doping)，灰化和干刻工艺，以及轻掺杂、灰化、剥离等工艺，形成N-gate。
第五次mask制作接触层，具体步骤包括：先进行清洗工艺，然后采用化学气相沉积法形成层间绝缘层ILD，然后进行预清洗，接着进行活化(activation)、氢化(hydrogen)、源漏层光刻(S/D photo)、干刻、剥离等工艺；
第六次mask制作输入电极85和输出电极86，具体步骤包括：刻蚀(Etch)，溅射形成Ti/Al/Ti复合金属层，然后对还复合金属层进行构图工艺，该构图工艺依次包括：光刻胶层形成、曝光、显影、干刻工艺以及剥离剩余光刻胶的过程，最后进行退火(Anneal)。
第七次mask制作用于连接阳极83与输出电极86的过孔，具体步骤包括：形成平坦层PLN，具体可采用丙烯酸树脂，通过coating工艺形成，然后采用构图工艺在PLN上形成能够暴露输出电极86的过孔，最后进行固化工艺。
第八次mask制作阴极层84，具体步骤包括：预处理(descum)工艺，然后进行清洗工艺，接着采用溅射工艺形成氧化铟锡(ITO)膜层，对该ITO膜层进行构图工艺，该构图工艺依次包括：形成光刻胶层、曝光、显影、湿法刻蚀以及剥离剩余光刻胶层工艺，最后形成所述阴极层84。
第九次mask制作钝化层PVX，具体步骤包括：先进行清洗工艺、然后采用化学气相沉积法形成钝化层，然后对该钝化层进行构图工艺，该工艺具体包括：形成光刻胶层、曝光、显影、干法刻蚀以及最终将剩余的光刻胶层去除，最终形成具有能够暴露输出电极86的过孔的钝化层PVX。
第十次mask制作阳极83，具体步骤包括：先进行清洗工艺，然后溅射形成氧化铟锡(ITO)膜层，对该ITO膜层进行构图工艺，该构图工艺依次包括：形成光刻胶层、曝光、显影、灰化工艺、湿法刻蚀以及剥离剩余光刻胶层工艺，然后进行退火(Anneal)，最后形成所述阳极83。
完成阵列基板的制作后，可对阵列基板进行测试，测试没有问题后，可进行该阵列基板的出厂。
具体地，如图17～图30所示，示出了有机发光二极管(Organic Light-Emitting Diode，OLED)阵列基板的制作流程，下面对OLED阵列基板的具体制作流程进行说明。
如图17所示，先采用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)，在基底10上依次形成第一缓冲层11和第二缓冲层12，所述第一缓冲层11可具体选用SiNx材料制作，厚度为
Figure PCTCN2020103313-appb-000003
所述第二缓冲层12可具体选用SiOx材料制作，厚度为
Figure PCTCN2020103313-appb-000004
如图18和图19所示，制作有源层的步骤：进行初步清洗(initial clean)工作，然后采用PECVD方法，在所述第二缓冲层12远离所述基底的表面沉积非晶硅(a-Si)材料形成有源薄膜13，然后进行预清洗工作，接着进行准分子激光退火(ELA)工艺和光刻工艺，形成多晶硅(Poly-Si)材质的有源层82，该有源层82的厚度为
Figure PCTCN2020103313-appb-000005
如图20所示，采用PECVD方法，继续沉积SiOx材料形成第一栅极绝缘层GI1，所述第一栅极绝缘层GI1的厚度为
Figure PCTCN2020103313-appb-000006
如图21所示，进行Mo金属的溅射工艺，形成Mo薄膜，然后对Mo薄膜进行构图工艺，该构图工艺包括：光刻胶层形成、曝光、显影、剥离等工艺，最后进行离子掺杂形成第一栅金属图形13，所述第一栅金属图形13的厚度为
Figure PCTCN2020103313-appb-000007
如图22所示，继续进行重掺杂工艺(B2H6 Heavy Doping)。
如图23所示，采用PECVD方法，继续沉积SiNx材料形成第二栅极绝缘层GI2，所述第二栅极绝缘层GI2的厚度为
Figure PCTCN2020103313-appb-000008
如图24所示，进行Mo金属的溅射工艺，形成Mo薄膜，然后对Mo薄膜进行构图工艺，该构图工艺包括：光刻胶层形成、曝光、显影、剥离等工艺，最后进行离子掺杂形成第二栅金属图形14，以及贯穿所述第二栅金属图形14的过孔，所述第二栅金属图形14的厚度为
Figure PCTCN2020103313-appb-000009
如图25所示，采用PECVD方法，继续沉积SiOx材料形成层间绝缘层ILD，所述层间绝缘层ILD的厚度为
Figure PCTCN2020103313-appb-000010
如图26所示，采用光刻工艺，形成贯穿所述第一栅极绝缘层GI1、所述第二栅极绝缘层GI2和所述层间绝缘层ILD的过孔，将部分所述第一栅金属图形13暴露出来。
如图27所示，进行Ti/Al/Ti金属的溅射工艺，形成层叠设置的Ti/Al/Ti薄膜，其中Ti薄膜的厚度为
Figure PCTCN2020103313-appb-000011
Al薄膜的厚度为
Figure PCTCN2020103313-appb-000012
对Ti/Al/Ti薄膜进行构图工艺，形成位于过孔中的源漏金属图形15。
如图28所示，继续采用有机材料制作平坦层PLN，所述平坦层PLN的厚度为
Figure PCTCN2020103313-appb-000013
对所述平坦层进行构图形成暴露所述源漏金属图形15的过孔。
如图29所示，进行ITO/Ag/ITO金属的溅射工艺，形成层叠设置的ITO/Ag/ITO薄膜，其中ITO的厚度为
Figure PCTCN2020103313-appb-000014
Ag的厚度为
Figure PCTCN2020103313-appb-000015
对ITO/Ag/ITO薄膜进行构图工艺，形成位于过孔中的阳极图形15。
如图30所示，继续采用有机材料制作像素界定层PDL，所述像素界定层PDL的厚度为
Figure PCTCN2020103313-appb-000016
对所述像素界定层PDL进行构图工艺，形成能够暴露部分阳极图形15的像素开口。
采用本公开实施例提供的制作方法制作的阵列基板中，通过设置所述第一功能层20位于所述段差区域的部分具有目标坡度角，所述目标坡度角为所述第二功能层30满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层30在满足其自身功能需求、且在所述段差区域不会发生断裂的厚度；使得所述阵列基板在实现了所述第一功能层20具有最大的坡度角的同时，保证了所述第二功能层30具有满足其自身功能需求、且在所述段差区域不会发生断裂的最小厚度，因此，采用本公开实施例提供的制作方法制作的阵列基板在保证所述功能层不断裂的情况下，实现了最大的坡度角和最薄的第二功能层30，使得阵列基板能够更好的应用于薄型化以及高分辨率显示产品中，同时更好的提升阵列基板的产品良率，降低原材料成本。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属 领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：基底，以及层叠设置在所述基底上的第一功能层和第二功能层；
    所述第一功能层在所述基底上形成段差区域，所述第二功能层覆盖所述段差区域；
    所述第一功能层位于所述段差区域的部分具有目标坡度角，所述目标坡度角为所述第二功能层满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层在满足其自身功能需求、且在所述段差区域不会发生断裂的厚度；
    所述第一功能层的所述目标坡度角和所述第二功能层的所述预设厚度满足关系式：
    Tan(a)-1≤N(x-y)/y≤Tan(a)+1；
    其中，N＝z×W×K IC，z为常数，W为预设值，K IC为所述第二功能层的断裂韧性参数，x为所述第二功能层的预设厚度，y为所述第一功能层位于所述段差区域的部分的厚度，a为所述第一功能层的所述目标坡度角。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一功能层包括第一功能图形，所述第一功能图形在所述基底上形成第一段差区域；
    所述第二功能层包括：第一功能膜层和第二功能膜层；所述第一功能膜层，设置于所述第一功能图形远离所述基底的一侧，所述第二功能膜层，设置于所述第一功能膜层远离所述基底的一侧；
    所述第一功能膜层和所述第二功能膜层均覆盖所述第一段差区域，所述第一功能膜层和所述第二功能膜层的断裂韧性参数大致相同；
    所述第一功能膜层的厚度均匀，所述第二功能膜层的厚度均匀；
    所述第一功能图形位于所述第一段差区域的部分具有第一目标坡度角，所述第一目标坡度角为所述第一功能膜层和所述第二功能膜层满足第一预设厚度条件下的最大坡度角；
    所述第一预设厚度为所述第一功能膜层和所述第二功能膜层在满足各自 功能需求、且在所述第一段差区域均不发生断裂时，所述第一功能膜层具有的厚度与所述第二功能膜层具有的厚度之和。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第一功能层还包括第二功能图形，所述第二功能图形与所述第一功能图形同层同材料设置，所述第二功能图形在所述基底上形成第二段差区域；
    所述第一功能膜层覆盖所述第二段差区域；
    所述第二功能图形位于所述第二段差区域的部分具有第二目标坡度角，所述第二目标坡度角为所述第一功能膜层满足第二预设厚度条件下的最大坡度角；
    所述第二预设厚度为所述第一功能膜层在满足其自身功能需求且在所述第二段差区域不发生断裂的厚度；
    所述第二目标坡度角小于所述第一目标坡度角。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一功能层还包括第三功能图形，所述第三功能图形位于所述第一功能膜层远离所述基底的一侧，所述第三功能图形在所述基底上形成第三段差区域；
    所述第二功能膜层覆盖所述第三段差区域；
    所述第三功能图形位于所述第三段差区域的部分具有第三目标坡度角，所述第三目标坡度角为所述第二功能膜层满足第三预设厚度条件下的最大坡度角；所述第三预设厚度为所述第二功能膜层在满足其自身功能需求且在所述第三段差区域不发生断裂时的厚度；
    所述第三目标坡度角大于所述第二目标坡度角，小于所述第一目标坡度角。
  5. 根据权利要求1所述的阵列基板，其中，
    所述第一功能层包括第四功能图形，所述第四功能图形在所述基底上形成沿远离所述基底的方向依次排布的至少两个第四段差区域；
    所述第二功能层包括设置于所述第四功能图形远离所述基底的一侧，所述平坦层完全覆盖所述第四功能图形；
    所述第四功能图形位于各所述第四段差区域的部分具有对应的第四目标 坡度角，该第四目标坡度角为：所述平坦层中位于该第四目标坡度角对应的第四段差区域的第一部分在满足第四预设厚度条件下的最大坡度角；该第四预设厚度为所述第一部分在满足其自身功能需求且在所述第四段差区域不发生断裂时的最薄厚度。
  6. 根据权利要求5所述的阵列基板，其中，
    所述第一功能层包括第一功能图形，所述第一功能图形在所述基底上形成第一段差区域；
    所述第二功能层包括：第一功能膜层和第二功能膜层；所述第一功能膜层，设置于所述第一功能图形远离所述基底的一侧，所述第二功能膜层，设置于所述第一功能膜层远离所述基底的一侧；所述第一功能膜层和所述第二功能膜层均覆盖所述第一段差区域；
    所述第四功能图形位于所述第二功能膜层远离所述基底的一侧，所述第四功能图形覆盖所述第一段差区域。
  7. 根据权利要求5所述的阵列基板，其中，所述平坦层包括第一平坦层和第二平坦层，所述第一功能层还包括另一第四功能图形所述另一第四功能图形位于所述第一平坦层远离所述基底的一侧，且所述另一第四功能图形在所述基底上形成另一第四段差区域，所述另一第四功能图形位于所述另一第四段差区域的部分具有另一第四目标坡度角，所述第二平坦层覆盖所述另一第四功能图形。
  8. 根据权利要求1所述的阵列基板，其中，
    所述第一功能层包括沿远离所述基底的方向依次层叠设置的第五功能图形和第六功能图形；
    所述第二功能层包括设置于所述第五功能图形和所述第六功能图形之间的第二功能膜层，以及设置于所述第六功能图形远离所述基底的一侧的平坦层；其中，所述第二功能膜层上设置有第一过孔，所述第二功能膜层在所述第一过孔的边缘形成第五段差区域；
    所述第二功能膜层位于所述第五段差区域的部分具有第五目标坡度角；
    所述第六功能图形通过所述第一过孔与所述第五功能图形耦接，所述第六功能图形覆盖所述第五段差区域，在所述第五段差区域对应的位置形成第 六段差区域；
    所述第六功能图形位于所述第六段差区域的部分具有第六目标坡度角，所述第六目标坡度角为：所述平坦层中位于所述第六段差区域的第二部分满足第六预设厚度条件下的最大坡度角；该第六预设厚度为所述第二部分在满足其自身功能需求且在所述第六段差区域不发生断裂时的最薄厚度；
    所述第五目标坡度角，与所述第六目标坡度角大致相等。
  9. 根据权利要求1所述的阵列基板，其中，所述第一功能层包括：
    设置于所述基底上的第七功能图形，所述第七功能图形在所述基底上形成第七段差区域；
    设置于所述第七功能图形远离所述基底的一侧的第八功能图形，所述第八功能图形包括：覆盖所述第七段差区域的第三部分，覆盖所述第七功能图形除位于所述第七段差区域之外的其余部分的第四部分，以及未覆盖所述第七功能图形的第五部分；
    设置于所述第八功能图形远离所述基底的一侧的平坦层，所述平坦层上设置有第二过孔，所述第二过孔在所述基底上的正投影位于所述第八功能图形在所述基底上的正投影的内部，所述平坦层在所述第二过孔的边缘形成第八段差区域和第九段差区域，所述第八段差区域在所述基底上的正投影与所述第四部分在所述基底上的正投影交叠，所述第九段差区域在所述基底上的正投影与所述第五部分在所述基底上的正投影交叠；
    所述第二功能层包括第二功能膜层和第九功能图形；其中，所述第二功能膜层位于所述第七功能图形和所述第八功能图形之间，所述第九功能图形位于所述平坦层远离所述基底的一侧，且通过所述第二过孔与所述第八功能图形耦接；所述第九功能图形覆盖所述第八段差区域和所述第九段差区域；所述第九功能图形厚度均匀；
    所述平坦层位于所述第八段差区域的部分具有第八目标坡度角，所述第八目标坡度角为：所述第九功能图形满足第八预设厚度条件下的最大坡度角；该第八预设厚度为所述第九功能图形在满足其自身功能需求且在所述第八段差区域不发生断裂时的厚度；
    所述平坦层位于所述第九段差区域的部分具有第九目标坡度角，所述第 九目标坡度角为：所述第九功能图形满足第九预设厚度条件下的最大坡度角；该第九预设厚度为所述第九功能图形在满足其自身功能需求且在所述第九段差区域不发生断裂时的厚度。
  10. 根据权利要求9所述的阵列基板，其中，所述第七功能图形在所述基底上的正投影与所述第八功能图形在所述基底上的正投影形成第一交叠区域，所述第一交叠区域沿第一方向具有第一尺寸；
    所述第八功能图形中没有位于所述第一交叠区域的部分沿所述第一方向具有第二尺寸；
    所述第九功能图形与所述第八功能图形形成第一接触区域，沿所述第一方向，所述第一接触区域的边界与所述第八功能图形的第一端之间的最小距离为第一间距，所述第一接触区域的边界与所述第八功能图形的第二端之间的最小距离为第二间距；所述第一端与所述第二端沿所述第一方向相对，所述第一端在所述基底上的正投影与所述第七功能图形交叠，所述第二端在所述基底上的正投影与所述第七功能图形不交叠；
    所述第一尺寸与所述第二尺寸之间的差值对应的第一绝对值，与所述第一间距与所述第二间距之间的差值对应的第二绝对值成正比。
  11. 根据权利要求10所述的阵列基板，其中，所述第一间距与所述第二间距之间的差值对应的第二绝对值，与所述第一间距与所述第八功能图形沿所述第一方向上的第一宽度的比值成正比。
  12. 根据权利要求10所述的阵列基板，其中，
    当所述第一尺寸大于所述第一间距时，所述第八目标坡度角大于所述第九目标坡度角；或者，
    所述第八目标坡度角与所述第九目标坡度角之间的差值，与所述第一尺寸成正比。
  13. 根据权利要求10所述的阵列基板，其中，所述第八目标坡度角与所述第九目标坡度角之间的差值小于所述第七功能图形在所述第七段差区域具有的第七目标坡度角；
    所述第七目标坡度角为所述第二功能膜层满足第七预设厚度条件下的最大坡度角；所述第七预设厚度为所述第二功能膜层在满足其自身功能需求且 在所述第七段差区域不会发生断裂的厚度。
  14. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括电容结构；
    所述第一功能层包括所述电容结构的第一极板，所述第一极板在所述基底上形成极板段差区域；
    所述第二功能层包括位于所述第一极板远离所述基底的一侧的介质层，所述介质层完全覆盖所述第一极板；所述第一极板位于所述极板段差区域的部分具有极板目标坡度角，所述极板目标坡度角为所述介质层满足第十预设厚度条件下的最大坡度角；所述第十预设厚度为所述介质层在满足其自身功能需求且在所述极板段差区域不会发生断裂的厚度；
    所述电容结构的第二极板位于所述介质层远离所述基底的一侧，所述第二极板在所述基底上的正投影与所述第一极板在所述基底上的正投影形成第一交叠区域，所述第二极板覆盖所述极板段差区域。
  15. 根据权利要求14所述的阵列基板，其中，所述电容结构包括：第一电容结构、第二电容结构和第三电容结构；所述第一电容结构的容值大于所述第二电容结构的容值，和/或所述第一电容结构的容值大于所述第三电容结构的容值；
    所述第一电容结构的第一极板对应的极板目标坡度角，大于所述第二电容结构的第一极板对应的极板目标坡度角；和/或，所述第一电容结构的第一极板对应的极板目标坡度角，大于所述第三电容结构的第一极板对应的极板目标坡度角。
  16. 根据权利要求15所述的阵列基板，其中，
    所述第一电容结构对应的第一介质层的厚度，小于所述第二电容结构对应的第二介质层的厚度；和/或，
    所述第一电容结构对应的第一介质层的厚度，小于所述第三电容结构对应的第三介质层的厚度。
  17. 根据权利要求15所述的阵列基板，其中，
    所述第一电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角，大于所述第二电容结构的第二极板中位于对应的第一交叠区域的部 分包括的坡度角；和/或，
    所述第一电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角，大于所述第三电容结构的第二极板中位于对应的第一交叠区域的部分包括的坡度角。
  18. 根据权利要求1所述的阵列基板，其中，所述第一功能层包括复合金属图形，所述复合金属图形包括沿远离所述基底的方向依次层叠设置的第一金属子图形、第二金属子图形和第三金属子图形，所述第一金属子图形与所述第三金属子图形的材料相同；
    在刻蚀形成所述第一功能层时，所述第一功能层具有的目标坡度角与所述第三金属子图形的刻蚀速率成反比。
  19. 一种显示装置，包括如权利要求1～18中任一项所述的阵列基板。
  20. 一种阵列基板的制作方法，用于制作如权利要求1～18中任一项所述的阵列基板，包括：
    在基底上形成第一功能层，所述第一功能层在所述基底上形成段差区域，所述第一功能层位于所述段差区域的部分具有目标坡度角；
    在所述第一功能层远离所述基底的一侧形成第二功能层，所述第二功能层覆盖所述段差区域；所述目标坡度角为所述第二功能层满足预设厚度条件下的最大坡度角；所述预设厚度为所述第二功能层在满足其自身功能需求、且在所述段差区域不会发生断裂的厚度；
    所述第一功能层的所述目标坡度角和所述第二功能层的预设厚度满足关系式：
    Tan(a)-1≤N(x-y)/y≤Tan(a)+1；
    其中，N＝z×W×K IC，z为常数，W为预设值，K IC为所述第二功能层的断裂韧性参数，x为所述第二功能层的预设厚度，y为所述第一功能层位于所述段差区域的部分的厚度，a为所述第一功能层的所述目标坡度角。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112071843A (zh) * 2020-09-18 2020-12-11 长江存储科技有限责任公司 半导体结构及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111244117B (zh) 2020-04-24 2020-07-28 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN115831047A (zh) * 2020-11-27 2023-03-21 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示基板及显示装置
CN117280891A (zh) * 2022-04-19 2023-12-22 京东方科技集团股份有限公司 显示基板及制作方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040018749A1 (en) * 2002-07-08 2004-01-29 Dorfman Benjamin F. Method of decreasing brittleness of single crystals, semiconductor wafers, and solid-state devices
CN101779280A (zh) * 2007-08-09 2010-07-14 国际商业机器公司 多层互连的波纹界面
CN107579081A (zh) * 2017-09-27 2018-01-12 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN111244117A (zh) * 2020-04-24 2020-06-05 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI250337B (en) * 1998-02-09 2006-03-01 Seiko Epson Corp An electro-optical apparatus and electronic appliances
JP4092851B2 (ja) * 2000-04-19 2008-05-28 セイコーエプソン株式会社 電気光学装置、電気光学装置の製造方法及び電子機器
KR20110116803A (ko) * 2010-04-20 2011-10-26 삼성전자주식회사 표시 기판, 이를 포함하는 액정 표시 장치 및 이의 제조 방법
US9040432B2 (en) * 2013-02-22 2015-05-26 International Business Machines Corporation Method for facilitating crack initiation during controlled substrate spalling
CN103412444B (zh) * 2013-07-23 2015-08-26 北京京东方光电科技有限公司 一种阵列基板及其制作方法和显示面板
JP6545394B2 (ja) * 2016-08-22 2019-07-17 三菱電機株式会社 半導体装置
CN108666347B (zh) * 2018-04-26 2021-07-30 上海天马微电子有限公司 显示面板及其制造方法、显示装置
CN209447790U (zh) * 2019-03-15 2019-09-27 浙江荷清柔性电子技术有限公司 半导体器件互连装置及柔性电路板
CN109873025B (zh) 2019-04-11 2021-10-08 京东方科技集团股份有限公司 有机发光二极管阵列基板及显示装置
CN110212118B (zh) * 2019-07-19 2021-07-16 武汉天马微电子有限公司 显示面板及其制备方法、显示装置
CN114144886B (zh) * 2020-05-15 2023-01-31 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040018749A1 (en) * 2002-07-08 2004-01-29 Dorfman Benjamin F. Method of decreasing brittleness of single crystals, semiconductor wafers, and solid-state devices
CN101779280A (zh) * 2007-08-09 2010-07-14 国际商业机器公司 多层互连的波纹界面
CN107579081A (zh) * 2017-09-27 2018-01-12 上海天马有机发光显示技术有限公司 一种显示面板和显示装置
CN111244117A (zh) * 2020-04-24 2020-06-05 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4141934A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112071843A (zh) * 2020-09-18 2020-12-11 长江存储科技有限责任公司 半导体结构及其制造方法

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