WO2021203969A1 - 反熔丝器件及反熔丝单元 - Google Patents

反熔丝器件及反熔丝单元 Download PDF

Info

Publication number
WO2021203969A1
WO2021203969A1 PCT/CN2021/082650 CN2021082650W WO2021203969A1 WO 2021203969 A1 WO2021203969 A1 WO 2021203969A1 CN 2021082650 W CN2021082650 W CN 2021082650W WO 2021203969 A1 WO2021203969 A1 WO 2021203969A1
Authority
WO
WIPO (PCT)
Prior art keywords
fuse
doped region
gate
substrate
drain
Prior art date
Application number
PCT/CN2021/082650
Other languages
English (en)
French (fr)
Inventor
刘志拯
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/310,896 priority Critical patent/US11985818B2/en
Publication of WO2021203969A1 publication Critical patent/WO2021203969A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
    • G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
    • G11C2229/76—Storage technology used for the repair
    • G11C2229/763—E-fuses, e.g. electric fuses or antifuses, floating gate transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • the invention relates to an anti-fuse device and an anti-fuse unit.
  • redundant memory cells There are usually redundant memory cells on the DRAM chip, and these redundant memory cells can replace the defective memory cells when the DRAM chip generates defective memory cells to achieve the purpose of repairing the DRAM.
  • OTP one-time-programmable
  • a first aspect of the present invention provides an anti-fuse device, the anti-fuse device including:
  • An anti-fuse gate the anti-fuse gate is partially embedded in the substrate, and the portion of the anti-fuse gate embedded in the substrate has sharp corners;
  • An anti-fuse gate oxide layer is located between the anti-fuse gate and the substrate.
  • a second aspect of the present invention provides an anti-fuse unit, the anti-fuse unit including:
  • FIG. 1 is a schematic diagram showing the structure of an anti-fuse device according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram showing the structure of an anti-fuse device according to another embodiment of the present invention.
  • Figure 3 is a structural diagram of an anti-fuse unit in one of the embodiments of the present invention.
  • FIG. 4 is a structural diagram of an anti-fuse unit in other optional embodiments of the present invention.
  • Fig. 5 is a structural diagram of an anti-fuse unit in another embodiment of the present invention.
  • the breakdown of the anti-fuse device is unstable.
  • some products may not break down, which affects the yield of the product.
  • the present invention provides an anti-fuse device.
  • the anti-fuse device 20 includes a substrate 10, an anti-fuse gate 11, and an anti-fuse gate oxide layer 12.
  • the anti-fuse gate 11 part Embedded in the substrate 10, and the part of the anti-fuse gate 11 embedded in the substrate 10 has sharp corners, the anti-fuse gate oxide layer 12 is located between the anti-fuse gate 11 and the substrate 10, so the gate oxide layer is the same It is embedded in the substrate 10 and has sharp corners.
  • the thickness of the gate oxide layer 12 at the sharp corners is thinner than that at other locations, and the sharp corners are prone to tip discharge, so the gate oxide layer 12 at the sharp corners is more likely to be hit Put on.
  • the substrate 10 also has a shallow trench isolation structure 13, and the anti-fuse gate 11 is embedded in the substrate 10 and the shallow trench isolation structure 13 at the same time, and can be formed by the following process:
  • the upper surface of the bottom 10 is spin-coated to form a mask layer and pattern the mask layer.
  • the patterned mask layer exposes part of the substrate 10 and part of the shallow trench isolation structure 13, and the exposed part of the substrate 10 and the shallow trench are etched.
  • the trench isolation structure 13 is partially formed to form a groove. Because the etching selection ratio of the substrate 10 and the shallow trench isolation structure 13 are different, the shallow trench isolation structure 13 is etched deeper than the substrate 10, so the groove is shallower.
  • a sharp corner is formed at the junction of the trench isolation structure 13 and the substrate 10; an anti-fuse gate oxide layer 12 is formed on the inner wall of the groove and the surface of the substrate 10 and deposited to form an anti-fuse gate 11, and the anti-fuse gate 11 is filled With full grooves, the anti-fuse gate 11 and the anti-fuse gate oxide layer 12 obtained in this way have sharp corners inside the substrate 10, and the number of sharp corners can be no less than 2, and there are multiple breakdown points The uniformity of the anti-fuse devices 20 produced in the same batch is better, and the consistency of the performance of a batch of products is improved.
  • the sharp angle may be a right angle or an obtuse angle.
  • the depth of the anti-fuse gate 11 embedded in the shallow trench isolation structure 13 is greater than the depth of the anti-fuse gate 11 embedded in the substrate 10, which makes the anti-fuse gate oxide layer 12 and
  • the contact area of the substrate 10 is larger, which increases the effective area of the antifuse gate oxide layer 12. Since the effective area of the bent antifuse gate oxide layer 12 is larger, the antifuse device 20 can be installed in a smaller size. The size can also have a sufficient area of the anti-fuse gate oxide layer 12, which is beneficial to the miniaturization of the anti-fuse device 20.
  • the thickness of the anti-fuse gate oxide layer 12 at the sharp corners is smaller than the thickness of the anti-fuse gate oxide layer 12 at the non-sharp corners, and the oxygen concentration and the reaction area are controlled during the formation process.
  • the area of the anti-fuse layer at the sharp corners is thinner, and the thickness of the anti-fuse oxide layer 12 at the sharp corners is smaller, which is more conducive to the tip discharge breakdown of the anti-fuse gate oxide layer 12.
  • the anti-fuse device 20 further includes a heavily doped region 14, which is located in the substrate 10, and is located at a portion of the anti-fuse gate 11 away from the shallow trench isolation structure 13 On the other hand, the heavily doped region 14 makes the anti-fuse device 20 more easily broken down.
  • the anti-fuse device 20 further includes an anti-fuse injection region 15, the anti-fuse injection region 15 is located inside the substrate 10, and the anti-fuse injection region 15 covers With the anti-fuse gate 11 embedded in the substrate 10, the anti-fuse device 20 covered by the anti-fuse injection region 15 is more likely to be broken down.
  • the doping concentration of the anti-fuse injection region 15 can be controlled.
  • the breakdown voltage of the anti-fuse device 20 is controlled; specifically, the greater the doping concentration of the anti-fuse injection region 15 is, the smaller the breakdown voltage of the anti-fuse device 20 is, and the two have a negative correlation.
  • the anti-fuse injection region 15 is also covered with the heavily doped region 14.
  • the doping type of the heavily doped region 14 and the anti-fuse injection region 15 are both N-type doping, both can be formed by ion implantation.
  • the present invention also provides an anti-fuse unit.
  • the anti-fuse unit includes the anti-fuse device 20 and the transistor 30 in the above embodiment, wherein the transistor 30 is located far away from the anti-fuse gate 11
  • the transistor 30 On one side of the shallow trench isolation 13, the transistor 30 has a source doped region, a drain doped region 16, a gate 17 and a gate oxide layer 19, and the source doped region is electrically connected to the anti-fuse device 20.
  • the thickness of the anti-fuse gate oxide layer 12 is less than or equal to the thickness of the gate oxide layer 19 of the transistor 30.
  • the source doped region of the transistor 30 is overlapped with the heavily doped region 14
  • the doped region 14 overlaps.
  • the source doped region of the transistor 30 can be the same region as the heavily doped region 14; of course, in other examples, the drain doped region of the transistor 30 can also be heavily doped.
  • the regions 14 overlap. At this time, the source doped region is located on the side of the gate 17 away from the anti-fuse device 20.
  • both the periphery of the drain doped region 16 and the periphery of the heavily doped region 14 of the transistor 30 are formed with a lightly doped drain structure 18.
  • neither the periphery of the drain doped region 16 nor the periphery of the heavily doped region 14 of the transistor 30 is formed with a lightly doped drain structure 18.
  • the edge of the drain doped region 16 of the transistor 30 has a lightly doped drain structure 18, so that The transistor 30 is an asymmetrical transistor 30.
  • the two sides of the gate are asymmetrical, and the resistance on the side without the lightly doped drain structure 18 is smaller.
  • the lightly doped drain structure 18 may only be located on the side of the drain doped region 16 adjacent to the gate 17, and the lightly doped drain structure 18 makes the breakdown voltage of the drain doped region 16 in the vertical direction higher .
  • the upper surface of the lightly doped drain structure 18 is flush with the upper surface of the drain doped region 16, and the lower surface is higher than the lower surface of the drain doped region 16, reducing the lightly doped drain structure 18 The resistance rises.
  • the lightly doped drain structure 18 may also be located only on the side of the heavily doped region 14 adjacent to the gate 17.
  • the anti-fuse device 20 of the present application makes the anti-fuse gate 11 and the anti-fuse gate oxide layer 12 have sharp corners inside the substrate 10, so that the anti-fuse device 20 has multiple tips.
  • the discharge point is easier to be broken down.
  • multiple breakdown points the uniformity of the anti-fuse device 20 produced in the same batch is better, and the consistency of the performance of a batch of products is improved.
  • the bent anti-fuse The effective area of the gate oxide layer 12 is larger, so that the anti-fuse device 20 can obtain a larger area of the anti-fuse gate oxide layer 12 with a smaller size, which is beneficial to the miniaturization of the anti-fuse device 20.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Fuses (AREA)

Abstract

一种反熔丝器件，反熔丝器件包括：衬底；反熔丝栅极，反熔丝栅极部分嵌入衬底内，反熔丝栅极嵌入衬底内的部分具有尖角；以及反熔丝栅氧化层，反熔丝栅氧化层位于反熔丝栅极与衬底之间。

Description

反熔丝器件及反熔丝单元
相关申请交叉引用
本申请要求2020年04月08日递交的、标题为“反熔丝器件及反熔丝单元”、申请号为2020102684010的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及一种反熔丝器件及反熔丝单元。
背景技术
在DRAM芯片上通常会有冗余存储单元，这些冗余存储单元可以在DRAM芯片产生缺陷存储单元时替换缺陷存储单元以达到修复DRAM的目的。在对DRAM芯片进行修复时，会借助到一次可编程(OTP，one time program)器件，如反熔丝单元。
发明内容
根据多个实施例，本发明第一方面提供一种反熔丝器件，所述反熔丝器件包括：
衬底；
反熔丝栅极，所述反熔丝栅极部分嵌入所述衬底内，所述反熔丝栅极嵌入所述衬底内的部分具有尖角；以及
反熔丝栅氧化层，所述反熔丝栅氧化层位于所述反熔丝栅极与所述衬底之间。
根据多个实施例，本发明第二方面提供一种反熔丝单元，所述反熔丝单元包括：
上述的反熔丝器件；以及
晶体管，位于所述反熔丝栅极远离所述浅沟槽隔离结构的一侧，所述晶体管具有源极掺杂区和漏极掺杂区，所述源极掺杂区或所述漏极掺杂区与所述反熔丝器件电连接。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明一个实施例展示反熔丝器件的结构示意图；
图2为本发明另一个实施例展示反熔丝器件的结构示意图；
图3为本发明其中一个实施例中反熔丝单元的结构图；
图4为本发明的其他可选的实施例中反熔丝单元的结构图；
图5为本发明的另一个实施例中反熔丝单元的结构图。
附图标记：10、衬底；11、反熔丝栅极；12、反熔丝栅氧化层；13、浅沟槽隔离结构；14、重掺杂区；15、反熔丝注入区；16、漏极掺杂区；17、栅极；18、轻掺杂漏结构；19、栅极氧化层；20、反熔丝器件；30、晶体管。
具体实施方式
在现有技术中，反熔丝器件的击穿存在不稳定的情况，当栅极接击穿电压时会出现部分产品并未击穿的情况，影响产品的良率。
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、 “水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
如图1所示，本发明提供了一种反熔丝器件，该反熔丝器件20包括衬底10、反熔丝栅极11和反熔丝栅氧化层12，反熔丝栅极11部分嵌入衬底10内，且反熔丝栅极11嵌入衬底10内的部分具有尖角，反熔丝栅氧化层12位于反熔丝栅极11和衬底10之间，因此栅氧化层同样嵌入衬底10内部，且具有尖角，尖角处的栅氧化层12的厚度相比其他位置的更薄，且尖角容易产生尖端放电，因此尖角处的栅氧化层12更容易被击穿。
在一个可选的实施例中，衬底10内还具有浅沟槽隔离结构13，反熔丝栅极11同时嵌入衬底10及浅沟槽隔离结构13内部，可以通过以下过程形成：于衬底10上表面旋涂形成掩膜层并图形化掩膜层，图形化过后的掩膜层暴露出部分衬底10和部分浅沟槽隔离结构13，刻蚀暴露出的衬底10部分和浅沟槽隔离结构13部分以形成凹槽，由于衬底10和浅沟槽隔离结构13的刻蚀选择比不同，导致浅沟槽隔离结构13比衬底10刻蚀的更深，因此凹槽在浅沟槽隔离结构13与衬底10交界处形成尖角；于凹槽的内壁和衬底10表面形成反熔丝栅氧化层12并沉积形成反熔丝栅极11，反熔丝栅极11填满凹槽，这样获得的反熔丝栅极11和反熔丝栅氧化层12在衬底10内部均是具有尖角的，且尖角的数量可以不小于2，有了多个击穿点使得同一批次生产的反熔丝器件20的均匀性更好，提高了一批次产品性能的一致性。在一个可选的实施例中，尖角可以为直角或者是钝角。
在一个可选的实施例中，反熔丝栅极11嵌入浅沟槽隔离结构13内的深度大于反熔丝栅极11嵌入衬底10内的深度，这使得反熔丝栅氧化层12与衬底10接触的面积更大，提高了反熔丝栅氧化层12的有效面积，由于弯折的反熔丝栅氧化层12有效面积更大，因此使得反熔丝器件20能够在更小的尺寸也能够有足够的反熔丝栅氧化层12面积，有利于反熔丝器件20的小型化。
在一个可选的实施例中，尖角处的反熔丝栅氧化层12的厚度小于非尖角处的反熔丝栅氧化层12的厚度，在形成的过程中通过控制氧气浓度和反应面积使得尖角处的反熔丝化层面积更薄，尖角处的反熔丝氧化层12的厚度更 小，更有利于尖端放电击穿反熔丝栅氧化层12。
在一个可选的实施例中，反熔丝器件20还包括一重掺杂区14，重掺杂区14位于衬底10内，且位于反熔丝栅极11远离浅沟槽隔离结构13的一侧，重掺杂区14使得反熔丝器件20更加容易被击穿。
如图2所示，在其他可选的实施例中，反熔丝器件20还包括反熔丝注入区15，反熔丝注入区15位于衬底10内部，且反熔丝注入区15包覆了反熔丝栅极11嵌入衬底10内的部分，反熔丝注入区15包覆的反熔丝器件20更加容易被击穿，同时可以通过控制反熔丝注入区15的掺杂浓度来控制反熔丝器件20击穿电压的大小；具体地，反熔丝注入区15的掺杂浓度越大，反熔丝器件20的击穿电压越小，两者呈负相关关系。在一个可选的实施例中，反熔丝注入区15还包覆了重掺杂区14，在其中一个实施例中，重掺杂区14和反熔丝注入区15的掺杂类型均为N型掺杂，两者均可通过离子注入的方式形成。
如图3所示，本发明还提供一种反熔丝单元，该反熔丝单元包括了上述实施例中的反熔丝器件20和晶体管30，其中，晶体管30位于反熔丝栅极11远离浅沟槽隔离13的一侧，晶体管30具有源极掺杂区、漏极掺杂区16、栅极17及栅极氧化层19，源极掺杂区与反熔丝器件20电连接。
在一个可选的实施例中，反熔丝栅氧化层12的厚度小于等于晶体管30的栅极氧化层19的厚度。
在一个可选的实施例中，源极掺杂区与重掺杂区14至少有一部分是重叠的，如图3所示，在其中一个实施例中，晶体管30的源极掺杂区与重掺杂区14重叠，具体地，晶体管30的源级掺杂区可以与重掺杂区14为相同的区域；当然，在其他示例中，也可以为晶体管30的漏极掺杂区域重掺杂区14重叠，此时源极掺杂区位于栅极17远离反熔丝器件20的一侧。
在一个可选的实施例中，如图3所示，晶体管30的漏极掺杂区16外围及重掺杂区14的外围均形成有轻掺杂漏结构18。
在另一个可选的实施例中，如图4所示，晶体管30的漏极掺杂区16外围及重掺杂区14的外围均未形成有轻掺杂漏结构18。
在又一个可选的实施例中，如图5所示，重掺杂区14外围没有轻掺杂漏结构18，而晶体管30的漏极掺杂区16边缘具有轻掺杂漏结构18，使得晶体 管30为非对称晶体管30，栅极两侧是不对称的，同时没有轻掺杂漏结构18的一侧电阻更小。在一个实施例中，轻掺杂漏结构18可以仅位于漏极掺杂区16临近栅极17的一侧，轻掺杂漏结构18使得漏极掺杂区16垂直方向的击穿电压更高。轻掺杂漏结构18的上表面与漏极掺杂区16的上表面平齐，且下表面高于漏极掺杂区16的下表面，减小了因为轻掺杂漏结构18带来的电阻升高。
当然，在其他示例中，轻掺杂漏结构18也可以仅位于重掺杂区14临近栅极17的一侧。
综上所述，本申请的反熔丝器件20通过令反熔丝栅极11和反熔丝栅氧化层12在衬底10内部均具有尖角，使得反熔丝器件20有了多个尖端放电点，更加容易被击穿，有了多个击穿点使得同一批次生产的反熔丝器件20的均匀性更好，提高了一批次产品性能的一致性，弯折的反熔丝栅氧化层12有效面积更大，因此使得反熔丝器件20能够以更小的尺寸获得更大的反熔丝栅氧化层12面积，有利于反熔丝器件20的小型化。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种反熔丝器件，所述反熔丝器件包括：
    衬底；
    反熔丝栅极，所述反熔丝栅极部分嵌入所述衬底内，所述反熔丝栅极嵌入所述衬底内的部分具有尖角；以及
    反熔丝栅氧化层，所述反熔丝栅氧化层位于所述反熔丝栅极与所述衬底之间。
  2. 根据权利要求1所述的反熔丝器件，其中所述衬底内还具有浅沟槽隔离结构，所述反熔丝栅极同时嵌入所述衬底及所述浅沟槽隔离结构内。
  3. 根据权利要求2所述的反熔丝器件，其中所述反熔丝栅极嵌入所述浅沟槽隔离结构内的深度大于所述反熔丝栅极嵌入所述衬底内的深度。
  4. 根据权利要求3所述的反熔丝器件，其中所述尖角为直角或钝角。
  5. 根据权利要求4所述的反熔丝器件，其中所述尖角处的反熔丝栅氧化层的厚度小于非尖角处的反熔丝栅氧化层的厚度。
  6. 根据权利要求2至5中任一项所述的反熔丝器件，其中所述反熔丝器件还包括一重掺杂区，所述重掺杂区位于所述衬底内，且位于所述反熔丝栅极远离所述浅沟槽隔离结构的一侧。
  7. 根据权利要求6所述的反熔丝器件，其中所述反熔丝器件还包括反熔丝注入区，所述反熔丝注入区位于所述衬底内，所述反熔丝注入区包覆所述反熔丝栅极嵌入所述衬底内的部分，且所述反熔丝注入区包覆所述重掺杂区。
  8. 根据权利要求6所述的反熔丝器件，其中所述重掺杂区和所述反熔丝注入区的掺杂类型均为N型。
  9. 一种反熔丝单元，所述反熔丝单元包括：
    如权利要求6至8中任一项所述的反熔丝器件；以及
    晶体管，位于所述反熔丝栅极远离所述浅沟槽隔离结构的一侧，所述晶体管具有源极掺杂区和漏极掺杂区，所述源极掺杂区或所述漏极掺杂区与所述反熔丝器件电连接。
  10. 根据权利要求9所述的反熔丝单元，其中所述源极掺杂区或所述漏极掺杂区与所述重掺杂区至少部分重叠。
  11. 根据权利要求10所述的反熔丝单元，其中所述晶体管为非对称晶体管，晶体管的所述部分重叠区域一侧没有轻掺杂漏结构。
  12. 根据权利要求10所述的反熔丝单元，其中反熔丝栅氧化层的厚度小于等于所述晶体管的栅极氧化层的厚度。
  13. 根据权利要求9所述的反熔丝单元，其中所述晶体管的所述漏极掺杂区的外围及所述重掺杂区的外围均形成有所述轻掺杂漏结构。
  14. 根据权利要求9所述的反熔丝单元，其中所述晶体管的所述漏极掺杂区的外围及所述重掺杂区的外围均未形成有所述轻掺杂漏结构。
  15. 根据权利要求9所述的反熔丝单元，其中所述重掺杂区的外围没有所述轻掺杂漏结构，而所述晶体管的所述漏极掺杂区的边缘具有所述轻掺杂漏结构。
  16. 根据权利要求9所述的反熔丝单元，其中所述轻掺杂漏结构仅位于所述漏极掺杂区临近所述栅极的一侧。
  17. 根据权利要求15所述的反熔丝单元，其中所述轻掺杂漏结构的上表面与所述漏极掺杂区的上表面平齐，且下表面高于所述漏极掺杂区的下表面。
  18. 根据权利要求9所述的反熔丝单元，其中所述轻掺杂漏结构仅位于所述重掺杂区临近所述栅极的一侧。
PCT/CN2021/082650 2020-04-08 2021-03-24 反熔丝器件及反熔丝单元 WO2021203969A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/310,896 US11985818B2 (en) 2020-04-08 2021-03-24 Anti-fuse devices and anti-fuse units

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010268401.0A CN113496987B (zh) 2020-04-08 2020-04-08 反熔丝器件及反熔丝单元
CN202010268401.0 2020-04-08

Publications (1)

Publication Number Publication Date
WO2021203969A1 true WO2021203969A1 (zh) 2021-10-14

Family

ID=77995736

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/082650 WO2021203969A1 (zh) 2020-04-08 2021-03-24 反熔丝器件及反熔丝单元

Country Status (3)

Country Link
US (1) US11985818B2 (zh)
CN (1) CN113496987B (zh)
WO (1) WO2021203969A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116847650A (zh) * 2022-03-22 2023-10-03 长鑫存储技术有限公司 一种半导体结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102057441A (zh) * 2008-04-04 2011-05-11 赛鼎矽公司 低阈值电压反熔丝器件
CN103531589A (zh) * 2012-07-05 2014-01-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
CN104620383A (zh) * 2012-09-13 2015-05-13 高通股份有限公司 反熔丝器件
CN109390317A (zh) * 2017-08-11 2019-02-26 长鑫存储技术有限公司 反熔丝结构及其形成方法、半导体器件

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6936909B2 (en) * 2002-08-29 2005-08-30 Micron Technology, Inc. Gate dielectric antifuse circuit to protect a high-voltage transistor
US7157782B1 (en) * 2004-02-17 2007-01-02 Altera Corporation Electrically-programmable transistor antifuses
US7795094B2 (en) * 2004-09-02 2010-09-14 Micron Technology, Inc. Recessed gate dielectric antifuse
KR20070089544A (ko) * 2006-02-28 2007-08-31 주식회사 하이닉스반도체 논플라나 안티퓨즈
KR20100010724A (ko) * 2008-07-23 2010-02-02 주식회사 하이닉스반도체 퓨즈를 구비하는 반도체 장치 및 그 제조방법
KR101159677B1 (ko) * 2010-06-10 2012-06-26 에스케이하이닉스 주식회사 반도체 소자의 안티퓨즈의 제조 방법
JP2012064858A (ja) * 2010-09-17 2012-03-29 Elpida Memory Inc 半導体装置及びその製造方法
KR102191909B1 (ko) * 2014-02-17 2020-12-18 에스케이하이닉스 주식회사 안티 퓨즈 및 그 제조 방법
WO2015147782A1 (en) * 2014-03-24 2015-10-01 Intel Corporation Antifuse element using spacer breakdown
US9508396B2 (en) 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory
US10236249B2 (en) 2016-12-09 2019-03-19 Samsung Electronics Co., Ltd. Anti-fuse device and memory device including the same
US10446562B1 (en) * 2017-01-10 2019-10-15 Synopsys, Inc. One-time programmable bitcell with partially native select device
CN108039345B (zh) * 2017-12-29 2018-12-11 长鑫存储技术有限公司 反熔丝结构及其形成方法、半导体器件
CN210073860U (zh) * 2019-05-23 2020-02-14 长鑫存储技术有限公司 半导体结构及存储器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102057441A (zh) * 2008-04-04 2011-05-11 赛鼎矽公司 低阈值电压反熔丝器件
CN103531589A (zh) * 2012-07-05 2014-01-22 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
CN104620383A (zh) * 2012-09-13 2015-05-13 高通股份有限公司 反熔丝器件
CN109390317A (zh) * 2017-08-11 2019-02-26 长鑫存储技术有限公司 反熔丝结构及其形成方法、半导体器件

Also Published As

Publication number Publication date
CN113496987A (zh) 2021-10-12
CN113496987B (zh) 2024-03-29
US11985818B2 (en) 2024-05-14
US20220320122A1 (en) 2022-10-06

Similar Documents

Publication Publication Date Title
US7518915B2 (en) Nonvolatile semiconductor storage device
US7799641B2 (en) Method for forming a semiconductor device having recess channel
US20060008963A1 (en) Method for forming polysilicon local interconnects
JPH09120997A (ja) 半導体記憶装置とその製造方法
US8093631B2 (en) Non-volatile memory device and method for fabricating the same
CN1779916A (zh) 制造半导体器件的方法
JPH10189783A (ja) 半導体メモリ素子及びその製造方法
WO2021203969A1 (zh) 反熔丝器件及反熔丝单元
CN1945798A (zh) 制造非易失性存储器件的方法
US8044513B2 (en) Semiconductor device and semiconductor device manufacturing method
US7439603B2 (en) Non-volatile memory device and fabricating method thereof
KR101498170B1 (ko) 반도체 기억 장치 및 그의 제조 방법
JP2011134981A (ja) 不揮発性半導体記憶装置及びその製造方法
WO2021203907A1 (zh) 反熔丝单元及反熔丝阵列
US6528840B1 (en) Semiconductor device
US20070170491A1 (en) Nonvolatile memory device and method of fabricating the same
KR100529605B1 (ko) 반도체 소자 제조 방법
CN102903718A (zh) 半导体装置
KR101102966B1 (ko) 고전압 반도체 소자 및 그 제조 방법
JP3253846B2 (ja) 半導体装置およびその製造方法
TWI675457B (zh) 記憶體結構及其製造方法
JP2011187531A (ja) 半導体記憶装置及びその製造方法
TW202412309A (zh) 半導體結構
CN116997183A (zh) 反熔丝结构及其形成方法、存储器
CN101930948B (zh) 氮化物只读存储器的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21785192

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21785192

Country of ref document: EP

Kind code of ref document: A1