WO2021196993A1 - 时钟信号产生电路、时钟信号产生方法及电子设备 - Google Patents

时钟信号产生电路、时钟信号产生方法及电子设备 Download PDF

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Publication number
WO2021196993A1
WO2021196993A1 PCT/CN2021/079743 CN2021079743W WO2021196993A1 WO 2021196993 A1 WO2021196993 A1 WO 2021196993A1 CN 2021079743 W CN2021079743 W CN 2021079743W WO 2021196993 A1 WO2021196993 A1 WO 2021196993A1
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Prior art keywords
frequency
target
circuit
control word
sub
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PCT/CN2021/079743
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English (en)
French (fr)
Inventor
魏祥野
修黎明
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to US17/765,933 priority Critical patent/US11689193B2/en
Publication of WO2021196993A1 publication Critical patent/WO2021196993A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence

Definitions

  • the present disclosure relates to the field of communication technology, and in particular to a clock signal generation circuit, a clock signal generation method, and electronic equipment.
  • the clock signal is one of the indispensable signals for the operation of electronic equipment, and the frequency of the clock signal determines the data processing efficiency of the electronic equipment, that is, determines the operating rate of the electronic equipment.
  • a clock signal generating circuit in order to generate a clock signal with a frequency, a clock signal generating circuit provided in an electronic device generally includes a frequency source (such as a crystal oscillator) capable of generating an oscillation frequency.
  • a frequency source such as a crystal oscillator
  • the oscillation frequency generated by the frequency source is prone to deviation (that is, frequency deviation phenomenon occurs), which may cause the generated clock signal to be abnormal.
  • the present disclosure provides a clock signal generation circuit, a clock signal generation method, and electronic equipment.
  • the technical solutions are as follows:
  • a clock signal generation circuit includes: an initial clock supply circuit, a control word supply circuit, and a target clock generation circuit;
  • the initial clock providing circuit is connected to the target clock generating circuit, and the initial clock providing circuit is configured to generate an initial clock signal of an initial frequency, and output the initial clock signal to the target clock generating circuit;
  • the control word providing circuit is connected to the target clock generating circuit, and the control word providing circuit is used to detect a target parameter that affects the frequency offset of the initial frequency, and determine the target frequency offset of the initial frequency based on the target parameter , Generating a frequency control word based on the target frequency deviation, and outputting the frequency control word to the target clock generating circuit;
  • the target clock generation circuit is used to generate a target clock signal of a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with the frequency control word and is related to the initial clock signal.
  • the frequency is positively correlated.
  • the target parameter includes: temperature
  • the control word providing circuit includes: a temperature detection subcircuit, a frequency offset determination subcircuit, and a control word generation subcircuit;
  • the temperature detection sub-circuit is connected to the frequency offset determination sub-circuit, and the temperature detection sub-circuit is used to detect a target temperature and output the target temperature to the frequency offset determination sub-circuit;
  • the frequency offset determination sub-circuit is also connected to the control word generation sub-circuit, and the frequency offset determination sub-circuit is configured to determine the target frequency offset of the initial frequency based on the target temperature, and output the target frequency offset To the control word generating sub-circuit;
  • the control word generation sub-circuit is also connected to the target clock generation circuit, and the control word generation sub-circuit is used to generate a frequency control word based on the target frequency deviation, the historical frequency control word and the reference output frequency, and the frequency Outputting the control word to the target clock generating circuit, and using the frequency control word to update the historical frequency control word;
  • the frequency offset determining sub-circuit includes: a controller and a memory, and a plurality of candidate frequency offsets corresponding to a plurality of different temperatures in a one-to-one correspondence are stored in the memory;
  • the controller is respectively connected to the memory and the control word generation sub-circuit, and the controller is configured to search for a target candidate frequency offset corresponding to the target temperature from a plurality of candidate frequency offsets stored in the memory , Determining the target candidate frequency offset as the target frequency offset, and outputting the target frequency offset to the control word generating sub-circuit.
  • the memory has multiple storage areas, each of the storage areas stores one of the candidate frequency offsets, and the candidate frequency offsets stored in each of the storage areas are different;
  • the controller is configured to determine an address of a target storage area from the plurality of storage areas based on the target temperature, and obtain the target frequency offset from the target storage area based on the address of the target storage area;
  • the frequency deviation determination sub-circuit is configured to determine a target frequency deviation based on the target temperature output by the temperature detection sub-circuit every detection period;
  • the control word generation sub-circuit is also used to determine whether the target frequency deviation is equal to the historical frequency deviation, and if the target frequency deviation is not equal to the historical frequency deviation, then based on the target frequency deviation and the historical frequency deviation
  • the control word and the reference output frequency generate frequency control word
  • the historical frequency deviation is the target frequency deviation determined by the frequency deviation determination sub-circuit in the previous detection period.
  • control word generation sub-circuit includes: a register, a comparator, and a control word generation unit;
  • the register is respectively connected to the frequency deviation determining sub-circuit, the comparator, and the control word generating unit, and the register is used to output the historical frequency deviation to the comparator, and is used to output the historical frequency deviation to the control word.
  • the generating unit outputs the target frequency offset generated by the frequency offset determining sub-circuit, and is used to update the historical frequency offset using the target frequency offset;
  • the comparator is also connected to the frequency offset determining sub-circuit and the control word generating unit respectively, and the comparator is used to determine whether the target frequency offset is equal to the historical frequency offset, and if the target frequency offset is equal to If the historical frequency deviations are not equal, output an enable signal to the control word generation unit;
  • the control word generating unit is also connected to the target clock generating circuit, and the control word generating unit is configured to generate frequency control based on the target frequency deviation, historical frequency control word, and reference output frequency in response to the enable signal. Word, output the frequency control word to the target clock generation circuit, and use the frequency control word to update the historical frequency control word.
  • the target clock generation circuit includes: an alternative clock generation sub-circuit and a target clock generation sub-circuit;
  • the candidate clock generating sub-circuit is respectively connected to the initial clock providing circuit and the target clock generating sub-circuit, and the candidate clock generating sub-circuit is configured to be based on the initial clock signal output by the initial clock providing circuit Generate a plurality of candidate clock signals, and output the plurality of candidate clock signals to the target clock generation sub-circuit, wherein the period of each candidate clock signal is the same, and any two adjacent ones of the The phase difference between the alternative clock signals is the same;
  • the target clock generation sub-circuit is also connected to the control word supply circuit, and the target clock generation sub-circuit is configured to generate a target clock signal based on the plurality of candidate clock signals and the frequency control word output by the control word supply circuit.
  • the target clock signal of the output frequency is also connected to the control word supply circuit, and the target clock generation sub-circuit is configured to generate a target clock signal based on the plurality of candidate clock signals and the frequency control word output by the control word supply circuit.
  • the target clock signal of the output frequency is also connected to the control word supply circuit, and the target clock generation sub-circuit is configured to generate a target clock signal based on the plurality of candidate clock signals and the frequency control word output by the control word supply circuit.
  • the target clock generation sub-circuit includes: an input module, a selection module, and an output module;
  • the input module is connected to the control word providing circuit, and the input module is configured to output a selection control signal to the selection module based on the frequency control word;
  • the selection module is also connected to the candidate clock generation sub-circuit and the output module respectively, and the selection module is configured to select a target device from the plurality of candidate clock signals in response to the selection control signal. Select a clock signal and output it to the output module;
  • the output module is used to convert the target candidate clock signal into the target clock signal.
  • the input module includes: a first register, a second register, a third register, a fourth register, and two adders;
  • the selection module includes: a first selector, a second selector, and a third selector
  • the output module includes: a D flip-flop, a first inverter and a second inverter;
  • the two adders are respectively connected to the control word providing circuit and the third register, and one adder, the first register, the second register, and the first selector are connected in sequence , The other said adder, said third register, said fourth register and said second selector are connected in sequence;
  • the first selector and the second selector are also respectively connected to the alternative clock generation sub-circuit and the third selector, and the third selector is also connected to the first D flip-flop. Input terminal connection;
  • the second input terminal of the D flip-flop is connected to the output terminal of the first inverter, and the input terminal of the first inverter and the input terminal of the second inverter are both connected to the D trigger The output terminal of the device is connected.
  • a clock signal generation method which is used in the clock signal generation circuit as described in the above aspect, and the method includes:
  • the initial clock providing circuit generates an initial clock signal of an initial frequency, and outputs the initial clock signal to the target clock generating circuit;
  • the control word providing circuit detects a target parameter that affects the frequency deviation of the initial frequency, determines the target frequency deviation of the initial frequency based on the target parameter, generates a frequency control word based on the target frequency deviation, and configures the frequency control word Output to the target clock generating circuit, wherein the frequency control word is positively correlated with the target frequency offset;
  • the target clock generation circuit generates a target clock signal of a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with the frequency control word and positively correlated with the initial frequency.
  • the target parameter includes: temperature;
  • the control word providing circuit includes: a temperature detecting sub-circuit, a frequency deviation determining sub-circuit, and a control word generating sub-circuit; the control word providing circuit detects the influence of the initial frequency
  • the target parameter of the frequency offset, determining the target frequency offset of the initial frequency based on the target parameter, and generating a frequency control word based on the target frequency offset includes:
  • the temperature detection sub-circuit detects the target temperature, and outputs the target temperature to the frequency offset determination sub-circuit;
  • the frequency offset determination sub-circuit determines the target frequency offset of the initial frequency based on the target temperature, and outputs the target frequency offset to the control word generation sub-circuit;
  • the method further includes: the control word generation sub-circuit uses the frequency control word to update the historical frequency control word.
  • the frequency offset determination sub-circuit includes: a controller and a memory, and a plurality of candidate frequency offsets corresponding to a plurality of different temperatures are stored in the memory; the frequency offset determination sub-circuit is based on the The target temperature determining the target frequency deviation of the initial frequency includes:
  • the controller searches for a target candidate frequency offset corresponding to the target temperature from a plurality of candidate frequency offsets stored in the memory;
  • the controller determines the target candidate frequency offset as the target frequency offset.
  • an electronic device comprising: a controlled circuit, and the clock signal generating circuit as described in the foregoing aspect;
  • the controlled circuit is connected to the clock signal generating circuit, and the controlled circuit is configured to work in response to the target clock signal of the target output frequency output by the clock signal generating circuit.
  • FIG. 1 is a schematic structural diagram of a clock signal generating circuit provided by an embodiment of the present disclosure
  • Fig. 2 is a schematic structural diagram of another clock signal generating circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a frequency offset determination sub-circuit provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of another frequency offset determination sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a control word generation sub-circuit provided by an embodiment of the present disclosure
  • Fig. 6 is a schematic structural diagram of another control word generation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of an alternative clock signal generated by an alternative clock generation sub-circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a target clock generating circuit provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another target clock generating circuit provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the working principle of a target clock generating circuit provided by an embodiment of the present disclosure
  • FIG. 11 is a flowchart of a method for generating a clock signal according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.
  • the data processing (including acquisition, transmission, operation, and storage) rate requirements of electronic devices have become higher and higher, especially in the 5th general mobile networks (5G).
  • the signal that determines the rate is a clock signal.
  • a clock signal generating circuit that generates a clock signal generally includes a frequency source capable of generating an oscillating frequency.
  • the oscillating frequency generated by the frequency source is prone to drift due to factors such as temperature, air pressure, or process.
  • the clock signal generating circuit The frequency of the generated clock signal will drift accordingly, which can also be referred to as a frequency offset phenomenon.
  • the influence of the frequency offset phenomenon on the operation of the electronic device will be gradually amplified, and eventually the electronic device will work abnormally.
  • the embodiments of the present disclosure provide a clock signal generating circuit, which can compensate the frequency based on factors that affect the frequency offset (that is, the frequency offset of the frequency), so that the frequency of the finally generated clock signal does not drift. , Or, the drift is small.
  • the electronic device provided by the embodiments of the present disclosure is not prone to abnormal operation and has good stability.
  • FIG. 1 is a schematic structural diagram of a clock signal generating circuit provided by an embodiment of the present disclosure. As shown in FIG. 1, the circuit may include: an initial clock providing circuit 10, a control word providing circuit 20, and a target clock generating circuit 30.
  • the initial clock supply circuit 10 can be connected to the target clock generation circuit 30.
  • the initial clock providing circuit 10 may be used to generate an initial clock signal of an initial frequency, and output the initial clock signal to the target clock generating circuit 30.
  • the initial clock providing circuit may also be referred to as a frequency source, and the frequency source may be a crystal oscillator, other oscillation sources, or a micro-electro-mechanical system (MEMS).
  • MEMS micro-electro-mechanical system
  • the control word providing circuit 20 can be connected to the target clock generating circuit 30.
  • the control word providing circuit 20 can be used to detect the target parameter of the frequency offset that affects the initial frequency, determine the target frequency offset of the initial frequency based on the target parameter, generate the frequency control word based on the target frequency offset, and output the frequency control word to the target clock to generate Circuit 30.
  • the target parameter may include: temperature, air pressure, and/or the manufacturing process of the clock signal generating circuit.
  • the temperature may include: the temperature of the external environment or the temperature of the electronic device integrated with the clock signal generation circuit.
  • the target clock generating circuit 30 can be used to generate a target clock signal of a target output frequency based on the frequency control word and the initial clock signal.
  • the target output frequency may be negatively correlated with the frequency control word, and may be positively correlated with the initial frequency. That is, the target output frequency (the frequency of the clock signal finally generated by the clock signal generating circuit) is jointly determined by the initial frequency and the frequency control word, and the influence of the initial frequency and the frequency control word on the target output frequency is exactly the opposite.
  • the frequency control word can be flexibly generated to make the final target output frequency deviation less affected by the target parameter.
  • control word providing circuit can flexibly generate the frequency control word based on the size of the target frequency deviation and the deviation of the initial frequency (that is, the initial frequency becomes smaller or larger due to the influence of the target parameter). Moreover, if the offset of the initial frequency becomes smaller, the larger the target frequency offset (that is, the smaller the initial frequency offset becomes), the smaller the generated frequency control word should be, that is, for the offset, the generated frequency
  • the size of the control word can be negatively correlated with the size of the target frequency offset.
  • the larger the target frequency offset that is, the larger the initial frequency offset becomes
  • the larger the generated frequency control word should be, that is, for the offset, the generated frequency control
  • the size of the word can be positively correlated with the size of the target frequency offset.
  • the embodiments of the present disclosure provide a clock signal generation circuit. Since the target output frequency of the clock signal finally generated by the clock signal generating circuit is positively correlated with the initial frequency and negatively correlated with the frequency control word, when the initial frequency is affected by the target parameter and the frequency deviation occurs, the frequency can be flexibly generated based on the target frequency deviation The control word realizes the reliable compensation of the initial frequency, so that the frequency of the target clock signal finally generated is less affected by the target parameter.
  • the clock signal generating circuit generates a clock signal with better reliability.
  • the target output frequency fs may satisfy:
  • fc is the initial frequency
  • F is the frequency control word.
  • FIG. 2 is a schematic structural diagram of another clock signal generating circuit provided by an embodiment of the present disclosure.
  • the control word providing circuit 20 may include: a temperature detecting sub-circuit 201, a frequency deviation determining sub-circuit 202, and a control word generating sub-circuit 203.
  • the temperature detection sub-circuit 201 may be connected to the frequency offset determination sub-circuit 202.
  • the temperature detection sub-circuit 201 can be used to detect the target temperature and output the target temperature to the frequency offset determination sub-circuit 202.
  • the temperature detection sub-circuit 201 can not only be used to detect the current target temperature, but also can convert the detected target temperature into an electrical signal (eg, voltage, current, or frequency). That is, in actual work, the temperature detection sub-circuit 201 first converts the detected target temperature into an electrical signal for indicating the target temperature and then outputs it to the frequency offset determination sub-circuit 202. The frequency offset determination sub-circuit 202 can be based on receiving The received electrical signal determines the target temperature.
  • the temperature detection sub-circuit 201 may include a bipolar junction transistor sensor, a thermal resistance sensor, or a crystal temperature sensor.
  • the frequency offset determination sub-circuit 202 can also be connected to the control word generation sub-circuit 203.
  • the frequency offset determination sub-circuit 202 can be used to determine the target frequency offset of the initial frequency based on the target temperature, and output the target frequency offset to the control word generation sub-circuit 203.
  • FIG. 3 is a schematic structural diagram of a frequency offset determination sub-circuit provided by an embodiment of the present disclosure.
  • the frequency offset determining sub-circuit 202 may include: a controller 2021 and a memory 2022, and the memory 2022 may pre-store multiple candidate frequency offsets corresponding to multiple different temperatures in a one-to-one manner.
  • the controller 2021 may be respectively connected to the memory 2022 and the control word generation sub-circuit 203 (not shown in FIG. 3), and the controller 2021 may be used to find a target corresponding to the target temperature from a plurality of candidate frequency deviations Alternative frequency offset, and determine the target alternative frequency offset as the target frequency offset.
  • the corresponding relationship between the temperature and the candidate frequency offset stored in the memory 2022 may be the result of multiple tests before leaving the factory, which has a certain degree of reliability.
  • the controller 2021 included in the frequency offset determination sub-circuit 202 can traverse a plurality of candidate frequency offsets stored in it based on the acquired target temperature, thereby determining the backup corresponding to the target temperature. Select the frequency offset, and determine the candidate frequency offset as the target frequency offset.
  • the memory 2022 may have multiple storage areas. Each storage area may store a candidate frequency offset, and the candidate frequency offsets stored in each storage area may be different.
  • the memory 2022 shown therein includes n storage areas, and n candidate frequency offsets ⁇ f to ⁇ fn are respectively stored.
  • the controller 2021 included in the frequency offset determination sub-circuit 202 can determine the address of the target storage area from a plurality of storage areas based on the target temperature, and obtain the target frequency offset from the target storage area based on the address of the target storage area. That is, the controller 2021 may first determine the address of the target storage area storing the target frequency offset based on the target temperature, and then directly read the target frequency offset from the target storage area.
  • the address A1 of the target storage area can satisfy:
  • A0 is the reference address
  • T is the target temperature
  • r is the detection resolution of the temperature detection sub-circuit 201.
  • the reference address may refer to the start address pre-allocated for the first storage area among the plurality of storage areas.
  • the detection resolution may refer to the minimum temperature change that can be sensed by the temperature detection sub-circuit 201. If the detection resolution is assumed to be 0.1 degrees, then only the current detected target temperature changes relative to the last detected target temperature. When the amount is greater than 0.1 degrees, the temperature detection sub-circuit 201 will further convert the current detected temperature into an electrical signal and output it to the frequency offset determination sub-circuit 202 (eg, output to the controller 2021 included in the frequency offset determination sub-circuit 202).
  • the detection resolution can be pre-configured in the controller 2021 included in the frequency offset determination sub-circuit 202 at the factory.
  • the data stored in the target storage area corresponding to the address of the target storage area is the target frequency offset.
  • the controller 2021 included in the frequency offset determination sub-circuit 202 may also include a divider J1 and an adder J2. After obtaining the target temperature After T, the controller 2021 can calculate the ratio T/r between the target temperature T and the detection resolution r through the divider J1, and calculate the sum T/r+A0 of T/r and the reference address A0 through the adder J2, thereby obtaining The address of the target storage area with the target frequency offset is stored, and the target frequency offset ( ⁇ f as shown in FIG. 4) is further obtained and output to the control word generation sub-circuit 203.
  • the reliability and efficiency of the determination can be improved.
  • the frequency offset determination sub-circuit 202 described in the foregoing embodiment is based on a target temperature search to determine the target frequency offset
  • the frequency offset determination sub-circuit 202 may also be referred to as a temperature-frequency lookup table (f-T lookup table).
  • f-T lookup table temperature-frequency lookup table
  • the method for the frequency offset determining sub-circuit 202 to determine the target frequency offset is not limited to the two optional implementation manners described in the foregoing embodiment.
  • the frequency offset determination sub-circuit 202 (for example, the controller 2021) may have a built-in algorithm for calculating the frequency offset based on temperature. After obtaining the target temperature, the frequency offset determination sub-circuit 202 may directly substitute the target temperature into the frequency offset algorithm. The target frequency offset can be obtained by calculation.
  • the temperature detection sub-circuit 201 may be replaced with a sub-circuit capable of detecting air pressure.
  • the frequency deviation determining sub-circuit 202 can determine the target frequency deviation based on the detected air pressure; details are not described herein again.
  • control word generation sub-circuit 203 (also referred to as the control word conversion sub-circuit) can also be connected to the target clock generation circuit 30, and the control word generation sub-circuit 203 can be used to control words based on the target frequency deviation and historical frequency. And the reference output frequency to generate a frequency control word, output the frequency control word to the target clock generating circuit 30, and use the frequency control word to update the historical frequency control word.
  • the frequency control word F may satisfy:
  • F0 is the historical frequency control word
  • ⁇ f is the target frequency deviation
  • fs' is the reference output frequency.
  • the historical frequency control word F0 refers to the frequency control word received at the target historical moment
  • the target historical moment refers to the most recent historical moment from the current moment when the frequency control word F is received.
  • the reference output frequency fs' refers to the frequency of the clock signal generated by the target clock generating circuit 30 based on the initial frequency without frequency deviation and the initial frequency control word. Generate the frequency control word in the sub-circuit 203. That is, the reference output frequency fs' of the clock signal generating circuit is generally fixed.
  • the ultimate goal of the embodiments of the present disclosure is to make the frequency of the clock signal generated based on the initial frequency shifted in frequency (that is, the target output frequency) different from the frequency of the clock signal generated based on the initial frequency that does not shift in frequency (that is, the reference output frequency). )same. Because the cost of directly adjusting the initial frequency is relatively high, the embodiment of the present disclosure provides a control word providing circuit 20 and flexibly generates a frequency control word based on the frequency deviation of the initial frequency, thereby ensuring the final generated clock signal in a low-cost manner. The frequency of is less affected by the target parameter, or even not affected by the target parameter, that is, it is ensured that the frequency of the final generated clock signal is not affected by the frequency deviation of the initial frequency.
  • the optional process of generating the frequency control word F is shown: assuming the target frequency offset is ⁇ f, if not Adjust the frequency control word, that is, do not adjust the frequency, and the frequency fs of the final generated clock signal meets:
  • the frequency offset determination sub-circuit 202 may be used to determine the target frequency offset based on the target temperature output by the temperature detection sub-circuit 201 every detection period.
  • the detection period may be pre-configured by the frequency offset determining sub-circuit 202 when it leaves the factory, or it may be input by the user in real time based on the current target parameter change, which is not limited in the embodiment of the present disclosure.
  • the temperature detection sub-circuit 201 may detect the temperature in real time, or may also detect the temperature once every detection period.
  • control word generation sub-circuit 203 can also be used to determine whether the target frequency offset and the historical frequency offset are equal, and if they are not equal, the frequency control word is generated based on the target frequency offset, the historical frequency control word and the reference output frequency.
  • the historical frequency offset is the target frequency offset determined by the frequency offset determining sub-circuit 202 in the previous detection cycle. That is, the control word generation sub-circuit 203 can first determine whether the currently acquired target frequency offset has changed relative to the last acquired target frequency offset, and when it does, it may further generate a frequency control word based on the target frequency offset. . Through this design, power consumption can be effectively reduced, and the problem of continuous generation of frequency control words based on the target frequency offset can be avoided, resulting in errors in the results.
  • FIG. 5 is a schematic structural diagram of a control word generation sub-circuit 203 provided by an embodiment of the present disclosure.
  • the control word generating sub-circuit 203 may include: a register 2031, a comparator 2032, and a control word generating unit 2033.
  • the register 2031 may be connected to the frequency offset determination sub-circuit 202 (not shown in FIG. 5), the comparator 2032, and the control word generation unit 2033, respectively.
  • the register 2031 can be used to output the historical frequency offset to the comparator 2032 ( ⁇ f' as shown in Figure 5), and can be used to output the target frequency offset input by the frequency offset determination sub-circuit 202 to the control word generating unit 2033 ( Figure 5
  • the ⁇ f shown in Figure 5 can be used to update the historical frequency offset using the target frequency offset ( ⁇ f as shown in Figure 5).
  • the comparator 2032 may also be connected to the frequency offset determination sub-circuit 202 (not shown in FIG. 5) and the control word generation unit 2033, respectively.
  • the comparator 2032 can be used to determine whether the target frequency offset is equal to the historical frequency offset, and if not, output an enable signal to the control word generating unit 2033. If they are equal, output a disable signal to the control word generation unit 2033.
  • the disable signal can be used to instruct the control word generation unit 2033 to stop outputting the frequency control word to the target clock supply circuit, or it can be used to instruct the control word generation
  • the unit 2033 does not generate a frequency control word, that is, it controls the control word generation unit 2033 to stop working.
  • the control word generating unit 2033 may also be connected to the target clock generating circuit 30 (not shown in FIG. 5).
  • the control word generation unit 2033 can be used to generate a frequency control word based on the target frequency deviation, historical frequency control word and reference output frequency in response to the enable signal (as shown in F in Figure 5), and output the frequency control word to the target clock to generate
  • the circuit 30 uses the frequency control word to update the historical frequency control word.
  • the comparator 2032 can only be connected to the register 2031 and the control word generation unit 2033, and the register 2031 can also be used to output the target frequency offset to the comparator 2032, that is, the register 2031 outputs the target frequency offset and the control word generation unit 2032 at the same time. Historical frequency deviation.
  • the register 2031 may only be connected to the comparator 2032. When the comparator 2032 determines that the target frequency offset is not equal to the historical frequency offset, it may output the enable signal and the target frequency offset to the control word generating unit 2033.
  • the register 2031 may only be connected to the comparator 2032, and the control word generation unit 2033 is also connected to the frequency offset determination sub-circuit 202, and the control word generation unit 2033 may directly receive the target frequency offset input by the frequency offset determination sub-circuit 202.
  • FIG. 6 shows a schematic structural diagram of another control word generating sub-circuit 203 provided by an embodiment of the present disclosure.
  • the control word generating unit 2033 may include a divider J3, an adder J4, and an enabling unit.
  • the comparator 2032 can be connected to the enabling unit. When the comparator 2032 judges that the target frequency deviation is not equal to the historical frequency deviation, it can output an enabling signal to the enabling unit to control the enabling unit to control the divider J3 and the adder J4. The branch is connected.
  • control word generation unit 2033 can generate the frequency control word F through the divider J3 and the adder J4, and based on the target frequency offset ⁇ f, the historical frequency control word F0, the reference output frequency fs' and the above formula (3) .
  • the frequency deviation determining sub-circuit 202 and the control word generating sub-circuit 203 included in the control word providing circuit 20 described above may be composed of hardware, that is, a hardware circuit; or, it may be a virtual circuit configured with a code program. Circuits (such as processing chips). The embodiments of the present disclosure do not limit this.
  • the target clock generating circuit 30 may include: an alternative clock generating sub-circuit 301 and a target clock generating sub-circuit 302.
  • the alternative clock generating sub-circuit 301 may be connected to the initial clock providing circuit 10 and the target clock generating sub-circuit 302, respectively.
  • the alternative clock generation sub-circuit 301 may be used to generate multiple alternative clock signals based on the initial clock signal output by the initial clock providing circuit 10, and output the multiple alternative clock signals to the target clock generation sub-circuit 302, each of which is The period and frequency of the selected clock signal are the same, and the phase difference between any two adjacent candidate clock signals is the same.
  • FIG. 7 shows a schematic diagram of the candidate clock signals by taking the candidate clock generating sub-circuit 301 generating a total of K candidate clock signals as an example.
  • the phase difference ⁇ between every two adjacent candidate clock signals can satisfy:
  • K is the number of candidate clock signals
  • f is the frequency of each candidate clock signal.
  • the alternative clock generation sub-circuit 301 may also be referred to as a K-inputs circuit.
  • the number K of candidate clock signals that can be generated by the candidate clock generating sub-circuit 301 can be pre-configured in the circuit, for example, can be set in the circuit by a user (eg, a developer) when producing the circuit.
  • K can be 2 to the power of i, and i can be an integer greater than or equal to 1.
  • K can be 16, 32, 128, or others.
  • the target clock generating sub-circuit 302 may also be connected to the control word providing circuit 20, and the target clock generating sub-circuit 302 may be used to generate a target clock of the target output frequency based on a plurality of candidate clock signals and the frequency control word output by the control word providing circuit 20 Signal.
  • the target clock generation sub-circuit 302 shown in FIG. 2 is connected to the control word generation sub-circuit 203 in the control word supply circuit 20 that finally generates the frequency control word F.
  • FIG. 8 is a schematic structural diagram of each sub-circuit in a target clock generating circuit 30 provided by an embodiment of the present disclosure.
  • the alternative clock generation sub-circuit 301 may include: Johns on Counter. Since the John counter can generate a larger number of candidate clock signals, and because the clock signal duty cycle resolution is the reciprocal of the number of candidate clock signals, the resolution can be improved and the accuracy is higher.
  • the target clock generating sub-circuit 302 may include: an input module 3021, a selection module 3022 and an output module 3023.
  • the input module 3021 may be connected to the control word providing circuit 20 (not shown in FIG. 8), and the input module 3021 may be used to output a selection control signal to the selection module 3022 based on the frequency control word (F shown in FIG. 8).
  • the selection module 3022 can also be connected to the alternative clock generation sub-circuit 301 and the output module 3023 respectively.
  • the selection module 3022 can be used to select a target alternative clock signal from a plurality of alternative clock signals in response to the selection control signal and output it to Output module 3023.
  • the output module 3023 can be used to convert the target candidate clock signal into a target clock signal.
  • FIG. 9 is a schematic structural diagram of each sub-circuit in a target clock generating circuit 30 provided by an embodiment of the present disclosure.
  • the input module 3021 may include: a first register R1, a second register R2, a third register R3, a fourth register R4, and two adders J11 and J12.
  • the selection module 3022 may include: a first selector X1, a second selector X2, and a third selector X3.
  • the output module 3023 may include a D flip-flop, a first inverter F1, and a second inverter F2.
  • the two adders J11 and J12 can be respectively connected to the control word providing circuit 20 and the third register R3, and one adder J11, the first register R1, the second register R2 and the first selector X1 are connected in sequence; the other adder The device J12, the third register R3, the fourth register R4 and the second selector X2 are connected in sequence.
  • the two adders J11 and J12 shown in FIG. 9 are both connected to the connection line connecting the third register R3 and the fourth register R4.
  • the first selector X1 and the second selector X2 may also be connected to the alternative clock generation sub-circuit 301 and the third selector X3, respectively, and the third selector X3 may also be connected to the first input terminal of the D flip-flop.
  • the second input terminal of the D flip-flop may be connected to the output terminal of the first inverter F1, and the input terminal of the first inverter F1 and the input terminal of the second inverter F2 may be connected to the output terminal of the D flip-flop.
  • the output terminal of the D flip-flop can be used as the output of the first clock signal terminal CLK1
  • the output terminal of the second inverter F2 can be used as the output of the second clock signal terminal CLK2
  • the first clock signal The clock signals provided by the terminal CLK1 and the second clock signal terminal CLK2 are only opposite in phase and have the same frequency.
  • both the first selector X1 and the second selector X2 can be K->1 as shown in FIG. 9 Selector (that is, select 1 target candidate clock signal from K candidate clock signals). Since the third selector X3 is used to select one of the two, with reference to Figure 9, the third selector X3 can be a 2->1 selector (that is, one target candidate is selected from the two candidate clock signals). Clock signal).
  • an adder J11 can add a part of the frequency control word F (F/2 as shown in Figure 9) and the most significant bit (such as 5 bits) stored in the third register R3, and then add it to the second clock signal
  • the addition result is stored in the first register R1 at the rising edge of the second clock signal provided by the terminal CLK2; or, an adder J11 can add a part of the frequency control word F and all the information stored in the third register R3, Then, at the rising edge of the second clock signal, the addition result is stored in the first register R1.
  • the most significant bit stored in the first register R1 will be stored in the second register R2 and used as the selection signal of the first selector X1.
  • the first selector X1 can respond to the selection signal to select a target candidate clock signal from the K candidate clock signals as the output signal of the first selector X1 and output it to the third selector X3.
  • another adder J12 can add the frequency control word F and the most significant bit stored in the third register R3, and then save the addition result in the third register R3 at the rising edge of the second clock signal CLK2.
  • another adder J12 may add the frequency control word F and all the information stored in the third register R3, and then save the addition result in the third register R3 at the rising edge of the second clock signal CLK2.
  • the most significant bit stored in the third register R3 will be stored in the fourth register R4 and used as the selection signal of the second selector X2.
  • the second selector X2 can select a target candidate clock signal from the K candidate clock signals as the output signal of the second selector X2 and output it to the third selector X3 in response to the selection signal.
  • the third selector X3 may select one of the output signal from the first selector X1 and the output signal from the first selector X2 as the output of the third selector X3 at the rising edge of the first clock signal
  • the signal is output to the D flip-flop as the input clock signal of the D flip-flop.
  • the clock signal output by one of the output terminal of the D flip-flop and the output terminal of the second inverter F2 can be used as the final output signal. So far, the generation of the target clock signal is realized.
  • the selection signal output by the fourth register R4 can be used as a falling edge selection signal
  • the selection signal output by the second register R2 can be used as a rising edge selection signal
  • the signal fed back to the adder J12 by the third register R3 can be used to control the generation The cycle of the clock is switched.
  • the selection signal output by the fourth register R4 may be called a falling edge control word
  • the selection signal output by the second register R2 may be called a rising edge control word.
  • the size of the frequency control word output to the two adders J11 and J12 can be flexibly set by the user based on the target output frequency of the target clock signal he needs; or, it can be generated by the TAF-DPS circuit based on the final needs
  • the target output frequency of the target clock signal can be set flexibly, and the target output frequency can be input into the TAF-DPS circuit by the user.
  • the target clock generating circuit 30 described in the embodiment of the present disclosure may be referred to as a time-average-frequency direct period synthesis (TAF-DPS) circuit.
  • TAF-DPS time-average-frequency direct period synthesis
  • the working principle of the TAF-DPS circuit can be implemented based on time average frequency (TAF).
  • TAF time average frequency
  • the achievable process of obtaining the target output frequency based on the TAF method is schematically illustrated in conjunction with Fig. 10:
  • the two time periods can be synthesized through the "period synthesis" technology to obtain a clock signal whose period is the target period, and the target period T TAF can satisfy:
  • T TAF (1-r1)*T A +r1*T B formula (8);
  • r1 can control the probability of occurrence of T B , that is, the fractional part r1 of the frequency control word F can control the switching frequency between the periods T A and T B.
  • the frequency f TAF of the clock signal output by the TAF-DPS circuit can be further calculated to satisfy:
  • the f TAF is the target output frequency fs recorded in the embodiment of the present disclosure.
  • the target output frequency fs may be the first clock signal or the second clock signal finally output by the TAF-DPS circuit.
  • the clock signal generation circuit described in the embodiments of the present disclosure has good reliability and safety, and because the circuit has a low implementation cost, it can be reused in various electronic devices.
  • the embodiments of the present disclosure provide a clock signal generation circuit. Since the target output frequency of the clock signal finally generated by the clock signal generating circuit is positively correlated with the initial frequency and negatively correlated with the frequency control word, when the initial frequency is affected by the target parameter and the frequency deviation occurs, the frequency can be flexibly generated based on the target frequency deviation The control word realizes the reliable compensation of the initial frequency, so that the frequency of the target clock signal finally generated is less affected by the target parameter.
  • the clock signal generating circuit generates a clock signal with better reliability.
  • FIG. 11 is a clock signal generation method provided by an embodiment of the present disclosure, which can be applied to the clock signal generation circuit shown in FIG. 1 or FIG. 2. As shown in Figure 11, the method may include:
  • Step 1101 The initial clock providing circuit generates an initial clock signal of an initial frequency, and outputs the initial clock signal to the target clock generating circuit.
  • Step 1102 The control word providing circuit detects the target parameter of the frequency offset that affects the initial frequency, determines the target frequency offset of the initial frequency based on the target parameter, generates a frequency control word based on the target frequency offset, and outputs the frequency control word to the target clock generating circuit.
  • Step 1103 The target clock signal generating circuit generates a target clock signal of the target output frequency based on the frequency control word and the initial clock signal.
  • the target output frequency can be negatively correlated with the frequency control word, and can be positively correlated with the initial frequency.
  • the embodiments of the present disclosure provide a clock signal generation method. Because the target output frequency of the clock signal finally generated by the clock signal generation method is positively correlated with the initial frequency and negatively correlated with the frequency control word, when the initial frequency is When a frequency offset occurs due to the influence of the target parameter, the frequency control word can be flexibly generated based on the target frequency offset to achieve reliable compensation of the initial frequency, so that the frequency of the target clock signal finally generated is less affected by the target parameter.
  • the clock signal generating circuit generates a clock signal with better reliability.
  • FIG. 12 shows an electronic device provided by an embodiment of the present disclosure.
  • the electronic device includes: a controlled circuit 01, and a clock signal generating circuit 02 as shown in FIG. 1 or FIG. 2.
  • the controlled circuit 01 may be connected to the clock signal generating circuit 02, and the controlled circuit 01 may be used to work in response to the target clock signal of the target output frequency output by the clock signal generating circuit 02.
  • the electronic device may be a single-chip microcomputer, a mobile terminal or an embedded device.

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Abstract

一种时钟信号产生电路、时钟信号产生方法及电子设备，属于通信技术领域。该时钟信号产生电路中，初始时钟提供电路(10)可以生成初始频率的初始时钟信号；控制字提供电路(20)可以基于检测到的目标参数确定初始频率的目标频偏，且可以基于目标频偏生成频率控制字；目标时钟产生电路(30)可以基于频率控制字和初始时钟信号生成目标输出频率的目标时钟信号，该目标输出频率与频率控制字负相关，且与初始频率正相关。基于目标输出频率与初始频率和频率控制字的关系可知，通过灵活生成频率控制字，即可以使得时钟信号产生电路最终生成的时钟信号的频率受目标参数影响较小。

Description

时钟信号产生电路、时钟信号产生方法及电子设备
本公开要求于2020年4月3日提交的申请号为202010260304.7、发明名称为“时钟信号产生电路、时钟信号产生方法及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及通信技术领域，特别涉及一种时钟信号产生电路、时钟信号产生方法及电子设备。
背景技术
时钟信号是电子设备工作必不可少的信号之一，且时钟信号的频率决定了电子设备的数据处理效率，即决定了电子设备的工作速率。
相关技术中，为了产生具有频率的时钟信号，电子设备中设置的时钟信号产生电路一般包括：能够产生振荡频率的频率源(如晶振)。
但是，受温度、气压和工艺等因素的影响，频率源产生的振荡频率容易发生偏移(即发生频偏现象)，进而可能导致产生的时钟信号出现异常。
发明内容
本公开提供了一种时钟信号产生电路、时钟信号产生方法及电子设备，所述技术方案如下：
一方面，提供了一种时钟信号产生电路，所述电路包括：初始时钟提供电路、控制字提供电路和目标时钟产生电路；
所述初始时钟提供电路与所述目标时钟产生电路连接，所述初始时钟提供电路用于生成初始频率的初始时钟信号，并将所述初始时钟信号输出至所述目标时钟产生电路；
所述控制字提供电路与所述目标时钟产生电路连接，所述控制字提供电路用于检测影响所述初始频率的频偏的目标参数，基于所述目标参数确定所述初始频率的目标频偏，基于所述目标频偏生成频率控制字，并将所述频率控制字 输出至所述目标时钟产生电路；
所述目标时钟产生电路用于基于所述频率控制字和所述初始时钟信号生成目标输出频率的目标时钟信号，其中，所述目标输出频率与所述频率控制字负相关，且与所述初始频率正相关。
可选的，所述目标输出频率fs满足：fs＝fc/F，其中，fc为所述初始频率，F为所述频率控制字。
可选的，所述目标参数包括：温度，所述控制字提供电路包括：温度检测子电路、频偏确定子电路和控制字生成子电路；
所述温度检测子电路与所述频偏确定子电路连接，所述温度检测子电路用于检测目标温度，并将所述目标温度输出至所述频偏确定子电路；
所述频偏确定子电路还与所述控制字生成子电路连接，所述频偏确定子电路用于基于所述目标温度确定所述初始频率的目标频偏，并将所述目标频偏输出至所述控制字生成子电路；
所述控制字生成子电路还与所述目标时钟产生电路连接，所述控制字生成子电路用于基于所述目标频偏、历史频率控制字和基准输出频率生成频率控制字，将所述频率控制字输出至所述目标时钟产生电路，以及采用所述频率控制字更新所述历史频率控制字；
其中，所述频率控制字F满足：F＝F0+△f/fs'，F0为所述历史频率控制字，△f为所述目标频偏，fs'为所述基准输出频率。
可选的，所述频偏确定子电路包括：控制器和存储器，所述存储器中存储有与多个不同的温度一一对应的多个备选频偏；
所述控制器分别与所述存储器和所述控制字生成子电路连接，所述控制器用于从所述存储器存储的多个备选频偏中查找与所述目标温度对应的目标备选频偏，将所述目标备选频偏确定为所述目标频偏，并将所述目标频偏输出至所述控制字生成子电路。
可选的，所述所述存储器具有多个存储区域，每个所述存储区域中存储有一个所述备选频偏，且各个所述存储区域中存储的所述备选频偏不同；
所述控制器用于基于所述目标温度从所述多个存储区域中确定目标存储区域的地址，并基于所述目标存储区域的地址从所述目标存储区域中获取所述目标频偏；
其中，所述目标存储区域的地址A1满足：A1＝T/r+A0，A0为基准地址，T为所述目标温度，r为所述温度检测子电路的检测分辨率。
可选的，所述频偏确定子电路用于每隔检测周期基于所述温度检测子电路输出的目标温度确定一次目标频偏；
所述控制字生成子电路还用于判断所述目标频偏与历史频偏是否相等，若所述目标频偏与所述历史频偏不相等，则基于所述目标频偏、所述历史频率控制字和所述基准输出频率生成频率控制字；
其中，所述历史频偏为所述频偏确定子电路在上一个检测周期确定的目标频偏。
可选的，所述控制字生成子电路包括：寄存器、比较器和控制字生成单元；
所述寄存器分别与所述频偏确定子电路、所述比较器和所述控制字生成单元连接，所述寄存器用于向所述比较器输出所述历史频偏，用于向所述控制字生成单元输出所述频偏确定子电路生成的目标频偏，以及用于采用所述目标频偏更新所述历史频偏；
所述比较器还分别与所述频偏确定子电路和所述控制字生成单元连接，所述比较器用于判断所述目标频偏与所述历史频偏是否相等，若所述目标频偏与所述历史频偏不相等，则向所述控制字生成单元输出使能信号；
所述控制字生成单元还与所述目标时钟产生电路连接，所述控制字生成单元用于响应于所述使能信号，基于所述目标频偏、历史频率控制字和基准输出频率生成频率控制字，将所述频率控制字输出至所述目标时钟产生电路，并采用所述频率控制字更新所述历史频率控制字。
可选的，所述目标时钟产生电路包括：备选时钟产生子电路和目标时钟产生子电路；
所述备选时钟产生子电路分别与所述初始时钟提供电路和所述目标时钟产生子电路连接，所述备选时钟产生子电路用于基于所述初始时钟提供电路输出的所述初始时钟信号生成多个备选时钟信号，并将所述多个备选时钟信号输出至所述目标时钟产生子电路，其中每个所述备选时钟信号的周期相同，且任意两个相邻的所述备选时钟信号之间的相位差相同；
所述目标时钟产生子电路还与所述控制字提供电路连接，所述目标时钟产生子电路用于基于所述多个备选时钟信号和所述控制字提供电路输出的频率控 制字，生成目标输出频率的目标时钟信号。
可选的，所述目标时钟产生子电路包括：输入模块、选择模块和输出模块；
所述输入模块与所述控制字提供电路连接，所述输入模块用于基于所述频率控制字向所述选择模块输出选择控制信号；
所述选择模块还分别与所述备选时钟产生子电路和所述输出模块连接，所述选择模块用于响应于所述选择控制信号，从所述多个备选时钟信号中选择一个目标备选时钟信号并输出至所述输出模块；
所述输出模块用于将所述目标备选时钟信号转换为所述目标时钟信号。
可选的，所述输入模块包括：第一寄存器、第二寄存器、第三寄存器、第四寄存器和两个加法器；所述选择模块包括：第一选择器、第二选择器和第三选择器；所述输出模块包括：D触发器、第一反相器和第二反相器；
所述两个加法器均分别与所述控制字提供电路和所述第三寄存器连接，且一个所述加法器、所述第一寄存器、所述第二寄存器和所述第一选择器依次连接，另一个所述加法器、所述第三寄存器、所述第四寄存器和所述第二选择器依次连接；
所述第一选择器和所述第二选择器还均分别与所述备选时钟产生子电路和所述第三选择器连接，所述第三选择器还与所述D触发器的第一输入端连接；
所述D触发器的第二输入端与所述第一反相器的输出端连接，所述第一反相器的输入端和所述第二反相器的输入端均与所述D触发器的输出端连接。
另一方面，提供了一种时钟信号产生方法，用于如上述方面所述的时钟信号产生电路中，所述方法包括：
初始时钟提供电路生成初始频率的初始时钟信号，并将所述初始时钟信号输出至目标时钟产生电路；
控制字提供电路检测影响所述初始频率的频偏的目标参数，基于所述目标参数确定所述初始频率的目标频偏，基于所述目标频偏生成频率控制字，并将所述频率控制字输出至所述目标时钟产生电路，其中，所述频率控制字与所述目标频偏正相关；
所述目标时钟产生电路基于所述频率控制字和所述初始时钟信号生成目标输出频率的目标时钟信号，其中，所述目标输出频率与所述频率控制字负相关，且与所述初始频率正相关。
可选的，所述目标参数包括：温度；所述控制字提供电路包括：温度检测子电路、频偏确定子电路和控制字生成子电路；所述控制字提供电路检测影响所述初始频率的频偏的目标参数，基于所述目标参数确定所述初始频率的目标频偏，基于所述目标频偏生成频率控制字，包括：
所述温度检测子电路检测目标温度，并将所述目标温度输出至频偏确定子电路；
所述频偏确定子电路基于所述目标温度确定所述初始频率的目标频偏，并将所述目标频偏输出至所述控制字生成子电路；
所述控制字生成子电路基于所述目标频偏、历史频率控制字和基准输出频率生成频率控制字，所述频率控制字F满足：F＝F0+△f/fs'，F0为所述历史频率控制字，△f为所述目标频偏，fs'为所述基准输出频率；
所述方法还包括：所述控制字生成子电路采用所述频率控制字更新所述历史频率控制字。
可选的，所述频偏确定子电路包括：控制器和存储器，所述存储器中存储有与多个不同的温度一一对应的多个备选频偏；所述频偏确定子电路基于所述目标温度确定所述初始频率的目标频偏，包括：
所述控制器从所述存储器存储的多个备选频偏中查找与所述目标温度对应的目标备选频偏；
所述控制器将所述目标备选频偏确定为所述目标频偏。
又一方面，提供了一种电子设备，所述电子设备包括：被控电路，以及如上述方面所述的时钟信号产生电路；
所述被控电路与所述时钟信号产生电路连接，所述被控电路用于响应于所述时钟信号产生电路输出的目标输出频率的目标时钟信号工作。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种时钟信号产生电路的结构示意图；
图2是本公开实施例提供的另一种时钟信号产生电路的结构示意图；
图3是本公开实施例提供的一种频偏确定子电路的结构示意图；
图4是本公开实施例提供的另一种频偏确定子电路的结构示意图；
图5是本公开实施例提供的一种控制字生成子电路的结构示意图；
图6是本公开实施例提供的另一种控制字生成子电路的结构示意图；
图7是本公开实施例提供的一种备选时钟产生子电路生成的备选时钟信号示意图；
图8是本公开实施例提供的一种目标时钟产生电路的结构示意图；
图9是本公开实施例提供的另一种目标时钟产生电路的结构示意图；
图10是本公开实施例提供的一种目标时钟产生电路的工作原理示意图；
图11是本公开实施例提供的一种时钟信号产生方法的流程图；
图12是本公开实施例提供的一种电子设备的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
随着通信技术的快速发展，对电子设备的数据处理(包括获取、传输、运行和保存)速率要求变得越来越高，尤其是在第五代移动通信技术(5th genera tion mobile networks，5G)来临之后。且，决定速率的信号为时钟信号。
相关技术中，生成时钟信号的时钟信号产生电路一般包括能够生成振荡频率的频率源，但是，频率源生成的振荡频率受温度、气压或工艺等因素影响易出现偏移，进而，时钟信号产生电路生成的时钟信号的频率即会相应的发生漂移，也可以称为频率偏移现象。随着工作时长的增长，该频率偏移现象对电子设备运行带来的影响会被逐渐放大，最终导致电子设备工作出现异常。
本公开实施例提供了一种时钟信号产生电路，该时钟信号产生电路能够基于影响频率偏移(即频率的频偏)的因素对频率进行补偿，使得最终生成的时钟信号的频率不会发生漂移，或，漂移较小。相应的，本公开实施例提供的电子设备的工作不易出现异常，稳定性较好。
图1是本公开实施例提供的一种时钟信号产生电路的结构示意图。如图1 所示，该电路可以包括：初始时钟提供电路10、控制字提供电路20和目标时钟产生电路30。
该初始时钟提供电路10可以与目标时钟产生电路30连接。该初始时钟提供电路10可以用于生成初始频率的初始时钟信号，并将初始时钟信号输出至目标时钟产生电路30。
可选的，该初始时钟提供电路也可以称为频率源，该频率源可以为晶振、其他振荡源或微机电系统(micro-electro-mechanical system，MEMS)。
该控制字提供电路20可以与目标时钟产生电路30连接。该控制字提供电路20可以用于检测影响初始频率的频偏的目标参数，基于目标参数确定初始频率的目标频偏，基于目标频偏生成频率控制字，并将频率控制字输出至目标时钟产生电路30。
可选的，该目标参数可以包括：温度、气压和/或时钟信号产生电路的制作工艺。该温度可以包括：外界环境温度或集成有时钟信号产生电路的电子设备的自身温度。
该目标时钟产生电路30可以用于基于频率控制字和初始时钟信号生成目标输出频率的目标时钟信号。
在本公开实施例中，该目标输出频率可以与频率控制字负相关，且可以与初始频率正相关。即目标输出频率(该时钟信号产生电路最终生成的时钟信号的频率)由初始频率和频率控制字共同决定，且初始频率和频率控制字对目标输出频率的影响恰好相反。相应的，即可以通过灵活生成频率控制字来使得最终生成的目标输出频偏受目标参数影响较小。
可选的，控制字提供电路可以基于目标频偏的大小，以及初始频率的偏移情况(即，初始频率受目标参数影响变小还是变大)灵活生成频率控制字。且，若初始频率的偏移情况为变小，则目标频偏越大(即初始频偏变得越小)，生成的频率控制字也应该越小，即对于该偏移情况，生成的频率控制字的大小可以与目标频偏的大小负相关。若初始频率的偏移情况为变大，则目标频偏越大(即初始频偏变得越大)，生成的频率控制字应该也应该越大，即对于该偏移情况，生成的频率控制字的大小可以与目标频偏的大小正相关。
综上所述，本公开实施例提供了一种时钟信号产生电路。由于该时钟信号产生电路最终生成的时钟信号的目标输出频率与初始频率正相关，与频率控制 字负相关，因此当初始频率受目标参数影响发生频偏时，可以通过基于目标频偏灵活生成频率控制字来实现对初始频率的可靠补偿，从而使得最终生成的目标时钟信号的频率受目标参数影响较小。该时钟信号产生电路生成时钟信号的可靠性较好。
可选的，在本公开实施例中，该目标输出频率fs可以满足：
fs＝fc/F    公式(1)；
其中，fc为初始频率，F为频率控制字。下述实施例以目标参数包括温度为例，对时钟信号产生电路进行描述：
图2是本公开实施例提供的另一种时钟信号产生电路的结构示意图。如图2所示，该控制字提供电路20可以包括：温度检测子电路201、频偏确定子电路202和控制字生成子电路203。
其中，该温度检测子电路201可以与频偏确定子电路202连接。该温度检测子电路201可以用于检测目标温度，并将目标温度输出至频偏确定子电路202。
需要说明的是，为了保证信号传递可靠性，该温度检测子电路201不仅可以用于检测当前的目标温度，且可以将检测到的目标温度转换为电信号(如，电压、电流或频率)。即，在实际工作中，温度检测子电路201是将检测到的目标温度先转换为用于指示目标温度的电信号后再输出至频偏确定子电路202，频偏确定子电路202可以基于接收到的电信号确定目标温度。例如，该温度检测子电路201可以包括双极结型晶体管传感器、热电阻感器或晶振温度传感器。
该频偏确定子电路202还可以与控制字生成子电路203连接。该频偏确定子电路202可以用于基于目标温度确定初始频率的目标频偏，并将目标频偏输出至控制字生成子电路203。
可选的，图3是本公开实施例提供的一种频偏确定子电路的结构示意图。如图3所示，该频偏确定子电路202可以包括：控制器2021和存储器2022，且存储器2022中可以预先存储有与多个不同的温度一一对应的多个备选频偏。
参考图3，控制器2021可以分别与存储器2022和控制字生成子电路203(图3中未示出)连接，控制器2021可以用于从多个备选频偏中查找与目标温度对应的目标备选频偏，并将目标备选频偏确定为目标频偏。
需要说明的是，该存储器2022中存储的温度和备选频偏的对应关系可以为 在出厂前进行多次测试得到的结果，具有一定的可靠性。
作为一种可选的实现方式，该频偏确定子电路202包括的控制器2021可以基于获取到的目标温度对其存储的多个备选频偏进行遍历，从而确定出与目标温度对应的备选频偏，并将该备选频偏确定为目标频偏。
作为另一种可选的实现方式，如图4所示，存储器2022可以具有多个存储区域。每个存储区域中可以存储有一个备选频偏，且各个存储区域中存储的备选频偏可以不同。如，参考图4，其示出的存储器2022共包括n个存储区域，分别存储有n个备选频偏△f至△fn。
相应的，频偏确定子电路202包括的控制器2021可以基于目标温度从多个存储区域中确定目标存储区域的地址，并基于目标存储区域的地址从目标存储区域中获取目标频偏。即控制器2021可以先基于目标温度确定出存储有目标频偏的目标存储区域的地址，然后再直接从该目标存储区域中读取目标频偏。
在本公开实施例中，该目标存储区域的地址A1可以满足：
A1＝T/r+A0    公式(2)；
其中，A0为基准地址，T为目标温度，r为温度检测子电路201的检测分辨率。该基准地址可以是指为多个存储区域中第一个存储区域预先分配的起始地址。该检测分辨率可以是指温度检测子电路201所能感知的温度最小变化量，如假设检测分辨率为0.1度，则只有在当前检测到的目标温度相对于上一次检测到的目标温度的变化量大于0.1度时，温度检测子电路201才会进一步将当前检测温度转换为电信号并输出至频偏确定子电路202(如，输出至频偏确定子电路202包括的控制器2021中)。且，该检测分辨率可以在出厂时预先配置于频偏确定子电路202包括的控制器2021中。该目标存储区域的地址对应的目标存储区域中存储的数据(即DATA A1)即为目标频偏。
为了基于公式(2)计算得到目标存储区域的地址，示例的，参考图4，该频偏确定子电路202包括的控制器2021中还可以包括除法器J1和加法器J2，在获取到目标温度T后，控制器2021可以通过除法器J1计算目标温度T和检测分辨率r的比值T/r，并通过加法器J2计算T/r和基准地址A0之和T/r+A0，从而得出存储有目标频偏的目标存储区域的地址，进一步得出目标频偏(如图4所示的△f)并输出至控制字生成子电路203。通过该实现方式确定目标频偏，可以提高确定可靠性和确定效率。
由于上述实施例记载的频偏确定子电路202均是基于目标温度查找以确定目标频偏，因此，该频偏确定子电路202也可以称为温度频率查找表(f-T lookup table)。当然，频偏确定子电路202确定目标频偏的方法不局限于上述实施例记载的两种可选实现方式。例如，频偏确定子电路202(如，控制器2021)中可以内置有基于温度计算频偏的算法，在获取到目标温度后，频偏确定子电路202可以直接将目标温度代入频偏算法中以计算得到目标频偏。
可选的，若目标参数包括气压，则该温度检测子电路201可以用能够检测气压的子电路来替换。相应的，频偏确定子电路202可以基于检测到的气压确定目标频偏；在此不再赘述。
继续参考图2，控制字生成子电路203(也可以称为控制字转换子电路)还可以与目标时钟产生电路30连接，控制字生成子电路203可以用于基于目标频偏、历史频率控制字和基准输出频率生成频率控制字，将频率控制字输出至目标时钟产生电路30，以及采用频率控制字更新历史频率控制字。
可选的，在本公开实施例中，频率控制字F可以满足：
F＝F0+△f/fs'    公式(3)；
其中，F0为历史频率控制字，△f为目标频偏，fs'为基准输出频率。历史频率控制字F0是指目标历史时刻接收到的频率控制字，该目标历史时刻是指距接收到该频率控制字F的当前时刻最近一次的历史时刻。该基准输出频率fs'是指目标时钟产生电路30基于未发生频偏的初始频率和初始频率控制字生成的时钟信号的频率，该初始频率控制字是指在出厂或首次工作时配置于控制字生成子电路203中的频率控制字。即，时钟信号产生电路的基准输出频率fs'一般是固定不变的。
本公开实施例最终目的是使得基于频率发生偏移的初始频率生成的时钟信号的频率(即目标输出频率)，与基于频率未发生偏移的初始频率生成的时钟信号的频率(即基准输出频率)相同。由于直接调整初始频率成本较大，因此本公开实施例通过设置控制字提供电路20，并通过基于初始频率的频偏灵活生成频率控制字的方式，以低成本的方式保证了最终生成的时钟信号的频率受目标参数影响较小，或是甚至不受目标参数的影响，即保证最终生成的时钟信号的频率不受初始频率的频偏影响。
示例的，以对初始频率控制字进行初次调整，即以历史控制字F0为初始频 率控制字为例，示出生成频率控制字F的可选过程：假设目标频偏为△f，则若不调整频率控制字，即不调整频率，最终生成的时钟信号的频率fs”即满足：
fs”＝(fc+△f)/F0   公式(4)。
而为了保证最终生成的时钟信号的频率不受初始频率的频偏影响，则需要使得fs”＝fs'。假设fs'满足上述公式(1)，则可以推导得出fc即满足：
fc＝F0*fs'；
将该fc代入上述公式(4)，可以得出：
fs”＝fs'＝(F0*fs'+△f)/F；
整理即可得到频率控制字F满足：
F＝F0+△f/fs'，即得到上述公式(3)。
可选的，在本公开实施例中，频偏确定子电路202可以用于每隔检测周期基于温度检测子电路201输出的目标温度确定一次目标频偏。该检测周期可以为频偏确定子电路202出厂时预先配置好的，或者也可以为用户在后续基于当前目标参数变化情况实时输入的，本公开实施例对此不做限定。且，温度检测子电路201可以实时检测温度，或者，也可以每隔检测周期检测一次温度。
相应的，控制字生成子电路203还可以用于判断目标频偏与历史频偏是否相等，若不相等，则基于目标频偏、历史频率控制字和基准输出频率生成频率控制字。其中，历史频偏为频偏确定子电路202在上一个检测周期确定的目标频偏。也即是，控制字生成子电路203可以先判断当前获取到的目标频偏相对于最近一次获取到的目标频偏是否发生变化，并在发生变化时，再进一步基于目标频偏生成频率控制字。通过该设计，可以有效降低功耗，且可以避免不断基于目标频偏生成频率控制字而导致结果出错的问题。
示例的，图5是本公开实施例提供的一种控制字生成子电路203的结构示意图。如图5所示，该控制字生成子电路203可以包括：寄存器2031、比较器2032和控制字生成单元2033。
寄存器2031可以分别与频偏确定子电路202(图5未示出)、比较器2032和控制字生成单元2033连接。寄存器2031可以用于向比较器2032输出历史频偏(如图5示出的△f')，可以用于向控制字生成单元2033输出频偏确定子电路202输入的目标频偏(如图5示出的△f)，并可以用于采用目标频偏(如图5示出的△f)更新历史频偏。
比较器2032还可以分别与频偏确定子电路202(图5未示出)和控制字生成单元2033连接。比较器2032可以用于判断目标频偏与历史频偏是否相等，若不相等，则向控制字生成单元2033输出使能信号。若相等，则向控制字生成单元2033输出去使能信号，该去使能信号可以用于指示控制字生成单元2033停止向目标时钟提供电路输出频率控制字，或者，可以用于指示控制字生成单元2033不生成频率控制字，即控制该控制字生成单元2033停止工作。
控制字生成单元2033还可以与目标时钟产生电路30(图5未示出)连接。控制字生成单元2033可以用于响应于使能信号，基于目标频偏、历史频率控制字和基准输出频率生成频率控制字(如图5示出的F)，将频率控制字输出至目标时钟产生电路30，并采用频率控制字更新历史频率控制字。
需要说明的是，比较器2032可以仅与寄存器2031和控制字生成单元2033连接，寄存器2031还可以用于向比较器2032输出目标频偏，即由寄存器2031向比较器2032同时输出目标频偏和历史频偏。或者，寄存器2031可以仅与比较器2032连接，比较器2032在确定目标频偏与历史频偏不相等时，可以向控制字生成单元2033输出使能信号和目标频偏。又或者，寄存器2031可以仅与比较器2032连接，且控制字生成单元2033还与频偏确定子电路202连接，控制字生成单元2033可以直接接收频偏确定子电路202输入的目标频偏。
以图5示出的控制字生成子电路为例，图6示出了本公开实施例提供的另一种控制字生成子电路203的结构示意图。参考图6，该控制字生成单元2033可以包括：除法器J3、加法器J4和使能单元。其中比较器2032可以与使能单元连接，比较器2032在判断目标频偏与历史频偏不相等时，可以向使能单元输出使能信号，以控制使能单元控制除法器J3和加法器J4所在支路连通。相应的，该控制字生成单元2033即可以通过除法器J3和加法器J4，并基于目标频偏△f、历史频率控制字F0、基准输出频率fs'和上述公式(3)生成频率控制字F。
需要说明的是，上述记载的控制字提供电路20包括的频偏确定子电路202和控制字生成子电路203可以由硬件组成，即可以为硬件电路；或者，还可以为配置有代码程序的虚拟电路(如处理芯片)。本公开实施例对此不做限定。
继续参考图2，本公开实施例提供的目标时钟产生电路30可以包括：备选时钟产生子电路301和目标时钟产生子电路302。
其中，备选时钟产生子电路301可以分别与初始时钟提供电路10和目标时 钟产生子电路302连接。备选时钟产生子电路301可以用于基于初始时钟提供电路10输出的初始时钟信号生成多个备选时钟信号，并将多个备选时钟信号输出至目标时钟产生子电路302，其中每个备选时钟信号的周期和频率均相同，且任意两个相邻的备选时钟信号之间的相位差相同。
示例的，图7以备选时钟产生子电路301共生成K个备选时钟信号为例，示出了备选时钟信号的示意图。结合图7，每相邻两个备选时钟信号之间的相位差Δ可以满足：
Δ＝1/K*f    公式(5)；
其中，K为备选时钟信号的数量，f为每个备选时钟信号的频率。相应的，该备选时钟产生子电路301也可以称为K-inputs电路。
可选的，备选时钟产生子电路301能够生成的备选时钟信号数量K可以预先配置于该电路中，如，可以由用户(如，开发人员)在生产该电路时设置于该电路中。且，K可以为2的i次方，i可以为大于等于1的整数。例如，K可以为16、32、128或其他。
目标时钟产生子电路302还可以与控制字提供电路20连接，目标时钟产生子电路302可以用于基于多个备选时钟信号和控制字提供电路20输出的频率控制字生成目标输出频率的目标时钟信号。如图2示出的目标时钟产生子电路302与控制字提供电路20中最终生成频率控制字F的控制字生成子电路203连接。
图8是本公开实施例提供的一种目标时钟产生电路30中各子电路的结构示意图。如图8所示，该备选时钟产生子电路301可以包括：约翰计数器(Johns on Counter)。由于约翰计数器可以产生较多数量备选时钟信号，且由于时钟信号占空比分辨率为备选时钟信号数量的倒数，因此可以提高分辨率，精度更高。
继续参考图8，该目标时钟产生子电路302可以包括：输入模块3021、选择模块3022和输出模块3023。
其中，该输入模块3021可以与控制字提供电路20(图8未示出)连接，输入模块3021可以用于基于频率控制字(如图8示出的F)向选择模块3022输出选择控制信号。
选择模块3022还可以分别与备选时钟产生子电路301和输出模块3023连接，选择模块3022可以用于响应于选择控制信号，从多个备选时钟信号中选择一个目标备选时钟信号并输出至输出模块3023。
输出模块3023可以用于将目标备选时钟信号转换为目标时钟信号。
图9是本公开实施例提供的一种目标时钟产生电路30中各子电路的结构示意图。如图9所示，输入模块3021可以包括：第一寄存器R1、第二寄存器R2、第三寄存器R3、第四寄存器R4和两个加法器J11和J12。选择模块3022可以包括：第一选择器X1、第二选择器X2和第三选择器X3。输出模块3023可以包括：D触发器、第一反相器F1和第二反相器F2。
两个加法器J11和J12可以均分别与控制字提供电路20和第三寄存器R3连接，且一个加法器J11、第一寄存器R1、第二寄存器R2和第一选择器X1依次连接；另一个加法器J12、第三寄存器R3、第四寄存器R4和第二选择器X2依次连接。例如，图9示出的两个加法器J11和J12均连接至第三寄存器R3与第四寄存器R4相连的连接线上。
第一选择器X1和第二选择器X2还可以均分别与备选时钟产生子电路301和第三选择器X3连接，第三选择器X3还可以与D触发器的第一输入端连接。
D触发器的第二输入端可以与第一反相器F1的输出端连接，第一反相器F1的输入端和第二反相器F2的输入端可以与D触发器的输出端连接。需要说明的是，参考图9，D触发器输出端可以作为第一时钟信号端CLK1的输出，第二反相器F2的输出端可以作为第二时钟信号端CLK2的输出，且第一时钟信号端CLK1和第二时钟信号端CLK2提供的时钟信号仅相位相反且频率相同。
例如，结合图7和图9，假设备选时钟产生子电路301共生成K个备选时钟信号，则第一选择器X1和第二选择器X2均可以为图9所示的K->1选择器(即从K个备选时钟信号中选择1个目标备选时钟信号)。由于第三选择器X3用于从两个中选择一个，因此结合图9，该第三选择器X3可以为2->1选择器(即从2个备选时钟信号中选择1个目标备选时钟信号)。
结合图9，以第二寄存器R2和第三选择器X3连接第一时钟信号端CLK1，且第一寄存器R1、第三寄存器R3和第四寄存器R4均连接第二时钟信号端CLK2为例，对目标时钟产生电路30生成目标时钟信号的原理进行说明：
例如，一个加法器J11可以将频率控制字F的一部分(如图9所示的F/2)和第三寄存器R3存储的最高有效位(如，5比特)相加，然后在第二时钟信号端CLK2提供的第二时钟信号的上升沿时将相加结果保存到第一寄存器R1中；或者，一个加法器J11可以将频率控制字F的一部分和第三寄存器R3存储的所有 信息相加，然后在第二时钟信号的上升沿时将相加结果保存到第一寄存器R1中。在下一个第一时钟信号的上升沿时，第一寄存器R1存储的最高有效位将被存储到第二寄存器R2中，并作为第一选择器X1的选择信号。相应的，第一选择器X1即可以响应于该选择信号，从K个备选时钟信号中选择一个目标备选时钟信号作为第一选择器X1的输出信号并输出至第三选择器X3。
同理，另一个加法器J12可以将频率控制字F和第三寄存器R3存储的最高有效位相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器R3中。或者，另一个加法器J12可以将频率控制字F和第三寄存器R3存储的所有信息相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器R3中。在下一个第二时钟信号的上升沿时，第三寄存器R3存储的最高有效位将被存储到第四寄存器R4中，并作为第二选择器X2的选择信号。相应的，第二选择器X2即可以响应于该选择信号从K个备选时钟信号中选择一个目标备选时钟信号作为第二选择器X2的输出信号并输出至第三选择器X3。
进一步的，第三选择器X3可以在第一时钟信号的上升沿时，选择来自第一选择器X1的输出信号和来自第一选择器X2的输出信号中的一个作为第三选择器X3的输出信号并输出至D触发器，以作为D触发器的输入时钟信号。然后，D触发器的输出端和第二反相器F2的输出端之一输出的时钟信号即可以作为最终的输出信号，至此，即实现了目标时钟信号的生成。
可选的，第四寄存器R4输出的选择信号可以作为下降沿选择信号，第二寄存器R2输出的选择信号可以作为上升沿选择信号，第三寄存器R3反馈至加法器J12的信号可以用于控制生成的时钟的周期切换。相应的，可以将第四寄存器R4输出的选择信号称为下降沿控制字，将第二寄存器R2输出的选择信号称为上升沿控制字。
需要说明的是，输出至两个加法器J11和J12的频率控制字的大小可以由用户基于其所需的目标时钟信号的目标输出频率灵活设置；或者，可以由TAF-DPS电路基于最终需要生成的目标时钟信号的目标输出频率灵活设置，该目标输出频率可以由用户输入至TAF-DPS电路中。
还需要说明的是，本公开实施例记载的目标时钟产生电路30可以称为基于时间平均频率脉冲直接合成(Time-Average-Frequency Direct Period Synthesis，TAF-DPS)电路。该TAF-DPS电路的工作原理可以基于时间平均频率(time  average frequency，TAF)来实现。结合图10对基于该TAF方式得到目标输出频率的可实现过程进行示意性说明：
假设频率控制字为F，任两个相邻的备选时钟信号的相位差为Δ，F为F＝I+r1，I代表整数部分，r1代表小数部分。则通过该TAF方式可以输出两种时间周期T A和T B：
T A＝I*Δ  公式(6)；
T B＝(I+1)*Δ  公式(7)；
将该两种时间周期通过“周期合成”技术可以合成得到一个周期为目标周期的时钟信号，且该目标周期T TAF可以满足：
T TAF＝(1-r1)*T A+r1*T B   公式(8)；
将公式(6)和公式(7)代入公式(8)可以得到：
T TAF＝(I+r1)*Δ  公式(9)；
根据公式(9)可以看出，r1可以控制T B出现的概率，即频率控制字F的小数部分r1可以控制周期T A和T B之间的切换频率。基于公式(9)可以进一步计算出TAF-DPS电路输出的时钟信号的频率f TAF满足：
f TAF＝1/T TAF＝1/[(I+r1)*Δ]＝1/F*Δ   公式(10)；
将公式(5)计算得出的Δ代入公式(10)即可以得出：f TAF＝(K*f)/F。
该f TAF即为本公开实施例记载的目标输出频率fs。且，结合图9，该目标输出频率fs可以为TAF-DPS电路最终输出的第一时钟信号或第二时钟信号。
备选时钟产生子电路301其实是将初始时钟提供电路10输出的初始频率fc的初始时钟信号分频为K个频率为f的备选时钟信号，即K*f实际为fc，从而推导得出公式(1)记载的目标输出频率fs满足的条件：fs＝f TAF＝fc/F。
本公开实施例记载的时钟信号产生电路的可靠性和安全性较好，且因该电路的实现成本较低，因此可在各类电子设备中重复使用。
综上所述，本公开实施例提供了一种时钟信号产生电路。由于该时钟信号产生电路最终生成的时钟信号的目标输出频率与初始频率正相关，与频率控制字负相关，因此当初始频率受目标参数影响发生频偏时，可以通过基于目标频偏灵活生成频率控制字来实现对初始频率的可靠补偿，从而使得最终生成的目标时钟信号的频率受目标参数影响较小。该时钟信号产生电路生成时钟信号的可靠性较好。
图11是本公开实施例提供的一种时钟信号产生方法，可以应用于如图1或图2所示的时钟信号产生电路中。如图11所示，该方法可以包括：
步骤1101、初始时钟提供电路生成初始频率的初始时钟信号，并将初始时钟信号输出至目标时钟产生电路。
步骤1102、控制字提供电路检测影响初始频率的频偏的目标参数，基于目标参数确定初始频率的目标频偏，基于目标频偏生成频率控制字，并将频率控制字输出至目标时钟产生电路。
步骤1103、目标时钟信号产生电路基于频率控制字和初始时钟信号生成目标输出频率的目标时钟信号。
其中，目标输出频率可以与频率控制字负相关，且可以与初始频率正相关。
综上所述，本公开实施例提供了一种时钟信号产生方法，由于该时钟信号产生方法最终生成的时钟信号的目标输出频率与初始频率正相关，与频率控制字负相关，因此当初始频率受目标参数影响发生频偏时，可以通过基于目标频偏灵活生成频率控制字来实现对初始频率的可靠补偿，从而使得最终生成的目标时钟信号的频率受目标参数影响较小。该时钟信号产生电路生成时钟信号的可靠性较好。
需要说明的是，对于时钟信号产生电路包括的各电路的可选结构，以及步骤1101至步骤1103相应的可选实现方式可以参考上述针对装置侧的记载，在方法侧实施例不再赘述。
另外，图12示出了本公开实施例提供的一种电子设备。如图12所示，该电子设备包括：被控电路01，以及如图1或图2所示的时钟信号产生电路02。
其中，被控电路01可以与时钟信号产生电路02连接，被控电路01可以用于响应于时钟信号产生电路02输出的目标输出频率的目标时钟信号工作。
由于本公开实施例记载的时钟信号产生电路02输出的时钟信号的频率受目标参数影响较小或甚至不受目标参数影响，因此使得目标器件的工作安全性和可靠性更高。可选的，该电子设备可以为单片机、移动终端或嵌入式设备。
应当理解的是，在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的时钟信号产生电路包括的各电路、各子电路、各模块以及各器件的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种时钟信号产生电路，所述电路包括：初始时钟提供电路、控制字提供电路和目标时钟产生电路；
    所述初始时钟提供电路与所述目标时钟产生电路连接，所述初始时钟提供电路用于生成初始频率的初始时钟信号，并将所述初始时钟信号输出至所述目标时钟产生电路；
    所述控制字提供电路与所述目标时钟产生电路连接，所述控制字提供电路用于检测影响所述初始频率的频偏的目标参数，基于所述目标参数确定所述初始频率的目标频偏，基于所述目标频偏生成频率控制字，并将所述频率控制字输出至所述目标时钟产生电路；
    所述目标时钟产生电路用于基于所述频率控制字和所述初始时钟信号生成目标输出频率的目标时钟信号，其中，所述目标输出频率与所述频率控制字负相关，且与所述初始频率正相关。
  2. 根据权利要求1所述的时钟信号产生电路，其中，所述目标输出频率fs满足：fs＝fc/F，其中，fc为所述初始频率，F为所述频率控制字。
  3. 根据权利要求1所述的时钟信号产生电路，其中，所述目标参数包括：温度，所述控制字提供电路包括：温度检测子电路、频偏确定子电路和控制字生成子电路；
    所述温度检测子电路与所述频偏确定子电路连接，所述温度检测子电路用于检测目标温度，并将所述目标温度输出至所述频偏确定子电路；
    所述频偏确定子电路还与所述控制字生成子电路连接，所述频偏确定子电路用于基于所述目标温度确定所述初始频率的目标频偏，并将所述目标频偏输出至所述控制字生成子电路；
    所述控制字生成子电路还与所述目标时钟产生电路连接，所述控制字生成子电路用于基于所述目标频偏、历史频率控制字和基准输出频率生成频率控制字，将所述频率控制字输出至所述目标时钟产生电路，以及采用所述频率控制字更新所述历史频率控制字；
    其中，所述频率控制字F满足：F＝F0+△f/fs'，F0为所述历史频率控制字，△f为所述目标频偏，fs'为所述基准输出频率。
  4. 根据权利要求3所述的时钟信号产生电路，其中，所述频偏确定子电路包括：控制器和存储器，所述存储器中存储有与多个不同的温度一一对应的多个备选频偏；
    所述控制器分别与所述存储器和所述控制字生成子电路连接，所述控制器用于从所述存储器存储的多个备选频偏中查找与所述目标温度对应的目标备选频偏，将所述目标备选频偏确定为所述目标频偏，并将所述目标频偏输出至所述控制字生成子电路。
  5. 根据权利要求4所述的时钟信号产生电路，其中，所述存储器具有多个存储区域，每个所述存储区域中存储有一个所述备选频偏，且各个所述存储区域中存储的所述备选频偏不同；
    所述控制器用于基于所述目标温度从所述多个存储区域中确定目标存储区域的地址，并基于所述目标存储区域的地址从所述目标存储区域中获取所述目标频偏；
    其中，所述目标存储区域的地址A1满足：A1＝T/r+A0，A0为基准地址，T为所述目标温度，r为所述温度检测子电路的检测分辨率。
  6. 根据权利要求3所述的时钟信号产生电路，其中，所述频偏确定子电路用于每隔检测周期基于所述温度检测子电路输出的目标温度确定一次目标频偏；
    所述控制字生成子电路还用于判断所述目标频偏与历史频偏是否相等，若所述目标频偏与所述历史频偏不相等，则基于所述目标频偏、所述历史频率控制字和所述基准输出频率生成频率控制字；
    其中，所述历史频偏为所述频偏确定子电路在上一个检测周期确定的目标频偏。
  7. 根据权利要求6所述的时钟信号产生电路，其中，所述控制字生成子电路包括：寄存器、比较器和控制字生成单元；
    所述寄存器分别与所述频偏确定子电路、所述比较器和所述控制字生成单元连接，所述寄存器用于向所述比较器输出所述历史频偏，用于向所述控制字生成单元输出所述频偏确定子电路生成的目标频偏，以及用于采用所述目标频偏更新所述历史频偏；
    所述比较器还分别与所述频偏确定子电路和所述控制字生成单元连接，所述比较器用于判断所述目标频偏与所述历史频偏是否相等，若所述目标频偏与所述历史频偏不相等，则向所述控制字生成单元输出使能信号；
    所述控制字生成单元还与所述目标时钟产生电路连接，所述控制字生成单元用于响应于所述使能信号，基于所述目标频偏、历史频率控制字和基准输出频率生成频率控制字，将所述频率控制字输出至所述目标时钟产生电路，并采用所述频率控制字更新所述历史频率控制字。
  8. 根据权利要求1至7任一所述的时钟信号产生电路，其中，所述目标时钟产生电路包括：备选时钟产生子电路和目标时钟产生子电路；
    所述备选时钟产生子电路分别与所述初始时钟提供电路和所述目标时钟产生子电路连接，所述备选时钟产生子电路用于基于所述初始时钟提供电路输出的所述初始时钟信号生成多个备选时钟信号，并将所述多个备选时钟信号输出至所述目标时钟产生子电路，其中每个所述备选时钟信号的周期相同，且任意两个相邻的所述备选时钟信号之间的相位差相同；
    所述目标时钟产生子电路还与所述控制字提供电路连接，所述目标时钟产生子电路用于基于所述多个备选时钟信号和所述控制字提供电路输出的频率控制字，生成目标输出频率的目标时钟信号。
  9. 根据权利要求8所述的时钟信号产生电路，其中，所述目标时钟产生子电路包括：输入模块、选择模块和输出模块；
    所述输入模块与所述控制字提供电路连接，所述输入模块用于基于所述频率控制字向所述选择模块输出选择控制信号；
    所述选择模块还分别与所述备选时钟产生子电路和所述输出模块连接，所述选择模块用于响应于所述选择控制信号，从所述多个备选时钟信号中选择一个目标备选时钟信号并输出至所述输出模块；
    所述输出模块用于将所述目标备选时钟信号转换为所述目标时钟信号。
  10. 根据权利要求9所述的时钟信号产生电路，其中，所述输入模块包括：第一寄存器、第二寄存器、第三寄存器、第四寄存器和两个加法器；所述选择模块包括：第一选择器、第二选择器和第三选择器；所述输出模块包括：D触发器、第一反相器和第二反相器；
    所述两个加法器均分别与所述控制字提供电路和所述第三寄存器连接，且一个所述加法器、所述第一寄存器、所述第二寄存器和所述第一选择器依次连接，另一个所述加法器、所述第三寄存器、所述第四寄存器和所述第二选择器依次连接；
    所述第一选择器和所述第二选择器还均分别与所述备选时钟产生子电路和所述第三选择器连接，所述第三选择器还与所述D触发器的第一输入端连接；
    所述D触发器的第二输入端与所述第一反相器的输出端连接，所述第一反相器的输入端和所述第二反相器的输入端均与所述D触发器的输出端连接。
  11. 根据权利要求7所述的时钟信号产生电路，其中，所述目标输出频率fs满足：fs＝fc/F，其中，fc为所述初始频率，F为所述频率控制字；
    所述频偏确定子电路包括：控制器和存储器，所述存储器具有多个存储区域，每个所述存储区域中存储有一个备选频偏，且各个所述存储区域中存储的所述备选频偏不同；
    所述控制器分别与所述存储器和所述控制字生成子电路连接，所述控制器用于基于所述目标温度从所述多个存储区域中确定目标存储区域的地址，并基于所述目标存储区域的地址从所述目标存储区域中获取所述目标频偏；
    其中，所述目标存储区域的地址A1满足：A1＝T/r+A0，A0为基准地址，T为所述目标温度，r为所述温度检测子电路的检测分辨率；
    所述目标时钟产生电路包括：约翰计数器、第一寄存器、第二寄存器、第三寄存器、第四寄存器、两个加法器、第一选择器、第二选择器、第三选择器、D触发器、第一反相器和第二反相器；
    所述两个加法器均与所述控制字提供电路连接，且一个所述加法器、所述第一寄存器、所述第二寄存器和所述第一选择器依次连接，另一个所述加法器、 所述第三寄存器、所述第四寄存器和所述第二选择器依次连接；
    所述第一选择器和所述第二选择器还均分别与所述备选时钟产生子电路和所述第三选择器连接，所述第三选择器还与所述D触发器的第一输入端连接；
    所述D触发器的第二输入端与所述第一反相器的输出端连接，所述第一反相器的输入端和所述第二反相器的输入端均与所述D触发器的输出端连接。
  12. 一种时钟信号产生方法，其中，用于如权利要求1至11任一所述的时钟信号产生电路中，所述方法包括：
    初始时钟提供电路生成初始频率的初始时钟信号，并将所述初始时钟信号输出至目标时钟产生电路；
    控制字提供电路检测影响所述初始频率的频偏的目标参数，基于所述目标参数确定所述初始频率的目标频偏，基于所述目标频偏生成频率控制字，并将所述频率控制字输出至所述目标时钟产生电路；
    所述目标时钟产生电路基于所述频率控制字和所述初始时钟信号生成目标输出频率的目标时钟信号，其中，所述目标输出频率与所述频率控制字负相关，且与所述初始频率正相关。
  13. 根据权利要求12所述的方法，其中，所述目标参数包括：温度；所述控制字提供电路包括：温度检测子电路、频偏确定子电路和控制字生成子电路；所述控制字提供电路检测影响所述初始频率的频偏的目标参数，基于所述目标参数确定所述初始频率的目标频偏，基于所述目标频偏生成频率控制字，包括：
    所述温度检测子电路检测目标温度，并将所述目标温度输出至频偏确定子电路；
    所述频偏确定子电路基于所述目标温度确定所述初始频率的目标频偏，并将所述目标频偏输出至所述控制字生成子电路；
    所述控制字生成子电路基于所述目标频偏、历史频率控制字和基准输出频率生成频率控制字，所述频率控制字F满足：F＝F0+△f/fs'，F0为所述历史频率控制字，△f为所述目标频偏，fs'为所述基准输出频率；
    所述方法还包括：所述控制字生成子电路采用所述频率控制字更新所述历史频率控制字。
  14. 根据权利要求13所述的方法，其中，所述频偏确定子电路包括：控制器和存储器，所述存储器中存储有与多个不同的温度一一对应的多个备选频偏；所述频偏确定子电路基于所述目标温度确定所述初始频率的目标频偏，包括：
    所述控制器从所述存储器存储的多个备选频偏中查找与所述目标温度对应的目标备选频偏；
    所述控制器将所述目标备选频偏确定为所述目标频偏。
  15. 一种电子设备，其中，所述电子设备包括：被控电路，以及如权利要求1至11任一所述的时钟信号产生电路；
    所述被控电路与所述时钟信号产生电路连接，所述被控电路用于响应于所述时钟信号产生电路输出的目标输出频率的目标时钟信号工作。
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