WO2021196307A1 - 阵列基板检测键及显示面板 - Google Patents

阵列基板检测键及显示面板 Download PDF

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Publication number
WO2021196307A1
WO2021196307A1 PCT/CN2020/085873 CN2020085873W WO2021196307A1 WO 2021196307 A1 WO2021196307 A1 WO 2021196307A1 CN 2020085873 W CN2020085873 W CN 2020085873W WO 2021196307 A1 WO2021196307 A1 WO 2021196307A1
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Prior art keywords
layer
array substrate
detection key
source
substrate detection
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English (en)
French (fr)
Inventor
谭刚
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/765,430 priority Critical patent/US11527450B2/en
Publication of WO2021196307A1 publication Critical patent/WO2021196307A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers

Definitions

  • the invention relates to the field of display, in particular to an array substrate detection key and a display panel.
  • the existing method for the electrical monitoring of the array substrate is to make the TEG Test Key at the same time as the array substrate is made. Voltage is applied to the array substrate and the square resistance is measured at the test key. The voltage value is divided by the TEG Test Key. The resistance value can be used to obtain the current value, that is, the current value change curve of the array substrate can be detected, and characteristics such as the uniformity of the array substrate can be obtained through comparative analysis, and the quality of the array substrate can be understood.
  • FIG. 1 is a plan view of an existing array substrate detection key.
  • the array substrate detection key 200 includes two test areas 210 and a connection area 220 located between the two test areas 210.
  • the area 210 is provided with a groove 21, and the resistance value of the connection area 220 is measured by connecting probes in the grooves 21 of the two test areas 210 respectively.
  • FIG. 2 is a partial structural cross-sectional view of the detection key of the array substrate shown in FIG.
  • the connection region 220 also includes an indium tin oxide layer 219 on the flat organic layer 218, wherein The source and drain electrode layers 217 and the indium tin oxide layer 219 are alternately arranged at intervals, and pass through the flat organic layer 218 through the vias 22 to achieve electrical connection.
  • the groove 21 is substantially rectangular, and the groove 21 penetrates the flat organic layer 218 and exposes the source and drain electrode layer 217.
  • the flat organic layer 218 in the existing array substrate detection key 200 is prone to peeling off at the outer boundary of the groove 21, the array substrate detection key 200 is abnormal and cannot be used for monitoring.
  • the purpose of the present invention is to provide an array substrate detection key and a display panel, which can solve the problem that the flat organic layer in the prior art is prone to peeling off at the boundary, which causes the array substrate detection key to be abnormal and cannot be used for monitoring.
  • the problem is to ensure that the array substrate detection key is normal.
  • the present invention provides an array substrate detection key, which includes a glass substrate, multiple buffer layers, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source and drain electrode layer stacked in sequence. And a flat organic layer; wherein the array substrate detection key defines two test areas and a connection area between the two test areas; each test area is provided with a groove, the groove penetrates the flat The organic layer, the source and drain electrode layers, and the interlayer insulating layer expose the gate layer; the gate layer located in the test area extends toward the connection area and is connected to the connection area The source and drain electrode layers are electrically connected.
  • the gate layer located in the test area is electrically connected to the source and drain electrode layers in the connection area through a plurality of first via holes penetrating the interlayer insulating layer.
  • the source and drain electrode layers of the connection area are arranged at intervals
  • the source and drain electrode layers further include an indium tin oxide layer
  • the indium tin oxide layer and the source and drain electrode layers are alternately arranged at intervals and Partly overlapping, the indium tin oxide layer and the source and drain electrode layers are electrically connected through the flat organic layer through a second via hole at the overlapping position.
  • the width of the connection area is smaller than the width of the test area.
  • the multi-buffer layer includes a light-shielding layer, a first buffer layer, and a second buffer layer that are stacked; the light-shielding layer is arranged opposite to the active layer; the first buffer layer is located on the light-shielding layer and The light shielding layer is completely covered; the second buffer layer is located on the first buffer layer.
  • the material of the first buffer layer includes SiNx.
  • the material of the second buffer layer includes SiOx.
  • the material of the gate insulating layer includes SiOx.
  • the material of the interlayer insulating layer includes SiNx or SiOx.
  • the present invention also provides a display panel including the array substrate detection key, the display panel further includes an array substrate, and the test area of the array substrate detection key is electrically connected to the array substrate.
  • the beneficial effect of the present invention is to provide a detection key of an array substrate and a display panel thereof, which realizes electrical connection with the source and drain electrode layers of the connection area by extending the gate layer located in the test area, instead of existing
  • the thickness that is, increase from the flat organic layer on the source and drain electrode layer in the prior art to the interlayer insulating layer, the source and drain electrode layer, and the flat organic layer on the gate layer, Prevent it from peeling off at the boundary, so as to ensure that the array substrate detection key is normal and avoid abnormal phenomena in monitoring.
  • Fig. 1 is a plan view of a detection key of an existing array substrate
  • FIG. 2 is a partial structural cross-sectional view of the detection key of the existing array substrate shown in FIG. 1 along the A-A direction;
  • Figure 3 is a plan view of the detection key of the array substrate of the present invention.
  • FIG. 4 is a partial structural cross-sectional view of the detection key of the array substrate of the present invention shown in FIG. 3 along the B-B direction;
  • FIG. 5 is a schematic diagram of the structure of the multiple buffer layers of the detection key of the array substrate of the present invention.
  • Gate layer 16. Interlayer insulating layer, 17, Source and drain electrode layer, 18. Flat organic layer,
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, “plurality” means two or more than two, unless otherwise specifically defined.
  • the array substrate detection key 100 includes a glass substrate 11, a multi-buffer layer 12, an active layer 13, a gate insulating layer 14, and a gate layer which are stacked in sequence. 15.
  • Each test area 10 is provided with a groove 101, the groove 101 penetrates the flat organic layer 18, the source and drain electrode layer 17 and the interlayer insulating layer 16 and exposes the gate layer 15;
  • the gate layer 15 of the test area 10 extends toward the connection area 20 and is electrically connected to the source/drain electrode layer 17 of the connection area 20.
  • the gate layer 15 located in the test area 10 passes through a plurality of first via holes 201 penetrating the interlayer insulating layer 16 and the source/drain electrode layer 17 of the connection area 20 Realize electrical connection.
  • the source and drain electrode layers 17 of the connection region 20 are arranged at intervals, the source and drain electrode layers 17 further include an indium tin oxide layer 19, and the indium tin oxide layer 19 and the The source and drain electrode layers 17 are alternately arranged and partially overlapped.
  • the indium tin oxide layer 19 and the source and drain electrode layers 17 are electrically connected through the flat organic layer 18 through the second via 202 at the overlapping position.
  • the connecting area 20 is composed of a plurality of repeating units to form a wire with a certain resistance to connect the test area 10 at both ends of the connecting area 20, and each repeating unit is composed of the indium tin oxide layer 19 and the source
  • the drain electrode layer 17 is formed by connecting the second via 202 at the overlapping position.
  • the second via 202 has a relatively large resistance value.
  • the resistance value of the connecting region 20 is measured and divided by the number of repeating units.
  • the resistance value of each repeating unit can be obtained by the number, and the measurement method is the prior art, and will not be repeated here.
  • the width of the connection area 20 is smaller than the width of the test area 10.
  • the width of the groove 101 on the side of the test area 10 facing the connection area 20 is equal to the width of the connection area 20.
  • the groove 101 is approximately rectangular, and is used to connect probes to measure the resistance of the connection area 20.
  • the test area 10 extends toward the gate layer 15 on the side of the connection area 20.
  • the width of the groove 101 is narrowed to form a connecting end, and the width of the connecting end is equal to the width of the connecting area 20.
  • the multi-buffer layer 12 includes a light shielding layer 121, a first buffer layer 122 and a second buffer layer 123 that are stacked.
  • the light-shielding layer 121 is disposed opposite to the active layer 13;
  • the first buffer layer 122 is located on the light-shielding layer 121 and completely covers the light-shielding layer 121;
  • the second buffer layer 123 is located on the first On the buffer layer 122.
  • the material of the first buffer layer includes SiNx.
  • the material of the second buffer layer includes SiOx.
  • the material of the gate insulating layer 14 includes SiOx.
  • the material of the interlayer insulating layer 16 includes SiNx or SiOx.
  • the interlayer insulating layer 16 may be one layer or multiple layers, and the arrangement of the multiple layers of the interlayer insulating layer 16 is that the SiNx layer and the SiOx layer are overlapped.
  • the present invention also provides a display panel, including the array substrate detection key 100, the display panel further includes an array substrate (not shown), the test area 10 of the array substrate detection key 100 and the array substrate The substrate is electrically connected. Wherein, the structure of the test area 10 and the display panel can be manufactured at the same time.
  • the gate layer 15 in the test area 10 and the gate layer 15 in the display area of the display panel are not connected to each other, and the gate layer 15 in the test area 10 only serves as a The lead-out function of the array substrate detection key 100 is described. And the formation of the gate layer 15 in the test area 10 can effectively increase the film thickness of the groove 101 around the test area 10, preventing it from peeling off at the boundary, and being exposed through the groove 101
  • the gate layer 15 is electrically connected to an external device for measuring the resistance value of the connection area 20.
  • a voltage U can be applied to the display panel where the detection key 100 of the array substrate is located, and the gate layer 15 exposed in the groove 101 of the two test areas 10 can be connected to the probe respectively.
  • a needle is used to measure the resistance value R of the connection area 20, and by calculating U/R, it can be known that the current I passing through the array substrate detection key 100 is the current I passing through the display panel where the array substrate detection key 100 is located.
  • U/R the current I passing through the array substrate detection key 100 is the current I passing through the display panel where the array substrate detection key 100 is located.
  • the display can be inferred.
  • the resistance value R is a square resistance, and its measurement method is in the prior art, which will not be repeated here.
  • the thickness range of the panel can also be inferred through the resistance value R, which is also the prior art and will not be repeated here.
  • the existing measurement result range is 45-65 ⁇ /cm 2
  • the measurement result range of the embodiment of the present invention is an increase of 0.8-1.2 ⁇ on the basis of 45-65 ⁇ /cm 2 /cm 2 , because the area of the array substrate detection key 100 is small relative to the area of the display panel, the increased resistance is negligible, so there is no need to adjust other existing related equipment, which has a strong Practicality.
  • the beneficial effect of the present invention is to provide a detection key of an array substrate and a display panel thereof, which realizes electrical connection with the source and drain electrode layers of the connection area by extending the gate layer located in the test area, instead of existing
  • the thickness that is, increase from the flat organic layer on the source and drain electrode layer in the prior art to the interlayer insulating layer, the source and drain electrode layer, and the flat organic layer on the gate layer, Prevent it from peeling off at the boundary, so as to ensure that the array substrate detection key is normal and avoid abnormal phenomena in monitoring.

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Abstract

一种阵列基板检测键（100）及其显示面板。阵列基板检测键（100）包括依次层叠设置的玻璃基板（11）、多缓冲层（12）、有源层（13）、栅极绝缘层（14）、栅极层（15）、层间绝缘层（16）、源漏电极层（17）和平坦有机层（18）；阵列基板检测键（100）定义有两个测试区（10）和连接区（20）；每一测试区（10）设有裸露栅极层（15）的凹槽（101）；位于测试区（10）的栅极层（15）与连接区（20）的源漏电极层（17）电连接。

Description

阵列基板检测键及显示面板 技术领域
本发明涉及显示领域，尤其涉及一种阵列基板检测键及显示面板。
 背景技术
针对阵列基板电性监控的现有方法为在阵列基板制作的同时在其周边同时制作检测键（TEG Test Key），通过对阵列基板施加电压，并在检测键处测量方块电阻，用电压值除以电阻值可得到电流值，即可检测阵列基板的电流值变化曲线，通过对比分析可得出阵列基板的均匀性等特性，进而可了解阵列基板的品质。
请参阅图1所示，为现有阵列基板检测键的平面图，所述阵列基板检测键200包括两个测试区210和位于所述两个测试区210之间的连接区220，在所述测试区210设置一凹槽21，通过在所述两个测试区210的所述凹槽21内分别连接探针来测量所述连接区220的电阻值。
请参阅图2所示，为图1所示阵列基板检测键沿A-A方向的局部结构剖面图，所述测试区210包括依次层叠设置的玻璃基板211、多缓冲层212、有源层213、栅极绝缘层214、栅极层215、层间绝缘层216、源漏电极层217和平坦有机层218；所述连接区220还包括位于所述平坦有机层218上的氧化铟锡层219，其中所述源漏电极层217与所述氧化铟锡层219间隔交错设置，并通过过孔22贯穿所述平坦有机层218实现电连接。
请同时参阅图1和图2所示，所述凹槽21大体呈矩形，所述凹槽21贯穿所述平坦有机层218并裸露所述源漏电极层217。但由于现有的阵列基板检测键200中的所述平坦有机层218在所述凹槽21外侧边界处易出现剥落，从而导致所述阵列基板检测键200异常而无法用于监控。
 技术问题
本发明的目的在于，提供一种阵列基板检测键及显示面板，可解决现有技术中的所述平坦有机层在边界处易出现剥落从而导致所述阵列基板检测键异常无法用于监控的技术问题，保证所述阵列基板检测键正常。
 技术解决方案
为了解决上述问题，本发明中提供一种阵列基板检测键，包括依次层叠设置的玻璃基板、多缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏电极层和平坦有机层；其中，所述阵列基板检测键定义有两个测试区和位于所述两个测试区之间的连接区；每一测试区设有一凹槽，所述凹槽贯穿所述平坦有机层、所述源漏电极层和所述层间绝缘层并裸露所述栅极层；位于所述测试区的所述栅极层朝向所述连接区延伸并与所述连接区的所述源漏电极层电连接。
进一步的，其中位于所述测试区的所述栅极层通过多个贯穿所述层间绝缘层的第一过孔与所述连接区的所述源漏电极层实现电连接。
进一步的，其中所述连接区的所述源漏电极层间隔设置，所述源漏电极层上还包括一氧化铟锡层，所述氧化铟锡层与所述源漏电极层间隔交错设置且部分重叠，所述氧化铟锡层与所述源漏电极层在重叠位置通过第二过孔贯穿所述平坦有机层实现电连接。
进一步的，其中所述连接区的宽度小于所述测试区的宽度。
进一步的，其中所述多缓冲层包括层叠设置的遮光层、第一缓冲层和第二缓冲层；所述遮光层与所述有源层相对设置；第一缓冲层位于所述遮光层上且完全覆盖所述遮光层；第二缓冲层位于所述第一缓冲层上。
进一步的，其中所述第一缓冲层的材料包括SiNx。
进一步的，其中所述第二缓冲层的材料包括SiOx。
进一步的，其中所述栅极绝缘层的材料包括SiOx。
进一步的，其中所述层间绝缘层的材料包括SiNx或SiOx。
本发明还提供一种显示面板，包括所述阵列基板检测键，所述显示面板还包括有一阵列基板，所述阵列基板检测键的所述测试区与所述阵列基板电连接。
 有益效果
本发明的有益效果是：提供一种阵列基板检测键及其显示面板，通过延伸位于所述测试区的所述栅极层实现与所述连接区的所述源漏电极层电连接，代替现有技术延伸位于所述测试区的所述源漏电极层实现与所述连接区的所述氧化铟锡层电连接，从而增加了所述测试区与所述连接区电连接部位上的膜层厚度，即从现有技术所述源漏电极层上的所述平坦有机层增加为所述栅极层上的所述层间绝缘层、所述源漏电极层和所述平坦有机层，可防止其在边界处出现剥落，从而保证所述阵列基板检测键正常并避免监控出现异常现象。
 附图说明
图1为现有阵列基板检测键的平面图；
图2为图1所示现有阵列基板检测键沿A-A方向的局部结构剖面图；
图3为本发明阵列基板检测键的平面图；
图4为图3所示本发明阵列基板检测键沿B-B方向的局部结构剖面图；
图5为本发明阵列基板检测键的多缓冲层的结构示意图。
图中部件标识如下：
100、阵列基板检测键,10、测试区,20、连接区,
11、玻璃基板，12、多缓冲层，13、有源层，14、栅极绝缘层，
15、栅极层，16、层间绝缘层，17、源漏电极层，18、平坦有机层，
19、氧化铟锡层，101、凹槽，201、第一过孔，202、第二过孔，
121、遮光层，122、第一缓冲层，123、第二缓冲层。
 本发明的实施方式
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
请参阅图3、图4所示，本发明一实施例中，阵列基板检测键100包括依次层叠设置的玻璃基板11、多缓冲层12、有源层13、栅极绝缘层14、栅极层15、层间绝缘层16、源漏电极层17和平坦有机层18；其中，所述阵列基板检测键100定义有两个测试区10和位于所述两个测试区10之间的连接区20；每一测试区10设有一凹槽101，所述凹槽101贯穿所述平坦有机层18、所述源漏电极层17和所述层间绝缘层16并裸露所述栅极层15；位于所述测试区10的所述栅极层15朝向所述连接区20延伸并与所述连接区20的所述源漏电极层17电连接。
在本实施例中，位于所述测试区10的所述栅极层15通过多个贯穿所述层间绝缘层16的第一过孔201与所述连接区20的所述源漏电极层17实现电连接。
请参阅图4所示，所述连接区20的所述源漏电极层17间隔设置，所述源漏电极层17上还包括一氧化铟锡层19，所述氧化铟锡层19与所述源漏电极层17间隔交错设置且部分重叠，所述氧化铟锡层19与所述源漏电极层17在重叠位置通过第二过孔202贯穿所述平坦有机层18实现电连接。所述连接区20由多个重复单元构成一个具有一定电阻的接线来连接位于所述连接区20两端的所述测试区10，每一重复单元均由所述氧化铟锡层19与所述源漏电极层17在重叠位置通过所述第二过孔202连接组成，所述第二过孔202处存在较大的电阻值，通过测量所述连接区20的电阻值并除以重复单元的个数即可得知每一重复单元的电阻值，其测量方式为现有技术，在此不做赘述。
在本实施例中，所述连接区20的宽度小于所述测试区10的宽度。
在本实施例中，所述凹槽101在所述测试区10朝向所述连接区20一侧的宽度等于所述连接区20的宽度。所述凹槽101大致呈矩形，用于连接探针来测量所述连接区20的电阻值，在所述测试区10朝向所述连接区20一侧延伸的所述栅极层15上的所述凹槽101的宽度变窄形成连接端，连接端的宽度等于所述连接区20的宽度。
请参阅图5所示，所述多缓冲层12包括层叠设置的遮光层121、第一缓冲层122和第二缓冲层123。具体地讲，所述遮光层121与所述有源层13相对设置；第一缓冲层122位于所述遮光层121上且完全覆盖所述遮光层121；第二缓冲层123位于所述第一缓冲层122上。
在本实施例中，所述第一缓冲层的材料包括SiNx。
在本实施例中，所述第二缓冲层的材料包括SiOx。
在本实施例中，所述栅极绝缘层14的材料包括SiOx。
在本实施例中，所述层间绝缘层16的材料包括SiNx或SiOx。所述层间绝缘层16可以为一层，也可以为多层，多层所述层间绝缘层16的设置方式为SiNx层与SiOx层交叠设置。
本发明还提供一种显示面板，包括所述阵列基板检测键100，所述显示面板还包括有一阵列基板（图未示），所述阵列基板检测键100的所述测试区10与所述阵列基板电连接。其中，所述测试区10与所述显示面板的结构可同时制作。
值得注意的是，位于所述测试区10的所述栅极层15与位于显示面板显示区的所述栅极层15互不连接，所述测试区10的所述栅极层15仅仅作为所述阵列基板检测键100的引出作用。并且在所述测试区10制作所述栅极层15可有效增加所述凹槽101在所述测试区10的四周的膜层厚度，防止其在边界处出现剥落，通过所述凹槽101裸露的所述栅极层15与外部设备电连接用于测量所述连接区20的电阻值。
在使用时，可通过在所述阵列基板检测键100所在的显示面板上施加一个电压U，在所述两个测试区10的所述凹槽101内裸露的所述栅极层15分别连接探针来测量所述连接区20的电阻值R,通过计算U/R可知通过所述阵列基板检测键100的电流I，即为通过所述阵列基板检测键100所在的显示面板的电流I。通过统计所述电流I随时间变化的曲线，并与标准变化曲线对比可知所述显示面板通过的电流I变化是否正常，尤其是通过对比所述电流I的最大趋向值，即可推知所述显示面板的所述阵列基板部分的均匀性是否良好，从而可判断所述显示面板的寿命长短。另外，所述电阻值R为方块电阻，其测量方式为现有技术，在此不做赘述。通过所述电阻值R也可推算得知所述面板的厚度范围，其也为现有技术，在此不做赘述。
当测量所述连接区20的电阻值R时，现有的测量结果范围为45-65Ω/cm 2，本发明实施例的测量结果范围为在45-65Ω/cm 2基础上增加0.8-1.2Ω/cm 2，由于所述阵列基板检测键100的面积相对于所述显示面板的面积很小，因此其增加的电阻可忽略不计，因此不需要对现有其他相关设备进行调整，其具有很强的实用性。
本发明的有益效果是：提供一种阵列基板检测键及其显示面板，通过延伸位于所述测试区的所述栅极层实现与所述连接区的所述源漏电极层电连接，代替现有技术延伸位于所述测试区的所述源漏电极层实现与所述连接区的所述氧化铟锡层电连接，从而增加了所述测试区与所述连接区电连接部位上的膜层厚度，即从现有技术所述源漏电极层上的所述平坦有机层增加为所述栅极层上的所述层间绝缘层、所述源漏电极层和所述平坦有机层，可防止其在边界处出现剥落，从而保证所述阵列基板检测键正常并避免监控出现异常现象。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板检测键，包括依次层叠设置的玻璃基板、多缓冲层、有源层、栅极绝缘层、栅极层、层间绝缘层、源漏电极层和平坦有机层；
    其中，所述阵列基板检测键定义有两个测试区和位于所述两个测试区之间的连接区；
    每一测试区设有一凹槽，所述凹槽贯穿所述平坦有机层、所述源漏电极层和所述层间绝缘层并裸露所述栅极层；
    位于所述测试区的所述栅极层朝向所述连接区延伸并与所述连接区的所述源漏电极层电连接。
  2. 根据权利要求1所述的阵列基板检测键，其中，位于所述测试区的所述栅极层通过多个贯穿所述层间绝缘层的第一过孔与所述连接区的所述源漏电极层实现电连接。
  3. 根据权利要求1所述的阵列基板检测键，其中，
    所述连接区的所述源漏电极层间隔设置，所述源漏电极层上还包括一氧化铟锡层，所述氧化铟锡层与所述源漏电极层间隔交错设置且部分重叠，所述氧化铟锡层与所述源漏电极层在重叠位置通过第二过孔贯穿所述平坦有机层实现电连接。
  4. 根据权利要求1所述的阵列基板检测键，其中，所述连接区的宽度小于所述测试区的宽度。
  5. 根据权利要求1所述的阵列基板检测键，其中，
    所述多缓冲层包括
    遮光层，与所述有源层相对设置；
    第一缓冲层，位于所述遮光层上且完全覆盖所述遮光层；以及
    第二缓冲层，位于所述第一缓冲层上。
  6. 根据权利要求5所述的阵列基板检测键，其中，所述第一缓冲层的材料包括SiNx。
  7. 根据权利要求5所述的阵列基板检测键，其中，所述第二缓冲层的材料包括SiOx。
  8. 根据权利要求1所述的阵列基板检测键，其中，所述栅极绝缘层的材料包括SiOx。
  9. 根据权利要求1所述的阵列基板检测键，其中，所述层间绝缘层的材料包括SiNx或SiOx。
  10. 一种显示面板，其包括权利要求1所述的阵列基板检测键，所述显示面板还包括有一阵列基板，所述阵列基板检测键的所述测试区与所述阵列基板电连接。
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