WO2019196404A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2019196404A1
WO2019196404A1 PCT/CN2018/115070 CN2018115070W WO2019196404A1 WO 2019196404 A1 WO2019196404 A1 WO 2019196404A1 CN 2018115070 W CN2018115070 W CN 2018115070W WO 2019196404 A1 WO2019196404 A1 WO 2019196404A1
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WIPO (PCT)
Prior art keywords
substrate
conductive layer
display
metal
disposed
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PCT/CN2018/115070
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English (en)
French (fr)
Inventor
张博
王静妮
郭坤
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/466,709 priority Critical patent/US11404448B2/en
Publication of WO2019196404A1 publication Critical patent/WO2019196404A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3001—Structure
    • H01L2224/3003—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3005—Shape
    • H01L2224/30051—Layer connectors having different shapes

Definitions

  • Embodiments of the present disclosure relate to a display substrate, a method of fabricating the same, and a display device.
  • the display substrate in the display has a bonding area, and the panel and the flexible printed wiring board (FPC) are combined and turned on according to a certain working flow by an anisotropic conductive adhesive, and connected to a structure such as a control IC. Thereby, the input and control of signals in the display can be achieved.
  • FPC flexible printed wiring board
  • the current display substrate, the manufacturing method, and the display device still need to be improved.
  • An embodiment of the present disclosure provides a display substrate, including:
  • a substrate substrate including a bonding region
  • connection terminal located in the bonding region of the substrate substrate, comprising: a first conductive layer and a second conductive layer in contact with each other, wherein the first conductive layer and the direction perpendicular to the substrate substrate The second conductive layers overlap each other.
  • the orthographic projection of the first conductive layer on the substrate substrate and the orthographic projection of the second conductive layer on the substrate substrate differ in at least one of a shape and a size.
  • the first conductive layer is located on a side of the second conductive layer away from the substrate substrate, and an orthographic projection of the first conductive layer on the substrate substrate is smaller than the second conductive
  • An orthographic projection of a layer on the substrate substrate, and the orthographic projection of the first conductive layer on the substrate substrate is entirely at the positive side of the second conductive layer on the substrate substrate Within the projection.
  • the substrate substrate further includes a display region that does not overlap the bonding region, the thin film transistor and the pixel electrode are located in the display region, and the thin film transistor includes a gate and a source and a drain.
  • the first conductive layer is electrically connected to the thin film transistor, and the second conductive layer is electrically connected only to the first conductive layer.
  • the second conductive layer is of the same material as the gate, and the first conductive layer is of the same material as the source and drain.
  • the second conductive layer is disposed in the same material as the pixel electrode, and the first conductive layer and the source and drain layers are disposed in the same material.
  • the second conductive layer is disposed in the same material as the touch electrode, and the first conductive layer and the source and drain layers are disposed in the same material.
  • At least one of the first conductive layer and the second conductive layer includes a plurality of sub-conductive layers.
  • the first conductive layer includes a Ti/Al/Ti stack
  • the second conductive layer includes at least one of molybdenum and indium tin oxide.
  • connection terminal is configured to be electrically connected to a circuit board.
  • a display device including:
  • a further embodiment of the present disclosure provides a method for fabricating the above display substrate, including:
  • connection terminal is provided in the bonding region of the substrate substrate.
  • the substrate substrate does not overlap with the bonding region
  • the thin film transistor and the pixel electrode are located in the display region
  • the thin film transistor includes a gate and a source and a drain.
  • disposing the connection terminal in the bonding region of the substrate substrate includes:
  • the second conductive layer and the gate of the thin film transistor are synchronously disposed by a first patterning process
  • the first conductive layer and the source and drain of the thin film transistor are synchronously disposed by a second patterning process.
  • disposing the connection terminal in the bonding region of the substrate substrate includes:
  • the first conductive layer and the source and drain of the thin film transistor are synchronously disposed by a first patterning process
  • the second conductive layer and the pixel electrode are synchronously disposed on a side of the first conductive layer away from the substrate substrate by a second patterning process.
  • the display substrate further includes a touch electrode on the substrate substrate,
  • the connecting terminal is disposed in the bonding area of the substrate substrate, including:
  • the first conductive layer and the source and drain of the thin film transistor are synchronously disposed by using a first patterning process
  • the second conductive layer and the touch electrode are synchronously disposed on a side of the first conductive layer away from the substrate substrate by a second patterning process.
  • FIG. 1 shows a schematic structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a view showing an electron micrograph showing the connection of the connection terminal of the bonding region of the substrate in the related art
  • FIG. 4 is a schematic structural view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 6 shows a schematic structural view of a display substrate according to another embodiment of the present disclosure
  • FIG. 7 is a schematic structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic structural view of a display substrate according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic structural view of a display device according to an embodiment of the present disclosure.
  • FIG. 10 illustrates a bonding process of a display device according to an embodiment of the present disclosure
  • FIG. 11 shows a flow chart of fabricating a display substrate in accordance with one embodiment of the present disclosure.
  • a display device having a flexible printed wiring board is susceptible to damage to a connection terminal connected to a flexible printed wiring board due to a display substrate (such as an array substrate or a back sheet of an OLED), thereby affecting performance of the display device.
  • a display substrate such as an array substrate or a back sheet of an OLED
  • the connection terminal is easily scratched.
  • the scratch or blow of the connection terminal may cause the signal in the control unit connected to the connection terminal to be input to the display through the connection terminal, thereby causing the display screen to be abnormal and the display quality to be poor.
  • the display substrate and the manufacturing method thereof and the display device provided by the embodiments of the present disclosure can at least alleviate or solve at least one of the above mentioned problems to some extent.
  • the present disclosure provides a display substrate.
  • the display substrate includes a substrate substrate 100 and a connection terminal 200.
  • the substrate substrate 100 includes a bonding region 10
  • the connection terminal 200 is disposed on the bonding region 10 of the substrate substrate 100.
  • the connection terminal 200 includes a first metal 210 and a sacrificial metal 220 that are stacked and in contact with each other.
  • the first metal 210 is an example of a first conductive layer
  • the sacrificial metal 220 is an example of a second conductive layer.
  • connection terminal of the bonding region of the display substrate has a double-layer metal, whereby when the upper metal is scratched or blown, the underlying metal can be used for conduction, thereby avoiding signals caused by scratching or burning of the upper metal.
  • the problem that the conduction cannot be performed can improve the production yield of the display substrate and improve the display quality of the display device to which the display substrate is applied.
  • connection terminal for displaying the bonding region of the substrate is composed of a layer of metal, and the connection terminal is easily scratched or blown during the cutting, detecting, module process or during the handling of the display substrate.
  • the scratch or blow of the connection terminal may cause the signal in the control unit connected to the connection terminal to be input to the display through the connection terminal, thereby causing the display screen to be abnormal and the display quality to be poor.
  • FIG. 2 The case where the connection terminal is scratched is referred to FIG. 2, and the left side is a front view.
  • the surface of the connection terminal 200 has many scratches, and the right side is a back photo, and the scratch on the back surface of the connection terminal 200 is not obvious.
  • connection terminals are not cut, the scratches may affect the connection of the connection terminals to the flexible printed wiring board in the subsequent process, resulting in problems such as poor contact.
  • FIG. 3 for the case where the connection terminal is blown, and the front view is a front view.
  • the surface of the connection terminal 200 has a cauterization area, and the right side is a photo of the back surface.
  • the cavities are also present at the back of the connection terminal 200 and the front side, and the connection terminal 200 is blown. , causing the signal to be unconductive.
  • the methods used to alleviate the above problems are mainly improvements in the workmanship, for example, improving the cutting method, but the improvement in the workmanship cannot fundamentally solve the above problems.
  • the structure of the display substrate bonding region connection terminal is improved: the connection terminal includes a bimetal layer, and in the case where the upper metal is scratched or blown, the underlying metal can be used for conduction, thereby The problem that the signal caused by scratching or blowing of the upper metal is prevented from being turned on, thereby improving the production yield of the display substrate and improving the display quality of the display device to which the display substrate is applied.
  • the connection terminal 200 includes the first metal 210 and the sacrificial metal 220.
  • the positional relationship of the first metal and the sacrificial metal is not particularly limited as long as the first metal and the sacrificial metal are stacked and brought into contact with each other.
  • the sacrificial metal 220 is disposed on the substrate substrate 100, and the first metal 210 is disposed on a side of the sacrificial metal 220 away from the substrate substrate 100.
  • the signal can still be transmitted through the sacrificial metal at the breakpoint.
  • the first metal 210 is disposed on the substrate substrate 100, and the sacrificial metal 220 is disposed on a side of the first metal 210 away from the substrate substrate 100.
  • the first metal can be protected by the sacrificial metal, and the scratch or blow of the first metal can be avoided to ensure the conduction of the signal.
  • the first metal 210 is connected to the thin film transistor, and the sacrificial metal 220 is an island structure.
  • the sacrificial metal 220 is only electrically connected to the first metal 210 and is not electrically connected to any other conductive member.
  • the display substrate transmits the input signal to the thin film transistor through the first metal, and the sacrificial metal is only used as the first metal A transitional structure when wounded or blown, or sacrificial metal is only a protective layer of the first metal to avoid the adverse effects of the first metal scratch or blow on the transmission of electrical signals.
  • the orthographic projection of the sacrificial metal 220 on the substrate substrate 100 differs from the orthographic projection of the sacrificial metal 220 on the substrate substrate 100 in at least one of a shape and a size.
  • the first metal 210 when the sacrificial metal 220 is disposed on the substrate substrate 100, the first metal 210 is disposed on a side of the sacrificial metal 220 away from the substrate substrate 100, and the first metal 210 is positive on the substrate substrate 100.
  • the projection is smaller than the orthographic projection of the sacrificial metal 220 on the substrate substrate 100.
  • the orthographic projection of the first metal 210 on the substrate substrate 100 is entirely within the orthographic projection of the sacrificial metal 220 on the substrate substrate 100. That is, the orthographic projection of the first metal 210 on the substrate substrate 100 does not exceed the edge of the orthographic projection of the sacrificial metal 220 on the substrate substrate 100.
  • any scratch or blow of the first metal anywhere ensures that the signal can still be transmitted through the sacrificial metal at the breakpoint.
  • the orthographic projection of the sacrificial metal 220 on the substrate substrate 100 is completely smaller than the first The orthographic projection of the metal 210 on the substrate substrate 100.
  • the orthographic projection of the sacrificial metal 220 on the substrate substrate 100 is entirely within the orthographic projection of the first metal 210 on the substrate substrate 100.
  • the orthographic projection of the sacrificial metal 220 on the substrate substrate 100 does not exceed the edge of the orthographic projection of the first metal 210 on the substrate substrate 100.
  • any sacrificial metal is scratched or blown at any point to ensure that the signal can be transmitted through the first metal.
  • the specific material of the first metal and the sacrificial metal is not particularly limited as long as it has good conductivity.
  • the sacrificial metal may include at least one of molybdenum (Mo) and indium tin oxide (ITO), and the first metal may include three sub-conductive layers, for example, the first metal includes titanium/aluminum/titanium (Ti/Al/Ti).
  • Mo molybdenum
  • ITO indium tin oxide
  • the first metal may include three sub-conductive layers, for example, the first metal includes titanium/aluminum/titanium (Ti/Al/Ti).
  • titanium/aluminum/titanium is a stack of three layers of titanium, aluminum and titanium, wherein the aluminum metal is coated on the first layer of titanium metal, and the second layer of titanium metal is coated on the aluminum metal away from the first layer.
  • One side of titanium is a stack of three layers of titanium, aluminum and titanium, wherein the aluminum metal is coated on the first layer of titanium metal, and the second layer of titanium metal is coated on the aluminum metal away from the first layer.
  • the first metal 210 is disposed on a side of the sacrificial metal 220 away from the substrate substrate 100, and the first layer of titanium metal in the first metal 210 is disposed On the side of the sacrificial metal 220 away from the substrate substrate 100, the aluminum metal in the first metal 210 is disposed on a side of the first layer of titanium metal away from the sacrificial metal 220, and the second layer of titanium in the first metal 210 is disposed on the aluminum The metal is away from the side of the first layer of titanium.
  • the first metal 210 when the first metal 210 is disposed on the substrate substrate 100 and the sacrificial metal 220 is disposed on a side of the first metal 210 away from the substrate substrate 100, the first layer of titanium in the first metal 210 Disposed on the substrate substrate 100, the aluminum metal in the first metal 210 is disposed on a side of the first layer of titanium metal away from the substrate substrate 100, and the second layer of titanium metal in the first metal 210 is disposed on the aluminum metal away from the first On one side of the layer of titanium metal, the sacrificial metal 220 is disposed on the side of the second layer of titanium metal away from the aluminum metal.
  • the display substrate may further include a buffer layer 300 and a gate insulating layer 400, wherein the buffer layer 300 is disposed between the sacrificial metal 220 and the substrate substrate 100 (as shown in FIG. 4
  • the buffer layer 300 is disposed between the first metal 210 and the substrate substrate 100 (as shown in FIG. 5), and the gate insulating layer 400 is disposed on a side of the buffer layer 300 away from the substrate substrate 100.
  • the buffer layer can be added to increase the bonding force between the substrate substrate and the metal layer, thereby improving the performance of the display substrate, and the gate insulating layer can be used to realize the function of using the display substrate.
  • a connection terminal is fabricated on a display substrate by using an existing fabrication process, thereby not introducing a new process, saving equipment, and saving cost.
  • the sacrificial metal is disposed on the substrate substrate, the first metal is disposed on a side of the sacrificial metal away from the substrate substrate, and the sacrificial metal is disposed in the same layer as the gate in the thin film transistor, and is to be first
  • the metal and the thin film transistor have the same material and drain in the same layer, so that the sacrificial metal and the first metal can be fabricated by using the existing process, thereby saving cost. For example, referring to FIG.
  • the substrate substrate 100 includes a display region 30.
  • the display region 30 is provided with a thin film transistor including a gate 510, a source 530, and a drain 540, wherein the sacrificial metal 220 is the same layer as the gate 510.
  • the material is disposed, and the first metal 210 is disposed in the same material as the source and drain.
  • the source and drain of the thin film transistor include a source 530 and a drain 540.
  • the first metal 210 may be disposed in the same material as any one of the source 530 and the drain 540.
  • both the sacrificial metal and the gate electrode may be composed of Mo, and the first metal and the source and the drain may both be composed of Ti/Al/Ti.
  • the active layer 520 can also be included in the thin film transistor in order to realize the function of the thin film transistor.
  • the first conductive layer is disposed on the substrate substrate, the second conductive layer is disposed on a side of the first metal away from the substrate substrate, and the second conductive layer is disposed in the same material as the pixel electrode,
  • the first conductive layer is disposed in the same material as the source and the drain of the thin film transistor, whereby the sacrificial metal and the first metal can be fabricated by using an existing process, thereby saving cost.
  • the substrate substrate 100 includes a display area 30 provided with a pixel electrode 600 and a thin film transistor including a source 530 and a drain 540, wherein the second conductive layer 220 is the same as the pixel electrode 600.
  • both the sacrificial metal and the pixel electrode may be composed of ITO, and the first metal and the source and the drain may each be composed of Ti/Al/Ti.
  • the first conductive layer is disposed on the substrate substrate, the second conductive layer is disposed on a side of the first metal away from the substrate substrate, and the second conductive layer is disposed in the same material as the touch electrode.
  • the first conductive layer is disposed in the same material as the source and the drain of the thin film transistor, whereby the second conductive layer and the first conductive layer can be fabricated by using an existing process, thereby saving cost.
  • the substrate substrate 100 includes a display area 30.
  • the display area 30 is provided with a touch electrode 800 and a thin film transistor.
  • the thin film transistor includes a source 530 and a drain 540.
  • the second conductive layer 220 and the touch electrode are included.
  • the second conductive layer and the touch electrode may be made of ITO, and the first conductive layer and the source and the drain may be made of Ti/Al/Ti.
  • the touch electrodes can have multiple locations in the display substrate.
  • the second conductive layer according to the embodiment of the present disclosure may be disposed in the same material as the touch electrodes in the display substrate, thereby simplifying the production process. It can be understood by those skilled in the art that when the touch electrode is disposed in the display substrate, the planarization layer 40 may be disposed on a side of the touch electrode 800 adjacent to the gate insulating layer 400.
  • the insulating layer when the second conductive layer is disposed in the same material as the pixel electrode, or when the second conductive layer is disposed in the same material as the touch electrode, the insulating layer is disposed in the bonding region of the substrate substrate 100.
  • the layer 700, the insulating layer 700 is disposed on a side of the gate insulating layer 400 away from the buffer layer 300, thereby preventing interference of external traces.
  • the insulating layer 700 may be prepared in synchronization with a structure such as a passivation layer, a planarization layer, an interlayer insulating layer, or the like.
  • the present disclosure proposes a display device.
  • the display device includes the display substrate described above, whereby the display device has all of the features and advantages of the display substrate described above, and details are not described herein.
  • the display device has a high display quality.
  • the display device may further include a flexible printed wiring board 900 having a metal terminal 910, and the metal terminal 910 and the connection terminal 200 are connected in one-to-one correspondence through the conductive film 20.
  • a flexible printed wiring board 900 having a metal terminal 910, and the metal terminal 910 and the connection terminal 200 are connected in one-to-one correspondence through the conductive film 20.
  • a display substrate 1000 according to an embodiment of the present disclosure is first provided, and then a conductive film 20 is attached to a surface of a connection terminal on the display substrate 1000 by a press (as in (a) of FIG. 10).
  • the metal terminals on the flexible printed circuit board 900 are then accurately aligned with the connection terminals on the display substrate 1000, for example, using an industrial camera positioning (CCD) method, the industrial camera is equivalent to a magnifying glass, and the connection terminals are enlarged to complete the pre-bonding. ((b) in Figure 10).
  • CCD industrial camera positioning
  • the conductive film 20 is cured, and the conductive balls in the conductive film 20 are broken, and the connection terminals are turned on to complete the main bonding (Fig. 10 (c)). Finally, the impedance between the flexible printed wiring board 900 and the display substrate 1000 is tested to detect the conduction state between the two, and the realization of the use function of the final display device is ensured ((d) in FIG. 10).
  • the conductive film 20 may be an anisotropic conductive film, whereby the flexible printed wiring board and the display substrate may be connected by utilizing the adhesiveness of the anisotropic conductive film and the anisotropic conduction property. together.
  • the present disclosure provides a method of making a display substrate.
  • the display substrate fabricated by the method may be the display substrate described above, whereby the display substrate fabricated by the method may have the same features and advantages as the display substrate described above, and is no longer Narration.
  • the method includes:
  • a substrate substrate in this step, includes a bonding region to provide a connection terminal in the bonding region in a subsequent process.
  • a connection terminal is provided in a bonding region on the substrate substrate.
  • the connection terminal includes the first metal and the sacrificial metal which are stacked and in contact with each other.
  • the first metal 210 is an example of a first conductive layer; the sacrificial metal 220 is an example of a second conductive layer. The positional relationship between the first metal and the sacrificial metal has been described in detail above and will not be described herein.
  • a sacrificial metal is disposed on a substrate substrate, and a first metal is disposed on a side of the sacrificial metal away from the substrate substrate, whereby in the case where the first metal is scratched or blown, The signal can still be transmitted through the sacrificial metal at the breakpoint.
  • a first metal is disposed on a substrate substrate, and a sacrificial metal is disposed on a side of the first metal away from the substrate substrate, whereby the first metal may be protected by the sacrificial metal to avoid the first metal Scratched or blown.
  • the sacrificial metal and the first metal are fabricated using an existing process, whereby a new process is not introduced, and production cost is saved.
  • the display substrate includes a display region provided with a thin film transistor on which the sacrificial metal and the gate of the thin film transistor are synchronously disposed using the same patterning process; the sacrificial metal is away from the substrate substrate On one side, the first metal and the source and drain of the thin film transistor are synchronously arranged by the same patterning process.
  • the sacrificial metal and the gate can be formed synchronously by the process of fabricating the gate, and the first metal and the source and drain can be formed synchronously by the process of fabricating the source and the drain.
  • the sacrificial metal and the first metal can be fabricated by using an existing process, which simplifies the production process and saves costs.
  • the substrate substrate includes a display region on which the pixel electrode and the thin film transistor are disposed.
  • the first conductive layer and the source and drain of the thin film transistor are synchronously disposed by using the same patterning process; and the second conductive layer and the pixel electrode are synchronously disposed on the side of the first conductive layer away from the substrate substrate by using the same patterning process .
  • the first conductive layer and the source and drain electrodes can be formed synchronously by the process of fabricating the source and the drain, and the second conductive layer and the pixel electrode can be formed simultaneously by the process of fabricating the pixel electrode.
  • the second conductive layer and the first conductive layer can be fabricated by using an existing process, which simplifies the production process and saves costs.
  • the substrate substrate includes a display area on which the touch electrode and the thin film transistor are disposed, and the first conductive layer and the source and drain of the thin film transistor are synchronously disposed on the substrate substrate by using the same patterning process;
  • the second conductive layer and the touch electrode are synchronously disposed by the same patterning process. Therefore, the first conductive layer and the source and drain electrodes can be formed synchronously by the process of fabricating the source and the drain, and the second conductive layer and the touch electrode are simultaneously formed by the process of fabricating the touch electrode.
  • the second conductive layer and the first conductive layer can be fabricated by the existing process, the production process can be simplified, the cost can be saved, and the problem of poor conductivity of the display substrate having the touch function can be improved.
  • the two-layer conductive layer is used to form the connection terminal, and the sacrificial metal and the first metal in the connection terminal are fabricated by using the existing process, which can not introduce a new process, simplify the process, save production cost, and obtain a display for ensuring signal conduction.
  • the substrate further improves the yield of the display substrate and the display quality of the display device to which the display substrate is applied.
  • the bonding region 10 of the substrate substrate 100 and the display region 30 do not overlap each other in a direction perpendicular to the substrate substrate 100.
  • the second conductive layer may also include a plurality of sub-conductive layers in other embodiments.
  • the second conductive layer includes, in addition to the first sub-conductive layer of the same material as the pixel electrode, which may further include, for example, a second sub-conductive layer of the same material as the touch electrode.
  • the first sub-conductive layer is in direct contact with the second sub-conductive layer and overlaps each other in a direction perpendicular to the substrate substrate.
  • the description of the terms “one embodiment”, “another embodiment” or the like means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the present disclosure. .
  • the schematic representation of the above terms is not necessarily directed to the same embodiment or example.
  • the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.
  • various embodiments or examples described in the specification, as well as features of various embodiments or examples may be combined and combined.
  • the terms “first” and “second” are used for descriptive purposes only, and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.

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Abstract

提供了显示基板及其制作方法、显示装置。该显示基板包括：基板衬底（100），所述基板衬底（100）包括邦定区域（10）；以及连接端子（200），位于所述基板衬底（100）的所述邦定区域（10），包括：互相接触的第一导电层（210）以及第二导电层（220），其中，在垂直于基板衬底（100）的方向上，所述第一导电层（210）和所述第二导电层（220）彼此重叠。这样，可以提高显示品质。

Description

显示基板及其制作方法、显示装置
本申请要求于2018年4月10日递交的中国专利申请第201810315199.5号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示基板及其制作方法、显示装置。
背景技术
显示器中的显示基板具有邦定区域，利用各向异性导电胶按照一定的工作流程，将面板与柔性印刷线路板(FPC)组合到一起并导通，连接至控制IC等结构。由此，可以实现显示器中信号的输入与控制。
然而，目前的显示基板及制作方法、显示装置仍有待改进。
发明内容
本公开的实施例提供一种显示基板，包括：
基板衬底，所述基板衬底包括邦定区域；以及
连接端子，位于所述基板衬底的所述邦定区域，包括：互相接触的第一导电层以及第二导电层，其中，在垂直于基板衬底的方向上，所述第一导电层和所述第二导电层彼此重叠。
在一个示例中，所述第一导电层在所述基板衬底上的正投影和所述第二导电层在所述基板衬底上的正投影在形状和尺寸至少之一上不同。
在一个示例中，所述第一导电层位于所述第二导电层远离所述基板衬底的一侧，所述第一导电层在所述基板衬底上的正投影小于所述第二导电层在所述基板衬底上的正投影，且所述第一导电层在所述基板衬底上的所述正投影完全位于所述第二导电层在所述基板衬底上的所述正投影之内。
在一个示例中，所述基板衬底还包括与所述邦定区域不重叠的显示区域，薄膜晶体管和像素电极位于所述显示区域，所述薄膜晶体管包括栅极以及源 漏极。
在一个示例中，所述第一导电层与所述薄膜晶体管电性连接，所述第二导电层仅与所述第一导电层电性连接。
在一个示例中，所述第二导电层与所述栅极同层同材料，所述第一导电层与所述源漏极同层同材料。
在一个示例中，所述第二导电层与所述像素电极同层同材料设置，所述第一导电层与所述源漏极同层同材料设置。
在一个示例中，所述第二导电层与所述触控电极同层同材料设置，所述第一导电层与所述源漏极同层同材料设置。
在一个示例中，所述第一导电层和所述第二导电层的至少之一包括多个子导电层。
在一个示例中，所述第一导电层包括Ti/Al/Ti叠层，所述第二导电层包括钼以及氧化铟锡的至少之一。
在一个示例中，所述连接端子构造为与线路板电性连接。
本公开另一实施例提供一种显示装置，包括：
上述任一项的显示基板；
线路板，具有金属端子；以及
导电膜，连接所述金属端子与所述连接端子。
本公开又一实施例提供一种上述显示基板的制作方法，包括：
提供所述基板衬底；以及
在所述基板衬底的所述邦定区域设置所述连接端子。
在一个示例中，所述基板衬底与所述邦定区域不重叠的显示区域，薄膜晶体管和像素电极位于所述显示区域，所述薄膜晶体管包括栅极以及源漏极。
在一个示例中，在所述基板衬底的所述邦定区域设置所述连接端子包括：
在所述基板衬底上，利用第一构图工艺同步设置所述第二导电层以及所述薄膜晶体管的所述栅极；
在所述第二导电层的远离所述基板衬底的一侧，利用第二构图工艺同步设置所述第一导电层以及所述薄膜晶体管的所述源漏极。
在一个示例中，在所述基板衬底的所述邦定区域设置所述连接端子包括：
在所述基板衬底上，利用第一构图工艺同步设置所述第一导电层以及所 述薄膜晶体管的所述源漏极，
在所述第一导电层的远离所述基板衬底的一侧，利用第二构图工艺同步设置所述第二导电层以及所述像素电极。
在一个示例中，所述显示基板还包括位于基板衬底上的触控电极，
其中，在所述基板衬底的所述邦定区域设置所述连接端子包括：
在所述基板衬底上，利用第一构图工艺同步设置所述第一导电层以及所述薄膜晶体管的源漏极，
在所述第一导电层的远离所述基板衬底的一侧，利用第二构图工艺同步设置所述第二导电层以及所述触控电极。
这样，可以提高显示品质，简化生产工艺，节省成本。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
本公开的上述和/或附加的方面和优点从结合下面附图对实施例的描述中将变得明显和容易理解，其中：
图1显示了根据本公开一个实施例的显示基板的结构示意图；
图2显示了相关技术中显示基板邦定区域连接端子划伤的电镜照片；
图3显示了相关技术中显示基板邦定区域连接端子烧断的电镜照片；
图4显示了根据本公开一个实施例的显示基板的结构示意图；
图5显示了根据本公开另一个实施例的显示基板的结构示意图；
图6显示了根据本公开另一个实施例的显示基板的结构示意图；
图7显示了根据本公开另一个实施例的显示基板的结构示意图；
图8显示了根据本公开另一个实施例的显示基板的结构示意图；
图9显示了根据本公开一个实施例的显示装置的结构示意图；
图10显示了根据本公开一个实施例的显示装置的邦定过程；以及
图11显示了根据本公开一个实施例的制作显示基板的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本公开，而不能理解为对本公开的限制。
具有柔性印刷线路板的显示装置，容易由于显示基板(如阵列基板或OLED的背板)上，与柔性印刷线路板相连的连接端子发生损伤，影响显示器件的性能。例如，在切割显示基板邦定区域连接端子上方的玻璃基板时，容易将下方的连接端子划伤；或者，在检测环节，检测设备中的探针容易对裸露的连接端子造成划伤或烧断；再或者，在模组工艺中或在显示基板的搬运过程中，也容易造成连接端子的划伤。而连接端子的划伤或烧断，会导致与连接端子连接的控制单元中的信号无法通过连接端子输入到显示器中，从而造成显示屏幕显示异常，出现显示品质较差的问题。
本公开的实施例提供的显示基板及其制作方法以及显示装置能够至少一定程度上缓解或解决上述提及问题中至少一个。
在本公开的一个方面，本公开提出了一种显示基板。根据本公开的实施例，参考图1，该显示基板包括：基板衬底100以及连接端子200。其中，基板衬底100包括邦定区域10，连接端子200设置在基板衬底100的邦定区域10上。连接端子200包括层叠设置且互相接触的第一金属210以及牺牲金属220。这里，第一金属210是第一导电层的示例；牺牲金属220是第二导电层的示例。显示基板邦定区域的连接端子具有双层金属，由此，在上层金属被划伤或烧断的情况下，可以利用下层金属进行导通，从而可以避免上层金属划伤或烧断导致的信号无法导通的问题，从而可以提高显示基板的生产良率，提高应用该显示基板的显示装置的显示品质。
为了便于理解，下面首先对相关技术中的显示基板进行简单说明：
相关技术中显示基板邦定区域的连接端子由一层金属构成，连接端子在 切割、检测环节、模组工艺中或在显示基板的搬运过程中，容易划伤或烧断。而连接端子的划伤或烧断，会导致与连接端子连接的控制单元中的信号无法通过连接端子输入到显示器中，从而造成显示屏幕显示异常，出现显示品质较差的问题。连接端子被划伤的情况参考图2，左图为正面照片，连接端子200表面有许多划痕，右图为背面照片，连接端子200背面的划痕不明显。虽然连接端子未被划断，但是划痕会影响后续过程中连接端子与柔性印刷线路板的连接，造成接触不良等问题。连接端子被烧断的情况参考图3，左图为正面照片，连接端子200表面存在烧灼区域，右图为背面照片，连接端子200背面与正面对应处也存在烧灼区域，连接端子200被烧断，导致信号无法导通。而目前用于缓解上述问题的方法主要是在作业手法方面的改进，例如，改进切割方法，但作业手法方面的改进并不能从根本上解决上述问题。
根据本公开的实施例，对显示基板邦定区域连接端子的结构进行改进：连接端子包括双金属层，在上层金属被划伤或烧断的情况下，可以利用下层金属进行导通，从而可以避免上层金属划伤或烧断导致的信号无法导通的问题，从而可以提高显示基板的生产良率，提高应用该显示基板的显示装置的显示品质。
下面对根据本公开的具体实施例的该显示基板的各个结构进行详细说明：
根据本公开的实施例，连接端子200包括第一金属210以及牺牲金属220。关于第一金属与牺牲金属的位置关系不受特别限制，只要满足第一金属与牺牲金属层叠设置且互相接触即可。例如，根据本公开的具体实施例，参考图4，牺牲金属220设置在基板衬底100上，第一金属210设置在牺牲金属220远离基板衬底100的一侧。由此，在第一金属被划伤或烧断的情况下，信号在断点处仍可以通过牺牲金属进行传输。根据本公开的另一些实施例，参考图5，第一金属210设置在基板衬底100上，牺牲金属220设置在第一金属210远离基板衬底100的一侧。由此，可以利用牺牲金属保护第一金属，避免第一金属的划伤或烧断，保证信号的导通。根据本公开的实施例，第一金属210与薄膜晶体管相连，牺牲金属220为孤岛结构。例如，牺牲金属220仅与第一金属210电性连接，而不与其他任何导电构件电性连接。也即是说，无论第一金属设置在牺牲金属上方还是第一金属设置在牺牲金属下方，显示 基板均是通过第一金属将输入的信号传入薄膜晶体管中，牺牲金属只是作为第一金属划伤或烧断时的一个过渡结构，或者牺牲金属只是作为第一金属的一个保护层以避免第一金属划伤或烧断对电信号传送的不利影响。
在一个示例中，牺牲金属220在基板衬底100上的正投影与牺牲金属220在基板衬底100上的正投影在形状和尺寸至少之一上不同。
根据本公开的实施例，当牺牲金属220设置在基板衬底100上，第一金属210设置在牺牲金属220远离基板衬底100的一侧时，第一金属210在基板衬底100上的正投影小于牺牲金属220在基板衬底100上的正投影。进一步的，第一金属210在基板衬底100上的正投影完全位于牺牲金属220在基板衬底100上的正投影之内。也就是，第一金属210在基板衬底100上的正投影不超出牺牲金属220在基板衬底100上的正投影的边缘。由此，第一金属任意处被划伤或烧断，都能保证信号在断点处仍可以通过牺牲金属进行传输。或者，当第一金属210设置在基板衬底100上，牺牲金属220设置在第一金属210远离基板衬底100的一侧时，牺牲金属220在基板衬底100上的正投影完全小于第一金属210在基板衬底100上的正投影。牺牲金属220在基板衬底100上的正投影完全位于第一金属210在基板衬底100上的正投影之内。也就数，牺牲金属220在基板衬底100上的正投影不超出第一金属210在基板衬底100上的正投影的边缘。由此，牺牲金属任意处被划伤或烧断，都能保证信号可以通过第一金属进行传输。
关于第一金属以及牺牲金属的具体材料不受特别限制，只要具有良好的导电性即可。例如，根据本公开的实施例，牺牲金属可以包括钼(Mo)以及氧化铟锡(ITO)的至少之一，第一金属可以包括三个子导电层，例如，第一金属包括钛/铝/钛(Ti/Al/Ti)。由此，可以利用已知材料来构成牺牲金属以及第一金属，节省成本。
需要说明的是，钛/铝/钛为钛、铝、钛三层金属的堆叠，其中，铝金属涂覆在第一层钛金属上，第二层钛金属涂覆在铝金属远离第一层钛金属的一侧。
根据本公开的实施例，当牺牲金属220设置在基板衬底100上，第一金属210设置在牺牲金属220远离基板衬底100的一侧时，第一金属210中的第一层钛金属设置在牺牲金属220远离基板衬底100的一侧，第一金属210 中的铝金属设置在第一层钛金属远离牺牲金属220的一侧，第一金属210中的第二层钛金属设置在铝金属远离第一层钛金属的一侧。根据本公开的实施例，当第一金属210设置在基板衬底100上，牺牲金属220设置在第一金属210远离基板衬底100的一侧时，第一金属210中的第一层钛金属设置在基板衬底100上，第一金属210中的铝金属设置在第一层钛金属远离基板衬底100的一侧，第一金属210中的第二层钛金属设置在铝金属远离第一层钛金属的一侧，牺牲金属220设置在第二层钛金属远离铝金属的一侧。
根据本公开的实施例，参考图4以及图5，显示基板还可以包括缓冲层300以及栅绝缘层400，其中，缓冲层300设置在牺牲金属220与基板衬底100之间(如图4所示)，或者缓冲层300设置在第一金属210与基板衬底100之间(如图5所示)，栅绝缘层400设置在缓冲层300远离基板衬底100的一侧。设置缓冲层可以增加基板衬底与金属层的结合力，提高显示基板的性能，设置栅绝缘层可以实现显示基板的使用功能。
根据本公开的实施例，为了节省成本，利用现有制作工艺在显示基板上制作连接端子，由此，不引入新的工艺，节省设备、节省成本。根据本公开的实施例，牺牲金属设置在基板衬底上，第一金属设置在牺牲金属远离基板衬底的一侧，将牺牲金属与薄膜晶体管中的栅极同层同材料设置，将第一金属与薄膜晶体管中的源漏极同层同材料设置，由此，可以利用现有的工艺制作牺牲金属以及第一金属，节省成本。例如，参考图6，基板衬底100包括显示区域30，显示区域30设置有薄膜晶体管，薄膜晶体管包括栅极510、源极530以及漏极540，其中，牺牲金属220与栅极510同层同材料设置，第一金属210与源漏极同层同材料设置。本领域技术人员能够理解的是，薄膜晶体管的源漏极包括源极530、漏极540。根据本公开的实施例，第一金属210与源极530、漏极540中的任一个同层同材料设置即可。根据本公开的具体实施例，牺牲金属与栅极均可以是由Mo构成的，第一金属与源极、漏极均可以是由Ti/Al/Ti构成的。本领域技术人员能够理解的是，薄膜晶体管中还可以包括有源层520，以便实现薄膜晶体管的功能。
根据本公开的实施例，第一导电层设置在基板衬底上，第二导电层设置在第一金属远离基板衬底的一侧，将第二导电层与像素电极同层同材料设置，将第一导电层与薄膜晶体管中的源极、漏极同层同材料设置，由此，可以利 用现有的工艺制作牺牲金属以及第一金属，节省成本。例如，参考图7，基板衬底100包括显示区域30，显示区域30设置有像素电极600以及薄膜晶体管，薄膜晶体管包括源极530以及漏极540，其中，第二导电层220与像素电极600同层同材料设置，第一导电层210与源极530、漏极540同层同材料设置。根据本公开的具体实施例，牺牲金属与像素电极均可以是由ITO构成的，第一金属与源极、漏极均可以是由Ti/Al/Ti构成的。
根据本公开的实施例，第一导电层设置在基板衬底上，第二导电层设置在第一金属远离基板衬底的一侧，将第二导电层与触控电极同层同材料设置，将第一导电层与薄膜晶体管中的源极、漏极同层同材料设置，由此，可以利用现有的工艺制作第二导电层以及第一导电层，节省成本。例如，参考图8，基板衬底100包括显示区域30，显示区域30设置有触控电极800以及薄膜晶体管，薄膜晶体管包括源极530以及漏极540，其中，第二导电层220与触控电极800同层同材料设置，第一导电层210与源极530、漏极540同层同材料设置。根据本公开的具体实施例，第二导电层与触控电极均可以是由ITO构成的，第一导电层与源极、漏极均可以是由Ti/Al/Ti构成的。本领域技术人员能够理解的是，触控电极在显示基板中可以有多个位置。针对触控电极设置在显示基板内的情况，根据本公开实施例的第二导电层可以与显示基板中的触控电极同层同材料设置，由此，简化生产工艺。本领域技术人员能够理解的是，触控电极设置在显示基板中时，还可以在触控电极800靠近栅绝缘层400的一侧设置平坦化层40。
根据本公开的实施例，当第二导电层与像素电极同层同材料设置时，或者第二导电层与触控电极同层同材料设置时，在基板衬底100的邦定区域设置有绝缘层700，绝缘层700设置在栅绝缘层400远离缓冲层300的一侧，由此，可以防止外界走线的干扰。绝缘层700可以和钝化层、平坦化层、层间绝缘层等结构同步制备。
在本公开的另一方面，本公开提出了一种显示装置。根据本公开的实施例，该显示装置包括前面描述的显示基板，由此，该显示装置具有前面描述的显示基板的全部特征以及优点，在此不再赘述。总的来说，该显示装置具有较高的显示品质。
根据本公开的实施例，参考图9，该显示装置还可以包括柔性印刷线路 板900，柔性印刷线路板900具有金属端子910，金属端子910与连接端子200通过导电膜20一一对应连接。由此，可以实现信号的传输，实现显示装置的显示功能。
下面对柔性印刷线路板与显示基板的邦定过程进行简单说明：
参考图10，首先提供根据本公开实施例的显示基板1000，随后利用压具将导电膜20贴附到显示基板1000上的连接端子的表面(如图10中的(a))。随后将柔性印刷线路板900上的金属端子与显示基板1000上的连接端子进行精确对位，例如使用工业相机定位(CCD)的方法，工业相机相当于放大镜，将连接端子放大，完成预邦定(如图10中的(b))。随后在高温高压下，将导电膜20进行固化，导电膜20中的导电球破裂，使连接端子导通，完成主绑定(如图10中的(c))。最后测试柔性印刷线路板900与显示基板1000之间的阻抗，以检测二者之间的导通状态，保证最终显示装置的使用功能的实现(如图10中的(d))。根据本公开的实施例，导电膜20可以为各向异性导电膜，由此，可以利用各向异性导电膜的粘着性以及各向异性导通的特性，将柔性印刷线路板与显示基板连接在一起。
在本公开的另一方面，本公开提出了一种制作显示基板的方法。根据本公开的实施例，由该方法制作的显示基板可以为前面描述的显示基板，由此，由该方法制作的显示基板可以具有与前面描述的显示基板相同的特征以及优点，在此不再赘述。
根据本公开的实施例，参考图11，该方法包括：
S100：提供基板衬底；
根据本公开的实施例，在该步骤中，提供基板衬底。根据本公开的实施例，基板衬底包括邦定区域，以便后续过程中在邦定区域设置连接端子。
S200：在基板衬底上的邦定区域设置连接端子；
根据本公开的实施例，在该步骤中，在基板衬底上的邦定区域设置连接端子。根据本公开的实施例，连接端子包括层叠设置且互相接触的第一金属以及牺牲金属。这里，第一金属210是第一导电层的示例；牺牲金属220是第二导电层的示例。关于第一金属与牺牲金属的位置关系，前面已经进行了详细描述，在此不再赘述。例如，根据本公开的实施例，在基板衬底上设置牺牲金属，在牺牲金属远离基板衬底的一侧设置第一金属，由此，在第一金 属被划伤或烧断的情况下，信号在断点处仍可以通过牺牲金属进行传输。或者，根据本公开的实施例，在基板衬底上设置第一金属，在第一金属远离基板衬底的一侧设置牺牲金属，由此，可以利用牺牲金属保护第一金属，避免第一金属划伤或烧断。关于上述两种情况下的第一金属与牺牲金属的尺寸关系，前面也已经进行了详细描述，在此不再赘述。
根据本公开的实施例，为了简化生产工艺，利用现有工艺制作牺牲金属以及第一金属，由此，不会引入新的工艺，节省生产成本。例如，根据本公开的实施例，显示基板包括显示区域，显示区域设置有薄膜晶体管，在基板衬底上，利用同一构图工艺同步设置牺牲金属以及薄膜晶体管的栅极；在牺牲金属远离基板衬底的一侧，利用同一构图工艺同步设置第一金属以及薄膜晶体管的源漏极。由此，可以利用制作栅极的工艺同步形成牺牲金属以及栅极，利用制作源漏极的工艺同步形成第一金属以及源漏极。由此，可以利用现有工艺制作牺牲金属以及第一金属，简化生产工艺，节省成本。
根据本公开的实施例，基板衬底包括显示区域，显示区域上设置有像素电极以及薄膜晶体管。在基板衬底上，利用同一构图工艺同步设置第一导电层以及薄膜晶体管的源漏极；在第一导电层远离基板衬底的一侧，利用同一构图工艺同步设置第二导电层以及像素电极。由此，可以利用制作源漏极的工艺同步形成第一导电层以及源漏极，利用制作像素电极的工艺同步形成第二导电层以及像素电极。由此，可以利用现有工艺制作第二导电层以及第一导电层，简化生产工艺，节省成本。
根据本公开的实施例，基板衬底包括显示区域，显示区域上设置有触控电极以及薄膜晶体管，在基板衬底上，利用同一构图工艺同步设置第一导电层以及薄膜晶体管的源漏极；在第一导电层远离基板衬底的一侧，利用同一构图工艺同步设置第二导电层以及触控电极。由此，可以利用制作源漏极的工艺同步形成第一导电层以及源漏极，利用制作触控电极的工艺同步形成第二导电层以及触控电极。由此，可以利用现有工艺制作第二导电层以及第一导电层，简化生产工艺，节省成本，且能够改善具有触摸功能的显示基板导电不良的问题。
综上，采用双层导电层构成连接端子，并利用现有工艺制作连接端子中的牺牲金属以及第一金属，可以不引入新的工艺，简化工艺，节省生产成本， 获得保证信号导通的显示基板，进而提高显示基板的良率以及应用该显示基板的显示装置的显示品质。
在本公开的上述实施例中，基板衬底100的邦定区域10与显示区域30在垂直于基板衬底100的方向上是彼此不重叠的。
尽管在上述实施例中仅描述了第一导电层210可包括三个子导电层，在另外的实施例中第二导电层也可以包括多个子导电层。例如，在一个示例中，第二导电层除了包括与像素电极同层同材料的第一子导电层，其例如还可包括与触控电极同层同材料的第二子导电层。该第一子导电层与该第二子导电层直接接触且在垂直于基板衬底的方向上彼此重叠。
在本公开的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开而不是要求本公开必须以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本说明书的描述中，参考术语“一个实施例”、“另一个实施例”等的描述意指结合该实施例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。另外，需要说明的是，本说明书中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (17)

  1. 一种显示基板，包括：
    基板衬底，所述基板衬底包括邦定区域；以及
    连接端子，位于所述基板衬底的所述邦定区域，包括：互相接触的第一导电层以及第二导电层，其中，在垂直于基板衬底的方向上，所述第一导电层和所述第二导电层彼此重叠。
  2. 根据权利要求1所述的显示基板，其中，所述第一导电层在所述基板衬底上的正投影和所述第二导电层在所述基板衬底上的正投影在形状和尺寸至少之一上不同。
  3. 根据权利要求1所述的显示基板，其中，所述第一导电层位于所述第二导电层远离所述基板衬底的一侧，所述第一导电层在所述基板衬底上的正投影小于所述第二导电层在所述基板衬底上的正投影，且所述第一导电层在所述基板衬底上的所述正投影完全位于所述第二导电层在所述基板衬底上的所述正投影之内。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述基板衬底还包括与所述邦定区域不重叠的显示区域，薄膜晶体管和像素电极位于所述显示区域，所述薄膜晶体管包括栅极以及源漏极。
  5. 根据权利要求4所述的显示基板，其中，所述第一导电层与所述薄膜晶体管电性连接，所述第二导电层仅与所述第一导电层电性连接。
  6. 根据权利要求4所述的显示基板，其中，所述第二导电层与所述栅极同层同材料，所述第一导电层与所述源漏极同层同材料。
  7. 根据权利要求4所述的显示基板，其中，所述第二导电层与所述像素电极同层同材料设置，所述第一导电层与所述源漏极同层同材料设置。
  8. 根据权利要求4所述的显示基板，其中，所述第二导电层与所述触控电极同层同材料设置，所述第一导电层与所述源漏极同层同材料设置。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述第一导电层和所述第二导电层的至少之一包括多个子导电层。
  10. 根据权利要求9所述的显示基板，其中，所述第一导电层包括Ti/Al/Ti叠层，所述第二导电层包括钼以及氧化铟锡的至少之一。
  11. 根据权利要求1至10中任一项所述的显示基板，其中，所述连接端 子构造为与线路板电性连接。
  12. 一种显示装置，包括：
    权利要求1至11中任一项所述的显示基板；
    线路板，具有金属端子；以及
    导电膜，连接所述金属端子与所述连接端子。
  13. 一种权利要求1的显示基板的制作方法，包括：
    提供所述基板衬底；以及
    在所述基板衬底的所述邦定区域设置所述连接端子。
  14. 根据权利要求13所述的方法，其中，所述基板衬底与所述邦定区域不重叠的显示区域，薄膜晶体管和像素电极位于所述显示区域，所述薄膜晶体管包括栅极以及源漏极。
  15. 根据权利要求13所述的方法，其中，在所述基板衬底的所述邦定区域设置所述连接端子包括：
    在所述基板衬底上，利用第一构图工艺同步设置所述第二导电层以及所述薄膜晶体管的所述栅极；
    在所述第二导电层的远离所述基板衬底的一侧，利用第二构图工艺同步设置所述第一导电层以及所述薄膜晶体管的所述源漏极。
  16. 根据权利要求13所述的方法，其中，在所述基板衬底的所述邦定区域设置所述连接端子包括：
    在所述基板衬底上，利用第一构图工艺同步设置所述第一导电层以及所述薄膜晶体管的所述源漏极，
    在所述第一导电层的远离所述基板衬底的一侧，利用第二构图工艺同步设置所述第二导电层以及所述像素电极。
  17. 根据权利要求13所述的方法，其中，所述显示基板还包括位于基板衬底上的触控电极，
    其中，在所述基板衬底的所述邦定区域设置所述连接端子包括：
    在所述基板衬底上，利用第一构图工艺同步设置所述第一导电层以及所述薄膜晶体管的源漏极，
    在所述第一导电层的远离所述基板衬底的一侧，利用第二构图工艺同步设置所述第二导电层以及所述触控电极。
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