WO2021051495A1 - 阵列基板、制备方法及显示面板 - Google Patents

阵列基板、制备方法及显示面板 Download PDF

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Publication number
WO2021051495A1
WO2021051495A1 PCT/CN2019/115879 CN2019115879W WO2021051495A1 WO 2021051495 A1 WO2021051495 A1 WO 2021051495A1 CN 2019115879 W CN2019115879 W CN 2019115879W WO 2021051495 A1 WO2021051495 A1 WO 2021051495A1
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Prior art keywords
layer
pixel electrode
display area
substrate
thin film
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PCT/CN2019/115879
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English (en)
French (fr)
Inventor
聂晓辉
Original Assignee
武汉华星光电技术有限公司
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Priority to US16/632,393 priority Critical patent/US20210091121A1/en
Publication of WO2021051495A1 publication Critical patent/WO2021051495A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate, a preparation method and a display panel.
  • the contact impedance between the drain terminal electrode and the pixel electrode in the display panel determines the power consumption of the driving circuit and the pixel charging and discharging response speed. Therefore, after the pixel design of the display panel is completed, it is necessary to connect the drain terminal electrode and the pixel electrode. The contact resistance between them is measured. Because there are many layers in the display area of the panel, directly measuring the contact resistance between the drain terminal electrode and the pixel electrode will destroy other layers in the display area. Therefore, it is generally done by setting a detection device in the non-display area of the panel.
  • the detection device includes a thin film. A transistor and a pixel electrode, and the pixel electrode is connected to the pixel electrode of the display area through a wire to detect the contact impedance between the drain terminal electrode and the pixel electrode.
  • the embodiments of the present invention provide an array substrate, a preparation method, and a display panel, which aim to improve the structure of the array substrate and reduce the height difference between the detection device and the interlayer dielectric layer on the array substrate, so that the leads are between the detection device and the layer.
  • the junction of the dielectric layer is not prone to disconnection, which improves the reliability of the detection device.
  • the embodiments of the present invention provide an array substrate, a preparation method, and a display panel, which aim to improve the structure of the array substrate and reduce the height difference between the detection device and the interlayer dielectric layer on the array substrate, so that the leads are between the detection device and the layer.
  • the junction of the dielectric layer is not prone to disconnection, which improves the reliability of the detection device.
  • the present application provides an array substrate, the array substrate includes a substrate, the substrate includes a display area and a non-display area, a thin film transistor layer and a first pixel electrode layer are sequentially provided on the substrate, and the thin film
  • the transistor layer includes a thin film transistor located in the display area and an interlayer dielectric layer located in the non-display area, the first pixel electrode layer is connected to the thin film transistor layer, and the interlayer dielectric layer is located in
  • the non-display area of the substrate is provided with a first via hole; the non-display area of the substrate is provided with a detection device, and the detection device includes:
  • the second pixel electrode layer is deposited on the source and drain layer, and the second pixel electrode layer is connected to the first pixel electrode layer through a wire.
  • the array substrate further includes a planarization layer, the planarization layer is located between the thin film transistor layer and the first pixel electrode layer, and the planarization layer is formed in a non-display area of the substrate There is a second via to form a test area, and the first via is located in the test area.
  • the lead is deposited on the planarization layer and the interlayer dielectric layer.
  • the area of the first via hole is greater than or equal to the area of the first gate metal layer.
  • the area of the first via hole is greater than the area of the first gate metal layer, and the first source and drain layer is completely deposited inside the first via hole.
  • the height of the upper surface of the first gate metal layer is smaller than the height of the interlayer dielectric layer.
  • the height of the upper surface of the first source and drain layer is the same as the height of the upper surface of the interlayer dielectric layer.
  • the present application provides a method for manufacturing an array substrate, the array substrate including a display area and a non-display area, and the method includes:
  • the substrate including a display area and a non-display area
  • the thin film transistor including a thin film transistor located in the display area and an interlayer dielectric layer located in the non-display area,
  • the interlayer dielectric layer is provided with a first via hole in the non-display area of the substrate; the first gate metal layer and the first source/drain layer are located in the non-display area, and the first The gate layer corresponds to the position of the first via hole, and the first source and drain layer is located in the first via hole and is in contact with the gate layer;
  • a first pixel electrode layer, a second pixel electrode layer, and leads are formed on the thin film transistor layer, the first pixel electrode layer is connected to the thin film transistor, and the second pixel electrode layer is located in the first source and drain. On the electrode layer and connected to the first pixel electrode layer through a wire.
  • the method before forming the first pixel electrode layer, the second pixel electrode layer and the lead on the thin film transistor layer, the method further includes:
  • a second via hole is opened at a position of the planarization layer corresponding to the non-display area to form a test area; wherein, the first via hole is located in the test area, and the first pixel electrode layer is formed in the test area.
  • the second pixel electrode layer is formed on the source and drain layers, and the leads are formed on the planarization layer and the interlayer dielectric layer.
  • the lead is made of gallium indium zinc material.
  • the forming a thin film transistor, a first gate layer and a first source and drain layer on the substrate includes:
  • the thin film transistor is formed over the second gate layer.
  • the forming a first gate layer and a second gate layer on the substrate includes:
  • a wet etching process is performed to reduce the size of the patterned mask layer, and a part of the gate material layer is removed using the patterned mask layer as a mask to form a first gate metal layer and a second gate metal layer respectively.
  • the height of the upper surface of the first gate metal layer is smaller than the height of the interlayer dielectric layer.
  • the height of the upper surface of the first source and drain layer is the same as the height of the upper surface of the interlayer dielectric layer.
  • the present application also provides a display panel, the display panel includes an array substrate, the array substrate includes a substrate, the substrate includes a display area and a non-display area, the substrate is sequentially provided with a thin film transistor layer and A first pixel electrode layer, the thin film transistor layer includes a thin film transistor located in the display area and an interlayer dielectric layer located in the non-display area, the first pixel electrode layer is connected to the thin film transistor layer ,
  • the interlayer dielectric layer is provided with a first via hole in the non-display area of the substrate; the non-display area of the substrate is provided with a detection device, and the detection device includes:
  • the second pixel electrode layer is deposited on the source and drain layer, and the second pixel electrode layer is connected to the first pixel electrode layer through a wire.
  • the array substrate further includes a planarization layer, the planarization layer is located between the thin film transistor layer and the first pixel electrode layer, and the planarization layer is formed in a non-display area of the substrate There is a second via to form a test area, and the first via is located in the test area.
  • the lead is deposited on the planarization layer and the interlayer dielectric layer.
  • the area of the first via hole is greater than or equal to the area of the first gate metal layer.
  • the height of the upper surface of the first gate metal layer is smaller than the height of the interlayer dielectric layer.
  • the height of the upper surface of the first source and drain layer is the same as the height of the upper surface of the interlayer dielectric layer.
  • a via is provided in the interlayer dielectric layer of the array substrate, and the source and drain layers are completely deposited in the first via to reduce the gap between the source and drain layers and the array substrate.
  • the height difference between the dielectric layers makes the lead layer less likely to be disconnected at the junction of the source drain layer and the interlayer dielectric layer, thereby improving the reliability of the detection device.
  • FIG. 1 is a structural cross-sectional view of an embodiment of an array substrate provided by the present invention
  • FIG. 2 is a top view of the structure of an embodiment of the array substrate provided by the present invention.
  • FIG. 3 is a schematic flowchart of an embodiment of a method for manufacturing an array substrate provided by the present invention.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined with “first” and “second” may explicitly or implicitly include one or more of the features.
  • “plurality” means two or more than two, unless otherwise specifically defined.
  • the embodiment of the present invention provides an array substrate, a manufacturing method, and a display panel. Detailed descriptions are given below.
  • FIG. 1 it is a structural cross-sectional view of an embodiment of an array substrate provided by the present invention.
  • the array substrate includes a substrate 10, the substrate includes a display area and a non-display area, and a thin film transistor layer 20 and a first pixel are sequentially arranged on the substrate.
  • the electrode layer 30, the thin film transistor layer 20 includes a thin film transistor 201 located in the display area and an interlayer dielectric layer 202 located in the non-display area.
  • the thin film transistor 201 includes a second gate layer 2011 and a second source located in the display area.
  • the drain layer 2012, the second gate layer and the second source drain layer are connected by via holes; the thin film transistor 201 also includes some other structures, such as interlayer dielectric layer, polysilicon layer and insulating layer, etc., not shown in the figure ;
  • the interlayer dielectric layer 202 is provided with a first through hole 2021 in the non-display area of the substrate.
  • a detection device is provided in the non-display area of the substrate, wherein the detection device includes:
  • the first gate metal layer 40 is deposited on the substrate 10 and corresponds to the position of the first via 2021.
  • the first source and drain layer 50 is deposited on the first gate metal layer 40, and the first source and drain layer 50 is located in the first via 2021.
  • the second pixel electrode layer 60 is deposited on the first source and drain layer 50, and the second pixel electrode layer 60 is connected to the first pixel electrode layer 30 through wires.
  • the first via 2021 is provided in the interlayer dielectric layer 202 of the array substrate, and the first source and drain layer 50 is completely deposited in the first via 2021, which reduces
  • the height difference between the first source/drain layer 50 and the interlayer dielectric layer 202 of the array substrate makes the lead wires less likely to be disconnected at the junction of the first source/drain layer 50 and the interlayer dielectric layer 50, which improves detection.
  • the reliability of the device is provided in the interlayer dielectric layer 202 of the array substrate, and the first source and drain layer 50 is completely deposited in the first via 2021, which reduces
  • the height difference between the first source/drain layer 50 and the interlayer dielectric layer 202 of the array substrate makes the lead wires less likely to be disconnected at the junction of the first source/drain layer 50 and the interlayer dielectric layer 50, which improves detection.
  • the reliability of the device is provided in the interlayer dielectric layer 202 of the array substrate, and the first source and drain layer 50 is completely deposited in the first via 20
  • the array substrate may further include a planarization layer 70, the planarization layer 70 is an organic planarization layer, the organic planarization layer 70 is prepared on the interlayer dielectric layer 202, and the organic planarization The layer 70 is disposed between the thin film transistor layer 20 and the first pixel electrode layer 30, and the organic planarization layer 70 is used to help the upper surface of the display panel to be at the same height, so as to avoid unevenness and affect the display.
  • the organic planarization layer 70 is provided with a second via 701 in the non-display area of the substrate 10 to form a test area to facilitate subsequent testing of the display panel.
  • the first via 2021 is also located in the test area.
  • Other structures of the array substrate are prepared in the second via hole.
  • the prior art can be referred to here, and there is no limitation here.
  • the second pixel electrode layer is deposited on the organic planarization layer 70, and the lead is deposited on the test area formed by the second via 701; the second pixel electrode layer 60 is also deposited on the first source at the same time.
  • the lead wire is used to connect the second pixel electrode layer in the display area and the first pixel electrode layer in the non-display area, and then connect the display panel and the test area for subsequent testing.
  • the area of the first via 2021 is larger than the area of the first gate metal layer 40. Or in other embodiments of the present invention, the area of the first via 2021 is equal to the area of the first gate metal layer 40.
  • the first source-drain layer 50 is completely deposited inside the first via 2021, and the area of the first source-drain layer 50 The area is larger than the area of the first gate metal layer 40.
  • the height of the upper surface of the first source and drain layer 50 is the same as the height of the upper surface of the interlayer dielectric layer 202. That is, the height of the upper surface of the first source and drain layer 50 and the height of the upper surface of the interlayer dielectric layer 202 are at the same horizontal height.
  • FIG. 2 it is a top view of an embodiment of the array substrate provided by the present invention.
  • the planarization layer 70 is located at the outermost periphery of the array substrate, and the interlayer dielectric layer 202 is located above the planarization layer 70. The size is smaller than the size of the planarization layer 70.
  • the first gate metal layer 40 is located inside the interlayer dielectric layer 202, while the first source and drain layer 50 is deposited on the first gate metal layer 40, the first gate metal layer 40 and the first source and drain The layer 50 may be rectangular.
  • a second pixel electrode layer 60 is deposited on the first source and drain layer 50, and a first pixel electrode layer 30 is deposited on the interlayer dielectric layer 202.
  • the first pixel electrode layer 30 and the second pixel electrode layer 60 pass Lead connection, that is, the display area and non-display area of the display panel are connected by leads.
  • the material of the gate layer may be a metal material such as molybdenum, and the material of the source and drain may be an aluminum alloy, specifically, a Ti-Al-Ti alloy.
  • the display panel of the embodiment of the present invention may also include any other necessary structures as required. Not limited.
  • the present invention also provides a method for preparing an array substrate.
  • the array substrate includes a display area and a non-display area.
  • FIG. 3 it is a schematic flow chart of an embodiment of the method for preparing an array substrate provided by the present invention.
  • the method includes step 201 Go to step 203, and the detailed description is as follows:
  • a substrate is provided, and the substrate includes a display area and a non-display area.
  • a thin film transistor layer, a first gate layer and a first source and drain layer are formed on the substrate.
  • the thin film transistor includes a thin film transistor located in the display area and an interlayer dielectric layer located in the non-display area.
  • the non-display area of the substrate is provided with a first via hole; the first gate metal layer and the first source/drain layer are located in the non-display area, the first gate layer corresponds to the position of the first via hole, and the first source/drain layer is located In the first via hole and in contact with the gate layer.
  • a first pixel electrode layer, a second pixel electrode layer and a lead are formed on the thin film transistor layer.
  • the first pixel electrode layer is connected to the thin film transistor.
  • the second pixel electrode layer is located on the first source and drain layer and is connected to the The first pixel electrode layer is connected.
  • the manufacturing method of the array substrate provided by the present invention is to provide a via hole in the interlayer dielectric layer of the array substrate, and deposit the source drain layer completely in the first via hole, thereby reducing the source drain layer and the array substrate layer.
  • the height difference between the interlayer dielectric layers makes the lead layer less likely to be disconnected at the junction of the source drain layer and the interlayer dielectric layer, thereby improving the reliability of the detection device.
  • a thin film transistor layer and a first pixel electrode layer are sequentially prepared above the substrate, and the thin film transistor layer includes thin film transistors located in the display area of the display panel and interlayers located in the non-display area of the display panel. Electric layer.
  • the first via hole is opened in the position of the interlayer dielectric layer in the non-display area of the display panel.
  • step 21 forming a thin film transistor layer, a first gate layer and a first source and drain layer on the substrate may include:
  • a first source and drain layer is formed above the first gate layer
  • the thin film transistor is formed above the second gate layer.
  • a layer of gate material is coated on the substrate in the non-display area and the area corresponding to the first via hole, and at the same time, a layer of gate material is coated on the display area of the display panel; on the gate material layer A patterned mask layer is formed on the upper layer; the wet etching process is performed to reduce the size of the patterned mask layer, and a part of the gate material layer is removed using the patterned mask layer as a mask to form the first gate metal layer and the second gate electrode layer respectively.
  • Two gate metal layers After the first gate metal layer in the non-display area and the second gate metal layer in the display area are prepared, the first source and drain layer is prepared on the first gate metal layer, and the second gate metal layer is The thin film transistor layer is prepared above the layer.
  • the specific method for preparing the structure in the display panel such as the thin film transistor can refer to the prior art, which is not limited here.
  • the height of the upper surface of the first gate metal layer after preparation is smaller than the height of the interlayer dielectric layer.
  • a first source-drain layer is deposited on the first gate metal layer, and the height of the upper surface of the first source-drain layer is equal to the height of the upper surface of the interlayer dielectric layer, that is, the upper surface of the first source-drain layer
  • the height of the surface is at the same level as the height of the upper surface of the interlayer dielectric layer, and the first source and drain layer is completely deposited inside the first via hole and arranged corresponding to the first gate metal layer.
  • the area size of the first source and drain layer may be greater than or equal to the area size of the first gate metal layer.
  • the method may further include:
  • An organic planarization layer is formed on the thin film transistor layer.
  • the organic planarization layer is provided with a second via hole in the non-display area of the substrate to form a test area.
  • the first via hole is located in the test area; the first pixel electrode layer is formed on the organic planarization layer.
  • the second pixel electrode layer is formed on the source and drain layers, and the leads are formed on the organic planarization layer and the interlayer dielectric layer.
  • an organic planarization layer is prepared and formed above the thin film transistor, and at the same time, the organic planarization layer opens a second via hole in the non-display area of the substrate to form a test area, which is convenient for subsequent testing.
  • the first pass is located in the test area.
  • a first pixel electrode layer is prepared and formed on the organic planarization layer, and a second pixel electrode layer is prepared and formed on the first source and drain electrodes at the same time.
  • the lead wire can be prepared simultaneously with the pixel electrode, or can be separately prepared after the pixel electrode is completed to connect the first pixel electrode layer and the second pixel electrode layer.
  • the lead wire can be indium gallium zinc (ITO) material.
  • the detection device may be multiple, and the detection device is connected to the array substrate for detecting defects in the array substrate.
  • the present invention also provides a display panel, which includes the aforementioned array substrate.
  • the array substrate includes a substrate 10, the substrate includes a display area and a non-display area, and a thin film transistor layer 20 and a first pixel electrode layer 30 are sequentially arranged on the substrate.
  • the thin film transistor layer 20 includes a thin film transistor 201 located in the display area and a thin film transistor 201 located in the non-display area.
  • the interlayer dielectric layer 202 in the display area.
  • the first pixel electrode layer 30 is connected to the thin film transistor layer 20, and the interlayer dielectric layer 202 is provided with a first through hole 2021 in the non-display area of the substrate.
  • a detection device is provided in the non-display area of the substrate, wherein the detection device includes:
  • the first gate metal layer 40 is deposited on the substrate 10 and corresponds to the position of the first via 2021.
  • the first source and drain layer 50 is deposited on the first gate metal layer 40, and the first source and drain layer 50 is located in the first via 2021.
  • the second pixel electrode layer 60 is deposited on the first source and drain layer 50, and the second pixel electrode layer 60 is connected to the first pixel electrode layer 30 through wires.
  • a via is provided in the interlayer dielectric layer of the array substrate, and the source and drain layers are completely deposited in the first via hole, thereby reducing the interlayer dielectric between the source and drain layers and the array substrate.
  • the height difference between the layers makes the lead layer less likely to be disconnected at the junction of the source drain layer and the interlayer dielectric layer, thereby improving the reliability of the detection device.
  • each of the above units or structures can be implemented as independent entities, or can be combined arbitrarily, and implemented as the same or several entities.
  • specific implementation of each of the above units or structures please refer to the previous method embodiments. No longer.

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Abstract

本发明公开阵列基板、制备方法及显示面板，包括基板，基板包括非显示区，基板上有薄膜晶体管层和第一像素电极层，薄膜晶体管层包括层间介电层，层间介电层有第一过孔；非显示区有检测器件，包括：源漏极层，位于第一过孔内；第二像素电极层，通过引线与第一像素电极层连接。本发明的阵列基板，提高检测器件可靠性。

Description

阵列基板、制备方法及显示面板 技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板、制备方法及显示面板。
 背景技术
显示面板中漏极端电极与像素电极之间的接触阻抗决定了驱动电路的功耗大小和像素充放电响应速度，因此，在显示面板的像素设计完成后，需要对其漏极端电极与像素电极之间的接触阻抗进行测量。由于面板的显示区膜层较多，直接测量漏极端电极与像素电极之间的接触阻抗会破坏显示区的其它膜层，因此一般通过在面板的非显示区域设置检测器件，该检测器件包括薄膜晶体管和像素电极，且该像素电极通过引线与显示区域的像素电极连接，以检测漏极端电极与像素电极之间的接触阻抗。
 技术问题
但是，由于检测器件测试区域膜层较绕线电阻区域膜层多，因此测试区和显示区之间上的引线之间存在高度差，引线在有高度差的位置极容易断线导致器件失效。
 技术解决方案
本发明实施例提供一种阵列基板、制备方法及显示面板，旨在改进阵列基板的结构，降低阵列基板上检测器件与层间介电层之间的高度差，使得引线在检测器件与层间介电层的交界处不容易发生断线，提高检测器件的可靠性。
本发明实施例提供一种阵列基板、制备方法及显示面板，旨在改进阵列基板的结构，降低阵列基板上检测器件与层间介电层之间的高度差，使得引线在检测器件与层间介电层的交界处不容易发生断线，提高检测器件的可靠性。
第一方面，本申请提供一种阵列基板，所述阵列基板包括基板，所述基板包括显示区和非显示区，所述基板上依次设有薄膜晶体管层和第一像素电极层，所述薄膜晶体管层包括位于所述显示区内的薄膜晶体管和位于所述非显示区内的层间介电层，所述第一像素电极层与所述薄膜晶体管层连接，所述层间介电层在所述基板的非显示区开设有第一过孔；所述基板的非显示区设有检测器件，所述检测器件包括：
第一栅极金属层，沉积在所述基板上，并与所述第一过孔位置对应；
第一源漏极层，沉积在所述第一栅极金属层上，所述源漏极层位于所述第一过孔内；
第二像素电极层，沉积在所述源漏极层上，所述第二像素电极层通过引线与所述第一像素电极层连接。
可选的，所述阵列基板还包括平坦化层，所述平坦化层位于所述薄膜晶体管层与所述第一像素电极层之间，所述平坦化层在所述基板的非显示区开设有第二过孔以形成测试区域，所述第一过孔位于所述测试区域内。
可选的，所述引线沉积在所述平坦化层和所述层间介电层上。
可选的，所述第一过孔的面积大于或等于所述第一栅极金属层的面积。
可选的，所述第一过孔的面积大于所述第一栅极金属层的面积，所述第一源漏极层完全沉积在所述第一过孔的内部。
可选的，所述第一栅极金属层的上表面高度小于所述层间介电层高度。
可选的，所述第一源漏极层的上表面高度与所述层间介电层的上表面高度持平。
第二方面，本申请提供一种阵列基板的制备方法，所述阵列基板包括显示区和非显示区，所述方法包括：
提供基板，所述基板包括显示区和非显示区；
在所述基板上形成薄膜晶体管层、第一栅极层和第一源漏极层，所述薄膜晶体管包括位于所述显示区的薄膜晶体管和位于所述非显示区的层间介电层，所述层间介电层在所述基板的非显示区开设有第一过孔；所述第一栅极金属层和所述第一源漏极层位于所述非显示区，所述第一栅极层与所述第一过孔位置对应，所述第一源漏极层位于所述第一过孔内并与所述栅极层接触；
在所述薄膜晶体管层上形成第一像素电极层、第二像素电极层和引线，所述第一像素电极层与所述薄膜晶体管连接，所述第二像素电极层位于所述第一源漏极层上，并通过引线与所述第一像素电极层连接。
可选的，所述在所述薄膜晶体管层上形成第一像素电极层、第二像素电极层和引线之前，还包括：
在所述薄膜晶体管层上形成平坦化层；
在所述平坦化层对应所述非显示区的位置开设有第二过孔以形成测试区域；其中，所述第一过孔位于所述测试区域内，所述第一像素电极层形成于所述平坦化层上，所述第二像素电极层形成于所述源漏极层上，所述引线形成于所述平坦化层和所述层间介质层上。
可选的，所述引线为铟稼锌材料。
可选的，所述在所述基板上形成薄膜晶体管、第一栅极层和第一源漏极层，包括：
在所述基板上形成第一栅极层和第二栅极层；
在所述第一栅极层上方形成第一源漏极层；
在所述第二栅极层上方形成所述薄膜晶体管。
可选的，所述在所述基板上形成第一栅极层和第二栅极层，包括：
在所述基板上位于非显示区且与第一过孔对应的区域上涂覆一层栅极材料层，同时在所述显示面板的显示区涂覆一层栅极材料层；
在所述栅极材料层上形成一层图案化掩模层；
进行湿式蚀刻工艺微缩所述图案化掩模层的尺寸，以所述图案化掩模层为掩模，去除部分栅极材料层，分别形成第一栅极金属层和第二栅极金属层。
可选的，所述第一栅极金属层的上表面高度小于所述层间介电层的高度。
可选的，所述第一源漏极层的上表面高度与所述层间介电层的上表面高度持平。
第三方面，本申请还提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括基板，所述基板包括显示区和非显示区，所述基板上依次设有薄膜晶体管层和第一像素电极层，所述薄膜晶体管层包括位于所述显示区内的薄膜晶体管和位于所述非显示区内的层间介电层，所述第一像素电极层与所述薄膜晶体管层连接，所述层间介电层在所述基板的非显示区开设有第一过孔；所述基板的非显示区设有检测器件，所述检测器件包括：
第一栅极层，沉积在所述基板上，并与所述第一过孔位置对应；
第一源漏极层，沉积在所述栅极金属层上，所述源漏极层位于所述第一过孔内；
第二像素电极层，沉积在所述源漏极层上，所述第二像素电极层通过引线与所述第一像素电极层连接。
可选的，所述阵列基板还包括平坦化层，所述平坦化层位于所述薄膜晶体管层与所述第一像素电极层之间，所述平坦化层在所述基板的非显示区开设有第二过孔以形成测试区域，所述第一过孔位于所述测试区域内。
可选的，所述引线沉积在所述平坦化层和所述层间介电层上。
可选的，所述第一过孔的面积大于或等于所述第一栅极金属层的面积。
可选的，所述第一栅极金属层的上表面高度小于所述层间介电层高度。
可选的，所述第一源漏极层的上表面高度与所述层间介电层的上表面高度持平。
 有益效果
本发明实施例提供的阵列基板，通过在阵列基板的层间介电层中设置一过孔，且将源漏极层完全沉积在第一过孔中，降低源漏极层与阵列基板层间介电层之间的高度差，使得引线层在源漏极层与层间介电层的交界处不容易发生断线，提高检测器件的可靠性。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的阵列基板一实施例结构剖面图；
图2为本发明提供的阵列基板一实施例结构俯视图；
图3为本发明提供的阵列基板的制备方法一实施例流程示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本发明，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本发明。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本发明的描述变得晦涩。因此，本发明并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
本发明实施例提供一种阵列基板、制备方法及显示面板。以下分别进行详细说明。
如图1所示，为本发明提供的阵列基板一实施例结构剖面图，该阵列基板包括基板10，基板包括显示区和非显示区，而基板上依次设置有薄膜晶体管层20和第一像素电极层30，薄膜晶体管层20包括位于显示区内的薄膜晶体管201和位于非显示区内的层间介电层202，薄膜晶体管201又包括位于显示区内第二栅极层2011和第二源漏极层2012，第二栅极层和第二源漏极层通过过孔连接；薄膜晶体管201还包括一些其他结构，如层间介电层，多晶硅层和绝缘层等，图中未画出；层间介电层202在基板的非显示区内开设有第一通孔2021。而在基板的非显示区设有检测器件，其中，检测器件包括：
第一栅极金属层40，沉积在基板10上，并且与第一过孔2021位置对应。
第一源漏极层50，沉积在第一栅极金属层40上，且第一源漏极层50位于第一过孔2021内。
第二像素电极层60，沉积在第一源漏极层50上，第二像素电极层60通过引线与第一像素电极层30连接。
本发明提供的实施例提供的阵列基板，通过在阵列基板的层间介电层202中设置第一过孔2021，且将第一源漏极层50完全沉积在第一过孔2021中，降低第一源漏极层50与阵列基板层间介电层202之间的高度差，使得引线在第一源漏极层50与层间介电层50的交界处不容易发生断线，提高检测器件的可靠性。
而在本发明的另一些实施例中，阵列基板还可以包括平坦化层70，平坦化层70为有机平坦化层，有机平坦化层70制备于层间介电层202上，且有机平坦化层70设置在薄膜晶体管层20和第一像素电极层30之间，有机平坦化层70用于帮助显示面板的上表面处于同样的高度，避免出现凹凸不平，影响显示。同时，有机平坦化层70在基板10的非显示区开设有第二过孔701以形成测试区域，便于后续对显示面板进行测试，第一过孔2021也位于测试区域内。在第二过孔中制备有阵列基板的其他结构，此处可以参考现有技术，此处不做任何限定。
而在上述实施例的基础上，第二像素电极层沉积在有机平坦化层70上方，引线沉积在第二过孔701形成的测试区域上方；第二像素电极层60同时也沉积在第一源漏极层50上方，引线用于连接位于显示区的第二像素电极层和位于非显示区的第一像素电极层，进而连接显示面板与测试区域，以便后续进行检测。
在本发明的一个实施例中，第一过孔2021的面积大于第一栅极金属层40的面积。或在本发明的另一些实施例中，第一过孔2021的面积等于第一栅极金属层40的面积。
具体的，当第一过孔2021的面积大于第一栅极金属层40的面积时，第一源漏极层50完全沉积在第一过孔2021的内部，且第一源漏极层50的面积大于第一栅极金属层40的面积。同时，第一源漏极层50的上表面高度与层间介电层202的上表面高度持平。即第一源漏极层50的上表面高度与层间介电层202的上表面高度处于同一水平面高度。
如图2所示，为本发明提供的阵列基板一实施例俯视图，平坦化层70位于阵列基板最外围，而层间介电层202位于平坦化层70上方，且层间介电层202的大小小于平坦化层70的大小。而第一栅极金属层40位于层间介电层202的内部，同时第一源漏极层50沉积在第一栅极金属层40上方，第一栅极金属层40和第一源漏极层50可以为矩形。而在第一源漏极层50上方沉积有第二像素电极层60，在层间介电层202上方沉积有第一像素电极层30，第一像素电极层30和第二像素电极层60通过引线连接，即显示面板的显示区和非显示区通过引线连接。
在本发明的一些实施例中，栅极层的材料可以为钼等金属材料，而源漏极的材料可以为铝合金，具体的，可以为Ti-Al-Ti合金。
需要说明的是，上述阵列基板实施例中仅描述了上述结构，可以理解的是，除了上述结构之外，本发明实施例显示面板中，还可以根据需要包括任何其他的必要结构，具体此处不作限定。
本发明还提供一种阵列基板的制备方法，该阵列基板包括显示区和非显示区，如图3所示，为本发明提供的阵列基板的制备方法一实施例流程示意图，该方法包括步骤201至步骤203，详细说明如下：
201、提供基板，基板包括显示区和非显示区。
202、在基板上形成薄膜晶体管层、第一栅极层和第一源漏极层，薄膜晶体管包括位于显示区的薄膜晶体管和位于非显示区的层间介电层，层间介电层在基板的非显示区开设有第一过孔；第一栅极金属层和第一源漏极层位于非显示区，第一栅极层与第一过孔位置对应，第一源漏极层位于第一过孔内并与所述栅极层接触。
303、在薄膜晶体管层上形成第一像素电极层、第二像素电极层和引线，第一像素电极层与薄膜晶体管连接，第二像素电极层位于第一源漏极层上，并通过引线与第一像素电极层连接。
本发明提供的阵列基板的制作方法，通过在阵列基板的层间介电层中设置一过孔，且将源漏极层完全沉积在第一过孔中，降低源漏极层与阵列基板层间介电层之间的高度差，使得引线层在源漏极层与层间介电层的交界处不容易发生断线，提高检测器件的可靠性。
具体的，在提供了基板后，依次在基板的上方制备薄膜晶体管层和第一像素电极层，而薄膜晶体管层包括有位于显示面板显示区的薄膜晶体管和位于显示面板非显示区的层间介电层。同时，在制备层间介电层时，在层间介电层位于显示面板非显示区的位置上开设第一过孔。
在本发明的一个具体实施例中，步骤21在基板上形成薄膜晶体管层、第一栅极层和第一源漏极层，可以包括：
（1）、在基板上形成第一栅极层和第二栅极层；
（2）、在第一栅极层上方形成第一源漏极层；
（3）、在第二栅极层上方形成所述薄膜晶体管。
具体的，在基板上位于非显示区且与第一过孔对应的区域上涂覆一层栅极材料层，同时在显示面板的显示区涂覆一层栅极材料层；在栅极材料层上形成一层图案化掩模层；进行湿式蚀刻工艺微缩图案化掩模层的尺寸，以图案化掩模层为掩模，去除部分栅极材料层，分别形成第一栅极金属层和第二栅极金属层。在制备完成位于非显示区的第一栅极金属层和位于显示区的第二栅极金属层后，在第一栅极金属层上制备第一源漏极层，而在第二栅极金属层上方制备完成薄膜晶体管层。
在上述实施例中，制备薄膜晶体管等显示面板中的结构的具体方法可以参考现有技术，此处不做限定。
制备完成后的第一栅极金属层的上表面高度小于层间介电层的高度。同时，在第一栅极金属层上沉积第一源漏极层，且第一源漏极层的上表面高度与层间介电层的上表面高度持平，即第一源漏极层的上表面高度与层间介电层的上表面高度处于同一水平高度，第一源漏极层完全沉积在第一过孔内部且与第一栅极金属层对应设置。由于第一源漏极层上表面高度与层间介电层的上表面高度持平，使得第一源漏极上表面与层间介电层上表面没有高度差。同时第一源漏极层的面积大小可以大于或者等于第一栅极金属层的面积大小。
在本发明的一个实施例中，在步骤22在薄膜晶体管层上形成第一像素电极层、第二像素电极层和引线之前，本方法还可以包括：
在薄膜晶体管层上形成有机平坦化层，有机平坦化层在基板的非显示区开设有第二过孔以形成测试区域，第一过孔位于测试区域内；第一像素电极层形成于有机平坦化层上，第二像素电极层形成于源漏极层上，引线形成于有机平坦化层和层间介质层上。
具体的，在薄膜晶体管上方制备形成有机平坦化层，同时有机平坦化层在基板的非显示区开设第二过孔以形成测试区域，便于后续进行测试。第一过位于测试区域内。有机平坦化层制备完成后，在有机平坦化层上方制备形成第一像素电极层，同时在第一源漏极上方制备形成第二像素电极层。引线可以同时与像素电极制备完成，也可以在像素电极完成后，单独制备，连接第一像素电极层和第二像素电极层。引线可以为铟稼锌（ITO）材料。制备完成后的引线在显示面板的显示区与非显示区的连接处不存在高度差，因此引线不会发生断线，避免了引线断下导致的检测器件的不良。
需要说明的是，在本发明实施例提供的阵列基板中，检测器件可以为多个，且检测器件与阵列基板连接用于检测阵列基板中的不良。
本发明还提供一种显示面板，该显示面板包括前述阵列基板。该阵列基板包括基板10，基板包括显示区和非显示区，而基板上依次设置有薄膜晶体管层20和第一像素电极层30，薄膜晶体管层20包括位于显示区内的薄膜晶体管201和位于非显示区内的层间介电层202。而第一像素电极层30与薄膜晶体管层20连接，层间介电层202在基板的非显示区内开设有第一通孔2021。而在基板的非显示区设有检测器件，其中，检测器件包括：
第一栅极金属层40，沉积在基板10上，并且与第一过孔2021位置对应。
第一源漏极层50，沉积在第一栅极金属层40上，且第一源漏极层50位于第一过孔2021内。
第二像素电极层60，沉积在第一源漏极层50上，第二像素电极层60通过引线与第一像素电极层30连接。
本发明提供的显示面板，通过在阵列基板的层间介电层中设置一过孔，且将源漏极层完全沉积在第一过孔中，降低源漏极层与阵列基板层间介电层之间的高度差，使得引线层在源漏极层与层间介电层的交界处不容易发生断线，提高检测器件的可靠性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文针对其他实施例的详细描述，此处不再赘述。
具体实施时，以上各个单元或结构可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，以上各个单元或结构的具体实施可参见前面的方法实施例，在此不再赘述。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
以上对本发明实施例所提供的一种阵列基板集齐制备方法、显示面板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括基板，所述基板包括显示区和非显示区，所述基板上依次设有薄膜晶体管层和第一像素电极层，所述薄膜晶体管层包括位于所述显示区内的薄膜晶体管和位于所述非显示区内的层间介电层，所述第一像素电极层与所述薄膜晶体管层连接，所述层间介电层在所述基板的非显示区开设有第一过孔；所述基板的非显示区设有检测器件，所述检测器件包括：
    第一栅极金属层，沉积在所述基板上，并与所述第一过孔位置对应；
    第一源漏极层，沉积在所述第一栅极金属层上，所述源漏极层位于所述第一过孔内；
    第二像素电极层，沉积在所述源漏极层上，所述第二像素电极层通过引线与所述第一像素电极层连接。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括平坦化层，所述平坦化层位于所述薄膜晶体管层与所述第一像素电极层之间，所述平坦化层在所述基板的非显示区开设有第二过孔以形成测试区域，所述第一过孔位于所述测试区域内。
  3. 根据权利要求2所述的阵列基板，其中，所述引线沉积在所述平坦化层和所述层间介电层上。
  4. 根据权利要求1所述的阵列基板，其中，所述第一过孔的面积大于或等于所述第一栅极金属层的面积。
  5. 根据权利要求4所述的阵列基板，其中，所述第一过孔的面积大于所述第一栅极金属层的面积，所述第一源漏极层完全沉积在所述第一过孔的内部。
  6. 根据权利要求1所述的阵列基板，其中，所述第一栅极金属层的上表面高度小于所述层间介电层高度。
  7. 根据权利要求6所述的阵列基板，其中，所述第一源漏极层的上表面高度与所述层间介电层的上表面高度持平。
  8. 一种阵列基板的制备方法，其中，所述方法包括：
    提供基板，所述基板包括显示区和非显示区；
    在所述基板上形成薄膜晶体管层、第一栅极层和第一源漏极层，所述薄膜晶体管包括位于所述显示区的薄膜晶体管和位于所述非显示区的层间介电层，所述层间介电层在所述基板的非显示区开设有第一过孔；所述第一栅极金属层和所述第一源漏极层位于所述非显示区，所述第一栅极层与所述第一过孔位置对应，所述第一源漏极层位于所述第一过孔内并与所述栅极层接触；
    在所述薄膜晶体管层上形成第一像素电极层、第二像素电极层和引线，所述第一像素电极层与所述薄膜晶体管连接，所述第二像素电极层位于所述第一源漏极层上，并通过引线与所述第一像素电极层连接。
  9. 根据权利要求8所述的阵列基板的制备方法，其中，所述在所述薄膜晶体管层上形成第一像素电极层、第二像素电极层和引线之前，还包括：
    在所述薄膜晶体管层上形成平坦化层；
    在所述平坦化层对应所述非显示区的位置开设有第二过孔以形成测试区域；其中，所述第一过孔位于所述测试区域内，所述第一像素电极层形成于所述平坦化层上，所述第二像素电极层形成于所述源漏极层上，所述引线形成于所述平坦化层和所述层间介质层上。
  10. 根据权利要求9所述的阵列基板的制备方法，其中，所述引线为铟稼锌材料。
  11. 根据权利要求8所述的阵列基板的制备方法，其中，所述在所述基板上形成薄膜晶体管层、第一栅极层和第一源漏极层，包括：
    在所述基板上形成第一栅极层和第二栅极层；
    在所述第一栅极层上方形成第一源漏极层；
    在所述第二栅极层上方形成所述薄膜晶体管。
  12. 根据权利要求11所述的阵列基板的制备方法，其中，所述在所述基板上形成第一栅极层和第二栅极层，包括：
    在所述基板上位于非显示区且与第一过孔对应的区域上涂覆一层栅极材料层，同时在所述显示面板的显示区涂覆一层栅极材料层；
    在所述栅极材料层上形成一层图案化掩模层；
    进行湿式蚀刻工艺微缩所述图案化掩模层的尺寸，以所述图案化掩模层为掩模，去除部分栅极材料层，分别形成第一栅极金属层和第二栅极金属层。
  13. 根据权利要求8所述的阵列基板的制备方法，其中，所述第一栅极金属层的上表面高度小于所述层间介电层的高度。
  14. 根据权利要求13所述的阵列基板的制备方法，其中，所述第一源漏极层的上表面高度与所述层间介电层的上表面高度持平。
  15. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括基板，所述基板包括显示区和非显示区，所述基板上依次设有薄膜晶体管层和第一像素电极层，所述薄膜晶体管层包括位于所述显示区内的薄膜晶体管和位于所述非显示区内的层间介电层，所述第一像素电极层与所述薄膜晶体管层连接，所述层间介电层在所述基板的非显示区开设有第一过孔；所述基板的非显示区设有检测器件，所述检测器件包括：
    第一栅极层，沉积在所述基板上，并与所述第一过孔位置对应；
    第一源漏极层，沉积在所述栅极金属层上，所述源漏极层位于所述第一过孔内；
    第二像素电极层，沉积在所述源漏极层上，所述第二像素电极层通过引线与所述第一像素电极层连接。
  16. 根据权利要求15所述的显示面板，其中，所述阵列基板还包括平坦化层，所述平坦化层位于所述薄膜晶体管层与所述第一像素电极层之间，所述平坦化层在所述基板的非显示区开设有第二过孔以形成测试区域，所述第一过孔位于所述测试区域内。
  17. 根据权利要求16所述的显示面板，其中，所述引线沉积在所述平坦化层和所述层间介电层上。
  18. 根据权利要求15所述的显示面板，其中，所述第一过孔的面积大于或等于所述第一栅极金属层的面积。
  19. 根据权利要求15所述的显示面板，其中，所述第一栅极金属层的上表面高度小于所述层间介电层高度。
  20. 根据权利要求19所述的显示面板，其中，所述第一源漏极层的上表面高度与所述层间介电层的上表面高度持平。
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