WO2021189486A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021189486A1
WO2021189486A1 PCT/CN2020/081858 CN2020081858W WO2021189486A1 WO 2021189486 A1 WO2021189486 A1 WO 2021189486A1 CN 2020081858 W CN2020081858 W CN 2020081858W WO 2021189486 A1 WO2021189486 A1 WO 2021189486A1
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WIPO (PCT)
Prior art keywords
pad
layer
electrode
display
silicon
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PCT/CN2020/081858
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English (en)
French (fr)
Inventor
朱志坚
卢鹏程
敖雨
李云龙
田元兰
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/260,248 priority Critical patent/US11957013B2/en
Priority to EP20897674.6A priority patent/EP4131375B1/en
Priority to CN202080000385.5A priority patent/CN113748507B/zh
Priority to PCT/CN2020/081858 priority patent/WO2021189486A1/zh
Priority to CN202210812348.5A priority patent/CN115207060A/zh
Publication of WO2021189486A1 publication Critical patent/WO2021189486A1/zh
Priority to US17/954,377 priority patent/US20230017885A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • OLED Organic Light Emitting Display, Organic Light Emitting Diode
  • OLED display device has self-luminous, low driving voltage, high luminous efficiency, short response time, high definition and contrast, nearly 180° viewing angle, wide operating temperature range, and can realize flexible display and Large-area full-color display and many other advantages are considered to be the most promising new generation display technology.
  • OLED display devices are developing in the direction of miniaturization.
  • the purpose of the present disclosure is to provide a display panel and a display device.
  • a display panel including:
  • the silicon-based substrate includes a display area and a peripheral area surrounding the display area;
  • the first electrode layer is provided on the side of the driving layer away from the silicon-based substrate, and includes a plurality of first electrodes located in the display area, and each of the first electrodes is electrically connected to each of the first transistors. connect;
  • the organic light-emitting layer is arranged on the side of the first electrode layer away from the driving layer;
  • the second electrode layer is arranged on the side of the organic light-emitting layer away from the driving layer, and includes a second electrode located in the display area and an electrode ring located in the peripheral area.
  • the electrode ring surrounds the second electrode and is connected to the Second electrode connection;
  • a plurality of pads are located in the peripheral area on at least one side of the display area, the plurality of pads include a display signal access pad and a test signal access pad, and the test signal access pad is located in the peripheral area.
  • the display signal is connected to both sides of the pad;
  • the display signal access pad is configured to access a display signal in the display phase
  • the test signal access pad is configured to access a test signal in the test phase
  • the test signal access pad at least includes
  • the first set of test-stage access pads includes a first set of test-stage access pads and a second pad.
  • the first pad is electrically connected to the electrode ring
  • the second The pad is electrically connected to the silicon-based substrate.
  • each of the first transistors includes an active region formed in the silicon-based substrate, two doped regions in the active region, and two doped regions in the active region.
  • the channel region between the doped regions and the gate located on the channel region, the two doped regions respectively form a first pole and a second pole, and the second pad is connected to each of the first poles.
  • the active area of a transistor is electrically connected.
  • the test signal access pad further includes a second group of test stage access pads, and the second group of test stage access pads includes a third pad and a second set of test stage access pads.
  • the third pad is electrically connected to the electrode ring
  • the fourth pad is electrically connected to the silicon-based substrate.
  • the peripheral area includes a bonding area, and the third pad, the fourth pad, and the plurality of display signal access pads are located in the bonding area. within the area.
  • the first pad and the third pad are located on the same side of the display signal access pad, and the second pad and the fourth pad are located on the same side of the display signal access pad.
  • the disc is located on the other side of the display signal access pad.
  • the third pad and the fourth pad are respectively arranged adjacent to the display signal access pad.
  • the display panel is provided with one first pad and one second pad.
  • the display panel is provided with one third pad and one fourth pad.
  • the third pad is connected to the first pad, and the fourth pad is connected to the second pad.
  • test signal access pad and the first electrode are provided in the same layer.
  • the driving layer further includes:
  • a plurality of detection lines are connected to the connection line, and each of the detection lines is electrically connected to the active area of a row of the transistors.
  • the first pad is electrically connected to the electrode ring through a wire.
  • the display panel further includes:
  • the second transistor is formed in the peripheral region of the silicon-based substrate and includes an active region formed in the silicon-based substrate, two doped regions in the active region, and two doped regions in the active region.
  • the channel region between the doped regions and the gate located on the channel region, the two doped regions respectively form a first electrode and a second electrode; the second electrode of the second transistor and the gate
  • the electrode ring is electrically connected, and the first pad is electrically connected to the first electrode and the gate of the second transistor.
  • the driving layer includes:
  • a gate insulating layer disposed on the channel region on one side of the silicon-based substrate
  • the gate layer is provided on the side of the gate insulating layer away from the silicon-based substrate;
  • the first flat layer is provided on one side of the silicon-based substrate and covers the gate insulating layer and the gate layer;
  • the first conductive layer is provided on the side of the first flat layer away from the silicon-based substrate;
  • the dielectric layer is provided on the side of the first flat layer away from the silicon-based substrate and covers the first conductive layer;
  • the second conductive layer is provided on the side of the dielectric layer away from the silicon-based substrate;
  • the second flat layer is provided on the side of the dielectric layer away from the silicon-based substrate and covers the second conductive layer, and the first electrode layer is located on a side of the second flat layer away from the silicon-based substrate side.
  • the display panel further includes:
  • the first encapsulation layer is provided on the side of the second electrode layer away from the organic light-emitting layer;
  • the color film layer is arranged on the side of the first encapsulation layer away from the second electrode layer;
  • the second encapsulation layer is arranged on a side of the color filter layer away from the first encapsulation layer, and the third and fourth pads are exposed from the second encapsulation layer.
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure
  • Fig. 2 is an enlarged part of area A in Fig. 1;
  • Fig. 3 is an enlarged part of area B in Fig. 1;
  • FIG. 4 is a cross-sectional view of the C-C plane in FIG. 1 according to an embodiment of the present disclosure
  • Fig. 5 is a cross-sectional view of the C-C plane in Fig. 1 according to another embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of the connection between the test signal access pad and the first electrode and the second electrode provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a circuit in which the first pad and the electrode ring are electrically connected according to an embodiment of the disclosure.
  • the existing IVL test (characteristic curve test of current, voltage and brightness) and other test methods are difficult to implement on miniaturized display panels. Specifically, after the OLED evaporation is completed, Inline IVL (characteristic curve test of current, voltage and brightness in the cavity) test is required, and the probe of the Probe Board (probe card) can be pierced on the CP (Chip Probe) On the Pin (pin), and input the test signal for IVL test; however, there are multiple pairs of pads on the CP, and the IVL test is only one pair of pads. Due to the limitation of the layout, there is no area for designing the CP. .
  • the display panel 10 includes: a silicon-based substrate 20, a driving layer 30, a first electrode layer, an organic light-emitting layer 60, and a second Electrode layer 70, multiple pads.
  • the silicon-based substrate 20 includes a display area and a peripheral area surrounding the display area;
  • the driving layer 30 is formed in the silicon-based substrate 20 and includes a plurality of first transistors located in the display area;
  • the first electrode layer is provided on the driving layer 30 away from One side of the silicon-based substrate 20, and includes a plurality of first electrodes 40 located in the display area, each first electrode 40 is electrically connected to each first transistor;
  • the organic light emitting layer 60 is provided on the first electrode layer away from the driving layer 30 One side;
  • the second electrode layer 70 is provided on the side of the organic light-emitting layer 60 away from the drive layer 30, and includes a second electrode 720 located in the display area and an electrode ring 710 located in the peripheral area.
  • the electrode ring 710 surrounds the second electrode 720 and Connected to the second electrode 720; multiple pads are located in the peripheral area on at least one side of the display area, the multiple pads include display signal access pads and test signal access pads, the test signal access pads are located in the display signal connection Into both sides of the pad.
  • the display signal access pad is configured to access the display signal during the display phase
  • the test signal access pad is configured to access the test signal during the test phase
  • the test signal access pad includes at least the first set of test phase connections.
  • the access pads in the first group of test phases include a first pad and a second pad. The first pad is electrically connected to the electrode ring, and the second pad is electrically connected to the silicon-based substrate.
  • the second pad 52 is connected to the VDD (+5V direct current voltage) test signal
  • the first pad 51 is connected to the Vcom (-2.5V direct current voltage) test signal, where VDD passes the test signal.
  • the wire is connected to the silicon-based substrate area corresponding to each first transistor, and the PN junction is turned on by forward bias, so that the VDD test signal is sent to the first electrode 40; at the same time, Vcom sends the test signal to the first electrode 40 through the electrode ring 710
  • the second electrode 720 causes a voltage difference to be formed between the first electrode 40 and the second electrode 720, thereby illuminating the pixel unit to perform an IVL test and collect test data, so as to achieve the purpose of the ILV test.
  • the display panel provided by the present disclosure is connected to the electrode ring 710 through the first pad 51 to realize the connection with the second electrode 720; each first electrode 40 is connected to a first transistor, and each first transistor corresponds to a silicon substrate The bottom is connected to the second pad 52; the test signal is input through the first pad 51 and the second pad 52, so that a voltage difference is formed between the first electrode 40 and the second electrode 720, so that the pixel unit is lighted up and the IVL test is performed And collect test data to achieve the purpose of ILV test.
  • the first pad 51 and the second pad 52 are provided in the peripheral area of the silicon-based substrate 20. It occupies a small space and can meet the design of miniaturized silicon-based display panels.
  • the silicon-based substrate 20 constitutes a silicon-based OLED display panel.
  • the embodiments of the present disclosure provide a top-emission silicon-based OLED display panel.
  • a transistor includes an active region 380 formed in a silicon-based substrate, two doped regions located in the active region 380, a channel region located between the two doped regions, and a gate 320 located on the channel region , The two doped regions respectively form a first electrode 310 and a second electrode 330, and the second pad 52 is electrically connected to the active region 380 of each first transistor.
  • the first transistor is a P-type MOS transistor
  • the active region 380 is an N-type doped region
  • the first electrode 310 and the second electrode 320 are P-type doped regions on a silicon-based substrate
  • the first transistor The second electrode 330 is a drain
  • the first electrode 310 is a source.
  • the silicon-based substrate corresponding to each first transistor is the active area 380 of the first transistor.
  • the active area 380 of the first transistor is connected to the VDD test signal through the second pad 52, and the PN The junction is turned on, so that the VDD test signal is given to the anode.
  • the electrode ring 710 is a cathode ring
  • the cathode ring is a ring-shaped wiring that provides a cathode common voltage (negative) at the periphery of the display area.
  • the common cathode provides negative pressure.
  • the drain of the first transistor is connected to the first electrode 40 through the second conductive layer 350 and the first conductive layer 340.
  • the second conductive layer 350 and the first conductive layer 340 Reduce wiring area and improve resolution.
  • between the first electrode 40 and the second conductive layer 350, between the second conductive layer 350 and the first conductive layer 340, between the first conductive layer 340 and the second electrode 330, the gate 320 and the first electrode 310 Are electrically connected through contact holes 360, respectively.
  • the contact hole 360 is a tungsten hole.
  • C2 in FIG. 4 refers to the second transistor electrically connected to the electrode ring 710.
  • the second transistor is formed in the peripheral area of the silicon-based substrate, including the active area formed in the silicon-based substrate, and The two doped regions of the active region, the channel region between the two doped regions, and the gate 393 on the channel region, the two doped regions form a first electrode 391 and a second electrode 392, respectively.
  • the second electrode 392 of the second transistor is electrically connected to the electrode ring 710, and the first pad 51 is electrically connected to the first electrode 391 and the gate 393 of the second transistor.
  • the first pad 51 is electrically connected to the first electrode 391 and the gate 393 of the second transistor, so that Vcom is transmitted to the second electrode 720 through the electrode ring 710, so that the gap between the first electrode 40 and the second electrode 720 A pressure difference is formed, and then the pixel unit is lighted to perform an IVL test and collect test data to achieve the purpose of the ILV test.
  • the first electrode 391 may be a source electrode
  • the second electrode 392 may be a drain electrode.
  • the first pad 51 can also be electrically connected to the electrode ring 710 through a wire, so that Vcom can be transmitted to the second electrode 720 through the electrode ring 710, so that a voltage difference is formed between the first electrode 40 and the second electrode 720. Then light up the pixel unit to perform IVL test and collect test data to achieve the purpose of ILV test.
  • the first pad 51 and the electrode ring 710 are directly electrically connected through a wire, which reduces the process difficulty.
  • the test signal access pads also include a second group of test stage access pads, and the second group of test stage access pads include a third pad 53 and a fourth pad 54.
  • the third pad 53 is electrically connected to the electrode ring 710
  • the fourth pad 54 is electrically connected to the silicon-based substrate.
  • the third pad 53 and the fourth pad 54 are located in the peripheral area and can be exposed from the packaging layer of the display panel. Only the third pad 53 and the fourth pad 54 are required for the MIT test of the display panel. However, the pin angle required for MIT testing is reduced, which in turn reduces the number of probes required and reduces the cost.
  • the peripheral area of the silicon-based substrate includes a bonding area.
  • the third pad 53, the fourth pad 54 and a plurality of display signal access pads are located in the bonding area, and the display signal access pads are the bonding area.
  • Bonding Pad 41 Since the multi-layer organic and inorganic material covering of the display panel will cover the first pad 51 and the second pad 52 during the packaging process, the MIT test cannot be performed through the first pad 51 and the second pad 52 after packaging. Therefore, the third pad 53, the fourth pad 54 and multiple display signal access pads can be formed in the bonding area at the same time. The third pad 53 and the fourth pad 54 should be made with other bonding pads 41.
  • the photoresist layer followed by laser ablation, will ablate the photoresist layer together with the organic and inorganic materials in the evaporation and packaging process, so that the metal on the surface of each pad is exposed, which meets the need for MIT test probe cards.
  • the third pad 53 is electrically connected to the electrode ring 710
  • the fourth pad 54 is electrically connected to the silicon-based substrate, so that the MIT test is performed through the third pad 53 and the fourth pad 54.
  • the third pad 53 and the fourth pad 54 are respectively arranged adjacent to the display signal access pad.
  • a plurality of bonding pads 41 are provided on the bonding area on the side of the silicon-based substrate 20, and each bonding pad 41 is located between the third pad 53 and the fourth pad 54.
  • the third pad 53 and the fourth pad 54 are arranged in the bonding area and located at both ends of the bonding pad 41, which will not affect the layout of the bonding pad 41.
  • the third pad 53 and the fourth bonding pad The disk 54 and the bonding pad 41 can be exposed through the same laser ablation process, which reduces the process difficulty and process cost.
  • the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 are located between the bonding pad 41 and the FPC Mark (flexible circuit board reference point), and the Mark is All steps in the assembly process of the FPC flexible circuit board provide a common positionable circuit pattern.
  • the first pad 51 and the third pad 53 are located on the same side of the display signal access pad, and the second pad 52 and the fourth pad 54 are located on the other side of the display signal access pad.
  • the display panel only has one first pad 51 and one second pad 52, and the second pad 52 is electrically connected to the active area of each MOS transistor.
  • the IVL test can be realized by only two pads, so that the number of pads is minimized, and the arrangement of the first pad 51 and the second pad 52 on the silicon-based substrate 20 is facilitated.
  • the display panel 10 has only one third pad 53 and one fourth pad 54, and the fourth pad 54 is electrically connected to the active area of each MOS transistor.
  • the MIT test can be realized by only two pads, so that the number of pads is minimized, and the arrangement of the third pad 53 and the fourth pad 54 on the silicon-based substrate 20 is facilitated.
  • the third pad 53 is connected to the first pad 51. As shown in FIG. 2, the third pad 53 and the first pad 51 may be located on the same side of the silicon-based substrate 20. After the first pad 51 is connected to the electrode ring 710 through a wire, the third pad 53 may pass through a wire. Connecting to the first pad 51 and thereby indirectly connecting to the electrode ring 710 can reduce the number of wires connected to the electrode ring 710, thereby reducing the difficulty of the manufacturing process of the display panel 10.
  • the fourth pad 54 is connected to the second pad 52. As shown in FIG. 3, the fourth pad 54 and the second pad 52 may be located on the same side of the silicon-based substrate 20. After the second pad 52 is connected to each first electrode 40 through a wire, the fourth pad 54 may be The wires are connected to the second pads 52 to be indirectly connected to the first electrodes 40, which can reduce the wires connected to the first electrodes 40, thereby reducing the difficulty of the manufacturing process of the display panel 10.
  • the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 are arranged in the same layer as the first electrode 40.
  • the first pad 51 and the second pad can be formed by the same process. 52.
  • the third pad 53, the fourth pad 54 and the first electrode 40 facilitate the formation of the first pad 51, the second pad 52, the third pad 53, and the fourth pad 54 and reduce the display panel 10 manufacturing process difficulty.
  • the driving layer 30 further includes: a connection line 381 and a plurality of detection lines 382.
  • the connecting line 381 is electrically connected to the second pad 52 and the fourth pad 54; a plurality of detecting lines 382 are connected to the connecting line 381, and each detecting line 382 is electrically connected to the active area of a row of first transistors.
  • the multiple detection lines 382 are routed in a mesh pattern, which can reduce the influence of Loading.
  • the driving layer 30 includes a gate insulating layer 370, a gate layer, a first flat layer, a first conductive layer 340, a dielectric layer, a second conductive layer 350, and a second flat layer.
  • the gate insulating layer 370 is provided on the side of the silicon-based substrate 20; the gate layer is provided on the side of the gate insulating layer 370 away from the silicon-based substrate 20; the first flat layer is provided on the side of the silicon-based substrate 20 and covers The gate insulating layer 370 and the gate layer; the first conductive layer 340 is arranged on the side of the first flat layer away from the silicon-based substrate 20; the dielectric layer is arranged on the side of the first flat layer away from the silicon-based substrate 20 and covers the first flat layer A conductive layer 340; a second conductive layer 350 is provided on the side of the dielectric layer away from the silicon-based substrate 20; a second flat layer is provided on the side of the dielectric layer away from the silicon-based substrate 20 and covers the second conductive
  • connection line 381 and each detection line 382 can be provided in the same layer as the first conductive layer 340.
  • the connecting line 381 and each detection line 382 may also be arranged in layers, and each detection line 382 and the first conductive layer 340 may be arranged in the same layer; or, the connecting line 381, each detection line 382 and the first conductive layer 340 may be arranged in layers respectively , This disclosure does not limit this.
  • the display panel further includes a pixel definition layer (PDL) 42.
  • the pixel definition layer 42 is formed with a plurality of openings, and each first electrode 40 is provided in each opening in a one-to-one correspondence.
  • a PDL is provided between the electrode for connecting the second transistor and the electrode ring 710 and the adjacent first electrode 40 to insulate the electrode from the adjacent first electrode 40.
  • the silicon-based OLED display panel provided in the present disclosure may be a white light OLED display panel
  • the organic light emitting layer 60 includes a red light emitting layer, a green light emitting layer, and a blue light emitting layer that are sequentially stacked.
  • the stacking order of the red light emitting layer, the green light emitting layer and the blue light emitting layer can be changed.
  • the display panel 10 further includes a first encapsulation layer 81, a color filter layer 90 and a second encapsulation layer 82.
  • the third pad 53 and the fourth pad 54 are provided with a photoresist layer, and then laser ablation is used to burn the photoresist layer together with the first encapsulation layer 81, the color film layer 90, and the second encapsulation layer 82.
  • the surfaces of the third pad 53 and the fourth pad 54 are exposed to meet the pinning requirements of the MIT test probe card.
  • the display panel 10 further includes a cover glass (not shown in the figure), and the cover glass is provided on a side of the second encapsulation layer 82 away from the color filter layer 90.
  • An embodiment of the present disclosure also provides a display device, which includes the above-mentioned display panel.
  • a display device which includes the above-mentioned display panel.
  • the display device may be, for example, a head-mounted display device such as VR/AR.

Abstract

本公开关于一种显示装置、显示面板及其制造方法，该显示面板包括：硅基衬底、驱动层、第一电极层、有机发光层、第二电极层、多个焊盘。驱动层形成于硅基衬底中，且包括位于显示区的多个第一晶体管；各第一电极与各第一晶体管电连接；第二电极层于有机发光层背离驱动层的一侧，且包括位于显示区的第二电极和位于外围区的电极环；多个焊盘位于显示区至少一侧的外围区，多个焊盘包括显示信号接入焊盘和测试信号接入焊盘；其中显示信号接入焊盘被配置为在显示阶段接入显示信号，测试信号接入焊盘至少包括第一组测试阶段接入焊盘，第一组测试阶段接入焊盘包括第一焊盘和第二焊盘，第一焊盘与电极环电连接，第二焊盘与硅基衬底电连接。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
OLED(Organic Light Emitting Display，有机发光二极管)显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被认为是最有发展前途的新一代显示技术。但是，OLED显示装置正在向微型化的方向发展。
发明内容
本公开的目的在于提供一种显示面板与显示装置。
根据本公开的一个方面，提供了一种显示面板，该显示面板包括：
硅基衬底，包括显示区与围绕所述显示区的外围区；
驱动层，形成于所述硅基衬底中，且包括位于所述显示区的多个第一晶体管；
第一电极层，设于所述驱动层背离所述硅基衬底的一侧，且包括位于所述显示区的多个第一电极，各所述第一电极与各所述第一晶体管电连接；
有机发光层，设于所述第一电极层背离所述驱动层的一侧；
第二电极层，设于有机发光层背离所述驱动层的一侧，且包括位于显示区的第二电极和位于外围区的电极环，所述电极环围绕所述第二电极且与所述第二电极连接；
多个焊盘，位于所述显示区至少一侧的所述外围区，所述多个焊盘包括显示信号接入焊盘和测试信号接入焊盘，所述测试信号接入焊 盘位于所述显示信号接入焊盘的两侧；
其中，所述显示信号接入焊盘被配置为在显示阶段接入显示信号，所述测试信号接入焊盘被配置为在测试阶段接入测试信号，所述测试信号接入焊盘至少包括第一组测试阶段接入焊盘，所述第一组测试阶段接入焊盘包括第一焊盘和第二焊盘，所述第一焊盘与所述电极环电连接，所述第二焊盘与所述硅基衬底电连接。
在本公开的一种示例性实施例中，各所述第一晶体管包括形成于所述硅基衬底中的有源区、位于所述有源区的两个掺杂区、位于两个所述掺杂区之间的沟道区以及位于所述沟道区上的栅极，两个所述掺杂区分别形成第一极与第二极，所述第二焊盘与各所述第一晶体管的有源区电连接。
在本公开的一种示例性实施例中，所述测试信号接入焊盘还包括第二组测试阶段接入焊盘，所述第二组测试阶段接入焊盘包括第三焊盘和第四焊盘，所述第三焊盘与所述电极环电连接，所述第四焊盘与所述硅基衬底电连接。
在本公开的一种示例性实施例中，所述外围区包括绑定区域，所述第三焊盘、所述第四焊盘及所述多个显示信号接入焊盘位于所述绑定区域内。
在本公开的一种示例性实施例中，所述第一焊盘与所述第三焊盘位于所述显示信号接入焊盘的同一侧，所述第二焊盘与所述第四焊盘位于所述显示信号接入焊盘的另一侧。
在本公开的一种示例性实施例中，所述第三焊盘和所述第四焊盘分别与所述显示信号接入焊盘相邻设置。
在本公开的一种示例性实施例中，所述显示面板设有一个所述第一焊盘和一个所述第二焊盘。
在本公开的一种示例性实施例中，所述显示面板设有一个所述第三焊盘和一个所述第四焊盘。
在本公开的一种示例性实施例中，所述第三焊盘与所述第一焊盘连接，所述第四焊盘与所述第二焊盘连接。
在本公开的一种示例性实施例中，所述测试信号接入焊盘与所述第一电极同层设置。
在本公开的一种示例性实施例中，所述驱动层还包括：
连接线，与所述第二焊盘及所述第四焊盘电连接；
多个检测线，与所述连接线连接，且每个所述检测线与一列所述晶体管的有源区分别电连接。
在本公开的一种示例性实施例中，所述第一焊盘通过导线与所述电极环电连接。
在本公开的一种示例性实施例中，所述显示面板还包括：
第二晶体管，形成于所述硅基衬底的外围区中，且包括形成于所述硅基衬底中的有源区、位于所述有源区的两个掺杂区、位于两个所述掺杂区之间的沟道区以及位于所述沟道区上的栅极，两个所述掺杂区分别形成第一极与第二极；所述第二晶体管的第二极与所述电极环电连接，所述第一焊盘与所述第二晶体管的第一极及栅极电连接。
在本公开的一种示例性实施例中，所述驱动层包括：
栅绝缘层，设于所述硅基衬底一侧的所述沟道区上；
栅极层，设于所述栅绝缘层背离所述硅基衬底的一侧；
第一平坦层，设于所述硅基衬底的一侧并覆盖所述栅绝缘层与所述栅极层；
第一导电层，设于所述第一平坦层背离所述硅基衬底的一侧；
介质层，设于所述第一平坦层背离所述硅基衬底的一侧并覆盖所述第一导电层；
第二导电层，设于所述介质层背离所述硅基衬底的一侧；
第二平坦层，设于所述介质层背离所述硅基衬底的一侧并覆盖所述第二导电层，所述第一电极层位于第二平坦层背离所述硅基衬底的一侧。
在本公开的一种示例性实施例中，所述显示面板还包括：
第一封装层，设于所述第二电极层远离所述有机发光层的一侧；
彩膜层，设于所述第一封装层远离所述第二电极层的一侧；
第二封装层，设于所述彩膜层远离所述第一封装层的一侧，所述第三焊盘与所述第四焊盘从所述第二封装层露出。
根据本公开的又一个方面，提供了一种显示装置，该显示装置包括上述的显示面板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为本公开的一种实施例提供的显示面板的示意图；
图2为图1中A区域的放大部；
图3为图1中B区域的放大部；
图4为本公开的一种实施例提供的图1中C-C面的剖视图；
图5为本公开的另一种实施例提供的图1中C-C面的剖视图；
图6为本公开的一种实施例提供的测试信号接入焊盘与第一电极及第二电极连接的示意图；
图7为本公开的一种实施例提供的第一焊盘与电极环电连接的电路示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本发明将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于 方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的组成部分等；用语“第一”、“第二”仅作为标记使用，不是对其对象的数量限制。
申请人发现，目前随着VR(Virtual Reality，虚拟现实)/AR(Augmented Reality，增强现实)技术的日益进步和市场的快速增长，适用于VR/AR领域的显示面板也正在加急步伐向微型化、高PPI、快速响应和高色域的方向发展，而硅基OLED显示面板凭借着其微型化和高PPI的优势，也正在成为VR/AR领域的新的关注焦点。
然而，现有的IVL测试(电流、电压和亮度的特性曲线测试)等测试方法在微型化显示面板上难以实现。具体地，OLED蒸镀完毕后，需要进行Inline IVL(腔内电流、电压和亮度的特性曲线测试)测试，可以将Probe Board(探头卡)的探针扎在CP(Chip Probe、芯片探针)的Pin(引脚)上，并输入测试信号进行IVL测试；但是，CP上有多对pad(焊盘)，IVL测试只是其中一对pad，因版图Layout(布置)限制，没有设计CP的区域。此外，在现有设计中，完成IVL测试后，需要经过一次封装、彩胶、二次封装以及CG(盖板玻璃)贴片，CP被多层有机、无机材料覆盖，无法继续通过CP上的Pin输入测试信号。此外，MIT(模组检测)只能通过将Probe Board的探针扎在FPC/PCB bonding(绑定焊盘)上的5个用来实现正常显示的pad进行测试的。
本示例实施方式中首先提供了一种显示面板，如图1-图7所示，该显示面板10包括：硅基衬底20、驱动层30、第一电极层、有机发光层60、第二电极层70、多个焊盘。硅基衬底20包括显示区与围绕显示区的外围区；驱动层30形成于硅基衬底20中，且包括位于显示区的多个 第一晶体管；第一电极层设于驱动层30背离硅基衬底20的一侧，且包括位于显示区的多个第一电极40，各第一电极40与各第一晶体管电连接；有机发光层60设于第一电极层背离驱动层30的一侧；第二电极层70设于有机发光层60背离驱动层30的一侧，且包括位于显示区的第二电极720和位于外围区的电极环710，电极环710绕第二电极720且与第二电极720连接；多个焊盘位于显示区至少一侧的外围区，多个焊盘包括显示信号接入焊盘和测试信号接入焊盘，测试信号接入焊盘位于显示信号接入焊盘的两侧。
其中，显示信号接入焊盘被配置为在显示阶段接入显示信号，测试信号接入焊盘被配置为在测试阶段接入测试信号，测试信号接入焊盘至少包括第一组测试阶段接入焊盘，第一组测试阶段接入焊盘包括第一焊盘和第二焊盘，第一焊盘与电极环电连接，第二焊盘与硅基衬底电连接。
示例的，在显示面板进行IVL测试时，第二焊盘52接入VDD(+5V直流电压)测试信号、第一焊盘51接入Vcom(-2.5V直流电压)测试信号，其中VDD通过走线连接到各第一晶体管对应的硅基衬底区域，通过正向偏置使PN结导通，从而使VDD测试信号给到第一电极40；同时，Vcom通过电极环710将测试信号给到第二电极720，从而使第一电极40与第二电极720之间形成压差，进而点亮像素单元，以进行IVL测试并收集测试数据，实现ILV测试的目的。
本公开提供的显示面板，通过第一焊盘51与电极环710连接，进而实现与第二电极720的连接；各第一电极40均连接有第一晶体管，各第一晶体管对应的硅基衬底均连接第二焊盘52；通过第一焊盘51及第二焊盘52输入测试信号，使第一电极40与第二电极720之间形成压差，从而点亮像素单元，进行IVL测试并收集测试数据，实现ILV测试的目的。此外，进行ILV测试时，仅需给第一焊盘51及第二焊盘52输入测试信号即可，第一焊盘51及第二焊盘52设于硅基衬底20上的外围区，占用空间较小，可满足微型化硅基显示面板的设计。
具体地，如图4所示，硅基衬底20构成硅基OLED显示面板，本公开实施例提供的为顶发射型硅基OLED显示面板，图中C1所指的为第 一晶体管，各第一晶体管包括形成于硅基衬底中的有源区380、位于有源区380的两个掺杂区、位于两个掺杂区之间的沟道区以及位于沟道区上的栅极320，两个掺杂区分别形成第一极310与第二极330，第二焊盘52与各第一晶体管的有源区380电连接。
示例的，第一晶体管为P型MOS管，有源区380为N型掺杂区，第一极310与第二极320为硅基衬底上的P型掺杂区，第一晶体管的第二极330为漏极，第一极310为源极。各第一晶体管对应的硅基衬底即为该第一晶体管的有源区380，通过第二焊盘52给第一晶体管的有源区380接入VDD测试信号，通过正向偏置使PN结导通，从而使VDD测试信号给到阳极。其中，电极环710为阴极环，阴极环为显示区外围的提供阴极公共电压(负)的环型走线，阴极蒸镀时覆盖显示区且搭接在阴极环上，从而为整个显示区的公共阴极提供负压。
示例的，如图4所示，第一晶体管的漏极通过第二导电层350和第一导电层340与第一电极40连接，通过第二导电层350和第一导电层340的设置，能够减少布线面积，提高分辨率。其中，第一电极40与第二导电层350之间，第二导电层350与第一导电层340之间，第一导电层340与第二极330、栅极320及第一极310之间，分别通过接触孔360电连接。可选地，接触孔360为钨孔。
具体地，图4中C2所指的为与电极环710电连接的第二晶体管，第二晶体管形成于硅基衬底的外围区中，包括形成于硅基衬底中的有源区、位于有源区的两个掺杂区、位于两个掺杂区之间的沟道区以及位于沟道区上的栅极393，两个掺杂区分别形成第一极391与第二极392。如图7所示，第二晶体管的第二极392与电极环710电连接，第一焊盘51与第二晶体管的第一极391及栅极393电连接。通过第一焊盘51与第二晶体管的第一极391及栅极393电连接，从而实现将Vcom通过电极环710传输至第二电极720，从而使第一电极40与第二电极720之间形成压差，进而点亮像素单元，以进行IVL测试并收集测试数据，实现ILV测试的目的。其中，第一极391可为源极，第二极392可为漏极。
示例的，第一焊盘51还可通过导线与电极环710电连接，从而实现 将Vcom通过电极环710传输至第二电极720，使第一电极40与第二电极720之间形成压差，进而点亮像素单元，以进行IVL测试并收集测试数据，实现ILV测试的目的。此外，通过导线直接将第一焊盘51与电极环710电连接，降低了工艺难度。
如图4所示，测试信号接入焊盘还包括第二组测试阶段接入焊盘，第二组测试阶段接入焊盘包括第三焊盘53和第四焊盘54，第三焊盘53与电极环710电连接，第四焊盘54与硅基衬底电连接。本公开提供的显示面板，第三焊盘53与第四焊盘54位于外围区且能够从显示面板的封装层露出，显示面板进行MIT测试只需第三焊盘53与第四焊盘54即可，减少了MIT测试所需的pin角，进而减少所需探针，降低了成本。
具体地，硅基衬底的外围区包括绑定区域，第三焊盘53、第四焊盘54及多个显示信号接入焊盘位于绑定区域内，显示信号接入焊盘即为绑定焊盘(Bonding Pad)41。由于显示面板在封装工艺过程中多层有机、无机材料覆盖会将第一焊盘51与第二焊盘52覆盖，封装后无法通过第一焊盘51与第二焊盘52进行MIT测试。因此，可在绑定区域同时形成第三焊盘53、第四焊盘54及多个显示信号接入焊盘，第三焊盘53与第四焊盘54要同其它绑定焊盘41做光刻胶层，后续再通过激光烧蚀，将光刻胶层连同蒸镀、封装过程的有机、无机材料一起烧蚀干净，使各焊盘表面金属露出，满足MIT测试探针卡的扎针需要。其中，第三焊盘53与电极环710电连接，第四焊盘54与硅基衬底电连接，从而通过第三焊盘53与第四焊盘54进行MIT测试。
如图1-图3所示，第三焊盘53和第四焊盘54分别与显示信号接入焊盘相邻设置。多个绑定焊盘41设于硅基衬底20一侧的绑定区上，各绑定焊盘41位于第三焊盘53与第四焊盘54之间。将第三焊盘53与第四焊盘54设于绑定区且位于绑定焊盘41的两端，不会对绑定焊盘41的布设造成影响，第三焊盘53与第四焊盘54可与绑定焊盘41通过同一次激光烧蚀工艺露出，降低了工艺难度与工艺成本。
如图1所示，第一焊盘51、第二焊盘52、第三焊盘53及第四焊盘54位于绑定焊盘41与FPC Mark(柔性线路板基准点)之间，Mark为 FPC柔性线路板装配工艺中的所有步骤提供共同的可定位电路图案。其中，第一焊盘51与第三焊盘53位于显示信号接入焊盘的同一侧，第二焊盘52与第四焊盘54位于显示信号接入焊盘的另一侧。
具体地，如图1所示，显示面板仅设有一个第一焊盘51与一个第二焊盘52，第二焊盘52与各MOS晶体管的有源区电连接。仅通过两个焊盘即可实现IVL测试，使得焊盘的数量达到最少，便于第一焊盘51与第二焊盘52在硅基衬底20上的布置。
具体地，如图1所示，显示面板10仅设有一个第三焊盘53与一个第四焊盘54，第四焊盘54与各MOS晶体管的有源区电连接。仅通过两个焊盘即可实现MIT测试，使得焊盘的数量达到最少，便于第三焊盘53与第四焊盘54在硅基衬底20上的布置。
具体地，第三焊盘53与第一焊盘51连接。如图2所示，第三焊盘53与第一焊盘51可位于硅基衬底20的同一侧，第一焊盘51通过导线与电极环710连接后，第三焊盘53可通过导线与第一焊盘51连接，从而间接与电极环710连接，能够减少连接电极环710的导线，从而降低了显示面板10的制造工艺难度。
具体地，第四焊盘54与第二焊盘52连接。如图3所示，第四焊盘54与第二焊盘52可位于硅基衬底20的同一侧，第二焊盘52通过导线与各第一电极40连接后，第四焊盘54可通过导线与第二焊盘52连接，从而间接与各第一电极40连接，能够减少连接各第一电极40的导线，从而降低了显示面板10的制造工艺难度。
具体地，如图4所示，第一焊盘51、第二焊盘52、第三焊盘53、第四焊盘54与第一电极40同层设置。通过使第一焊盘51、第二焊盘52、第三焊盘53、第四焊盘54与第一电极40位于同一层，可通过同一次工艺形成第一焊盘51、第二焊盘52、第三焊盘53、第四焊盘54与第一电极40，便于第一焊盘51、第二焊盘52、第三焊盘53、第四焊盘54的形成，降低了显示面板10的制造工艺难度。
具体地，如图6所示，驱动层30还包括：连接线381和多个检测线382。连接线381与第二焊盘52及第四焊盘54电连接；多个检测线382 与连接线381连接，且每个检测线382与一列第一晶体管的有源区分别电连接。其中，多个检测线382呈网状走线，能够减少Loading(加载)的影响。
具体地，驱动层30包括：栅绝缘层370、栅极层、第一平坦层、第一导电层340、介质层、第二导电层350和第二平坦层。栅绝缘层370设于硅基衬底20的一侧；栅极层设于栅绝缘层370背离硅基衬底20的一侧；第一平坦层设于硅基衬底20的一侧并覆盖栅绝缘层370与栅极层；第一导电层340设于第一平坦层背离硅基衬底20的一侧；介质层设于第一平坦层背离硅基衬底20的一侧并覆盖第一导电层340；第二导电层350设于介质层背离硅基衬底20的一侧；第二平坦层设于介质层背离硅基衬底20的一侧并覆盖第二导电层350，第一电极层位于第二平坦层背离硅基衬底20的一侧。其中，连接线381和各检测线382可与第一导电层340同层设置。当然，也可连接线381与各检测线382分层设置，各检测线382与第一导电层340同层设置；或者，连接线381、各检测线382与第一导电层340分别分层设置，本公开对此不作限制。
具体地，如图4所示，显示面板还包括像素定义层(PDL)42，像素定义层42形成有多个开孔，各第一电极40一一对应设于各开孔中。此外，用于连接第二晶体管与电极环710的电极与相邻的第一电极40之间设有PDL，以将该电极与相邻的第一电极40绝缘。
示例的，本公开提供的硅基OLED显示面板可为白光OLED显示面板，有机发光层60包括依次层叠的红光发光层、绿光发光层和蓝光发光层。当然，红光发光层、绿光发光层和蓝光发光层的层叠顺序可进行变换。
具体地，如图5所示，显示面板10还包括第一封装层81、彩膜层90与第二封装层82。第三焊盘53与第四焊盘54上设有光刻胶层，后续再通过激光烧蚀，将光刻胶层连同第一封装层81、彩膜层90与第二封装层82一起烧净，使第三焊盘53与第四焊盘54的表面露出，满足MIT测试探针卡的扎针需要。
具体地，显示面板10还包括盖板玻璃(图中未示出)，盖板玻璃设 于第二封装层82远离彩膜层90的一侧。
本公开的实施例还提供了一种显示装置，该显示装置包括上述的显示面板。显示装置的有益效果可参考上述显示面板的有益效果，在此处不再赘述。显示装置例如可为VR/AR等头戴显示设备。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种显示面板，其中，包括：
    硅基衬底，包括显示区与围绕所述显示区的外围区；
    驱动层，形成于所述硅基衬底中，且包括位于所述显示区的多个第一晶体管；
    第一电极层，设于所述驱动层背离所述硅基衬底的一侧，且包括位于所述显示区的多个第一电极，各所述第一电极与各所述第一晶体管电连接；
    有机发光层，设于所述第一电极层背离所述驱动层的一侧；
    第二电极层，设于有机发光层背离所述驱动层的一侧，且包括位于显示区的第二电极和位于外围区的电极环，所述电极环围绕所述第二电极且与所述第二电极连接；
    多个焊盘，位于所述显示区至少一侧的所述外围区，所述多个焊盘包括显示信号接入焊盘和测试信号接入焊盘，所述测试信号接入焊盘位于所述显示信号接入焊盘的两侧；
    其中，所述显示信号接入焊盘被配置为在显示阶段接入显示信号，所述测试信号接入焊盘被配置为在测试阶段接入测试信号，所述测试信号接入焊盘至少包括第一组测试阶段接入焊盘，所述第一组测试阶段接入焊盘包括第一焊盘和第二焊盘，所述第一焊盘与所述电极环电连接，所述第二焊盘与所述硅基衬底电连接。
  2. 根据权利要求1所述的显示面板，其中，各所述第一晶体管包括形成于所述硅基衬底中的有源区、位于所述有源区的两个掺杂区、位于两个所述掺杂区之间的沟道区以及位于所述沟道区上的栅极，两个所述掺杂区分别形成第一极与第二极，所述第二焊盘与各所述第一晶体管的有源区电连接。
  3. 根据权利要求1或2所述的显示面板，其中，所述测试信号接入焊盘还包括第二组测试阶段接入焊盘，所述第二组测试阶段接入焊盘包 括第三焊盘和第四焊盘，所述第三焊盘与所述电极环电连接，所述第四焊盘与所述硅基衬底电连接。
  4. 根据权利要求3所述的显示面板，其中，所述外围区包括绑定区域，所述第三焊盘、所述第四焊盘及所述多个显示信号接入焊盘位于所述绑定区域内。
  5. 根据权利要求3或4所述的显示面板，其中，所述第一焊盘与所述第三焊盘位于所述显示信号接入焊盘的同一侧，所述第二焊盘与所述第四焊盘位于所述显示信号接入焊盘的另一侧。
  6. 根据权利要求3-5任一项所述的显示面板，其中，所述第三焊盘和所述第四焊盘分别与所述显示信号接入焊盘相邻设置。
  7. 根据权利要求3-6任一项所述的显示面板，其中，所述显示面板设有一个所述第一焊盘和一个所述第二焊盘。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板设有一个所述第三焊盘和一个所述第四焊盘。
  9. 根据权利要求8所述的显示面板，其中，所述第三焊盘与所述第一焊盘连接，所述第四焊盘与所述第二焊盘连接。
  10. 根据权利要求1-9任一项所述的显示面板，其中，所述测试信号接入焊盘与所述第一电极同层设置。
  11. 根据权利要求3-10任一项所述的显示面板，其中，所述驱动层还包括：
    连接线，与所述第二焊盘及所述第四焊盘电连接；
    多个检测线，与所述连接线连接，且每个所述检测线与一列所述晶体管的有源区分别电连接。
  12. 根据权利要求3-11任一项所述的显示面板，其中，所述第一焊盘通过导线与所述电极环电连接。
  13. 根据权利要求3-11任一项所述的显示面板，其中，所述显示面板还包括：
    第二晶体管，形成于所述硅基衬底的外围区中，且包括形成于所述硅基衬底中的有源区、位于所述有源区的两个掺杂区、位于两个所述掺杂区之间的沟道区以及位于所述沟道区上的栅极，两个所述掺杂区分别形成第一极与第二极；所述第二晶体管的第二极与所述电极环电连接，所述第一焊盘与所述第二晶体管的第一极及栅极电连接。
  14. 根据权利要求2所述的显示面板，其中，所述驱动层包括：
    栅绝缘层，设于所述硅基衬底一侧的所述沟道区上；
    栅极层，设于所述栅绝缘层背离所述硅基衬底的一侧；
    第一平坦层，设于所述硅基衬底的一侧并覆盖所述栅绝缘层与所述栅极层；
    第一导电层，设于所述第一平坦层背离所述硅基衬底的一侧；
    介质层，设于所述第一平坦层背离所述硅基衬底的一侧并覆盖所述第一导电层；
    第二导电层，设于所述介质层背离所述硅基衬底的一侧；
    第二平坦层，设于所述介质层背离所述硅基衬底的一侧并覆盖所述第二导电层，所述第一电极层位于第二平坦层背离所述硅基衬底的一侧。
  15. 根据权利要求3-14任一项所述的显示面板，其中，所述显示面板还包括：
    第一封装层，设于所述第二电极层远离所述有机发光层的一侧；
    彩膜层，设于所述第一封装层远离所述第二电极层的一侧；
    第二封装层，设于所述彩膜层远离所述第一封装层的一侧，所述第三焊盘与所述第四焊盘从所述第二封装层露出。
  16. 一种显示装置，其中，包括权利要求1-15任一项所述的显示面板。
PCT/CN2020/081858 2020-03-27 2020-03-27 显示面板及显示装置 WO2021189486A1 (zh)

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