WO2021186773A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2021186773A1
WO2021186773A1 PCT/JP2020/037993 JP2020037993W WO2021186773A1 WO 2021186773 A1 WO2021186773 A1 WO 2021186773A1 JP 2020037993 W JP2020037993 W JP 2020037993W WO 2021186773 A1 WO2021186773 A1 WO 2021186773A1
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Prior art keywords
electrode layer
layer
semiconductor device
electrode
resin layer
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PCT/JP2020/037993
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English (en)
Japanese (ja)
Inventor
悠香 杉政
一等 杉本
智康 古川
紺野　哲豊
田畑　利仁
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株式会社日立パワーデバイス
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Publication of WO2021186773A1 publication Critical patent/WO2021186773A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Definitions

  • the present invention relates to the structure of a semiconductor device, and particularly relates to a technique that is effective when applied to a power semiconductor module that requires high reliability, such as an in-vehicle inverter or an electric railway inverter.
  • Power semiconductor devices mounted on in-vehicle inverters, electric railway inverters, industrial inverters, etc. are required to have high durability and high reliability corresponding to high temperature operation in addition to withstand voltage performance and low switching loss. Since the high temperature operation allows operation at a higher temperature, the cooling mechanism such as a heat sink can be simplified, which contributes to weight reduction of the vehicle and the like.
  • Patent Document 1 describes a semiconductor device capable of maintaining an electrically and mechanically stable state of the surface electrode film of a semiconductor element even in a high temperature operation state.
  • a nickel film 3 is formed as a metal protective film on the aluminum electrode film in order to prevent an increase in electrical resistance due to deterioration of the aluminum electrode film and peeling of the aluminum wire 2.
  • Patent Document 2 describes a semiconductor device having improved reliability by suppressing the occurrence of cracks due to the stress of the electric field-free Ni plating layer.
  • a resin layer is formed so as to have a slope between the outer peripheral end faces of each of the metal layer and the electroless Ni plating layer and the passivation film, and the metal layer is arranged so as to be in contact with the passivation film. It is stated. "
  • Patent Document 3 describes a ceramic circuit board and a power module in which the yield at the time of mounting an electronic component is remarkably improved and the reliability and durability when the electronic component is used by applying a voltage are high.
  • Patent Document 3 in a ceramic circuit board in which a plurality of metal circuit boards are provided on at least one of the surfaces of a ceramic sintered body substrate, a corner shape of a corner portion of the metal circuit board and a corner portion adjacent thereto is formed. Is different.
  • Patent Document 1 does not describe the resin layer formed on the aluminum electrode, and does not mention the occurrence of cracks in the nickel film due to thermal expansion of the resin layer and the occurrence of energization failure due to the expansion of cracks. ..
  • the resin layer and the electroless Ni plating layer are in direct contact with each other, the stress of the Ni plating layer is not relaxed by the resin layer, and the Ni plating layer is cracked due to thermal expansion of the resin. It can occur.
  • Patent Document 3 does not describe measures against cracks in the electrode layer due to thermal expansion of the resin layer.
  • an object of the present invention is a semiconductor device having an electrode layer on its surface and a resin layer surrounding the outer periphery thereof, in which cracks in the electrode layer are less likely to occur due to thermal expansion of the resin layer, and the semiconductor device is excellent in reliability and durability. Is to provide.
  • the present invention presents a semiconductor element, a first electrode layer formed on the surface of the semiconductor element, and a second electrode formed on the first electrode layer and bonded to a bonding wire.
  • the resin layer is at least a part of the outer periphery of the second electrode layer.
  • the thickness between the contact point between the surface of the second electrode layer and the resin layer and the surface of the first electrode layer is the thickness at the joint portion of the bonding wire. It is characterized in that it is thinner than the thickness of the second electrode layer.
  • the present invention includes a semiconductor element, a first electrode layer formed on the surface of the semiconductor element, a second electrode layer formed on the first electrode layer and bonded to a bonding wire, and the first electrode layer.
  • the resin layer is the second electrode layer on at least a part of the outer periphery of the second electrode layer. It is characterized in that at least one corner of the second electrode layer and the resin layer when viewed from the plane direction is rounded.
  • the present invention includes a semiconductor element, a first electrode layer formed on the surface of the semiconductor element, a second electrode layer formed on the first electrode layer and bonded to a bonding wire, and the first electrode layer.
  • the resin layer is the second electrode layer on at least a part of the outer periphery of the second electrode layer.
  • the distance between the contact point between the side surface of the second electrode layer and the resin layer and the surface of the first electrode layer is from the surface of the first electrode layer at the joint portion of the bonding wire. It is characterized in that it is smaller than the distance to the surface of the second electrode layer.
  • a semiconductor device having an electrode layer and a resin layer surrounding the outer periphery thereof on the surface, cracks in the electrode layer are less likely to occur due to thermal expansion of the resin layer, and a semiconductor device having excellent reliability and durability is realized. can do.
  • FIG. 11 It is sectional drawing which shows the length measuring part for shape evaluation of the electrode structure (anode electrode) of the 1st semiconductor chip of the semiconductor device which concerns on 1st Embodiment of this invention. It is a top view which shows the structure of the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on 5th Embodiment of this invention. It is a figure which shows the modification of the 1st Embodiment (FIGS. 2 and 6). It is sectional drawing which shows the structure of the semiconductor device which concerns on 6th Embodiment of this invention. It is a figure which shows the modification of the 6th Embodiment (FIG. 11).
  • FIGS. 1 to 6 and 10 are cross-sectional views of the semiconductor device according to the present embodiment, and show a cross-sectional structure when a freewheel diode is used for the power semiconductor chip.
  • a diode using an n-type silicon (Si) substrate will be described, but the description is not limited to this. Even when a p-type Si substrate is used, it can be handled in the same manner. Further, it can be handled in the same manner in the electrode structure of the IGBT in which the current flows in the vertical direction. Further, wide-gap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO) can be handled in the same manner.
  • SiC silicon carbide
  • GaN gallium nitride
  • GaO gallium oxide
  • the semiconductor device 100 of this embodiment includes a semiconductor substrate 108 made of n-type Si.
  • the semiconductor substrate 108 includes an n + type semiconductor layer 108c composed of a p-type semiconductor layer 108a, an n-type drift layer 108b, and a high-concentration n-type impurity region in order from the surface (from the upper layer side to the lower layer side in FIG. 1).
  • the semiconductor element 150 made of these semiconductor layers is formed.
  • the semiconductor substrate 108 has a first surface 108e on which the electrode structure (anode electrode) 114 of the first semiconductor chip is formed and a second surface on which the electrode structure (cathode electrode) 113 of the second semiconductor chip is formed. It has 108d and.
  • the semiconductor device 100 is electrically connected to the semiconductor element 150 on the first surface 108e side of the semiconductor substrate 108 on which the semiconductor element 150 is formed, and is a first electrode layer (Al metal) made of aluminum (Al) or an Al alloy.
  • the second electrode layer 112 having a single layer structure of a nickel (Ni) or nickel-phosphorus (NiP) alloy or a laminated structure containing a nickel-phosphorus (NiP) alloy is arranged in this order (lower layer side of FIG. 1) with the layer 109. It has an electrode assembly (electrode electrode) 114 of the first semiconductor chip formed from the upper layer side.
  • a part of the first electrode layer (Al metal layer) 109 is in contact with the p-type semiconductor layer 108a of the semiconductor substrate 108, and the other part is in contact with the insulating oxide film 110. Further, a resin layer 111 which is a surface protective film is formed on the insulating oxide film 110, and a part of the resin layer 111 is formed on the first electrode layer 109.
  • the resin layer 111 is made of, for example, polyimide.
  • a second electrode layer 112 is formed whose outer periphery is surrounded by a resin layer 111 and which is bonded to the bonding wire 202 (see FIG. 2) by wire bonding.
  • the thickness (distance) 204 between the contact point 201 between the surface 112a of the second electrode layer 112 and the resin layer 111 and the surface 109a of the first electrode layer 109 is wire-bonded. It is configured to be thinner (smaller in distance) than the thickness 203 of the second electrode layer 112 in the portion. (Thickness 204 ⁇ Thickness 203)
  • the resin layer 111 presses the second electrode layer 112 by thermal expansion. Therefore, by reducing the area in contact between the resin layer 111 and the second electrode layer 112, the resin layer 111 expands. This has the effect of reducing the stress applied to the second electrode layer 112 and suppressing the occurrence of cracks.
  • the area in contact between the resin layer 111 and the second electrode layer 112 can be reduced by reducing the thickness of the interface between the resin layer 111 and the second electrode layer 112.
  • the thickness of the interface between the second electrode layer 112 and the resin layer 111 is thicker than 0% of the thickness of the second electrode layer 112 at the wire bonding portion and 80% or less of the thickness of the second electrode layer 112. Is desirable.
  • securing a space for escaping the volume expansion due to heat of the resin layer 111 also has the effect of reducing the stress applied to the second electrode layer 112 and suppressing cracks. It is desirable that the width from the end of the resin layer 111 surrounding the outer periphery of the second electrode layer 112 to the outermost outer peripheral portion of the second electrode layer 112 having the same thickness as the wire bonding portion is 1 ⁇ m or more. This width can be effective if it has a size that allows volume expansion to escape, but if it is too large, the area of the wire bonding portion will be narrowed, so the upper limit should be 50 ⁇ m or less. Is desirable, and more preferably 15 ⁇ m or less. By reducing the thickness of the interface and securing a wide width, a larger space (groove) can be secured at the interface between the resin layer 111 and the second electrode layer 112, so that the effect of crack reduction is enhanced.
  • an Al metal layer 106a made of Al or an Al alloy, a copper (Cu) diffusion prevention layer 107, an Al metal layer 106b made of Al or an Al alloy, and a Ni layer 104 are formed therein.
  • the electrode structure (cathode electrode) 113 of the second semiconductor chip formed in order (from the upper layer side to the lower layer side in FIG. 1) and the surface 104a of the Ni layer 104 are arranged via the copper sintered layer 103.
  • a conductive member 102 bonded to an electrode structure (cathode electrode) 113 of the second semiconductor chip is provided.
  • the electrode structure (cathode electrode) 113 of the second semiconductor chip is joined to the conductive member 102 on the ceramic insulating substrate 101 by using the copper sintered layer 103.
  • the semiconductor device 100 includes a semiconductor substrate 108, an electrode structure (anode electrode) 114 of the first semiconductor chip, and a resin layer 111.
  • FIGS. 3 and 4 are cross-sectional views showing each step of the manufacturing method of the semiconductor device 100.
  • FIG. 3A is a cross-sectional view of the present embodiment after forming the anode P-type semiconductor region.
  • a Si wafer (Si substrate) 90 for manufacturing a diode is prepared.
  • a wafer having a specific resistance corresponding to the withstand voltage can be used.
  • a diode having a withstand voltage of 1700 V can have a withstand voltage of about 120 ⁇ cm
  • a diode having a withstand voltage of 3.3 kV can have a withstand voltage of about 250 ⁇ cm.
  • the Si wafer 90 has a high specific resistance and plays the role of an n ⁇ layer.
  • the Si wafer 90 on which the p-type semiconductor layer 108a is formed is also referred to as an n-drift layer 108b.
  • a silicon oxide film is formed on the entire surface of the Si wafer 90 by thermal oxidation.
  • a photolithography step for forming a region for providing the p-type semiconductor layer 108a is performed.
  • a resist material is applied to the surface of the Si wafer 90, and then exposed and developed to form a resist pattern (mask) in which the p-type semiconductor layer 108a region is open.
  • p-type impurities are ion-implanted. Examples of the p-type impurity include boron.
  • the p-type semiconductor layer 108a is formed as shown in FIG. 3A.
  • FIG. 3B is a cross-sectional view after forming the contact portion in the present embodiment
  • FIG. 3C is a cross-sectional view after forming the anode electrode.
  • an insulating oxide film 110 is deposited on the surface (main surface) of the Si wafer 90 by thermal oxidation to form a silicon oxide film (not shown) and chemical vapor deposition (CVD) method, and p.
  • a photolithography step is performed to form a contact portion connecting the type semiconductor layer 108a and the first electrode layer 109 (see FIG. 3C).
  • the insulating oxide film 110 is etched using the resist pattern formed by exposure and development as a mask, so that the p-type semiconductor is shown in FIG. 3 (b).
  • a contact portion connecting the layer 108a and the first electrode layer 109 is formed.
  • the first electrode layer 109 made of Al or an Al alloy is formed by a sputtering method, and the resist is patterned and etched by a photolithography step to obtain the first electrode layer as shown in FIG. 3C. 109 is formed.
  • the resin layer 111 (see FIG. 4), which is a surface protective film, is formed.
  • a method for forming the surface protective film for example, a solution containing a precursor material and a photosensitive material of a polyimide resin is applied, and a termination region is exposed to make the precursor polyimide, thereby forming a resin layer (surface protective film). ) 111 can be formed.
  • FIG. 4A is a cross-sectional view of the front surface protective film and the back surface n + type semiconductor layer formed in the present embodiment.
  • the back surface of the n-type drift layer 108b is ground to reduce the wafer thickness.
  • the wafer thickness varies depending on the withstand voltage, and is, for example, about 190 ⁇ m for the 1700 V withstand voltage product and about 400 ⁇ m for the 3300 V withstand voltage product.
  • n-type impurities are performed on the entire surface of the wafer from the back surface side of the n-type drift layer 108b.
  • n-type impurity include phosphorus (P) and arsenic (As).
  • n + -type semiconductor layer 108c is formed.
  • FIG. 4B shows the formation of an Al metal layer 106a made of Al or an Al alloy, a copper (Cu) diffusion prevention layer 107, and an Al metal layer 106b made of Al or an Al alloy among the cathode electrodes 113 on the back surface in the present embodiment. It is a later sectional view.
  • the Al metal layer 106a, the copper (Cu) diffusion prevention layer 107, and the Al metal layer 106b are formed by sputtering the Al metal layer 106a with, for example, an AlSi alloy of 0.6 ⁇ m, and the copper (Cu) diffusion prevention layer 107 with, for example, titanium (Ti). It is formed by forming a 0.2 ⁇ m Al metal layer 106b with, for example, an AlSi alloy in the order of 2 ⁇ m.
  • a copper (Cu) diffusion prevention layer 107 made of titanium (Ti) is provided in the cathode electrode 113 on the back surface, and the bonding layer made of a copper sintered layer 103 described later is used to electrically connect to the connection terminal.
  • copper is prevented from diffusing from this bonding layer to the first semiconductor chip (p-type semiconductor layer 108a, n-type drift layer 108b, n + type semiconductor layer 108c), and long-term bonding reliability is improved.
  • titanium (Ti) is used for the copper (Cu) diffusion prevention layer 107.
  • titanium nitride (TiN) capable of forming a copper (Cu) diffusion prevention layer while maintaining conductivity.
  • TiW Titanium Tungsten
  • W Tungsten
  • FIG. 4C is a cross-sectional view after forming the second electrode layer 112 and the Ni layer 104 in the present embodiment.
  • the second electrode layer 112 and the Ni layer 104 are formed on both sides at the same time by an electroless plating method.
  • FIG. 5 shows the process flow of electroless Ni plating.
  • similar electrode structures electrode structure 114 of the first semiconductor chip and electrode structure 113 of the second semiconductor chip
  • the front and back surfaces of the Si wafer 90 are used. Since the electrode film having good symmetry is formed, the wafer warpage due to the stress of the electrode film can be reduced, and the manufacturability can be improved.
  • a surface protective tape is attached to the cathode electrode 113 side for electroless Ni plating. I do.
  • a surface protective tape is attached to the first electrode layer 109 side to perform electroless Ni plating.
  • the oil adhering to the surfaces of the first electrode layer 109 and the Al metal layer 106b is cleaned with an alkaline degreasing agent.
  • Step 1 Next, the surfaces of the first electrode layer 109 and the Al metal layer 106b are etched with a strong alkaline solution based on sodium hydroxide (NaOH) to remove the oxide film.
  • Step 2 Next, Al (OH) 3 and impurities generated when the oxide film is removed are removed by acid cleaning.
  • a zincate treatment for coating zinc (Zn) is performed so that Ni can be quickly replaced in the plating solution.
  • Step 4 Here, in the electroless plating step shown in FIG.
  • Step 5 since the first electrode layer 109 and the Al metal layer 106b, which are the base electrodes, easily form an oxide film, the purpose is to improve the adhesion with the Ni plating film.
  • a double zincate treatment is performed in which zinc (Zn) substitution is repeated twice.
  • Steps 5 and 6 Next, a Ni film of, for example, 3 ⁇ m is formed by electroless Ni plating.
  • Step 7) In the reaction of field-free Ni plating, hypophosphate, which is a reducing agent, is oxidized to phosphite. At this time, the plating proceeds by the following reaction that emits electrons and reduces Ni ions to form Ni (plating film).
  • the electroless Ni-plated films 104 and 112 contain phosphorus (P), and films having different properties can be obtained depending on the difference in P content.
  • a low phosphorus (P) type NiP plating bath Top UBP Nicolon MLP manufactured by Okuno Pharmaceutical Industry Co., Ltd. was used.
  • the contact 201 between the surface 112a of the second electrode layer 112 and the resin layer 111 and the contact 201 is formed to be thinner than the thickness 203 of the second electrode layer 112 at the bonding wire 202 junction.
  • the film forming method of the second electrode layer 112 and the Ni layer 104 may be a method other than the above-mentioned plating, and for example, a vapor deposition method or a sputtering method may be used.
  • the thickness 204 between the contact point 201 between the surface 112a of the second electrode layer 112 and the resin layer 111 and the surface 109a of the first electrode layer 109 is the thickness of the second electrode layer 112 at the wire 202 junction.
  • a method of forming the wire thinner than 203 a method of patterning the resist by a photolithography step and removing the resist after etching may be used.
  • the thickness of the second electrode layer 112 is 1 ⁇ m to 10 ⁇ m for the purpose of protecting the first electrode layer 109 during wire bonding.
  • the second electrode layer 112 may have a single layer structure of copper (Cu) or a multilayer structure containing copper (Cu) in order to reduce the electrical resistance of the second electrode layer 112.
  • the structure contains copper (Cu)
  • the semiconductor device 100 mounted on the power module which is a main component of a power converter such as an inverter, is a bonding agent using cupric oxide (CuO) particles, and is a conductive member 102 (for example, Cu) and a cathode electrode 113 on the back surface of the chip.
  • the power semiconductor chip is mounted on the ceramic insulating substrate 101 on which the wiring layer is formed by the conductive member 102.
  • multi-step heating and pressurization are performed in a reducing atmosphere.
  • a heat load of, for example, 350 ° C. is applied to the power semiconductor chip.
  • Table 1 shows the shape of the second electrode layer 112 after film formation and the crack number evaluation results after heat treatment, which were examined by the inventors of the present application.
  • the heat treatment temperature was 370 ° C. in consideration of the process margin.
  • the shape of the second electrode layer 112 was measured and evaluated by a scanning electron microscope using a cross-sectional observation sample prepared by cutting the semiconductor device 100 after embedding it in a resin and polishing the exposed cross section with an ion milling device.
  • the measured position is shown in Fig. 6.
  • the thickness 204 between the contact point 201 between the surface 112a of the second electrode layer 112 and the resin layer 111 and the surface 109a of the first electrode layer 109 is T1
  • the second electrode layer 112 at the wire bonding portion is T1
  • the thickness 203 is defined as T2
  • the width from the end of the resin layer 111 surrounding the outer periphery of the second electrode layer 112 to the outermost peripheral portion of the second electrode layer 112 which is the same thickness as the wire bonding portion T2 is defined as W1.
  • Comparative Example 1 with a crack occurrence rate of 100% is designated as “x”, a crack occurrence rate of 5% or less is designated as “ ⁇ ”, and a crack occurrence rate of more than 5% is marked with “ ⁇ ” based on the crack occurrence rate of 5%.
  • the crack occurrence rate was 17.6% in the form of the semiconductor device (No. 1 of the example) assumed in this embodiment.
  • a space having a width W1 and a height T2-T1 is formed between the resin layer 111 and the second electrode layer 112, so that the resin layer 111 undergoes thermal expansion during heat treatment. It is considered that the effect of reducing the pressure on the two-electrode layer 112 was obtained.
  • roundness is formed at the corners of the second electrode layer 112 when viewed from the cross-sectional direction. It is considered that this roundness also has the effect of reducing the crack occurrence rate by diffusing the internal stress concentrated on the corners of the second electrode layer 112 and eliminating the starting point of crack occurrence.
  • the width to the position of the second electrode layer 112 having the same thickness as (203) is shown only up to 15 ⁇ m, which is a more desirable range in Table 1, but as described above, it may be 1 ⁇ m or more, and 1 ⁇ m or more. It is desirable that it is 50 ⁇ m or less.
  • the corner portion in the second electrode layer 112 viewed from the cross-sectional direction, it is desirable to form the corner portion at a position away from the resin layer 111 so as to have an angle of 90 ° ⁇ 30 ° or 270 ° ⁇ 30 °. Further, as described above, it is more desirable that the corners are rounded.
  • a resin layer 111 is formed on the surface of the semiconductor element 150, and an electrode layer (second electrode layer 112) whose outer periphery is surrounded by the resin layer 111.
  • the thickness T1 between the contact point 201 between the surface 112a of the second electrode layer 112 and the resin layer 111 and the surface 109a of the first electrode layer 109 is set to the second at the wire joint.
  • FIG. 10 shows a modified example of the present embodiment (FIGS. 2 and 6).
  • 2 and 6 show an example in which a groove-like space having a width W1 and a height T2-T1 is provided between the resin layer 111 and the second electrode layer 112, but as shown in FIG. 10, the second The same effect can be obtained even when a substantially triangular space is formed between the resin layer 111 and the second electrode layer 112 when the end portion of the electrode layer 112 is inclined and viewed from the cross-sectional direction. be able to.
  • the corner portion of the second electrode layer 112 when the semiconductor device 100 is viewed from the plane (upper surface) direction has a radius of curvature.
  • a semiconductor device was produced and evaluated in the same manner as in the first embodiment (FIGS. 2 and 6).
  • the radius of curvature is R1
  • Table 1 shows the shape of the second electrode layer 112 after film formation, the value of the radius of curvature R1, and the evaluation results.
  • the resin layer 111 thermally expands by providing the radius of curvature R1 at the corners of the second electrode layer 112 when viewed from the plane direction.
  • the change in the resin shape does not concentrate on the corners of the second electrode layer 112, and the width W1 and the height T2-T1 are between the resin layer 111 and the second electrode layer 112 described in the first embodiment.
  • the value of the radius of curvature R1 is effective from 50 ⁇ m or more, but more preferably 150 ⁇ m or more, and preferably 50 ⁇ m or more and 300 ⁇ m or less.
  • Example No. No. 5 to No. In No. 7 the crack occurrence rate was 0% to 8.8%. As a result, it was found that cracks can be reduced even if the corner portion of the second electrode layer 112 viewed from the plane (upper surface) direction has a radius of curvature R1.
  • FIG. 8 is a cross-sectional view of the semiconductor device 100 of FIG. 1 after wire bonding.
  • the semiconductor device 100 of this embodiment is an example in which a freewheel diode is applied to a power semiconductor chip as in the first embodiment.
  • the electrode structure 114 of the first semiconductor chip is connected to the conductive member 102 on the ceramic insulating substrate 101 by the bonding wire 202. That is, the electrode structure 114 of the first semiconductor chip is a bonding pad (pad electrode) to which the bonding wire 202 is bonded.
  • the effect of reducing cracks in the manufacturing process before wire bonding has been described, but according to the configuration of the first to third embodiments, as in the fourth embodiment.
  • the cracks generated by the expansion of the resin layer due to the heat generated during wire bonding and the heat generated when the power module is operated after wire bonding can be prevented as in the first to third embodiments.
  • FIG. 9 is a cross-sectional view of the semiconductor device 300 according to the present embodiment.
  • the semiconductor device 300 of this embodiment is an example in which a freewheel diode is applied to a power semiconductor chip as in the first embodiment.
  • the semiconductor device 300 of the present embodiment has an Al metal layer 106a made of Al or an Al alloy and copper (Cu) diffusion prevention on the first surface 108e of the semiconductor substrate 108 on which the semiconductor element 150 is formed.
  • the layer 107, the Al metal layer 106b made of Al or an Al alloy, and the second electrode layer 112 are formed in this order (from the lower layer side to the upper layer side in FIG. 8).
  • the Al metal layer 106a, the copper (Cu) diffusion prevention layer 107, the Al metal layer 106b, and the second electrode layer 112 constitute an electrode structure (anode electrode) 301 of the third semiconductor chip.
  • the second electrode layer 112 of the electrode structure (anode electrode) 301 of the third semiconductor chip was bonded to the electrode structure 301 of the third semiconductor chip via the copper sintered layer 103.
  • a conductive member 102 is further provided, and the second electrode layer 112 is electroless, similarly to the Ni layer 104 of the electrode structure (node electrode) 113 of the second semiconductor chip on the second surface 108d side of the semiconductor substrate 108. It is a Ni plating layer.
  • the second electrode layer 112 may be a single layer containing copper (Cu).
  • the film forming method includes, for example, an electroless plating method, a sputtering method, and a thin film deposition method.
  • the film forming step is the same as the electroless Ni plating step of FIG. 5, from the cleaner treatment to the double zincate treatment, and then the electroless Cu plating treatment using the electroless Cu plating solution is carried out. do.
  • the electrode structure (cathode electrode) 113 of the second semiconductor chip and the electrode structure (electrode electrode) 301 of the third semiconductor chip are formed on both surfaces of the semiconductor substrate 108.
  • the conductive member 102 is formed and is joined to the electrode structure (cathode electrode) 113 of the second semiconductor chip and the electrode structure (electrode electrode) 301 of the third semiconductor chip via the copper sintered layer 103.
  • the electrode structure 113 of the second semiconductor chip and the electrode structure 301 of the third semiconductor chip are arranged vertically symmetrically with the semiconductor substrate 108 (semiconductor element 150) interposed therebetween.
  • the film thickness of each film constituting the electrode structure 113 is formed to be the same as the film thickness of each film constituting the electrode structure 301 of the third semiconductor chip which is symmetrical.
  • the electrode structure 301 of the third semiconductor chip is manufactured through the same steps as the manufacturing step of the electrode structure 113 of the second semiconductor chip described with reference to FIGS. 3 and 4 of the first embodiment.
  • the second electrode layer 112 is the electrode structure of the first semiconductor chip described with reference to FIGS. 3 and 4 of the first embodiment. It may be manufactured through the manufacturing step of 114 and the same steps as in the third embodiment.
  • a similar electrode structure (electrode structure 112 of the first semiconductor chip) is provided on both sides of the semiconductor substrate 108.
  • the electrode structure 301) of the third semiconductor chip are provided, and electrode films with good symmetry are formed on the front and back surfaces of the Si wafer 90, which is caused by the difference in thermal expansion of each member that becomes remarkable in a high temperature environment.
  • the thermal stress to be generated can be reduced.
  • the thermal stress generated in the copper sintered layer 103 is minimized, and long-term reliability is improved.
  • FIG. 11 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and is a modification of the first embodiment (FIGS. 2 and 10). Further, FIG. 12 is still another modified example of FIG.
  • the resin layer 111 and the second are viewed from the cross-sectional direction by providing an inclination or a step at the end on the second electrode layer 112 side.
  • a groove-shaped or substantially triangular space is formed between the electrode layers 112, but in the present embodiment, as shown in FIGS. 11 and 12, the surface is inclined toward the end of the resin layer 111, which is a surface protective film.
  • a substantially triangular or groove-shaped space is formed between the resin layer 111 and the second electrode layer 112 when viewed from the cross-sectional direction.
  • the resin layer 111 is in contact with the second electrode layer 112 at least a part of the outer circumference (side surface) of the second electrode layer 112, and the side surface 112b of the second electrode layer 112 and the resin layer.
  • the distance 204 between the contact 201 with the 111 and the surface 109a of the first electrode layer 109 is the distance from the surface 109a of the first electrode layer 109 to the surface 112a of the second electrode layer 112 at the joint portion of the bonding wire 202. It is configured to be smaller than 203.
  • the resin layer 111 viewed from the cross-sectional direction is inclined from the contact point 201 between the side surface 112b of the second electrode layer 112 and the resin layer 111 toward the direction away from the second electrode layer 112. There is.
  • the resin layer 111 is formed so that the thickness 204 of the resin layer 111 at the contact portion with the second electrode layer 112 when viewed from the cross-sectional direction is thinner than the thickness of the other portion of the resin layer 111.
  • a step is formed in.
  • the thickness (distance) 204 between the contact point 201 between the side surface 112b of the second electrode layer 112 and the resin layer 111 and the surface 109a of the first electrode layer 109 is the thickness of the second electrode layer 112 at the wire bonding portion. Since the points configured to be thinner than 203 (thickness 204 ⁇ thickness 203) are the same as in each of the first to fourth embodiments, detailed description thereof will be omitted.
  • an inclined or stepped portion is provided at the end on the resin layer 111 side, and a substantially triangular or groove-shaped space is provided between the resin layer 111 and the second electrode layer 112. Even when it is formed, the same effects as those of the first, second, fourth, and fifth embodiments can be obtained.
  • Comparative Example 1 In Comparative Example 1, the second electrode layer 112 was formed without using the additive in the electroless Ni plating used in the first embodiment, and the contact 201 between the surface 112a of the second electrode layer 112 and the resin layer 111 was formed. The same as the first embodiment except that the thickness 204 between the first electrode layer 109 and the surface 109a of the first electrode layer 109 is the same as the thickness 203 of the second electrode layer 112 at the wire 202 junction. A semiconductor device was manufactured and evaluated. Table 1 shows the shape of the second electrode layer 112 after film formation, the value of the radius of curvature R1, and the evaluation results.
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • the above examples have been described in detail to aid in understanding of the present invention, and are not necessarily limited to those having all the configurations described.
  • it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.
  • first electrode layer 110 ... Insulating oxide film, 111 ... resin layer (surface protective film), 112 ... second electrode layer (electroconducting Ni plating film), 112a ... surface of second electrode layer, 112b ... side surface of second electrode layer, 113 ... second Semiconductor chip electrode structure (cathode electrode), 114 ... First semiconductor chip electrode structure (anode electrode), 150 ... Semiconductor element, 201 ... Second electrode layer surface 112a (side surface 112b) and resin layer 111 Contact with, 202 ... Bonding wire, 203 ... Thickness of second electrode layer 112 at wire joint, 204 ... Thickness (distance) between contact 201 and surface 109a of first electrode layer, 301 ... Third Semiconductor chip electrode structure (anode electrode)

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

Il est prévu un dispositif à semi-conducteur qui comprend une couche d'électrode sur une surface du dispositif à semi-conducteur et une couche de résine entourant une périphérie externe de la couche d'électrode et qui présente une excellente fiabilité et une excellente durabilité, la formation de fissures dans la couche d'électrode due à l'expansion thermique de la couche de résine étant moins probable. Ce dispositif à semi-conducteur comprend : un élément semi-conducteur ; une première couche d'électrode qui est formée sur la surface de l'élément semi-conducteur ; une seconde couche d'électrode qui est formée sur la première couche d'électrode et qui est jointe à un fil de liaison ; et une couche de résine qui est formée sur la première couche d'électrode et qui entoure la périphérie externe de la seconde couche d'électrode. Le dispositif à semi-conducteur est caractérisé en ce que la couche de résine est en contact avec la seconde couche d'électrode dans au moins une partie de la périphérie externe de la seconde couche d'électrode et en ce que l'épaisseur entre la surface de la première couche d'électrode et un contact de la couche de résine et la surface de la seconde couche d'électrode est inférieure à l'épaisseur de la seconde couche d'électrode dans une partie de jonction du fil de liaison.
PCT/JP2020/037993 2020-03-19 2020-10-07 Dispositif à semi-conducteur WO2021186773A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399765A (en) * 1977-02-10 1978-08-31 Hitachi Ltd Semiconductor device having bonding pad
JPS63250142A (ja) * 1987-04-06 1988-10-18 Nec Corp 半導体装置
JP2003068738A (ja) * 2001-08-29 2003-03-07 Seiko Epson Corp 半導体装置及びその製造方法及び半導体チップ及びその実装方法
JP2009076703A (ja) * 2007-09-21 2009-04-09 Fuji Electric Device Technology Co Ltd 半導体装置
JP2012109325A (ja) * 2010-11-16 2012-06-07 Renesas Electronics Corp 半導体装置および半導体装置製造方法
JP2013038277A (ja) * 2011-08-09 2013-02-21 Semiconductor Components Industries Llc 半導体装置およびその製造方法
JP2018182195A (ja) * 2017-04-19 2018-11-15 トヨタ自動車株式会社 半導体装置
WO2019103028A1 (fr) * 2017-11-22 2019-05-31 三菱電機株式会社 Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5399765A (en) * 1977-02-10 1978-08-31 Hitachi Ltd Semiconductor device having bonding pad
JPS63250142A (ja) * 1987-04-06 1988-10-18 Nec Corp 半導体装置
JP2003068738A (ja) * 2001-08-29 2003-03-07 Seiko Epson Corp 半導体装置及びその製造方法及び半導体チップ及びその実装方法
JP2009076703A (ja) * 2007-09-21 2009-04-09 Fuji Electric Device Technology Co Ltd 半導体装置
JP2012109325A (ja) * 2010-11-16 2012-06-07 Renesas Electronics Corp 半導体装置および半導体装置製造方法
JP2013038277A (ja) * 2011-08-09 2013-02-21 Semiconductor Components Industries Llc 半導体装置およびその製造方法
JP2018182195A (ja) * 2017-04-19 2018-11-15 トヨタ自動車株式会社 半導体装置
WO2019103028A1 (fr) * 2017-11-22 2019-05-31 三菱電機株式会社 Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur

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