WO2021184684A1 - 超重掺红磷衬底外延方法 - Google Patents

超重掺红磷衬底外延方法 Download PDF

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WO2021184684A1
WO2021184684A1 PCT/CN2020/111366 CN2020111366W WO2021184684A1 WO 2021184684 A1 WO2021184684 A1 WO 2021184684A1 CN 2020111366 W CN2020111366 W CN 2020111366W WO 2021184684 A1 WO2021184684 A1 WO 2021184684A1
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substrate
silicon layer
intrinsic silicon
heavily doped
epitaxial
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PCT/CN2020/111366
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French (fr)
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韩少锋
顾广安
陈建纲
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上海晶盟硅材料股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

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  • the invention relates to a production method of an epitaxial wafer, in particular to an epitaxial method of a super-heavy red phosphorus-doped substrate.
  • Self-doping is due to the diffusion of by-products of thermal evaporation or chemical reaction to the substrate. Silicon and impurities in the substrate enter the gas phase, changing the doping composition and concentration in the gas phase, resulting in the actual impurity in the epitaxial layer. The phenomenon that the distribution deviates from the ideal situation.
  • the self-doping phenomenon in the epitaxy of the super heavily doped red phosphorus substrate is serious.
  • the doping composition and concentration in the weather have a greater impact on the resistivity, resulting in SRP (spreading at the edge and center of the epitaxial wafer). The difference in resistance profile is obvious.
  • Citride CN106505093A discloses a method for producing epitaxial wafers.
  • an intrinsic silicon layer (cap) is laid on the substrate, so that the resistivity uniformity of the epitaxial layer is less than 1.5% (calculation formula, ( MAX resistivity-MIN resistivity) ⁇ 100%/(MAX resistivity + MIN resistivity), the smaller the uniformity value calculated by this calculation formula, the higher the uniformity and the higher the quality of the epitaxial wafer), Thereby increasing the yield of epitaxial wafers.
  • Its working principle is to separate the substrate and the epitaxial layer by the intrinsic silicon layer, thereby avoiding the problem of self-doping between the substrate body and the epitaxial layer.
  • the thickness of the intrinsic silicon layer is positively related to the thickness of the substrate body .
  • this isolation method can only solve the self-doping between the substrate and the epitaxial layer, and cannot solve the influence of the gas phase doping composition and concentration on the resistivity, especially for the epitaxial process of the super heavily doped red phosphorus substrate.
  • the doping component has a greater influence on the resistivity, and the doping component in the gas phase will cause a significant difference in SRP between the edge and the center of the epitaxial wafer, resulting in a decrease in yield.
  • One of the main objectives of the present invention is to provide an epitaxial method to overcome the serious self-doping phenomenon of the super heavily doped red phosphorous substrate at the epitaxial edge, so that the edge of the super heavily doped red phosphorous substrate epitaxial wafer has the same height as the center of the SRP.
  • the present invention provides a method for epitaxy on a super heavily doped red phosphorous substrate, which includes the following steps:
  • the resistivity of the super-heavy red phosphorus-doped substrate is less than or equal to 1.0 mohm-cm.
  • the required thickness of the intrinsic silicon layer is positively related to the thickness of the substrate.
  • the excess thickness of the intrinsic silicon layer is positively correlated with the thickness of the substrate.
  • the excess thickness of the intrinsic silicon layer is not more than 20% of the thickness of the substrate.
  • the excess thickness of the intrinsic silicon layer is not more than 10% of the thickness of the substrate.
  • the growth rate of the intrinsic silicon layer is 2.0 ⁇ 0.1 ⁇ m/min.
  • the substrate is also baked before growing the intrinsic silicon layer.
  • cleaning is performed after the etching is performed, and then the epitaxy is performed.
  • the intrinsic silicon layer is generated by the reaction of trichlorosilane and hydrogen.
  • the present invention is completely different from the idea of isolation in the prior art.
  • the doping in the gas phase can be effectively removed to solve the problem of over-heavy doping.
  • the gas phase doping has a large influence on the resistivity.
  • the epitaxial wafer prepared by the epitaxial method of the present invention has the same SRP height between the edge and the center, which improves the yield of the product.
  • Figure 1 is the SRP linear comparison diagram of Example 1.
  • FIG. 2 is a comparison diagram of SRP LOG in Example 1.
  • FIG. 3 is another SRP linear comparison diagram of Example 1.
  • FIG. 4 is another SRP LOG comparison diagram of Embodiment 1.
  • Fig. 5 is a linear comparison diagram of SRP of Comparative Example 1.
  • Fig. 6 is a comparison diagram of SRP LOG of Comparative Example 1.
  • FIG. 7 is a linear comparison diagram of SRP of Comparative Example 2.
  • Fig. 8 is a comparison diagram of SRP LOG of Comparative Example 2.
  • 1, 3, 5, 7, 9, 11, 13, and 15 represent the SRP curves at the center of the epitaxial wafer in each figure
  • 2, 4, 6, 8, 10, 12, 14, and 16 represent The SRP curve at 3mm from the edge of the epitaxial wafer in each figure.
  • an over-thick intrinsic silicon layer is formed to absorb impurities in the gas phase, and then etched to a required thickness.
  • Step one BAKE the substrate.
  • the substrate is also called the substrate.
  • the main body of the substrate and the main body of the epitaxial layer consist of the same elements, both of which are silicon.
  • the substrate of this embodiment is a heavily phosphorus-doped substrate, and the resistivity of the substrate is less than or equal to 1.0 mohm-cm.
  • Step 2 Growing an intrinsic silicon layer (CAP) thicker than the required thickness on the super heavily doped red phosphorus substrate to absorb impurities in the gas phase.
  • the intrinsic silicon layer is generated by the reaction of trichlorosilane and hydrogen. That is, the single crystal silicon formed by the reaction is deposited on the upper surface of the substrate body to form the intrinsic silicon layer.
  • the thickness of the intrinsic silicon layer is not higher than 20% of the thickness of the substrate, preferably in a range not higher than 10% of the thickness of the substrate.
  • the required thickness of the intrinsic silicon layer is generally not higher than 10% of the substrate thickness, the growth rate of the intrinsic silicon layer is controlled at 2.0 ⁇ 0.1 ⁇ m/min, and the growth temperature can be controlled at 1110-1150°C.
  • Step 3 Etch (ETCH) the intrinsic silicon layer with hydrochloric acid to the required thickness.
  • Step 4 Cleaning (PURGE).
  • Step 5 Perform epitaxy (DEPOSIT) on the intrinsic silicon layer.
  • the preparation temperature of the epitaxy is 1110 ⁇ 1150°C, and the growth rate can be controlled at 0.5-1 ⁇ m/min.
  • the epitaxial equipment used in this embodiment uses an ASM 2000 machine.
  • the parameters of the epitaxial process used in the machine are as follows:
  • the preparation method is to prepare an intrinsic silicon layer of required thickness on the substrate to separate the substrate and the epitaxial layer.
  • the machine used in this method is the same as in Example 1.
  • the parameters of the epitaxial process used in the machine are:
  • the low-temperature process is used for epitaxial growth.
  • the machine used in this method is the same as that in Example 1.
  • the parameters of the epitaxial process used in the machine are:
  • the excessively thick intrinsic silicon layer of the present invention absorbs impurities in the gas phase, effectively removes the doping in the gas phase, and solves the problem that the gas phase doping has a greater impact on the resistivity in the epitaxial process of the super heavily doped red phosphorus substrate.
  • the big problem is that the SRP of the edge of the epitaxial wafer is highly consistent with the center of the epitaxial wafer, which improves the yield of the product.

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Abstract

本发明涉及超重掺红磷衬底外延方法，包括以下步骤：在超重掺红磷衬底上成长超过需要厚度的本征硅层以吸收气相中的杂质，刻蚀本征硅层至需要的厚度，在本征硅层上进行外延。本发明于现有技术中隔离的思路截然不同，通过生成过厚的本征硅层来吸收气相中的杂质，再刻蚀至需要的厚度，有效的去除的气相中的掺杂，解决超重掺红磷衬底外延工艺中，气相掺杂对于电阻率影响较大的问题，通过本发明的外延方法制得的外延片，边缘与中心的SRP高度一致，提高了产品的良率。

Description

超重掺红磷衬底外延方法 技术领域
本发明涉及外延片的生产方法，具体涉及超重掺红磷衬底外延方法。
背景技术
现有技术中的外延片生产过程中，普遍存在着自掺杂现象。自掺杂，是由于热蒸发或者化学反应的副产物对衬底的扩散，衬底中的硅及杂质进入气相，改变了气相中的掺杂成分和浓度，从而导致了外延层中的杂质实际分布偏离理想情况的现象。超重掺红磷衬底(衬底电阻率≤1.0mohm-cm)外延中自掺杂现象严重，气象中掺杂成分和浓度对于电阻率的影响较大，导致外延片边缘与中心的SRP(spreading resistance profile，扩展电阻曲线形貌)差异明显。
中国专利申请文献CN106505093A公开了一种外延片的生产方法，该方法中在衬底上铺设本征硅层(cap)，从而将外延层的电阻率均匀性做到小于1.5％(计算公式，(MAX电阻率-MIN电阻率)×100％/(MAX电阻率+MIN电阻率)，通过此计算公式计算得出的均匀性数值越小，则其均匀性越高，外延片质量越高)，从而增加了外延片的良率。其作用原理是通过本征硅层将衬底和外延层隔开，从而避免衬底本体与外延层之间产生自掺杂的问题，其本征硅层的厚度与衬底本体的厚度呈正相关。然而，这种隔离的方式只能解决衬底与外延层之间的自掺杂，无法解决气相掺杂成分和浓度对于电阻率的影响，尤其是对于超重掺红磷衬底的外延工艺而言，掺杂成分对于电阻率的影响较大，气相中的掺杂成分会造成外延片边缘与中心的SRP差异明显，导致成品率下降。
发明内容
本发明的主要目的之一提供一种外延方法，克服超重掺红磷衬底在外延边缘自掺杂严重的现象，使得超重掺红磷衬底外延片边缘与中心的SRP高度一致。
为了实现上述目的，本发明提供一种超重掺红磷衬底外延方法，包括以下步骤：
在超重掺红磷衬底上成长超过需要厚度的本征硅层以吸收气相中的杂质，
刻蚀本征硅层至需要的厚度，
在本征硅层上进行外延。
优选地，所述的超重掺红磷衬底的电阻率≤1.0mohm-cm。
优选地，本征硅层需要的厚度与衬底的厚度呈正相关。
优选地，本征硅层超过的厚度与衬底的厚度呈正相关。
优选地，本征硅层超过的厚度不高于衬底的厚度的20％。
优选地，本征硅层超过的厚度不高于衬底的厚度的10％。
优选地，本征硅层的成长速率为2.0±0.1μm/min。
优选地，在成长所述的本征硅层之前还对衬底进行烘烤。
优选地，进行所述的刻蚀后先进行清洗再进行所述的外延。
优选地，所述本征硅层由三氯硅烷与氢气反应生成。
本发明与现有技术中隔离的思路截然不同，通过生成过厚的本征硅层来吸收气相中的杂质，再刻蚀至需要的厚度，有效的去除的气相中的掺杂，解决超重掺红磷衬底外延工艺中，气相掺杂对于电阻率影响较大的问题，通过本发明的外延方法制得的外延片，边缘与中心的SRP高度一致，提高了产品的良率。
附图概述
本发明的特征、性能由以下的实施例及其附图进一步描述。
图1为实施例1的SRP线性比对图。
图2为实施例1的SRP LOG比对图。
图3为实施例1的另一SRP线性比对图。
图4为实施例1的另一SRP LOG比对图。
图5为比较例1的SRP线性比对图。
图6为比较例1的SRP LOG比对图。
图7为比较例2的SRP线性比对图。
图8为比较例2的SRP LOG比对图。
图中，1、3、5、7、9、11、13和15表示的为各个图中的外延片中心的SRP曲线，2、4、6、8、10、12、14、16表示的为各个图中的外延片边缘3mm处的SRP曲线。
本发明的较佳实施方式
本发明通过生成过厚的本征硅层来吸收气相中的杂质，再刻蚀至需要的厚度。以下结合实施例和附图对于本发明作进一步说明。
实施例1
步骤一、烘烤(BAKE)衬底。衬底也称为基板。衬底本体与外延层的主体构成的元素相同，均为硅。本实施例的衬底为重掺磷衬底，衬底的电阻率≤1.0mohm-cm。
步骤二、在超重掺红磷衬底上成长超过需要厚度的本征硅层(CAP)以吸收气相中的杂质，所述本征硅层由三氯硅烷与氢气反应生成。即，反应生成的单晶硅沉积在衬底本体的上表面形成所述本征硅层。本实施例中，本征硅层超过的厚度不高于衬底的厚度的20％，优选在不高于衬底的厚度10％的范围内。本征硅层所需要的厚度一般不高于衬底厚度的10％，本征硅层的成长速率控制在2.0±0.1μm/min，成长的温度可以控制在1110～1150℃。
步骤三、用盐酸刻蚀(ETCH)本征硅层至需要的厚度。
步骤四：进行清洗(PURGE)。
步骤五：在本征硅层上进行外延(DEPOSIT)。外延的制备温度在1110～1150℃，生长速率可以控制在0.5-1μm/min。
本实施例中采用的外延设备采用ASM 2000机台。在所述机台中采用的外延工艺的参数如下：
Figure PCTCN2020111366-appb-000001
Figure PCTCN2020111366-appb-000002
对得到的外延片用两个机台进行SRP检测，检测的线性图表和LOG图表如图1～4所示，可以看到外延片中心与边缘3mm出的SRP曲线高度重合。
比较例1
其制备方法是在衬底上制备需要厚度的本征硅层，用于隔开衬底与外延层。
该方法采用的机台与实施例1相同，在所述机台中采用的外延工艺的参数：
STEP NAME BAKE CAP DEPOSIT
CENTER 1150 1150 1150
DURATION 30～60 25～35 100
TOKEN      
DEP/VENT VENT DEPOSIT DEPOSIT
N 2H 2 SAME SAME SAME
V-PRESSURE ATM ATM ATM
HCL 0V 0V 0V
HCLHI 0V 0V 0V
TCS SAME D SAME D SAME D
PH 3/ASH 3 SAME SAME SAME
N-INJ MFC SAME SAME V SAME D
N-DIL MFC SAME SAME SAME
FRONT SAME SAME SAME
SIDE SAME SAME SAME
REAR SAME SAME SAME
ROTATION SAME SAME SAME
对得到的外延片进行SRP检测，检测的线性图表和LOG图表如图5～6所示，可以看到起中心与边缘3mm处的SRP曲线有较大差异。
比较例2
采用低温工艺进行外延生长，该方法采用的机台与实施例1相同，在所述机台中采用的外延工艺的参数：
STEP NAME BAKE DEPOSIT
CENTER 1100 1100
DURATION 30～60 100
TOKEN    
DEP/VENT VENT DEPOSIT
N 2H 2 SAME SAME
V-PRESSURE ATM ATM
HCL 0V 0V
HCLHI 0V 0V
TCS SAME D SAME D
PH 3/ASH 3 SAME SAME
N-INJ MFC SAME SAME D
N-DIL MFC SAME SAME
FRONT SAME SAME
SIDE SAME SAME
REAR SAME SAME
ROTATION SAME SAME
对得到的外延片进行SRP检测，检测的线性图表和LOG图表如图5～6所示，可以看到起中心与边缘3mm处的SRP曲线有较大差异。
经过上述比较可知，本发明过厚的本征硅层吸收了气相中的杂质，有效的去除的气相中的掺杂，解决超重掺红磷衬底外延工艺中，气相掺杂对于电阻率影响较大的问题，外延片边缘与中心的SRP高度一致，提高了产品的良率。
以上仅为本发明较佳的实施例，并不用于局限本发明的保护范围，任何在本发明精神内的修改、等同替换或改进等，都涵盖在本发明的权利要求范围内。

Claims (10)

  1. 一种超重掺红磷衬底外延方法，其特征在于包括以下步骤：
    在超重掺红磷衬底上成长超过需要厚度的本征硅层以吸收气相中的杂质，
    刻蚀本征硅层至需要的厚度，
    在本征硅层上进行外延。
  2. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于所述的超重掺红磷衬底的电阻率≤1.0mohm-cm。
  3. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于本征硅层需要的厚度与衬底的厚度呈正相关。
  4. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于本征硅层超过的厚度与衬底的厚度呈正相关。
  5. 如权利要求4所述的超重掺红磷衬底外延方法，其特征在于本征硅层超过的厚度不高于衬底的厚度的20％。
  6. 如权利要求5所述的超重掺红磷衬底外延方法，其特征在于本征硅层超过的厚度不高于衬底的厚度的10％。
  7. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于本征硅层的成长速率为2.0±0.1μm/min。
  8. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于在成长所述的本征硅层之前还对衬底进行烘烤。
  9. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于进行所述的刻蚀后先进行清洗再进行所述的外延。
  10. 如权利要求1所述的超重掺红磷衬底外延方法，其特征在于：所述本征硅层由三氯硅烷与氢气反应生成。
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