WO2021184632A1 - 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器 - Google Patents

锁相环的锁定检测方法、锁相环及其频率锁定检测控制器 Download PDF

Info

Publication number
WO2021184632A1
WO2021184632A1 PCT/CN2020/105104 CN2020105104W WO2021184632A1 WO 2021184632 A1 WO2021184632 A1 WO 2021184632A1 CN 2020105104 W CN2020105104 W CN 2020105104W WO 2021184632 A1 WO2021184632 A1 WO 2021184632A1
Authority
WO
WIPO (PCT)
Prior art keywords
phase
locked loop
frequency
output
signal
Prior art date
Application number
PCT/CN2020/105104
Other languages
English (en)
French (fr)
Inventor
廖英豪
张卫波
Original Assignee
深圳市紫光同创电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市紫光同创电子有限公司 filed Critical 深圳市紫光同创电子有限公司
Priority to KR1020227031051A priority Critical patent/KR20220139363A/ko
Publication of WO2021184632A1 publication Critical patent/WO2021184632A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the invention relates to a phase-locked loop, in particular to a phase-locked loop lock detection method, a phase-locked loop and a frequency lock detection controller thereof.
  • Phase locked loop (Phase Locked Loop) circuit is a widely used circuit system, especially for FPGA (Field Programmable Gate Array), VLSI (Very Large Scale Integrated Circuit, Very Large Scale Integrated Circuit). Large Scale Integration) system is essential.
  • the phase-locked loop is the core system for FPGA to provide clock resources, which can realize functions such as clock frequency synthesis, clock skew reduction (skew) and phase adjustment.
  • the frequency lock is realized.
  • the phase-locked loop that includes a low dropout linear regulator (LDO) inside
  • LDO low dropout linear regulator
  • the phase-locked loop needs to support a low power consumption mode, that is, the LDO needs to be turned off.
  • the LDO needs stabilization time, which often causes the internal logic of the phase-locked loop to be abnormal (such as phase Align between multiple frequency dividers), so that although the phase-locked loop can be locked in normal frequency, the output clock
  • the properties (especially the phase relationship between the clocks) and settings will be different.
  • the traditional design method is to add a delay cell (DELAY CELL) to the path of the phase-locked loop logic control signal (such as an enable signal or a reset signal), that is, the period from when the LDO is turned on to when it stabilizes.
  • the internal logic of the phase-locked loop does not work.
  • a large margin should be reserved for the delay unit design, and a single delay unit design also needs to occupy a large layout area.
  • the embodiment of the present invention provides a lock detection method of a phase-locked loop, a phase-locked loop and a frequency-locked detection controller thereof, which can solve the problem of abnormal internal logic during the power-on unstable process of the phase-locked loop, and has a simple structure and a design layout area. small.
  • the present invention provides a lock detection method of a phase-locked loop, including:
  • the first locking process the frequency of the phase-locked loop is first locked until the built-in voltage regulator of the phase-locked loop stabilizes, wherein the reset sequence of the digital logic and the power supply during the first locking process Whether it is stable or not is not required;
  • the second locking process After the built-in voltage regulator of the phase-locked loop is stable, the phase-locked loop performs the second locking process. At this time, the output clock of the voltage-controlled oscillator of the phase-locked loop has no glitches or power supply. Voltage stabilization realizes complex functions including phase alignment adjustment and duty cycle synthesis; finally, the output signal of the lock detection circuit of the phase-locked loop is output as the lock indication signal of the phase-locked loop.
  • the built-in voltage regulator of the phase-locked loop when the built-in voltage regulator of the phase-locked loop is turned on and the output voltage reaches a preset threshold that enables the phase-locked loop of the phase-locked loop to start working, the first locking process is started to start the The frequency of the phase-locked loop is locked.
  • the clock frequency division of the feedback signal is completed by a simple frequency divider and input to the frequency discriminator of the phase-locked loop, and the simple frequency divider means that only the frequency division is completed.
  • Frequency divider with frequency function is
  • a reset control signal is generated, so that the actual feedback frequency divider of the phase-locked loop and each output frequency divider are reset and released, and a selection control signal is generated at the same time ,
  • a selection control signal is generated at the same time .
  • the method further includes: detecting the output signal of the frequency lock detection circuit; after detecting that the output signal of the frequency lock detection circuit is pulled high, wait for a predetermined time, and reset the frequency lock detection circuit.
  • the clock frequency division of the feedback signal is completed by the actual feedback frequency divider of the phase-locked loop and input to the phase-frequency discriminator of the phase-locked loop.
  • the present invention provides a phase-locked loop, including: the actual feedback frequency divider of the phase-locked loop and a frequency lock detection circuit, and also includes: a frequency lock detection controller, a simple frequency divider, and a multiplexer ,
  • the simple frequency divider refers to a frequency divider that only completes the frequency division function.
  • the frequency lock detection controller is used to generate corresponding control signals according to the output signal state of the frequency lock detection circuit to control the frequency lock detection circuit, the actual feedback frequency divider of the phase-locked loop, and the simple frequency divider The working status of the device;
  • the simple frequency divider is used to perform clock frequency division of the feedback signal in the first lock process under the control of the frequency lock detection controller;
  • the first input end of the multiplexer is connected to the output end of the actual feedback frequency divider of the phase-locked loop, and the second input end of the multiplexer is connected to the output end of the simple frequency divider, so
  • the control end of the multiplexer is connected to the feedback input end of the frequency lock detection controller, and the output end of the multiplexer is connected to the frequency discriminator of the phase-locked loop, and the multiplexer is used for Under the control of the frequency lock detection controller, one of the output signal of the actual feedback frequency divider of the phase-locked loop and the output signal of the simple frequency divider is selected as the feedback signal and output to the frequency discriminator.
  • Phase device Phase device.
  • the frequency lock detection controller is also connected to the actual feedback frequency divider of the phase-locked loop and each output frequency divider, and the frequency lock detection controller is also used to control the phase-locked loop through a simple frequency divider. After completing the first locking of the frequency of the phase-locked loop, a reset control signal for resetting and releasing the actual feedback frequency divider of the phase-locked loop and each output frequency divider is generated.
  • the present invention provides a frequency lock detection controller, including: a memory; and a processor coupled to the memory, and the processor is configured to execute any of the above based on instructions stored in the memory.
  • the frequency lock detection controller includes:
  • the first flip-flop the trigger terminal of which receives the input signal of the phase-locked loop, the output terminal of which is connected to the input terminal of the first flip-flop through a first inverter, and the first flip-flop is in the phase-locked loop.
  • the falling edge of the input signal of the ring is triggered, and the first trigger outputs a selection control signal for controlling the multiplexer;
  • the AND gate the first input terminal of which is connected to the output terminal of the first flip-flop, the second output terminal of which receives the input signal of the phase-locked loop, and the output terminal of which outputs the lock indication signal of the phase-locked loop;
  • the second trigger has its trigger terminal connected to the output terminal of the first trigger, and its input terminal receives the high potential of the power supply voltage. The rising edge is triggered, and the second flip-flop outputs a reset control signal for resetting and releasing the actual feedback frequency divider of the phase-locked loop and each output frequency divider;
  • a third flip-flop the input terminal of which is connected to the output terminal of the first flip-flop, the trigger terminal of which inputs a feedback clock signal, the second flip-flop is triggered on the rising edge of the feedback clock signal, and the second trigger
  • the output terminal of the inverter is connected to the reset terminal of the counting module through the second inverter;
  • the counter module whose input clock terminal receives the feedback clock signal, and its enable terminal receives the input signal of the phase-locked loop, the counting module is used for timing, and waits for a predetermined value after the output signal of the frequency lock detection circuit is pulled high At time, output a signal to the frequency lock detection circuit to reset the frequency lock detection circuit.
  • the lock detection method of the phase-locked loop, the phase-locked loop and the frequency-locked detection controller provided by the present invention adopt two phase-locked loop locking technology: the first phase-locked loop lock is purely for locking the frequency of the phase-locked loop. There is no requirement for the reset sequence of digital logic and power supply stability; when the frequency is locked for the first time, an internal flag signal is generated to reset all the digital dividers (phase align) adjustment At this time, the output clock of the phase-locked loop voltage-controlled oscillator is normal (no glitch), and the power supply voltage is stable. There is almost no risk to the phase bonding function required for digital circuit design. At this time, it will be tested by the lock detection circuit. The output signal is output as the lock indication signal of the phase-locked loop.
  • the scheme provided by the present invention can ensure the correctness of the circuit logic function, and has simple logic, high reliability and small occupied area.
  • Figure 1 is a block diagram of a traditional phase-locked loop system
  • FIG. 2 is a flowchart of a lock detection method of a phase-locked loop provided by an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a phase-locked loop provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a frequency lock detection controller provided by an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a timing sequence of a phase-locked loop locking process provided by an embodiment of the present invention.
  • An embodiment of the present invention provides a lock detection method of a phase-locked loop. As shown in FIG. 2, the lock detection method includes:
  • the first locking process the frequency of the phase locked loop is locked for the first time until the built-in voltage regulator of the phase locked loop stabilizes, wherein the digital logic is reset during the first locking process Timing and whether the power supply is stable are not required.
  • the stability of the built-in voltage stabilizer of the phase-locked loop means that the built-in voltage stabilizer of the phase-locked loop is stable or nearly stable, otherwise the lock signal (LOCK signal) of the phase-locked loop will not be pulled high.
  • phase-locked loop power supply is close to stable or has stabilized.
  • the second locking process after the built-in voltage regulator of the phase-locked loop is stable, the phase-locked loop performs a second locking process, and the voltage-controlled oscillator output clock of the phase-locked loop has no glitches at this time , The power supply voltage is stable, and the complex functions including phase alignment adjustment and duty cycle synthesis are realized;
  • the phase-locked loop lock detection method of this embodiment uses two frequency locks.
  • the first frequency lock process is to wait for the built-in voltage regulator to stabilize.
  • the reset sequence of the digital logic and whether the power supply is stable is not done.
  • the second frequency locking process is to realize the phase alignment adjustment between the output frequency dividers of the phase-locked loop; at this time, the output clock of the voltage-controlled oscillator of the phase-locked loop is normal and the power supply voltage is stable.
  • the phase bonding function required for digital circuit design has almost no risk. After the output clock of the voltage-controlled oscillator of the phase-locked loop is normal and the power supply voltage is stable, the output signal of the lock detection circuit of the phase-locked loop is output as the lock indication signal of the phase-locked loop.
  • the built-in voltage regulator of the phase-locked loop when the built-in voltage regulator of the phase-locked loop is turned on and the output voltage reaches a preset threshold that enables the phase-locked loop of the phase-locked loop to start working, the first locking process is started to start the The frequency of the phase-locked loop is locked.
  • the clock frequency division of the feedback signal can be completed by a simple frequency divider and input to the frequency discriminator of the phase-locked loop.
  • a simple frequency divider can be used in the PLL loop for the first lock, which has strong reliability.
  • the reset sequence of the digital logic and whether the power supply is stable during the lock process when the phase locked loop is first locked After the secondary frequency lock indicator signal is pulled high, the representative built-in voltage regulator is stable, and it switches to the actual feedback frequency divider of the phase-locked loop, and each output frequency divider starts to work, and the phase-locked loop performs the second lock process; After the voltage-controlled oscillator output clock of the phase-locked loop has no glitches and the power supply voltage is stable, the logic circuit work of complex functions such as phase alignment adjustment is started; finally, the output signal of the lock detection circuit of the phase-locked loop It is output as a lock indication signal of the phase-locked loop.
  • the simple frequency divider means that the frequency divider only completes the frequency division function, without other complex logic functions such as phase alignment, duty cycle synthesis, and so on.
  • "Simple” mainly refers to simple functions and simple circuit structures. Therefore, if the power supply is unstable at the initial stage, or the output clock of the voltage-controlled oscillator has a glitch at the initial stage, the frequency divider can always divide the frequency correctly, and the phase-locked loop can finally wait until the power supply is stable. The simple frequency divider divides the frequency correctly, thus the PLL Correctly achieve the first lock frequency.
  • the actual feedback frequency divider of the phase-locked loop is a complex frequency divider as opposed to the simple frequency division, and the complex frequency divider (which can achieve complex functions such as phase alignment and duty cycle synthesis) has glitches in the initial input clock. Or the power supply is unstable and affects normal operation. Even if the output power of the phase-locked loop LDO is finally stable, functions such as phase alignment and duty cycle synthesis cannot be realized later.
  • the complex frequency divider means that in addition to the frequency division, it also needs to implement complex functions such as phase alignment and duty cycle synthesis.
  • the circuit structure is very complex, and there are clear requirements for the initial state of the circuit.
  • the output frequency divider of field programmable logic gate array must meet the control functions of programmable frequency division ratio, programmable phase, programmable duty cycle, etc., and have high levels of timing, reset, and power supply stability. Requirements.
  • the simple frequency divider is designed or selected to avoid the strict requirements on power supply and reset sequence when the complex frequency divider is working, so that the frequency division can work normally.
  • the structure is simple and the layout area is small.
  • the first lock is only the primary stage of the frequency lock of the phase-locked loop, and does not output a frequency lock signal.
  • Simple frequency divider mainly whether the power supply is stable or the VCO output clock is stable, the output frequency division function will not be affected too much, so that the first frequency lock detection PLL locks, waits for the LDO output to stabilize and provide a stable voltage Give PLL analog and digital logic circuits. If the output divider directly starts working under the condition that the power supply and LDO output are not stable, the initial state is uncertain, and it is possible that the output divider divider0 ⁇ n may not function properly. This circuit is mainly to achieve complex functions, comparing frequency division, phase adjustment, phase synchronization and other functional requirements.
  • the purpose of using two frequency lock detections is mainly Yes: Through the first lock, it is mainly to prove that the LDO output power supply voltage has been stable or close to stability, otherwise, the PLL output frequency will not be stable, and the indication output by the frequency detection (LOCK-DETECTOR) circuit will not be pulled up; Then after the internal LOCK indicator signal is pulled high, it means that the power supply is basically stable and the VCO output clock will not have glitches, because when the voltage is close to or has reached the normal value, the VCO output clock is normal.
  • the digital logic power supply LDO output is stable, and the first internal lock indicator signal is used to generate a feedback divider selection signal (selection control signal of the multiplexer) and a reset control signal, and the feedback divider is divided from the simple frequency Switch to the actual feedback divider, and at the same time serve as the reset release signal of the PLL output divider divider0 ⁇ n and the feedback divider DIVIDER_FB.
  • the PLL output divider divider0 ⁇ n and the feedback divider DIVIDER_FB.
  • it can reliably realize the complex functions of the PLL, such as phase alignment. That is, further, at the end of the first lock process: reset and release the actual feedback frequency divider and each output frequency divider of the phase-locked loop, so as to facilitate the subsequent second frequency lock.
  • a selection control signal (FBSEL) is generated to complete the work switch between the simple frequency divider and the actual feedback frequency divider of the phase-locked loop, so that the feedback signal passes through the actual feedback frequency divider of the phase-locked loop
  • the clock frequency division is completed and input to the frequency discriminator of the phase-locked loop.
  • the first frequency lock after the first frequency lock is completed, it further includes: detecting the output signal of the frequency lock detection circuit; when it is detected that the output signal is pulled high, wait for a predetermined time, and reset the frequency lock detection circuit. The detection result does not affect the subsequent frequency lock detection result during the second frequency lock.
  • the clock frequency division of the feedback signal is completed by the actual feedback frequency divider of the phase-locked loop and input to the phase-frequency discriminator of the phase-locked loop.
  • each output frequency divider of the phase-locked loop performs phase alignment adjustment.
  • the embodiment of the present invention also provides a phase-locked loop.
  • the phase-locked loop usually includes a phase frequency detector (PFD, Phase Frequency Detector), a charge pump (CP, charge pump), and a low-pass filter.
  • PFD Phase Frequency Detector
  • CP charge pump
  • LPF Low-pass filter
  • VCO voltage-controlled oscillator
  • DIVIVDERF actual feedback frequency divider of the phase-locked loop
  • LOCK CONTROL frequency lock detection circuit
  • FREQ LOCK DETECT Frequency lock detection controller
  • SIMPLE DIVIDERF simple frequency divider
  • MUX multiplexer
  • the frequency lock detection controller is used to generate corresponding control signals according to the output signal state of the frequency lock detection circuit to control the frequency lock detection circuit, the actual feedback frequency divider of the phase-locked loop, and the simple frequency divider
  • the working state of the multiplexer; the simple frequency divider is used to clock the feedback signal in the first lock process under the control of the frequency lock detection controller; the first input end of the multiplexer is connected to the The output end of the actual feedback frequency divider of the phase-locked loop, the second input end of the multiplexer is connected to the output end of the simple frequency divider, and the control end of the multiplexer is connected to the frequency lock
  • the feedback input terminal of the detection controller, the output terminal of the multiplexer is connected to the phase-frequency detector of the phase-locked loop, and the multiplexer is used to control the frequency lock detection controller under the control of the frequency lock detection controller.
  • One of the output signal of the actual feedback frequency divider of the phase-locked loop and the output signal of the simple frequency divider is selected as the feedback signal and output to
  • a frequency lock detection controller In this embodiment, a frequency lock detection controller, a simple frequency divider and a multiplexer are added on the basis of a commonly used phase-locked loop system.
  • the frequency lock detection controller generates a corresponding control signal according to the output signal state of the frequency lock detection circuit, and controls the working state of the frequency lock detection circuit and the simple frequency divider.
  • the simple frequency divider completes the clock frequency division and feeds back the output clock to the frequency discriminator according to the state of its own control signal.
  • the simple frequency divider is opposite to the complex frequency divider, which can avoid the strict requirements on the power supply and reset sequence when the complicated frequency divider is working.
  • the phase-locked loop provided in this embodiment adopts a frequency lock detection mechanism twice to ensure the correctness of the circuit sequence and function.
  • the first locking process is to wait for the built-in voltage regulator to stabilize, so that the phase-locked loop analog VCO output clock is continuously and stably output , And then use the first internal locking flag as the reset signal of phase bonding (phase bonding) which is more demanding for the phase locked loop, and then the phase locked loop enters the frequency re-locking process; the second locking process is to achieve all outputs of the phase locked loop Phase alignment between dividers.
  • the frequency lock detection controller is also connected to the actual feedback frequency divider of the phase-locked loop and each output frequency divider, and the frequency lock detection controller is also used to control the phase-locked loop through a simple frequency divider. After completing the first locking of the frequency of the phase-locked loop, a reset control signal for resetting and releasing the actual feedback frequency divider of the phase-locked loop and each output frequency divider is generated.
  • LOCK CONTROL frequency lock controller
  • the first flip-flop the trigger terminal of which receives the input signal LOCKIN of the phase-locked loop, and the output terminal of which is connected to the input terminal of the first flip-flop through a first inverter.
  • the falling edge of the input signal LOCKIN of the phase loop is triggered, and the first flip-flop outputs a selection control signal FBSEL for controlling the multiplexer;
  • the AND gate (&) its first input terminal is connected to the output terminal of the first flip-flop, its second output terminal receives the input signal LOCKIN of the phase-locked loop, and its output terminal outputs the lock indication of the phase-locked loop Signal LOCK;
  • a second flip-flop the trigger terminal of which is connected to the output terminal of the first flip-flop, the input terminal of which is input with a high potential of the power supply voltage, and the second flip-flop outputs the selection control signal FBSEL of the first flip-flop The rising edge of is triggered, and the second flip-flop outputs a reset control signal RSTN_ODIV for resetting and releasing the actual feedback frequency divider of the phase-locked loop and each output frequency divider;
  • the third flip-flop the input terminal of which is connected to the output terminal of the first flip-flop, the trigger terminal of which inputs the feedback clock signal REFCLK, the second flip-flop is triggered on the rising edge of the feedback clock signal REFCLK, the first The output terminal of the second flip-flop is connected to the reset terminal RSTN of the following counting module through the second inverter;
  • the counter module whose input clock terminal CLK receives the feedback clock signal REFCLK, and its enable terminal receives the input signal LOCKIN of the phase-locked loop, the counting module is used for timing, and the output signal of the frequency lock detection circuit is pulled high After waiting for a predetermined time, a signal RST_N is output to the frequency lock detection circuit to reset the frequency lock detection circuit.
  • the input signal LOCKIN of the phase-locked loop is used as the clock input of the flip-flop (DFF), the falling edge is valid, and the selection control signal FBSEL of the multiplexer is generated, and the selection control signal FBSEL is used to control the multiplexer to realize the feedback frequency division Switching of the device; at the same time, a reset control signal RSTN_DIV is generated using the rising edge of the selection control signal FBSEL.
  • the counter in the frequency lock controller counts several clock cycles and generates a reset signal RSTN, which is first pulled down, then pulled up, resets the frequency lock detection circuit once and then released; then the PLL divides the new feedback frequency The frequency detector is locked for the second time.
  • the main purpose of this circuit is that after the internal LOCKIN is pulled high, in the frequency lock detection controller, the frequency lock detection circuit is automatically reset and released after a few clock cycles using the counter. At this time, LOCKIN will generate a falling edge. Use this The falling edge divide by 2 circuit will generate a control signal FBSEL to pull high when this falling edge is detected, and the feedback divider will switch from the simple divider to the complex divider (that is, the actual feedback divider of the phase-locked loop) ; Then the frequency lock detection circuit starts the second frequency detection. After the frequency lock is pulled high, the LOCKIN and FBSEL signals are summed, and the resulting LOCK signal is used as the final output lock signal of the phase-locked loop.
  • the frequency lock controller In the first frequency lock detection process, the frequency lock controller (LOCK CONTROL) outputs the FBSEL control signal and selects the output of the simple divider (SIMPLE DIVIDER) as the feedback clock and sends it to the PFD module. At the same time, in order to save power consumption, the frequency lock controller outputs a reset control signal RSTN_DIV to make the actual feedback divider (DIVIDERF) of the phase-locked loop and all output dividers (DIVIDER0/1/.../n) in a reset state.
  • DIVIDERF actual feedback divider
  • DIVIDER0/1/.../n all output dividers
  • the frequency lock controller When the frequency is locked for the first time, after the frequency lock controller detects that the output signal LOCKIN of the frequency lock detection is pulled up, it waits for a few cycles and then outputs the signal RSTN to reset the frequency lock detection module, and outputs the feedback selection control signal FBSEL, which will
  • the control multiplexer selects the actual feedback divider output signal of the phase-locked loop as the feedback clock and sends it to the PFD, and the module releases the reset control signal RSTN_DIV, the actual feedback divider of the phase-locked loop and all output dividers start Work, RSTN_DIV also closes the counter through the internal LOGIC module, and the second lock detection process ends at this time.
  • the LOCKIN signal and the internal signal output the final lock detection signal through the AND gate logic.
  • the invention provides a two-time frequency locking technique for avoiding the risk of unstable output voltage of the phase-locked loop LDO power-on, which can ensure the correctness of the circuit logic function, reduce the layout area, and monitor whether the phase-locked loop power supply output is stable.
  • An embodiment of the present invention also provides a frequency lock detection controller, including: a memory; and a processor coupled to the memory, the processor is configured to enable a phase-locked loop based on instructions stored in the memory Perform the frequency lock detection method as described in any of the appeals.
  • the frequency lock detection controller can also be implemented by using other hardware other than FIG. 4, or in a manner of hardware plus software.
  • the program can be stored in a computer readable storage medium. During execution, it may include the procedures of the above-mentioned method embodiments.
  • the storage medium can be a magnetic disk, an optical disc, a read-only memory (Read-Only Memory, ROM), or a random access memory (Random Access Memory, RAM), etc.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本发明提供一种锁相环的锁定检测方法、锁相环及其频率锁定检测控制器，能够解决锁相环上电不稳定过程中内部逻辑异常的问题，并且结构简单、设计版图面积小。所述锁定检测方法包括：对锁相环的频率进行第一次锁定，直至锁相环的内置稳压器稳定，第一次锁定过程中对数字逻辑的复位时序以及电源是否稳定不做要求；当锁相环的内置稳压器稳定之后，锁相环的各输出分频器开始工作，锁相环进行第二次锁定过程，此时所述锁相环的压控振荡器输出时钟没有毛刺、电源电压稳定，实现包括相位对齐调整以及占空比合成的复杂功能；最后将锁相环的锁定检测电路的输出信号作为锁相环的锁定指示信号输出。

Description

锁相环的锁定检测方法、锁相环及其频率锁定检测控制器 技术领域
本发明涉及锁相环，尤其涉及一种锁相环的锁定检测方法、锁相环及其频率锁定检测控制器。
背景技术
锁相环(锁相环：Phase Locked Loop)电路是一种被广泛应用的电路系统，特别是对于FPGA(现场可编程逻辑门阵列，Field Programmable Gate Array)这种VLSI(超大规模集成电路，Very Large Scale Integration)系统是必不可少的。锁相环是FPGA提供时钟资源的核心系统，可以实现时钟频率综合、降低时钟偏移(skew)和相位调整等功能。
当锁相环的反馈时钟频率和输入参考频率在预先设定的误差范围内时，即实现频率锁定。对于内部包含低压差线性稳压器(Low Dropout Regulator，LDO)的锁相环，为了降低整个系统功耗，锁相环需要支持低功耗模式，即需要把LDO关闭。当再次开启锁相环时由于LDO需要稳定时间这往往会导致锁相环的内部逻辑异常(如多个分频器之间需要phase Align)，使得锁相环虽然可以正常频率锁定，但是输出时钟属性(特别是时钟之间相位关系)与设置会有差异。
在锁相环上电不稳定过程中，锁相环复位信号过早释放会给数字电路的相位绑定(Phase Align)等方面带来挑战。如图1所示，传统的设计方法是在锁相环逻辑控制信号(如使能信号或复位信号)路径上增加延时单元(DELAY CELL)，即，使LDO从开启到稳定这段时间，锁相环内部逻辑不工作。考虑到LDO稳定时间在不同工艺、电压和温度条件下有所差异，这样延时单元设计需要预留很大裕度，而且单个延时单元设计也需要占用很大版图面积。
发明内容
本发明实施例提供一种锁相环的锁定检测方法、锁相环及其频率锁定检测 控制器，能够解决锁相环上电不稳定过程中内部逻辑异常的问题，并且结构简单、设计版图面积小。
第一方面，本发明提供一种锁相环的锁定检测方法，包括：
第一次锁定过程：对所述锁相环的频率进行第一锁定，直至所述锁相环的内置稳压器稳定，其中，所述第一次锁定过程中对数字逻辑的复位时序以及电源是否稳定不做要求；
第二次锁定过程：当所述锁相环的内置稳压器稳定之后，所述锁相环进行第二次锁定过程，此时所述锁相环的压控振荡器输出时钟没有毛刺、电源电压稳定实现包括相位对齐调整以及占空比合成的复杂功能；最后将所述锁相环的锁定检测电路的输出信号作为所述锁相环的锁定指示信号输出。
可选地，在所述锁相环内置稳压器开启且输出电压达到能使所述锁相环的锁相环路开始工作的预设阈值时，启动所述第一次锁定过程，开始对所述锁相环的频率进行锁定。
可选地，在所述第一次锁定过程，通过简易分频器完成反馈信号的时钟分频并输入到所述锁相环的鉴频鉴相器，所述简易分频器指仅完成分频功能的分频器。
可选地，在所述第一次锁定过程结束时：产生一个复位控制信号，以使所述锁相环的实际反馈分频器和各输出分频器进行复位释放，同时产生一个选择控制信号，以完成简易分频器与所述锁相环的实际反馈分频器之间的工作切换，使反馈信号通过所述锁相环的实际反馈分频器完成时钟分频并输入到所述锁相环的鉴频鉴相器。
可选地，当完成第一次频率锁定后，还包括：检测频率锁定检测电路的输出信号；当检测到频率锁定检测电路的输出信号拉高后等待预定时间，复位所述频率锁定检测电路。
可选地，在所述第二次锁定过程，通过所述锁相环的实际反馈分频器完成反馈信号的时钟分频并输入到所述锁相环的鉴频鉴相器。
第二方面，本发明提供一种锁相环，包括：所述锁相环的实际反馈分频器和频率锁定检测电路，还包括：频率锁定检测控制器、简易分频器和多路选择器，所述简易分频器指仅完成分频功能的分频器。
所述频率锁定检测控制器用于根据所述频率锁定检测电路的输出信号状态产生相应控制信号，以控制所述频率锁定检测电路、所述锁相环的实际反馈分频器和所述简易分频器的工作状态；
所述简易分频器用于在所述频率锁定检测控制器的控制下在第一次锁定过程对反馈信号进行时钟分频；
所述多路选择器的第一输入端连接所述锁相环的实际反馈分频器的输出端，所述多路选择器的第二输入端连接所述简易分频器的输出端，所述多路选择器的控制端连接所述频率锁定检测控制器的反馈输入端，所述多路选择器的输出端连接所述锁相环的鉴频鉴相器，所述多路选择器用于在所述频率锁定检测控制器的控制下，在所述锁相环的实际反馈分频器的输出信号和所述简易分频器的输出信号中选择一个作为反馈信号输出至所述鉴频鉴相器。
所述频率锁定检测控制器还与所述锁相环的实际反馈分频器和各输出分频器相连，所述频率锁定检测控制器还用于在通过简易分频器对所述锁相环的频率完成第一次锁定后，生成使所述锁相环的实际反馈分频器和各输出分频器进行复位释放的复位控制信号。
第二方面，本发明提供一种频率锁定检测控制器，包括：存储器；以及耦接至所述存储器的处理器，所述处理器被配置为基于存储在所述存储器中的指令，执行上述任一项所述的频率锁定检测方法。
具体地，所述频率锁定检测控制器，包括：
第一触发器，其触发端接收所述锁相环的输入信号，其输出端通过第一反相器连接至所述第一触发器的输入端，所述第一触发器在所述锁相环的输入信号的下降沿被触发，所述第一触发器输出用于控制所述多路选择器的选择控制信号；
与门，其第一输入端与所述第一触发器输出端相连，其第二输出端接收所述锁相环的输入信号，其输出端输出所述锁相环的锁定指示信号；
第二触发器，其触发端与所述第一触发器输出端相连，其输入端接收电源电压的高电位，所述第二触发器在所述第一触发器输出的所述选择控制信号的上升沿被触发，所述第二触发器输出用于使所述锁相环的实际反馈分频器和各输出分频器进行复位释放的复位控制信号；
第三触发器，其输入端与所述第一触发器输出端相连，其触发端输入反馈时钟信号，所述第二触发器在所述反馈时钟信号的上升沿被触发，所述第二触发器输出端通过第二反相器连接至计数模块的复位端；
计数器模块，其输入时钟端接收所述反馈时钟信号，其使能端接收所述锁相环的输入信号，所述计数模块用于计时，并在频率锁定检测电路的输出信号拉高后等待预定时间，输出一信号至所述频率锁定检测电路，以复位所述频率锁定检测电路。
本发明提供的锁相环的锁定检测方法、锁相环及其频率锁定检测控制器，采用了两次锁相环锁定技术：第一次锁相环锁定，纯粹是为了锁定锁相环频率，对数字逻辑的复位时序以及电源稳定不做任何要求；当第一次频率锁定之后，产生一个内部标记(flag)信号重新复位所有的数字分频器(divider)，进行相位对齐(phase align)调整，此时锁相环压控振荡器输出时钟正常(无毛刺)，且电源电压稳定，对数字电路设计要的相位绑定(phase bonding)功能几乎没有风险，这时再将经过锁定检测电路检测的输出信号作为锁相环的锁定指示信号输出。本发明提供的方案可保证电路逻辑功能的正确性，且逻辑简单，可靠性高，占用面积小。
附图说明
图1为一种传统的锁相环系统框图；
图2为本发明实施例提供的锁相环的锁定检测方法的流程图；
图3为本发明实施例提供的锁相环的结构示意图；
图4为本发明实施例提供的频率锁定检测控制器的结构示意图；
图5为本发明实施例提供的锁相环锁定过程时序示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的实施例提供一种锁相环的锁定检测方法，如图2所示，所述锁定检测方法包括：
101、第一次锁定过程：对所述锁相环的频率进行第一次锁定，直至所述锁相环的内置稳压器稳定，其中，所述第一次锁定过程中对数字逻辑的复位时序以及电源是否稳定不做要求。此处，所述锁相环的内置稳压器稳定指的是所述锁相环的内置稳压器稳定或接近稳定，否则锁相环的锁定信号(LOCK信号)不会拉高。
只要锁相环的第一次内部LOCKIN信号拉高，基本可判断锁相环电源已接近稳定或已稳定。
102、第二次锁定过程：当所述锁相环的内置稳压器稳定之后，所述锁相环进行第二次锁定过程，此时所述锁相环的压控振荡器输出时钟没有毛刺、电源电压稳定，实现包括相位对齐调整以及占空比合成的复杂功能；
103、最后再将所述锁相环的锁定检测电路的输出信号作为所述锁相环的锁定指示信号输出。
本实施例的锁相环锁定检测方法，采用两次频率锁定，第一次频率锁定过程为等待内置稳压器稳定，第一次进行频率锁定时对数字逻辑的复位时序以及电源是否稳定不做要求；进行第二次频率锁定过程为实现所述锁相环的各输出分频器之间的相位对齐调整；此时，锁相环的压控振荡器输出时钟正常，且电 源电压稳定，对数字电路设计要的相位绑定(phase bonding)功能，几乎没有风险。在所述锁相环的压控振荡器输出时钟正常且电源电压稳定后，再将所述锁相环的锁定检测电路的输出信号作为所述锁相环的锁定指示信号输出。
可选地，在所述锁相环内置稳压器开启且输出电压达到能使所述锁相环的锁相环路开始工作的预设阈值时，启动所述第一次锁定过程，开始对所述锁相环的频率进行锁定。
可选地，在所述第一次锁定过程，可通过简易分频器完成反馈信号的时钟分频并输入到锁相环的鉴频鉴相器。
可选地，所述第一次锁定时PLL环路可以采用简易分频器，可靠性强，锁定过程中对数字逻辑的复位时序以及电源是否稳定不做要求：当所述锁相环第一次频率锁定指示信号拉高后，代表的内置稳压器稳定，切换至锁相环的实际反馈分频器，且各输出分频器开始工作，锁相环进行第二次锁定过程；此时在所述锁相环的压控振荡器输出时钟没有毛刺且电源电压稳定后，才开始进行相位对齐调整等复杂功能的逻辑电路工作；最后再将所述锁相环的锁定检测电路的输出信号作为所述锁相环的锁定指示信号输出。
其中，所述简易分频器指分频器仅仅完成分频功能，无其它如相位对齐，占空比合成等复杂逻辑功能，“简易”主要指功能简单，电路结构简单。因此，电源初期不稳定，或者压控振荡器输出时钟初期有毛刺，该分频器最终总能正确分频，锁相环最终能等到电源稳定，简易分频器正确分频，从而锁相环正确实现第一次锁定频率。锁相环的实际反馈分频器是与所述简易分频相对的复杂分频器，而复杂分频器(能实现相位对齐，占空比合成等复杂功能)由于初始的输入时钟有毛刺，或者电源不稳定影响正常工作，即使锁相环LDO输出电源最终稳定，后面也无法实现相位对齐，占空比合成等功能。亦即，复杂分频器指完成分频之外，还需要实现相位对齐，占空比合成等复杂功能，电路结构很复杂，对电路初始状态有明确要求。
通常现场可编程逻辑门阵列(FPGA)的输出分频器要满足可编程的分频 比、可编程的相位、可编程的占空比等控制功能，对时序、复位、电源稳定都有很高的要求。简易分频器是规避复杂分频器工作时对电源以及复位时序做严格的要求才能正常分频工作而设计或选择，结构简单，版图面积小。第一次锁定仅是锁相环的频率锁定的初级阶段，并不输出频率锁定信号。
简易分频器，主要是无论电源是否稳定，VCO输出时钟是否稳定，输出分频功能都不会受太大影响，这样让第一次锁频检测PLL锁定，等待LDO输出稳定，提供稳定的电压给PLL模拟以及数字逻辑电路。如果直接让输出分频器在电源、LDO输出都没稳定的条件下就开始工作，初始状态就不确定，有可能输出分频器divider0～n会功能不正常。这个电路主要是为了实现复杂的功能，比较分频，相位调整，相位同步等功能要求，所以，对系统复位释放时间以及电源问题都有比较严格要求；所以，采用两次频率锁定检测目的，主要是：通过第一次锁定，主要是证明LDO输出电源电压已经稳定或者接近稳定，否则，PLL输出频率是不会稳定的，频率检测(LOCK-DETECTOR)电路输出的指示也不会拉高的；然后内部的LOCK指示信号拉高后，说明电源基本稳定，VCO输出时钟也不会有毛刺，因为电压接近或者已达到正常值时，VCO输出时钟就是正常的，这个时候，一个干净没有毛刺的时钟，加上数字逻辑电源LDO输出稳定，利用第一次内部lock指示信号产生一个反馈分频器选择信号(多路选择器的选择控制信号)和一个复位控制信号，反馈分频器从简易分频器切换到实际的反馈分频器，同时作为PLL输出分频器divider0～n以及反馈分频器DIVIDER_FB的复位释放信号，同时，就可以很可靠地实现PLL复杂的功能，比如相位对齐等。即进一步，在所述第一次锁定过程结束时：对所述锁相环的实际反馈分频器和各输出分频器进行复位释放，便于后续进行第二次频率锁定。同时还产生一个选择控制信号(FBSEL)，以完成简易分频器与所述锁相环的实际反馈分频器之间的工作切换，使反馈信号通过所述锁相环的实际反馈分频器完成时钟分频并输入到所述锁相环的鉴频鉴相器。
可选地，当完成第一次频率锁定后，还包括：检测频率锁定检测电路的输 出信号；当检测到所述输出信号拉高后等待预定时间，复位所述频率锁定检测电路，这样前期的检测结果不影响后续第二次频率锁定时的频率锁定检测结果。
可选地，在所述第二次锁定过程，通过所述锁相环的实际反馈分频器完成反馈信号的时钟分频并输入到所述锁相环的鉴频鉴相器。在此过程，锁相环的各输出分频器进行相位对齐调整。
如图3所示，本发明的实施例还提供一种锁相环，锁相环通常包括鉴频鉴相器(PFD，Phase Frequency Detector)、电荷泵(CP，charge pump)、低通滤波器(LPF，Low-pass filter)和压控振荡器(VCO，voltage-controlled oscillator)；还包括：锁相环的实际反馈分频器(DIVIVDERF)和频率锁定检测电路(LOCK CONTROL)，还包括：频率锁定检测控制器(FREQ LOCK DETECT)、简易分频器(SIMPLE DIVIDERF)和多路选择器(MUX)。
所述频率锁定检测控制器用于根据所述频率锁定检测电路的输出信号状态产生相应控制信号，以控制所述频率锁定检测电路、所述锁相环的实际反馈分频器和所述简易分频器的工作状态；所述简易分频器用于在所述频率锁定检测控制器的控制下在第一次锁定过程对反馈信号进行时钟分频；所述多路选择器的第一输入端连接所述锁相环的实际反馈分频器的输出端，所述多路选择器的第二输入端连接所述简易分频器的输出端，所述多路选择器的控制端连接所述频率锁定检测控制器的反馈输入端，所述多路选择器的输出端连接所述锁相环的鉴频鉴相器，所述多路选择器用于在所述频率锁定检测控制器的控制下，在所述锁相环的实际反馈分频器的输出信号和所述简易分频器的输出信号中选择一个作为反馈信号输出至所述鉴频鉴相器。
本实施例在常用锁相环系统基础上增加频率锁定检测控制器、简易分频比器和多路选择器。频率锁定检测控制器根据频率锁定检测电路输出信号状态产生相应控制信号，控制频率锁定检测电路和简易分频器的工作状态。简易分频比器根据自身控制信号状态，完成时钟分频并将输出时钟反馈到鉴频鉴相器。
简易分频器与复杂分频器相对，能规避复杂分频器工作时对电源以及复位 时序做严格的要求才能正常分频工作的要求。
本实施例提供的锁相环，采用两次频率锁定检测机制保证电路时序和功能的正确性，第一次锁定过程为等待内置稳压器稳定，让锁相环模拟VCO输出时钟都连续稳定输出，然后利用第一内部锁定flag作为锁相环更高要求的相位绑定(phase bonding)的复位信号，然后锁相环进入重新锁定频率过程；第二次锁定过程为实现锁相环输出所有输出分频器之间的相位对齐(phase alignment)。
所述频率锁定检测控制器还与所述锁相环的实际反馈分频器和各输出分频器相连，所述频率锁定检测控制器还用于在通过简易分频器对所述锁相环的频率完成第一次锁定后，生成使所述锁相环的实际反馈分频器和各输出分频器进行复位释放的复位控制信号。
如图4中所示，为本实施例提供的一种频率锁定控制器(LOCK CONTROL)，包括：
第一触发器，其触发端接收所述锁相环的输入信号LOCKIN，其输出端通过第一反相器连接至所述第一触发器的输入端，所述第一触发器在所述锁相环的输入信号LOCKIN的下降沿被触发，所述第一触发器输出用于控制所述多路选择器的选择控制信号FBSEL；
与门(&)，其第一输入端与所述第一触发器输出端相连，其第二输出端接收所述锁相环的输入信号LOCKIN，其输出端输出所述锁相环的锁定指示信号LOCK；
第二触发器，其触发端与所述第一触发器输出端相连，其输入端输入电源电压的高电位，所述第二触发器在所述第一触发器输出的所述选择控制信号FBSEL的上升沿被触发，所述第二触发器输出用于使所述锁相环的实际反馈分频器和各输出分频器复位释放的复位控制信号RSTN_ODIV；
第三触发器，其输入端与所述第一触发器输出端相连，其触发端输入反馈时钟信号REFCLK，所述第二触发器在所述反馈时钟信号REFCLK的上升沿被触发，所述第二触发器输出端通过第二反相器连接至下述的计数模块的复位端 RSTN；
计数器模块，其输入时钟端CLK接收所述反馈时钟信号REFCLK，其使能端接收所述锁相环的输入信号LOCKIN，所述计数模块用于计时，并在频率锁定检测电路的输出信号拉高后等待预定时间，输出一信号RST_N至所述频率锁定检测电路，以复位所述频率锁定检测电路。
所述锁相环的输入信号LOCKIN作为触发器(DFF)的时钟输入，下降沿有效，产生多路选择器的选择控制信号FBSEL,选择控制信号FBSEL用于控制多路选择器以实现反馈分频器的切换；同时利用选择控制信号FBSEL的上升沿产生一个复位控制信号RSTN_DIV。同时，频率锁定控制器里的计数器(counter)计数几个时钟周期后，产生复位信号RSTN，先拉低，后拉高，把频率锁定检测电路复位一次后释放；然后PLL在新的反馈分频器下工作，频率检测器进行第二次锁定。
本电路的主要目的是，内部LOCKIN拉高后，在频率锁定检测控制器中，利用counter等几个时钟周期后自动把频率锁定检测电路复位后释放，此时LOCKIN会产生一个下降沿，利用这个下降沿除2电路，会在这个下降沿被检测到时生成一个控制信号FBSEL拉高，反馈分频器从简易分频器切换到复杂分频器(即锁相环的实际反馈分频器)；然后频率锁定检测电路开始第二次频率检测，频率锁定拉高后LOCKIN跟FBSEL信号求与，最终产生的LOCK信号作为锁相环最终的输出锁定信号。
具体可结合图5来理解。两次锁定频率时，通过图5的LOCKIN就可以看出；第一次锁定后，LOCKIN一定要自动复位拉低，然后重新锁定拉高。
如图5中所示，为锁相环锁定过程的时序示意图。下面结合附图进行原理性阐述：锁相环的LDO开启后输出电压开始爬升，当输出电压达到一定阈值(CP、LPF和VCO压控振荡器等模拟电路可正常工作，分频器和频率锁定等数字电路逻辑可正常翻转)，锁相环环路开始工作，此时为开始第一次锁定检测过程。
在第一次频率锁定检测过程，频率锁定控制器(LOCK CONTROL)输出 FBSEL控制信号并选择简易分频器(SIMPLE DIVIDER)的输出作为反馈时钟并送到PFD模块。同时为了节省功耗，该频率锁定控制器输出复位控制信号RSTN_DIV使锁相环的实际反馈分频器(DIVIDERF)和所有输出分频器(DIVIDER0/1/…/n)处于复位状态。
当第一次频率锁定时，频率锁定控制器检测到频率锁定检测的输出信号LOCKIN拉高后，等待几个周期后输出信号RSTN来复位频率锁定检测模块，输出反馈选择控制信号FBSEL，该信号会控制多路选择器选择锁相环的实际反馈分频器输出信号作为反馈时钟并送到PFD，同时该模块释放复位控制信号RSTN_DIV，锁相环的实际反馈分频器和所有输出分频器开始工作，RSTN_DIV也经内部LOGIC模块关闭计数器，此时第二次锁定检测过程结束。
当第二次频率锁定时，LOCKIN信号与内部信号经与门逻辑输出最终锁定检测信号。
本发明提供一种用于规避锁相环LDO上电输出电压不稳定风险的两次频率锁定技术，能保证电路逻辑功能的正确性，减小版图面积，监控锁相环电源输出是否稳定。
本发明实施例还提供一种频率锁定检测控制器，包括：存储器；以及耦接至所述存储器的处理器，所述处理器被配置为基于存储在所述存储器中的指令，使锁相环执行如上诉任一项所述的频率锁定检测方法。
可选地，所述频率锁定检测控制器也可采用除图4之外的其它硬件，或硬件加软件的方式实现。
本领域普通技术人员可以理解实现上述方法实施例中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于 此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (10)

  1. 一种锁相环的锁定检测方法，其特征在于，包括：
    第一次锁定过程：对所述锁相环的频率进行第一次锁定，直至所述锁相环的内置稳压器稳定，其中，所述第一次锁定过程中对数字逻辑的复位时序以及电源是否稳定不做要求；
    第二次锁定过程：当所述锁相环的内置稳压器稳定之后，对所述锁相环的频率进行第二次锁定，直至所述锁相环的压控振荡器输出时钟没有毛刺且电源电压稳定，以实现所述锁相环的各输出分频器之间的相位对齐调整以及占空比合成；
    将所述锁相环的锁定检测电路的输出信号作为所述锁相环的锁定指示信号输出。
  2. 根据权利要求1所述的锁相环锁定检测方法，其特征在于，在所述锁相环内置稳压器开启且输出电压达到能使所述锁相环的锁相环路开始工作的预设阈值时，启动所述第一次锁定过程，开始对所述锁相环的频率进行第一次锁定。
  3. 根据权利要求1所述的锁相环锁定检测方法，其特征在于，在所述第一次锁定过程中，通过简易分频器完成反馈信号的时钟分频并将分频后的反馈信号输入到所述锁相环的鉴频鉴相器，所述简易分频器指仅完成分频功能的分频器。
  4. 根据权利要求3所述的锁相环锁定检测方法，其特征在于，在所述第一次锁定过程结束时：产生一个复位控制信号，以使所述锁相环的实际反馈分频器和各输出分频器进行复位释放，同时产生一个选择控制信号，以完成简易分频器与所述锁相环的实际反馈分频器之间的工作切换，使反馈信号通过所述锁相环的实际反馈分频器完成时钟分频并将分频后的反馈信号输入到所述锁相环的鉴频鉴相器。
  5. 根据权利要求4所述的锁相环锁定检测方法，其特征在于，当完成第一次频率锁定后，还包括：
    检测频率锁定检测电路的输出信号；
    当检测到频率锁定检测电路的输出信号拉高后等待预定时间，复位所述频率锁定检测电路。
  6. 根据权利要求1-5任一项所述的锁相环锁定检测方法，其特征在于，在所述第二次锁定过程中，通过所述锁相环的实际反馈分频器完成反馈信号的时钟分频并将分频后的反馈信号输入到所述锁相环的鉴频鉴相器。
  7. 一种锁相环，包括：所述锁相环的实际反馈分频器和频率锁定检测电路，其特征在于，还包括：频率锁定检测控制器、简易分频器和多路选择器，所述简易分频器指仅完成分频功能的分频器；
    所述频率锁定检测控制器用于根据所述频率锁定检测电路的输出信号状态产生相应控制信号，以控制所述频率锁定检测电路、所述锁相环的实际反馈分频器和所述简易分频器的工作状态；
    所述简易分频器用于在所述频率锁定检测控制器的控制下在第一次锁定过程对反馈信号进行时钟分频；
    所述多路选择器的第一输入端连接所述锁相环的实际反馈分频器的输出端，所述多路选择器的第二输入端连接所述简易分频器的输出端，所述多路选择器的控制端连接所述频率锁定检测控制器的反馈输入端，所述多路选择器的输出端连接所述锁相环的鉴频鉴相器，所述多路选择器用于在所述频率锁定检测控制器的控制下，在所述锁相环的实际反馈分频器的输出信号和所述简易分频器的输出信号中选择一个作为反馈信号输出至所述鉴频鉴相器。
  8. 根据权利要求7所述的锁相环，其特征在于，所述频率锁定检测控制器还与所述锁相环的实际反馈分频器和各输出分频器相连，所述频率锁定检测控制器还用于在通过简易分频器对所述锁相环的频率完成第一次锁定后，生成使所述锁相环的实际反馈分频器和各输出分频器进行复位释放的复位控制信号。
  9. 根据权利要求7或8所述的锁相环，其特征在于，所述频率锁定检测控制器包括：
    第一触发器，其触发端接收所述锁相环的输入信号，其输出端通过第一反相器连接至所述第一触发器的输入端，所述第一触发器在所述锁相环的输入信号的下降沿被触发，所述第一触发器输出用于控制所述多路选择器的选择控制信号；
    与门，其第一输入端与所述第一触发器输出端相连，其第二输出端接收所述锁相环的输入信号，其输出端输出所述锁相环的锁定指示信号；
    第二触发器，其触发端与所述第一触发器输出端相连，其输入端接收电源电压的高电位，所述第二触发器在所述第一触发器输出的所述选择控制信号的上升沿被触发，所述第二触发器输出用于使所述锁相环的实际反馈分频器和各输出分频器进行复位释放的复位控制信号；
    第三触发器，其输入端与所述第一触发器输出端相连，其触发端输入反馈时钟信号，所述第二触发器在所述反馈时钟信号的上升沿被触发，所述第二触发器输出端通过第二反相器连接至计数模块的复位端；
    计数器模块，其输入时钟端接收所述反馈时钟信号，其使能端接收所述锁相环的输入信号，所述计数模块用于计时，并在频率锁定检测电路的输出信号拉高后等待预定时间，输出一信号至所述频率锁定检测电路，以复位所述频率锁定检测电路。
  10. 一种频率锁定检测控制器，其特征在于，包括：
    存储器；
    以及耦接至所述存储器的处理器，所述处理器被配置为基于存储在所述存储器中的指令，使锁相环执行如权利要求1至6中任一项所述的频率锁定检测方法。
PCT/CN2020/105104 2020-03-18 2020-07-28 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器 WO2021184632A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020227031051A KR20220139363A (ko) 2020-03-18 2020-07-28 위상 고정 루프의 고정 검출 방법, 위상 고정 루프 및 그 주파수 고정 검출 컨트롤러

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010194504.7 2020-03-18
CN202010194504.7A CN111371451B (zh) 2020-03-18 2020-03-18 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器

Publications (1)

Publication Number Publication Date
WO2021184632A1 true WO2021184632A1 (zh) 2021-09-23

Family

ID=71212013

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/105104 WO2021184632A1 (zh) 2020-03-18 2020-07-28 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器

Country Status (3)

Country Link
KR (1) KR20220139363A (zh)
CN (1) CN111371451B (zh)
WO (1) WO2021184632A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114095016A (zh) * 2021-11-25 2022-02-25 宁波奥拉半导体有限公司 采样锁相环电路、方法、时钟发生器及电子设备

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111371451B (zh) * 2020-03-18 2023-02-28 深圳市紫光同创电子有限公司 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器
CN113848384A (zh) * 2021-09-22 2021-12-28 浙江大学 一种基于鉴频鉴相器的高精度反馈式频率测量装置及方法
CN116094518B (zh) * 2022-12-30 2024-04-05 成都电科星拓科技有限公司 一种高精度全数字锁相环环路的复位方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278520A (en) * 1992-10-26 1994-01-11 Codex, Corp. Phase lock detection in a phase lock loop
CN103684432A (zh) * 2013-12-05 2014-03-26 龙芯中科技术有限公司 多相位时钟产生系统的时钟锁定方法及装置
US10243573B1 (en) * 2018-03-27 2019-03-26 Texas Instruments Incorporated Phase syncronizing PLL output across reference and VCO clock domains
CN110729996A (zh) * 2019-11-12 2020-01-24 中电科仪器仪表有限公司 一种小型化两次锁相的锁相环电路及方法
CN110808735A (zh) * 2019-11-18 2020-02-18 华南理工大学 一种快速频率锁定的数模混合锁相环
CN111371451A (zh) * 2020-03-18 2020-07-03 深圳市紫光同创电子有限公司 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8854095B2 (en) * 2012-11-12 2014-10-07 Stmicroelectronics International N.V. Fast lock acquisition and detection circuit for phase-locked loops
KR101735147B1 (ko) * 2013-05-22 2017-05-15 매그나칩 반도체 유한회사 Dll 회로 장치 및 그의 dll 락킹 방법
US9397673B2 (en) * 2014-04-23 2016-07-19 Telefonaktiebolaget L M Ericsson (Publ) Oscillator crosstalk compensation
CN108631774B (zh) * 2017-03-22 2021-07-13 中芯国际集成电路制造(上海)有限公司 锁相环及其启动电路、启动方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278520A (en) * 1992-10-26 1994-01-11 Codex, Corp. Phase lock detection in a phase lock loop
CN103684432A (zh) * 2013-12-05 2014-03-26 龙芯中科技术有限公司 多相位时钟产生系统的时钟锁定方法及装置
US10243573B1 (en) * 2018-03-27 2019-03-26 Texas Instruments Incorporated Phase syncronizing PLL output across reference and VCO clock domains
CN110729996A (zh) * 2019-11-12 2020-01-24 中电科仪器仪表有限公司 一种小型化两次锁相的锁相环电路及方法
CN110808735A (zh) * 2019-11-18 2020-02-18 华南理工大学 一种快速频率锁定的数模混合锁相环
CN111371451A (zh) * 2020-03-18 2020-07-03 深圳市紫光同创电子有限公司 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114095016A (zh) * 2021-11-25 2022-02-25 宁波奥拉半导体有限公司 采样锁相环电路、方法、时钟发生器及电子设备
CN114095016B (zh) * 2021-11-25 2023-01-24 宁波奥拉半导体股份有限公司 采样锁相环电路、方法、时钟发生器及电子设备

Also Published As

Publication number Publication date
KR20220139363A (ko) 2022-10-14
CN111371451B (zh) 2023-02-28
CN111371451A (zh) 2020-07-03

Similar Documents

Publication Publication Date Title
WO2021184632A1 (zh) 锁相环的锁定检测方法、锁相环及其频率锁定检测控制器
JP3665536B2 (ja) 広帯域遅延ロックループ回路
KR940005934B1 (ko) 위상차 검출회로
US7759990B2 (en) Clock switching circuit
US9680484B2 (en) Clock conditioner circuitry with improved holdover exit transient performance
JP4077979B2 (ja) 半導体集積回路装置
US20040066845A1 (en) PWM controller with integrated PLL
KR101950320B1 (ko) 위상 검출 회로 및 이를 이용한 동기 회로
US10491222B2 (en) Switch between input reference clocks of different frequencies in a phase locked loop (PLL) without phase impact
US6590949B1 (en) Circuit and method for compensating a phase detector
US6853252B2 (en) Phase-lock loop having programmable bandwidth
US7038508B2 (en) Methods and apparatuses for detecting clock loss in a phase-locked loop
JP2002026728A (ja) Ｐｌｌ回路のモード制御回路及び半導体装置
US6330296B1 (en) Delay-locked loop which includes a monitor to allow for proper alignment of signals
KR20040081530A (ko) 데드존을 제거하는 지연 구간에서 발생한 클럭 트랜지션을차지 펌프 제어에 반영하는 위상/주파수 검출기 및 그위상/주파수 검출 방법
EP1662663B1 (en) PLL circuit
JP7420537B2 (ja) 位相ロックループ回路
US6954510B2 (en) Phase-locked loop lock detector circuit and method of lock detection
US8432191B2 (en) Phase-locked loop having high-gain mode phase-frequency detector
US6990165B2 (en) Phase and frequency lock detector
US7327199B1 (en) Phase-locked loop (PLL) device and method for entering a test mode without a dedicated test pin
JPH0621811A (ja) 分周器同期回路
JPH11289253A (ja) Ｐｌｌ回路
JP2013213715A (ja) 半導体装置とそのテスト方法
JP3796908B2 (ja) 位相ロック検査回路、およびこれを備えたクロック生成装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20925423

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20227031051

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 20.02.2023.)

122 Ep: pct application non-entry in european phase

Ref document number: 20925423

Country of ref document: EP

Kind code of ref document: A1