WO2021184488A1 - 阵列基板、显示面板以及显示装置 - Google Patents

阵列基板、显示面板以及显示装置 Download PDF

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Publication number
WO2021184488A1
WO2021184488A1 PCT/CN2020/086436 CN2020086436W WO2021184488A1 WO 2021184488 A1 WO2021184488 A1 WO 2021184488A1 CN 2020086436 W CN2020086436 W CN 2020086436W WO 2021184488 A1 WO2021184488 A1 WO 2021184488A1
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Prior art keywords
layer
array substrate
semiconductor layer
data line
substrate
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PCT/CN2020/086436
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English (en)
French (fr)
Inventor
周帅
薛炎
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/980,398 priority Critical patent/US11552156B2/en
Publication of WO2021184488A1 publication Critical patent/WO2021184488A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention relates to the field of display, in particular to an array substrate, a display panel and a display device.
  • the optimization of the manufacturing process is an important consideration. By compressing the metal line width and line spacing, there is more space to meet the design requirements of the array substrate. However, the process optimization is affected by the equipment capacity and the panel yield, and the degree of optimization is limited.
  • FIG. 1 is a schematic diagram of an array substrate in a display device in the prior art, in which the semiconductor layer 10 is located at the bottom, the gate layer 200 is located above the semiconductor layer, and the semiconductor layer 10 is perpendicular to each other, and the data line 30 is located at the top ,
  • the data line includes a vertical data line and a horizontal data line, wherein the linear direction where the vertical data line is located is parallel to the linear direction where the semiconductor layer is located, and the linear direction where the horizontal data line is located is perpendicular to the linear direction where the semiconductor layer is located.
  • 10 and the data line 30 are not in the same plane up and down, so that the space occupied by the pixels is relatively large, which does not meet the current requirements for high pixel density.
  • the purpose of the present invention is to solve the technical problem that the pixels in the existing display device occupy a relatively large space and it is difficult to meet the requirements of the high pixel density display device.
  • the present invention provides an array substrate including: a substrate; a semiconductor layer provided on a surface of the substrate; a gate insulating layer provided on a surface of the semiconductor layer away from the substrate; The gate layer is arranged on the surface of the gate insulating layer away from the semiconductor; the interlayer insulating layer is arranged on the substrate and covers the gate layer, the gate insulating layer and the A semiconductor layer; and a data line, disposed on the interlayer insulating layer, and connected to the semiconductor layer through the interlayer insulating layer; wherein the semiconductor layer is directly below the data line.
  • the gate layer and the semiconductor layer are perpendicular to each other.
  • the array substrate further includes: a first inorganic layer disposed between the substrate and the semiconductor layer; and a second inorganic layer disposed on the data line and the interlayer insulating layer away from the The surface on one side of the first inorganic layer.
  • the gate layer is perpendicular to the data line.
  • the projection of the data line on the substrate completely falls into the projection of the semiconductor layer on the substrate.
  • the length direction of the data line is parallel to the length direction of the semiconductor layer.
  • the data line also serves as a drain wiring.
  • the present invention also provides a display panel, including a first array substrate and a second array substrate; the first array substrate is the array substrate as described above; the source connection of the first array substrate To the gate layer of the second array substrate.
  • the first array substrate includes a switching thin film transistor; the second array substrate includes a driving thin film transistor.
  • the present invention also provides a display device, including the display panel described above.
  • the technical effect of the present invention is that the semiconductor layer is arranged directly below the data line, and there is no need to reserve the design space of the display panel in the pixel, which can greatly save the space occupied by a single pixel in the display panel, and can increase the space of the pixel.
  • the utilization rate further, can meet the needs of high pixel density display devices.
  • FIG. 1 is a schematic diagram of an array substrate in the prior art
  • FIG. 2 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the array substrate according to the embodiment of the present invention.
  • FIG. 4 is a partial schematic diagram of the array substrate according to the embodiment of the present invention.
  • Substrate 2. First inorganic layer; 3. Semiconductor layer; 4. Gate insulating layer; 5. Gate layer; 6. Interlayer insulating layer; 7. Data line; 8. Second inorganic layer;
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, “plurality” means two or more than two, unless otherwise specifically defined.
  • installation should be interpreted broadly unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • the specific meanings of the above-mentioned terms in the present invention can be understood according to specific situations.
  • the "above” or “below” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • an embodiment of the present invention provides a display device that includes a display panel.
  • the display panel includes a first array substrate 100.
  • the second array substrate 200 is a first array substrate 100.
  • the first array substrate 100 includes a switching thin film transistor (Switching TFT), and the second array substrate 200 includes a driving thin film transistor (Driving TFT).
  • a capacitor is input from the data line. After the capacitor is stored, the power supply supplies current according to the current-voltage characteristics of the driving thin film transistor and the potential of the capacitor to drive the display panel.
  • the first array substrate 100 includes a substrate 1, a first inorganic layer 2, a semiconductor layer 3, a gate insulating layer 4, a gate layer 5, an interlayer insulating layer 6, a data line 7, and a second inorganic layer. 8.
  • the substrate 1 is a hard substrate, generally a glass substrate, which serves as a support and a substrate.
  • the first inorganic layer 2 is provided on the upper surface of the substrate 1 and functions as a buffer, and may also be called a buffer layer.
  • the material of the first inorganic layer 2 is an inorganic material, and the inorganic material includes silicon oxide or silicon nitride, or a multilayer structure.
  • the semiconductor layer 3 is provided on the upper surface of the first inorganic layer 2, the length direction of the semiconductor layer 3 is parallel to the length direction of the data line 7, the length direction of the semiconductor layer 3 is perpendicular to the length direction of the gate layer 5, and the semiconductor layer 3 shows The panel provides circuit support.
  • the material of the semiconductor layer 3 is a semiconductor material, and the semiconductor material includes indium gallium zinc oxide (IGZO), indium gallium titanium oxide (IZTO), and indium gallium zinc titanium oxide (IGZTO).
  • the gate insulating layer 4 is provided on the upper surface of the semiconductor layer 3, and the material of the gate insulating layer 4 is an inorganic material.
  • the inorganic material includes silicon oxide or silicon nitride or a multilayer film structure.
  • the gate insulating layer 4 and the semiconductor layer 3 are disposed opposite to each other, and the gate insulating layer 4 functions as an insulation to prevent short circuits between various circuits inside the display panel.
  • the gate layer 5 is arranged on the upper surface of the gate insulating layer 4, and the gate layer 5 is arranged opposite to the gate insulating layer 4, the length direction of the gate layer 5 is perpendicular to the length direction of the semiconductor layer 3, and the length of the gate layer 5
  • the length direction is perpendicular to the length direction of the data line 7, and the material of the gate layer 5 is a metal material, the metal material includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., or an alloy , Or multilayer film structure.
  • the interlayer insulating layer 6 is provided on the upper surface of the gate layer 5, the gate insulating layer 4, the semiconductor layer 3, and the first inorganic layer 2.
  • the material of the interlayer insulating layer 6 is an inorganic material, and the inorganic material includes silicon oxide. Material or silicon nitride or multi-layer film structure, which plays an insulating role to prevent short circuit of the circuit.
  • a through hole is provided above the semiconductor layer 3, and the through hole facilitates the electrical connection between the data line 7 and the semiconductor layer 3.
  • the data line 7 is provided on the upper surface of the interlayer insulating layer 6, the length direction of the data line 7 is parallel to the length direction of the semiconductor layer 3, and the length direction of the data line 7 is perpendicular to the length direction of the gate layer 5.
  • the material of the data line 7 includes a metal material, and the metal material includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., or an alloy, or a multilayer film structure. Part of the metal material is provided in the through hole, and the data line 7 is electrically connected to the semiconductor layer 3 through the through hole to form the drain wiring of the switching thin film transistor, the source wiring 27 of the array substrate and the gate of the driving thin film transistor The pole layers 25 are connected.
  • the second inorganic layer 8 is provided on the upper surface of the interlayer insulating layer 6 and the data line 7.
  • the second inorganic layer 8 may be a passivation layer, and its material includes silicon oxide material.
  • the second inorganic layer 8 plays a role of insulating and isolating water and oxygen from the outside.
  • the semiconductor layer 3 is facing the lower surface of the data line 7.
  • the projection of the data line 7 on the substrate 1 completely falls within the projection of the semiconductor layer 3 on the substrate 1, because The data line 7 is connected to pixels in multiple rows of the display panel, so the length of the data line 7 is greater than the length of the semiconductor layer 3.
  • the length direction of the semiconductor layer 3 is parallel to the length direction of the data line 7
  • the length direction of the semiconductor layer 3 is perpendicular to the length direction of the gate layer 5
  • the length direction of the gate layer 5 is perpendicular to the length direction of the data line 7.
  • the semiconductor layer 3 is arranged directly below the data line 7 and there is no need to reserve the design space of the display panel in the pixel, which can greatly save the space occupied by a single pixel in the display panel, and can improve the space utilization rate of the pixel.
  • the design of a switching thin film transistor occupies approximately 320 ⁇ m 2 of space.
  • the area of a sub-pixel is 10267 ⁇ m 2 , so the space that can be saved is 3.2%.
  • the current high pixel density display panel is the current development trend of display panels.
  • the display device described in this embodiment will play an increasingly important role in saving design space. The more obvious. For example, when the pixel density requirement doubles, the area of the sub-pixels will become 25% of the original area, and the space saved by the array substrate will increase to 12.8% of the pixel design space, so the space utilization of the pixels can be greatly improved. , Can also meet the demand for high pixel density.
  • the second array substrate 200 includes a substrate 21, a first inorganic layer 22, a semiconductor layer 23, a gate insulating layer 24, a gate layer 25, an interlayer insulating layer 26, a source wiring 27 and a second inorganic layer 28.
  • the substrate 21 is a hard substrate, generally a glass substrate, which serves as a support and a substrate.
  • the first inorganic layer 22 is provided on the upper surface of the substrate 21 and serves as a buffer, and may also be called a buffer layer.
  • the material of the first inorganic layer 22 is an inorganic material, and the inorganic material includes silicon oxide or silicon nitride, or a multilayer structure.
  • the semiconductor layer 3 is provided on the upper surface of the first inorganic layer 22, the material of the semiconductor layer 23 is a semiconductor material, and the semiconductor material includes indium gallium zinc oxide (IGZO), indium gallium titanium oxide (IZTO), indium gallium zinc titanium Oxide (IGZTO).
  • IGZO indium gallium zinc oxide
  • IZTO indium gallium titanium oxide
  • IGZTO indium gallium zinc titanium Oxide
  • the gate insulating layer 24 covers the upper surface of the semiconductor layer 23.
  • the material of the gate insulating layer 24 is an inorganic material.
  • the inorganic material includes silicon oxide or silicon nitride or a multilayer film structure.
  • the gate insulating layer 24 functions as an insulation and prevents short circuits between the lines inside the display panel.
  • the gate layer 25 covers the upper surface of the gate insulating layer 24, and the gate layer 25 is disposed opposite to the gate insulating layer 24.
  • the material of the gate layer 25 is a metal material, and the metal material includes molybdenum (Mo) and aluminum. (Al), copper (Cu), titanium (Ti), etc., or alloys, or multilayer film structures.
  • the interlayer insulating layer 26 is provided on the upper surface of the gate layer 25, the gate insulating layer 24, the semiconductor layer 23, and the first inorganic layer 22.
  • the material of the interlayer insulating layer 26 is an inorganic material, and the inorganic material includes silicon oxide. Material or silicon nitride or multi-layer film structure, which plays an insulating role to prevent short circuit of the circuit.
  • a through hole is provided above the semiconductor layer 3, and the through hole facilitates the electrical connection between the source wiring 27 and the semiconductor layer 23.
  • the metal layer is provided on the upper surface of the interlayer insulating layer 26, one end of which passes through the interlayer insulating layer 26 and is electrically connected to the gate layer 25 to form a source wiring 27, and the other end passes through the first array substrate 100.
  • the interlayer insulating layer 6 is electrically connected to the semiconductor layer 3 of the first array substrate 100 to form a drain wiring.
  • the second inorganic layer 28 is disposed on the upper surface of the interlayer insulating layer 26 and the source wiring 27.
  • the second inorganic layer 28 may be a passivation layer, and its material includes a silicon oxide material.
  • the second inorganic layer 28 plays a role of insulating and isolating water and oxygen from the outside.
  • the technical effect of the display device of this embodiment is that the semiconductor layer is arranged directly below the data line, and there is no need to reserve the design space of the display panel in the pixel, which can greatly save the space occupied by a single pixel in the display panel.
  • the space utilization rate of pixels can be improved, and further, the requirements of high pixel density display devices can be met.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种阵列基板、显示面板以及显示装置，所述阵列基板包括：基板、半导体层、栅极绝缘层、栅极层、层间绝缘层以及数据线，其中，所述半导体层正对于所述数据线的下方。

Description

阵列基板、显示面板以及显示装置 技术领域
本发明涉及显示领域，特别涉及一种阵列基板、显示面板以及显示装置。
 背景技术
随着OLED显示面板对像素密度需求的提高，像素的尺寸在逐渐减小，使得像素内部的设计空间受到压缩。因此，在有限的空间内，实现阵列基板的合理设计，成为重要的考量方向。
目前，制程的优化是考量的重要方向。通过对金属线宽、线距的压缩，使得有更多的空间满足阵列基板的设计需求，但是，制程优化受到设备能力、面板良率的影响，优化程度有限。
图1为现有技术中的显示装置中阵列基板的示意图，其中，半导体层10位于最下方，栅极层200设于半导体层的上方，与半导体层10相互垂直，数据线30设于最上方，数据线包括纵向数据线以及横向数据线，其中，所述纵向数据线所在直线方向与半导体层所在直线方向相互平行，所述横向数据线所在直线方向与半导体层所在直线方向相互垂直，半导体层10与数据线30并不在上下同一平面内，使得像素所占的空间相对较大，不适应当前对高像素密度的要求。
因此，在设计上进行优化，提升像素空间的利用率，成为重要的方向。
 技术问题
本发明的目的在于，解决现有的显示装置中像素所占空间相对较大，难以满足高像素密度显示装置的需求的技术问题。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，包括：基板；半导体层，设于所述基板一侧的表面；栅极绝缘层，设于所述半导体层远离所述基板一侧的表面；栅极层，设于所述栅极绝缘层远离所述半导体一侧的表面；层间绝缘层，设于所述基板上，且覆盖所述栅极层、所述栅极绝缘层以及所述半导体层；以及数据线，设于所述层间绝缘层上，且穿过所述层间绝缘层连接至所述半导体层；其中，所述半导体层正对于所述数据线的下方。
进一步地，所述栅极层与所述半导体层相互垂直。
进一步地，所述阵列基板还包括：第一无机层，设于所述基板与所述半导体层之间；以及第二无机层，设于所述数据线以及所述层间绝缘层远离所述第一无机层一侧的表面。
进一步地，所述栅极层垂直于所述数据线。
进一步地，在所述半导体层所在区域，所述数据线在所述基板上的投影完全落入所述半导体层在所述基板上的投影。
进一步地，所述数据线的长度方向与所述半导体层的长度方向平行。
进一步地，所述数据线亦作为漏极走线。
为实现上述目的，本发明还提供一种显示面板，包括第一阵列基板以及第二阵列基板；所述第一阵列基板为如前文所述的阵列基板；所述第一阵列基板的源极连接至所述第二阵列基板的栅极层。
进一步地，所述第一阵列基板包括开关薄膜晶体管；所述第二阵列基板包括驱动薄膜晶体管。
为实现上述目的，本发明还提供一种显示装置，包括前文所述的显示面板。
 有益效果
本发明的技术效果在于，将半导体层设于数据线的正下方，无需在像素内预留显示面板的设计空间，可大幅度节省单个像素在显示面板中所占的空间，可提高像素的空间利用率，进一步地，可满足高像素密度显示装置的需求。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为现有技术中阵列基板的示意图；
图2为本发明实施例所述显示面板的结构示意图；
图3为本发明实施例所述阵列基板的截面图；
图4为本发明实施例所述阵列基板的局部示意图。
部分组件标识如下：
10、半导体层；20、栅极层；30、数据线；
100、第一阵列基板；200、第二阵列基板；
1、基板；2、第一无机层；3、半导体层；4、栅极绝缘层；5、栅极层；6、层间绝缘层；7、数据线；8、第二无机层；
21、基板；22、第一无机层；23、半导体层；24、栅极绝缘层；25、栅极层；26、层间绝缘层；27、源极走线；28、第二无机层。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
具体的，请参阅图2至图4，本发明实施例提供一种显示装置，所述显示装置包括一种显示面板，具体地，如图2所示，所述显示面板包括第一阵列基板100以及第二阵列基板200。
第一阵列基板100包括开关薄膜晶体管（Switching TFT），第二阵列基板200包括驱动薄膜晶体管（Driving TFT），其工作原理为：当显示面板的扫描线被驱动后，开关薄膜晶体管被开启，信号由数据线处输入至一电容，当所述电容蓄电后，电源根据驱动薄膜晶体管的电流-电压特性与所述电容的电位供给电流以驱动显示面板。
如图3所示，第一阵列基板100包括基板1、第一无机层2、半导体层3、栅极绝缘层4、栅极层5、层间绝缘层6、数据线7以及第二无机层8。
基板1为硬质基板，一般为玻璃基板，起到支撑作用及衬底作用。
第一无机层2设于基板1的上表面，起到缓冲作用，也可叫做缓冲层。第一无机层2的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物，或是多层结构。
半导体层3设于第一无机层2的上表面，半导体层3的长度方向平行于数据线7的长度方向，半导体层3的长度方向垂直于栅极层5的长度方向，半导体层3给显示面板提供电路支持。半导体层3的材质为半导体材料，所述半导体材料包括铟镓锌氧化物（IGZO）、铟镓钛氧化物（IZTO），铟镓锌钛氧化物（IGZTO）。
栅极绝缘层4设于半导体层3的上表面，栅极绝缘层4的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构。栅极绝缘层4与半导体层3相对设置，栅极绝缘层4起到绝缘的作用，防止显示面板内部的各线路之间短路。
栅极层5设于栅极绝缘层4的上表面，且栅极层5与栅极绝缘层4相对设置，栅极层5的长度方向垂直于半导体层3的长度方向，栅极层5的长度方向垂直于数据线7的长度方向，栅极层5的材质为金属材料，所述金属材料包括钼（Mo）、铝（Al）、铜（Cu）、钛（Ti）等，或者是合金，或者是多层薄膜结构。
层间绝缘层6设于栅极层5、栅极绝缘层4、半导体层3及第一无机层2的上表面，层间绝缘层6的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构，起到绝缘作用，防止电路短路。在半导体层3的上方设有通孔，所述通孔便于数据线7与半导体层3之间的电性连接。
数据线7设于层间绝缘层6的上表面，数据线7的长度方向平行于半导体层3的长度方向，数据线7的长度方向垂直于栅极层5的长度方向。数据线7的材质包括金属材料，所述金属材料包括钼（Mo）、铝（Al）、铜（Cu）、钛（Ti）等，或者是合金，或者是多层薄膜结构。部分金属材料设于所述通孔内，数据线7过所述通孔电连接至半导体层3，形成开关薄膜晶体管的漏极走线，阵列基板的源极走线27与驱动薄膜晶体管的栅极层25相连。
第二无机层8设于层间绝缘层6及数据线7的上表面，第二无机层8可为钝化层，其材质包括硅的氧化物材料。第二无机层8起到绝缘作用及隔绝外界水氧的作用。
如图4所示，半导体层3正对于数据线7的下表面，在半导体层3所在区域处，数据线7在基板1上的投影完全落入半导体层3在基板1上的投影内，因为数据线7连接显示面板多行的像素，所以数据线7的长度大于半导体层3的长度。半导体层3的长度方向平行于数据线7的长度方向，半导体层3的长度方向垂直于栅极层5的长度方向，栅极层5的长度方向垂直于数据线7的长度方向。
将半导体层3设于数据线7的正下方，无需在像素内预留显示面板的设计空间，可大幅度节省单个像素在显示面板中所占的空间，可提高像素的空间利用率。
在现有技术中，一个开关薄膜晶体管的设计所占的空间约为320µm 2。以31inch UD 145PPI像素为例，一个子像素的面积为10267µm 2，故可节约的空间为3.2%。但是，目前高像素密度显示面板为当前显示面板发展的趋势，随着高像素密度需求的提升，像素的面积会快速减小，本实施例所述的显示装置对节约设计空间的作用会越来越明显。例如，当像素密度需求翻倍时，子像素的面积会变为原面积的25%，阵列基板节约的空间占像素设计空间的比例会上升至12.8%，故可大幅度提高像素的空间利用率，也能实现高像素密度的需求。
第二阵列基板200包括基板21、第一无机层22、半导体层23、栅极绝缘层24、栅极层25、层间绝缘层26、源极走线27以及第二无机层28。
基板21为硬质基板，一般为玻璃基板，起到支撑作用及衬底作用。
第一无机层22设于基板21的上表面，起到缓冲作用，也可叫做缓冲层。第一无机层22的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物，或是多层结构。
半导体层3设于第一无机层22的上表面，半导体层23的材质为半导体材料，所述半导体材料包括铟镓锌氧化物（IGZO）、铟镓钛氧化物（IZTO），铟镓锌钛氧化物（IGZTO）。
栅极绝缘层24包覆于半导体层23的上表面，栅极绝缘层24的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构。栅极绝缘层24起到绝缘的作用，防止显示面板内部的各线路之间短路。
栅极层25覆盖于栅极绝缘层24的上表面，且栅极层25与栅极绝缘层24相对设置，栅极层25的材质为金属材料，所述金属材料包括钼（Mo）、铝（Al）、铜（Cu）、钛（Ti）等，或者是合金，或者是多层薄膜结构。
层间绝缘层26设于栅极层25、栅极绝缘层24、半导体层23及第一无机层22的上表面，层间绝缘层26的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构，起到绝缘作用，防止电路短路。在半导体层3的上方设有通孔，所述通孔便于源极走线27与半导体层23之间的电性连接。
金属层设于层间绝缘层26的上表面，其一端穿过所述层间绝缘层26电连接至栅极层25，形成源极走线27，其另一端穿过第一阵列基板100的层间绝缘层6，电连接至第一阵列基板100的半导体层3，形成漏极走线。
第二无机层28设于层间绝缘层26及源极走线27的上表面，第二无机层28可为钝化层，其材质包括硅的氧化物材料。第二无机层28起到绝缘作用及隔绝外界水氧的作用。
本实施例所述显示装置的技术效果在于，将半导体层设于数据线的正下方，无需在像素内预留显示面板的设计空间，可大幅度节省单个像素在显示面板中所占的空间，可提高像素的空间利用率，进一步地，可满足高像素密度显示装置的需求。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本发明实施例所提供的一种阵列基板、显示面板以及显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。

Claims (10)

  1. 一种阵列基板，其包括：
    基板；
    半导体层，设于所述基板一侧的表面；
    栅极绝缘层，设于所述半导体层远离所述基板一侧的表面；
    栅极层，设于所述栅极绝缘层远离所述半导体一侧的表面；
    层间绝缘层，设于所述基板上，且覆盖所述栅极层、所述栅极绝缘层以及所述半导体层；以及
    数据线，设于所述层间绝缘层上，且穿过所述层间绝缘层连接至所述半导体层；
    其中，所述半导体层正对于所述数据线的下方。
  2. 如权利要求1所述的阵列基板，其中，
    所述栅极层与所述半导体层相互垂直。
  3. 如权利要求1所述的阵列基板，其还包括：
    第一无机层，设于所述基板与所述半导体层之间；以及
    第二无机层，设于所述数据线以及所述层间绝缘层远离所述第一无机层一侧的表面。
  4. 如权利要求3所述的阵列基板，其中，
    所述栅极层垂直于所述数据线。
  5. 如权利要求1所述的阵列基板，其中，
    在所述半导体层所在区域，所述数据线在所述基板上的投影完全落入所述半导体层在所述基板上的投影。
  6. 如权利要求1所述的阵列基板，其中，
    所述数据线的长度方向与所述半导体层的长度方向平行。
  7. 如权利要求1所述的阵列基板，其中，
    所述数据线亦作为漏极走线。
  8. 一种显示面板，其包括第一阵列基板以及第二阵列基板；
    所述第一阵列基板为如权利要求1所述的阵列基板；
    所述第一阵列基板的源极连接至所述第二阵列基板的栅极层。
  9. 如权利要求8所述的显示面板，其中，
    所述第一阵列基板包括开关薄膜晶体管；
    所述第二阵列基板包括驱动薄膜晶体管。
  10. 一种显示装置，包括如权利要求8所述的显示面板。
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