WO2021027216A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021027216A1
WO2021027216A1 PCT/CN2019/126461 CN2019126461W WO2021027216A1 WO 2021027216 A1 WO2021027216 A1 WO 2021027216A1 CN 2019126461 W CN2019126461 W CN 2019126461W WO 2021027216 A1 WO2021027216 A1 WO 2021027216A1
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WIPO (PCT)
Prior art keywords
display panel
auxiliary electrode
line
auxiliary
common electrode
Prior art date
Application number
PCT/CN2019/126461
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English (en)
French (fr)
Inventor
陈涛
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/970,949 priority Critical patent/US20230102616A1/en
Publication of WO2021027216A1 publication Critical patent/WO2021027216A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • This application relates to the display field, and in particular to a display panel and a display device.
  • the brightness uniformity of the display panel needs to be strictly considered and controlled during the manufacturing process of the display device.
  • the voltage drop in the circuit especially the voltage drop of the common electrode circuit, affects the brightness uniformity of the display panel and also increases the power consumption of the display panel.
  • the existing display panel has the problem of excessive line voltage drop, which needs to be solved.
  • the present application provides a display panel and a display device to alleviate the problem of excessive line voltage drop in the existing display panel.
  • the application provides a display panel, which includes:
  • Common electrode layer forming a common electrode
  • the auxiliary electrode layer is patterned to form an auxiliary electrode line, and both ends of the auxiliary electrode line are connected to the common electrode.
  • the auxiliary electrode layer is a pixel electrode layer, and the pixel electrode layer is patterned to form auxiliary electrode lines.
  • the auxiliary electrode line is a zigzag line, and the pixel electrode is located in an area between adjacent zigzag lines.
  • the auxiliary electrode line is a grid-type wiring, and the pixel electrode is located in an area enclosed by the grid-type wiring.
  • the auxiliary electrode line is connected to the common electrode layer through a strip-shaped via.
  • the two ends of the auxiliary electrode line are respectively connected to an auxiliary bus line perpendicular to the direction of the auxiliary electrode line.
  • the auxiliary electrode line is connected to the auxiliary bus at at least two opposite sides.
  • the auxiliary electrode layer includes a first auxiliary electrode layer and a second auxiliary electrode layer, the first auxiliary electrode layer is a pixel electrode layer, and the second auxiliary electrode layer is a source and drain. Floor.
  • the auxiliary electrode layer includes a first auxiliary electrode layer and a second auxiliary electrode layer, the first auxiliary electrode layer is a pixel electrode layer, and the second auxiliary electrode layer is a source and drain. Floor.
  • the pixel electrode layer is patterned to form a first auxiliary electrode line
  • the source and drain layer is patterned to form a second auxiliary electrode line.
  • the first auxiliary electrode line is a horizontal zigzag line
  • the second auxiliary electrode line is a vertical line parallel to the data line.
  • the first auxiliary electrode line is a vertical zigzag line
  • the second auxiliary electrode line is a vertical line parallel to the data line.
  • the first auxiliary electrode line is a grid-type wiring
  • the second auxiliary electrode line is a vertical wiring parallel to the data line.
  • the intersecting positions of the first auxiliary electrode line and the second auxiliary electrode line in the space are connected to each other through via holes.
  • the end point of the first auxiliary electrode line is connected to the common electrode layer through a via hole.
  • both ends of the first auxiliary electrode line are respectively connected to auxiliary buses perpendicular to the direction of the first auxiliary electrode line.
  • the first auxiliary electrode line is connected to the auxiliary bus at at least two opposite sides.
  • the auxiliary bus is connected to the common electrode layer through a strip-shaped via.
  • the distance between the auxiliary electrode line and the pixel electrode is greater than 2um.
  • the present application also provides a display device, which includes a display panel, and the display panel includes:
  • Common electrode layer forming a common electrode
  • the auxiliary electrode layer is patterned to form an auxiliary electrode line, and both ends of the auxiliary electrode line are connected to the common electrode.
  • the present application provides a display panel and a device.
  • the display panel includes a common electrode layer and an auxiliary electrode layer, the common electrode layer forms a common electrode, the auxiliary electrode layer is patterned to form an auxiliary electrode line, and both ends of the auxiliary electrode line are connected to the common electrode;
  • the auxiliary electrode line is added to the display panel, so that the common electric signal flows from one end of the common electrode into the auxiliary electrode line, after flowing through the auxiliary electrode line, and then flows out of the common electrode from the other end, so the common electric signal can be regarded as
  • the common electrode is connected in parallel with the auxiliary electrode line, and because the sheet resistance of the auxiliary electrode line is much smaller than the sheet resistance of the common electrode, the total resistance of the common electrode and auxiliary electrode line in parallel is much smaller than the resistance of the common electrode. Under the same current, The resistance is reduced and the voltage drop is reduced, that is, the embodiment of the present application reduces the voltage drop on the common electrode line of the display panel, thereby improving the brightness uniformity of the display
  • FIG. 1 is a schematic cross-sectional view of a first film structure of a display panel provided by an embodiment of the present invention.
  • FIG. 2(a) is a schematic top view of the common electrode layer of the first structure of the display panel provided by an embodiment of the present invention.
  • FIG. 2(b) is a schematic top view of the pixel electrode layer of the first structure of the display panel provided by the embodiment of the present invention.
  • FIG. 2(c) is a schematic plan view superimposed on the common electrode layer and the pixel electrode layer of the first structure of the display panel provided by the embodiment of the present invention.
  • FIG. 3(a) is a schematic top view of the common electrode layer of the second structure of the display panel provided by an embodiment of the present invention.
  • FIG. 3(b) is a schematic top view of the pixel electrode layer of the second structure of the display panel provided by the embodiment of the present invention.
  • FIG. 3(c) is a schematic diagram of a superimposed top view of the common electrode layer and the pixel electrode layer of the second structure of the display panel provided by an embodiment of the present invention.
  • Fig. 4(a) is a partial enlarged schematic diagram of area 11 in Fig. 2(c).
  • Fig. 4(b) is a partial enlarged schematic diagram of area 12 in Fig. 2(c).
  • Fig. 4(c) is a partial enlarged schematic diagram of area 13 in Fig. 3(c).
  • FIG. 5(a) is a schematic top view of a common electrode layer of a third structure of a display panel provided by an embodiment of the present invention.
  • FIG. 5(b) is a schematic top view of a pixel electrode layer of a third structure of a display panel provided by an embodiment of the present invention.
  • FIG. 5(c) is a schematic plan view superimposed on the common electrode layer and the pixel electrode layer of the third structure of the display panel provided by the embodiment of the present invention.
  • FIG. 6(a) is a schematic top view of a common electrode layer of a fourth structure of a display panel provided by an embodiment of the present invention.
  • FIG. 6(b) is a schematic top view of the pixel electrode layer of the fourth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 6(c) is a schematic plan view superimposed on the common electrode layer and the pixel electrode layer of the fourth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 7(a) is a schematic top view of a common electrode layer of a fifth structure of a display panel provided by an embodiment of the present invention.
  • FIG. 7(b) is a schematic top view of the pixel electrode layer of the fifth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 7(c) is a schematic plan view superimposed on the common electrode layer and the pixel electrode layer of the fifth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 8(a) is a schematic top view of a common electrode layer of a sixth structure of a display panel provided by an embodiment of the present invention.
  • FIG. 8(b) is a schematic top view of the pixel electrode layer of the sixth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 8(c) is a schematic plan view superimposed on the common electrode layer and the pixel electrode layer of the sixth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of a second film structure of a display panel provided by an embodiment of the present invention.
  • FIG. 10(a) is a schematic top view of a common electrode layer of a seventh structure of a display panel provided by an embodiment of the present invention.
  • FIG. 10(b) is a schematic top view of the pixel electrode layer of the seventh structure of the display panel provided by the embodiment of the present invention.
  • FIG. 10(c) is a schematic top view of the source and drain layers of the seventh structure of the display panel provided by an embodiment of the present invention.
  • FIG. 10(d) is a schematic diagram of a top view superimposed schematic diagram of the common electrode layer, the pixel electrode layer, and the source and drain layers of the seventh structure of the display panel provided by an embodiment of the present invention.
  • FIG. 11(a) is a schematic top view of the common electrode layer of the eighth structure of the display panel provided by an embodiment of the present invention.
  • FIG. 11(b) is a schematic top view of the pixel electrode layer of the eighth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 11(c) is a schematic top view of the source and drain layers of the eighth structure of the display panel provided by an embodiment of the present invention.
  • FIG. 11(d) is a schematic diagram of a top view superimposed schematic diagram of the common electrode layer, the pixel electrode layer, and the source and drain layers of the eighth structure of the display panel provided by an embodiment of the present invention.
  • Fig. 12(a) is a partial enlarged schematic diagram of area 14 in Fig. 10(d).
  • Fig. 12(b) is a partial enlarged schematic diagram of area 15 in Fig. 10(d).
  • Fig. 12(c) is a partial enlarged schematic diagram of area 16 in Fig. 11(d).
  • FIG. 13(a) is a schematic top view of a common electrode layer of a ninth structure of a display panel provided by an embodiment of the present invention.
  • FIG. 13(b) is a schematic top view of a pixel electrode layer of a ninth structure of a display panel provided by an embodiment of the present invention.
  • FIG. 13(c) is a schematic top view of the source and drain layers of the ninth structure of the display panel provided by an embodiment of the present invention.
  • FIG. 13 is a schematic top view superimposed schematic diagram of the common electrode layer, the pixel electrode layer, and the source and drain layers of the ninth structure of the display panel provided by an embodiment of the present invention.
  • FIG. 14(a) is a schematic top view of the common electrode layer of the tenth structure of the display panel provided by an embodiment of the present invention.
  • FIG. 14(b) is a schematic top view of the pixel electrode layer of the tenth structure of the display panel provided by the embodiment of the present invention.
  • FIG. 14(c) is a schematic top view of the source and drain layers of the tenth structure of the display panel provided by an embodiment of the present invention.
  • FIG. 14(d) is a schematic diagram of a top view superimposed schematic diagram of the common electrode layer, the pixel electrode layer, and the source and drain layers of the tenth structure of the display panel provided by an embodiment of the present invention.
  • Fig. 15(a) is a partial enlarged schematic diagram of area 17 in Fig. 13(d).
  • Fig. 15(b) is a partial enlarged schematic diagram of area 18 in Fig. 13(d).
  • Fig. 15(c) is a partial enlarged schematic diagram of area 19 in Fig. 14(d).
  • FIG. 16(a) is a schematic top view of the common electrode layer of the eleventh structure of the display panel provided by an embodiment of the present invention.
  • FIG. 16(b) is a schematic top view of the pixel electrode layer of the eleventh structure of the display panel provided by the embodiment of the present invention.
  • 16(c) is a schematic top view of the source and drain layers of the eleventh structure of the display panel provided by an embodiment of the present invention.
  • FIG. 16 (d) is a schematic diagram of a top view superimposed schematic diagram of the common electrode layer, the pixel electrode layer, and the source and drain layers of the eleventh structure of the display panel provided by an embodiment of the present invention.
  • the present application provides a display panel and a display device.
  • the display panel provided by the present application includes:
  • Common electrode layer forming a common electrode
  • the auxiliary electrode layer is patterned to form an auxiliary electrode line, and both ends of the auxiliary electrode line are connected to the common electrode.
  • an auxiliary electrode line is added to the display panel, so that the common electrical signal flows from one end of the common electrode into the auxiliary electrode line, and after flowing through the auxiliary electrode line, flows out of the common electrode from the other end, thus the transmission process of the common electrical signal
  • the common electrode and the auxiliary electrode line are connected in parallel, and since the sheet resistance of the auxiliary electrode line is much smaller than the sheet resistance of the common electrode, the total resistance of the common electrode and the auxiliary electrode line in parallel is much smaller than the resistance of the common electrode.
  • the embodiment of the present application effectively reduces the voltage drop on the common electrode line of the display panel, thereby improving the brightness uniformity of the display panel and reducing the power consumption of the display panel. .
  • the display panel provided in the embodiment of the present application may be an OLED display panel or an LCD display panel, which is not limited herein.
  • an OLED display panel will be taken as an example to further explain the display panel provided in the embodiments of the present application.
  • the display panel provided by the present application is an OLED display panel. As shown in FIG. 1, the OLED display panel 10 includes:
  • the substrate 110 includes a glass substrate and a flexible substrate.
  • the glass substrate is made of rigid glass material and is located at the bottom of the display panel; the flexible substrate is generally polyimide or polyethylene terephthalate. Other organic polymer materials are formed on a glass substrate.
  • the buffer layer 120 is used to block water and oxygen from entering the display panel 10 to avoid reducing the service life of the display panel; at the same time, it prevents impurity particles from diffusing into the thin film transistor to avoid reducing leakage current.
  • the buffer layer generally adopts a stacked structure of silicon nitride (SiN x ) and silicon oxide (SiO x ). Silicon nitride has a strong ion barrier capacity and a good water and oxygen insulation capacity, and the interface between silicon oxide and polysilicon is wetted It has better performance and can be better used as the base material for forming the active layer.
  • the thin-film crystal optical layer 130 includes an active layer, which is patterned to form an active region 131.
  • the active region 131 is doped to form a channel region and a doped region.
  • the material of the active layer is generally amorphous silicon or polysilicon;
  • a gate insulating layer 132 covers the buffer layer 120 and the active layer;
  • the first gate layer is formed on the first gate insulating layer 132, and the first gate 133 and gate scan lines (not shown) are patterned and formed Out);
  • the second gate insulating layer 134 covering the first gate insulating layer 132 and the first gate layer;
  • the second gate layer formed on the second gate insulating layer 134, patterned with a second gate 135;
  • Interlayer insulating layer 136 covering the second gate insulating layer 134 and the second gate layer;
  • Source and drain layer 137 formed on the interlayer insulating layer 136, patterned to form a drain 1371, a source 1372 Data line (not shown) and power line (
  • the planarization layer 140 is formed on the passivation layer 138 and is used to planarize the thin film transistor layer 130 to provide a planar substrate for subsequent preparation of pixel electrodes, and its material is organic.
  • the pixel electrode layer 150 is formed on the planarization layer 140.
  • the pixel electrode 151 is patterned and connected to the source electrode 1372 through the via holes in the planarization layer 140 and the passivation layer 138; the pixel electrode 151 is generally oxidized
  • the laminated structure of indium tin/silver/indium tin oxide (ITO/Ag/ITO) has a sheet resistance of 0.1 ⁇ 0.2 ⁇ / ⁇ .
  • the pixel defining layer 160 is formed on the planarization layer 140 and the pixel electrode layer 150, and the formed light emitting area is patterned, and the light emitting area is used to define the pixel area.
  • the light-emitting material layer 170 is formed in the light-emitting area defined by the pixel definition layer 160, and generally includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • the common electrode layer is formed on the pixel defining layer 160 and covering the luminescent material layer 170.
  • the common electrode layer is generally vapor-deposited on the pixel defining layer 160 and the luminescent material layer 170 on the entire surface.
  • the common electrode layer vaporized on the entire surface forms a display
  • the common electrode 180 of the panel; the material of the common electrode 180 is a low work function metal or alloy, the most commonly used is magnesium aluminum alloy, and its sheet resistance is 5-30 ⁇ / ⁇ .
  • the OLED display panel in this embodiment can be a top-gate structure as shown in FIG. 1, or a bottom-gate structure; it can be a double-gate structure as shown in FIG. 3, or a single-gate structure; the pixel electrode can be Connecting to the source can also be connected to the drain, which is not limited here.
  • the sheet resistance of the pixel electrode layer 150 is 0.1 ⁇ 0.2 ⁇ / ⁇
  • the sheet resistance of the source/drain layer 137 is 0.04 ⁇ 0.06 ⁇ / ⁇ , which are both smaller than the sheet resistance of the common electrode layer by 5-30 ⁇ / ⁇ . Therefore, the pixel electrode layer 150, the source and drain layers 137, or the first gate layer and the second gate layer can be used as auxiliary electrode layers at the same time, and auxiliary electrodes are added in the auxiliary electrode layers, and the auxiliary electrodes are connected in parallel with the common electrode.
  • the auxiliary electrode Used to assist the common electrode to transmit the common electrical signal, reduce the resistance on the common electrical signal transmission path, thereby reducing the voltage drop on the common electrode line during the transmission of the common electrical signal, thereby improving the brightness uniformity of the display panel, and reducing the The power consumption of the display panel.
  • the arrangement of the auxiliary electrode is different, and the total resistance after the auxiliary electrode and the common electrode are connected in parallel is different, so that the effect of reducing the voltage drop on the common electrode line of the display panel is also different.
  • the arrangement of the pixels is a diamond arrangement; in other embodiments, the arrangement of the pixels may also be in other ways, which is not limited here.
  • the auxiliary electrode layer is a pixel electrode layer. As shown in FIG. 1, the pixel electrode layer is further patterned to form auxiliary electrode lines 152. In the embodiments described in FIGS. 2 to 8 below, the pixel electrode layer is used as the auxiliary electrode layer, and the pixel electrode 151 and the auxiliary electrode line 152 are patterned and formed at the same time, in order to ensure that there is no gap between the auxiliary electrode line 152 and the pixel electrode 151. In the case of a short circuit, it is necessary to set the distance between the auxiliary electrode line 152 and the pixel electrode 151 to be greater than the threshold, which is generally 2um.
  • the auxiliary electrode line 152 is a horizontally broken line, that is, the auxiliary electrode line 152 is a broken line, and the direction of the broken line is along the display
  • the direction of the short side of the panel is the arrangement direction of the data lines in the display panel; the pixel electrode 151 is located in the area between adjacent horizontal zigzag lines.
  • the auxiliary electrode line 152 is connected to the common electrode 180 through the vias 101 at the two end points of the transverse fold line, so as to be connected in parallel with the common electrode 180
  • the total sheet resistance will be smaller than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode
  • the resistance on the circuit further reduces the voltage drop on the common electrode circuit of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel.
  • the auxiliary electrode lines 152 are connected to the auxiliary bus 153 perpendicular to the direction of the horizontal fold line at both ends of the horizontal fold line, and the auxiliary bus 153 Then, it is connected to the common electrode 180 through the strip-shaped trough 102 parallel to the auxiliary bus 153, so that the auxiliary electrode line 152 and the common electrode 180 are connected in parallel.
  • the total sheet resistance will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode line
  • the resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • this embodiment is first connected to both ends of the auxiliary electrode line through the auxiliary bus, and then connected to the common electrode through the strip-shaped trough, ensuring the connection between the auxiliary electrode line and the common electrode. It avoids the disconnection between the auxiliary electrode line and the common electrode due to the via hole; at the same time, the sheet resistance of the auxiliary bus is smaller than the sheet resistance of the common electrode.
  • the setting of the auxiliary bus further reduces the total resistance on the common electrode line and further reduces The voltage drop on the common electrode line of the display panel is further improved, the brightness uniformity of the display panel is further improved, and the power consumption of the display panel is further reduced.
  • the auxiliary electrode line 152 is a vertical broken line type, that is, the auxiliary electrode line 152 is a broken line type, and the direction of the broken line type is Along the direction of the short side of the display panel, that is, the arrangement direction of the data lines in the display panel; the pixel electrode 151 is located in the area between the adjacent vertical zigzag wires.
  • the auxiliary electrode line 152 is connected to the common electrode 180 through the vias 101 at the two end points of the vertical fold line.
  • the specific method can be referred to as shown in FIG. 4(b).
  • the total sheet resistance of the common electrode 180 and the auxiliary electrode line 152 after being connected in parallel will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reduce the resistance on the common electrode line, thereby reducing the voltage drop on the common electrode line of the display panel, improving the brightness uniformity of the display panel, and reducing the power consumption of the display panel.
  • the auxiliary electrode line 152 is connected to the auxiliary bus 153 perpendicular to the direction of the vertical fold line at both ends of the vertical fold line.
  • the parallel strip-shaped via 153 is connected to the common electrode 180, and the specific connection method can be referred to as shown in FIG.
  • the total sheet resistance will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode line
  • the resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • this embodiment is first connected to both ends of the auxiliary electrode line through the auxiliary bus, and then connected to the common electrode through the strip-shaped trough, ensuring the connection between the auxiliary electrode line and the common electrode. It avoids the disconnection between the auxiliary electrode line and the common electrode due to the via hole; at the same time, the sheet resistance of the auxiliary bus is smaller than the sheet resistance of the common electrode.
  • the setting of the auxiliary bus further reduces the total resistance on the common electrode line and further reduces The voltage drop on the common electrode line of the display panel is further improved, the brightness uniformity of the display panel is further improved, and the power consumption of the display panel is further reduced.
  • the auxiliary electrode line 152 is a grid-type wiring, and the pixel electrode 151 is located in an area enclosed by the grid-type wiring.
  • the auxiliary electrode line 152 is on at least two opposite sides, and its end point is connected to the common electrode 180 through the via 101.
  • the specific method can be referred to as shown in FIG. 4(b).
  • the effect of being connected in parallel with the common electrode 180 is achieved.
  • the opposite sides can be two horizontally opposite sides as shown in FIG. 7, or two vertical opposite sides, or two vertical opposite sides and two horizontal opposite sides, which are not limited here. .
  • the total sheet resistance will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode line
  • the resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • the auxiliary electrode line 152 is connected to the auxiliary bus 153 on at least two opposite sides, and the auxiliary bus 153 is then connected to the common electrode through a strip through slot 102 parallel to the auxiliary bus 153.
  • the specific connection method can refer to FIG. 4(c), so as to achieve the effect of the auxiliary electrode line 152 and the common electrode 180 in parallel.
  • the opposite sides can be two vertical opposite sides as shown in FIG. 8, or two horizontal opposite sides, or two vertical opposite sides and two horizontal opposite sides, which are not limited here. .
  • the total sheet resistance will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode line
  • the resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • this embodiment is first connected to both ends of the auxiliary electrode line through the auxiliary bus, and then connected to the common electrode through the strip-shaped groove, ensuring the connection between the auxiliary electrode line and the common electrode. It avoids the disconnection between the auxiliary electrode line and the common electrode due to the via hole; at the same time, the sheet resistance of the auxiliary bus is smaller than the sheet resistance of the common electrode.
  • the setting of the auxiliary bus further reduces the total resistance on the common electrode line and further reduces The voltage drop on the common electrode line of the display panel is further improved, the brightness uniformity of the display panel is further improved, and the power consumption of the display panel is further reduced.
  • the auxiliary electrode layer includes a first auxiliary electrode layer and a second auxiliary electrode layer.
  • the first auxiliary electrode layer is a pixel electrode layer
  • the second auxiliary electrode layer is a source and drain layer.
  • the pixel electrode layer is patterned to form a first auxiliary electrode line 152
  • the source and drain layer is patterned to form a second auxiliary electrode line 1273.
  • the pixel electrode layer is used as the first auxiliary electrode layer, and the pixel electrode 151 and the auxiliary electrode line 152 are patterned and formed at the same time, in order to ensure the space between the auxiliary electrode line 152 and the pixel electrode 151.
  • the distance between the auxiliary electrode line 152 and the pixel electrode 151 is greater than the threshold, which is generally 2um.
  • the source drain layer is used as the second auxiliary electrode, and the drain 1371, the source 1372, the second auxiliary electrode 1373, and the data line and the power line (not shown) are patterned at the same time. Because the data line and the power line are both vertical Therefore, the second auxiliary electrode line 1373 is a vertical line parallel to the data line and the power line, and is insulated from the data line and the power line.
  • the first auxiliary electrode line 152 is a horizontal zigzag line, and the pixel electrode 151 is located in an area between adjacent horizontal zigzag lines.
  • the intersecting positions of the first auxiliary electrode line 152 and the second auxiliary electrode line 1373 in the space are connected to each other through the via 103, so that the first auxiliary electrode 152 and the second auxiliary electrode 1373 are connected in parallel .
  • the first auxiliary electrode line 152 is connected to the common electrode 180 through the vias 101 at the two end points of the transverse fold line, so that the first auxiliary electrode line The electrode 152, the second auxiliary electrode 1373 and the common electrode 180 are simultaneously connected in parallel.
  • the total sheet resistance will be less than the sheet resistance of the second auxiliary electrode 1373 by 0.04 ⁇ 0.06 ⁇ / ⁇ is much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , which reduces the resistance on the common electrode circuit, thereby reducing the voltage drop on the common electrode circuit of the display panel and improving the brightness uniformity of the display panel. At the same time, it reduces the power consumption of the display panel.
  • this embodiment uses the pixel electrode layer as the first auxiliary electrode layer and the source and drain layer as the second auxiliary electrode layer. Resistance, the first auxiliary electrode, the second auxiliary electrode and the common electrode are connected in parallel at the same time to further reduce the resistance on the common electrode line, further reduce the voltage drop on the common electrode line of the display panel, and improve the brightness uniformity of the display panel , The effect of reducing the power consumption of the display panel.
  • the first auxiliary electrode line 152 is connected to the auxiliary bus 153 perpendicular to the direction of the horizontal fold line at both ends of the horizontal fold line. 153 is then connected to the common electrode 180 through a strip-shaped via 102 parallel to the auxiliary bus 153, so that the first auxiliary electrode 152, the second auxiliary electrode 1373, and the common electrode 180 are connected in parallel at the same time, and the first auxiliary electrode 152 and the second auxiliary electrode After 1373 and the common electrode 180 are connected in parallel, the total sheet resistance will be less than the sheet resistance of the second auxiliary electrode 1373 by 0.04 ⁇ 0.06 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode circuit The resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • this embodiment is first connected to both ends of the first auxiliary electrode line through the auxiliary bus, and then connected to the common electrode through the strip-shaped groove, ensuring that the first auxiliary electrode line is connected to the common electrode.
  • the connection of the electrodes avoids the disconnection between the first auxiliary electrode line and the common electrode due to the via hole; at the same time, the sheet resistance of the auxiliary bus is smaller than that of the common electrode, and the setting of the auxiliary bus further reduces the common electrode line
  • the total resistance of further reduces the voltage drop on the common electrode line of the display panel, further improves the brightness uniformity of the display panel, and further reduces the effect of the power consumption of the display panel.
  • the first auxiliary electrode line 152 is a vertical zigzag line, and the pixel electrode 151 is located in an area between adjacent vertical zigzag lines.
  • the intersecting positions of the first auxiliary electrode line 152 and the second auxiliary electrode line 1373 in the space are connected to each other through the via 103, so that the first auxiliary electrode 152 and the second auxiliary electrode 1373 are connected in parallel .
  • the first auxiliary electrode line 152 is connected to the common electrode 180 through the vias 101 at the two end points of the vertical fold line, so that the first The auxiliary electrode 152, the second auxiliary electrode 1373 and the common electrode 180 are simultaneously connected in parallel.
  • the total sheet resistance will be less than the sheet resistance of the second auxiliary electrode 1373 by 0.04 ⁇ 0.06 ⁇ / ⁇ , which is much smaller than the sheet resistance of the common electrode 180, 5 ⁇ 30 ⁇ / ⁇ , which reduces the resistance on the common electrode circuit, thereby reducing the voltage drop on the common electrode circuit of the display panel and improving the brightness uniformity of the display panel , While reducing the power consumption of the display panel.
  • the first auxiliary electrode line 152 is connected to the auxiliary bus 153 perpendicular to the direction of the vertical fold line at both ends of the vertical fold line,
  • the auxiliary bus 153 is then connected to the common electrode 180 through a strip-shaped via 102 parallel to the auxiliary bus 153, so that the first auxiliary electrode 152, the second auxiliary electrode 1373, and the common electrode 180 are connected in parallel at the same time.
  • the total sheet resistance will be less than the sheet resistance of the second auxiliary electrode 1373 by 0.04 ⁇ 0.06 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode circuit
  • the resistance on the display panel further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • this embodiment is first connected to both ends of the first auxiliary electrode line through the auxiliary bus, and then connected to the common electrode through the strip-shaped groove, ensuring that the first auxiliary electrode line is connected to the common electrode.
  • the connection of the electrodes avoids the disconnection between the first auxiliary electrode line and the common electrode due to the via hole; at the same time, the sheet resistance of the auxiliary bus is smaller than that of the common electrode, and the setting of the auxiliary bus further reduces the common electrode line
  • the total resistance of further reduces the voltage drop on the common electrode line of the display panel, further improves the brightness uniformity of the display panel, and further reduces the effect of the power consumption of the display panel.
  • the first auxiliary electrode line 152 is a grid-type wiring, and the pixel electrode 151 is located in an area enclosed by the grid-type wiring.
  • the intersecting positions of the first auxiliary electrode line 152 and the second auxiliary electrode line 1373 in the space are connected to each other through the via 103 so that the first auxiliary electrode 152 and the second auxiliary electrode 1373 are connected in parallel.
  • the first auxiliary electrode line 152 is on at least two opposite sides, and its end is connected to the common electrode 180 through a via hole.
  • the opposite sides may be two vertical opposite sides, two horizontal opposite sides, two vertical opposite sides and two horizontal opposite sides, which are not limited here.
  • the total sheet resistance will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode line
  • the resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • the first auxiliary electrode line 152 is on at least two opposite sides and is connected to the auxiliary bus 153, and the auxiliary bus 153 is then connected to the common electrode 180 through a strip-shaped via 102 parallel to the auxiliary bus 153, specifically
  • the manner can refer to FIG. 12(c) and FIG. 15(c), so as to achieve the effect of being connected in parallel with the common electrode 180.
  • the opposite sides may be two vertical opposite sides, two horizontal opposite sides, two vertical opposite sides and two horizontal opposite sides, which are not limited here.
  • the total sheet resistance will be less than the sheet resistance of the auxiliary electrode line 152 by 0.1 ⁇ 0.2 ⁇ / ⁇ , and much smaller than the sheet resistance of the common electrode 180 by 5 ⁇ 30 ⁇ / ⁇ , reducing the common electrode line
  • the resistance further reduces the voltage drop on the common electrode line of the display panel, improves the brightness uniformity of the display panel, and reduces the power consumption of the display panel at the same time.
  • an embodiment of the present application also provides a display device, which includes the display panel described in any of the above embodiments, the display panel includes a common electrode layer and an auxiliary electrode layer, the common electrode layer forms a common electrode, and the auxiliary electrode layer pattern An auxiliary electrode line is formed by chemistry, and both ends of the auxiliary electrode line are connected to the common electrode.
  • An embodiment of the present application provides a display device, which includes a display panel.
  • the display panel adds an auxiliary electrode line to make a common electrical signal flow from one end of the common electrode into the auxiliary electrode line, and after flowing through the auxiliary electrode line, flow out from the other end.
  • the common electrode so in the transmission process of the common electric signal, it can be regarded as the common electrode and the auxiliary electrode line in parallel, and because the sheet resistance of the auxiliary electrode line is much smaller than the sheet resistance of the common electrode, the total of the common electrode and the auxiliary electrode line in parallel is The resistance is much smaller than the resistance of the common electrode. Under the same current, the resistance is reduced and the voltage drop is reduced. That is, the embodiment of the present application reduces the voltage drop on the common electrode line of the display panel, thereby improving the brightness uniformity of the display panel , While reducing the power consumption of the display panel.
  • the auxiliary electrode layer is a pixel electrode layer.
  • the pixel electrode layer is patterned to form an auxiliary electrode line, the auxiliary electrode line is a horizontal zigzag line, and the pixel electrode is located in an area between adjacent horizontal zigzag lines.
  • the pixel electrode layer is patterned to form an auxiliary electrode line, the auxiliary electrode line is a vertical zigzag line, and the pixel electrode is located in an area between adjacent vertical zigzag lines.
  • the pixel electrode layer is patterned to form auxiliary electrode lines, the auxiliary electrode lines are grid-type wiring, and the pixel electrode is located in an area surrounded by the grid-type wiring.
  • the distance between the auxiliary electrode line and the pixel electrode is greater than a threshold.
  • the threshold is 2um.
  • the end of the auxiliary electrode line is connected to the common electrode layer through a via hole.
  • the two ends of the auxiliary electrode line are respectively connected to an auxiliary bus line perpendicular to the direction of the auxiliary electrode line.
  • the auxiliary electrode line is connected to the auxiliary bus at at least two opposite sides.
  • the auxiliary bus is connected to the common electrode layer through a strip-shaped via parallel to the auxiliary bus.
  • the two opposite sides are two opposite sides in a lateral direction.
  • the two opposite sides are two opposite sides vertically.
  • the auxiliary electrode layer includes a first auxiliary electrode layer and a second auxiliary electrode layer.
  • the first auxiliary electrode layer is a pixel electrode layer
  • the second auxiliary electrode layer is a source and drain layer
  • the pixel electrode layer is patterned to form a first auxiliary electrode line, and the source and drain layers are patterned to form a second auxiliary electrode line.
  • the intersecting positions of the first auxiliary electrode line and the second auxiliary electrode line in the space are connected to each other through a via hole.
  • the first auxiliary electrode line is a horizontal zigzag line
  • the second auxiliary electrode line is a vertical line parallel to the data line.
  • the first auxiliary electrode line is a vertical zigzag line
  • the second auxiliary electrode line is a vertical line parallel to the data line.
  • the first auxiliary electrode line is a grid-type wiring
  • the second auxiliary electrode line is a vertical wiring parallel to the data line.
  • the end of the first auxiliary electrode line is connected to the common electrode layer through a via hole.
  • the two ends of the first auxiliary electrode line are respectively connected to auxiliary bus lines perpendicular to the direction of the first auxiliary electrode line.
  • the first auxiliary electrode line is connected to the auxiliary bus at at least two opposite sides.
  • the auxiliary bus is connected to the common electrode layer through a strip-shaped via parallel to the auxiliary bus.
  • the present application provides a display panel and a device.
  • the display panel includes a common electrode layer and an auxiliary electrode layer, the common electrode layer forms a common electrode, the auxiliary electrode layer is patterned to form an auxiliary electrode line, and both ends of the auxiliary electrode line are connected to the common electrode;
  • the auxiliary electrode line is added to the display panel, so that the common electric signal flows from one end of the common electrode into the auxiliary electrode line, after flowing through the auxiliary electrode line, and then flows out of the common electrode from the other end, so the common electric signal can be regarded as
  • the common electrode is connected in parallel with the auxiliary electrode line, and because the sheet resistance of the auxiliary electrode line is much smaller than the sheet resistance of the common electrode, the total resistance of the common electrode and auxiliary electrode line in parallel is much smaller than the resistance of the common electrode. Under the same current, The resistance is reduced and the voltage drop is reduced, that is, the embodiment of the present application reduces the voltage drop on the common electrode line of the display panel, thereby improving the brightness uniformity of the display

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Abstract

一种显示面板（10）及显示装置，显示面板（10）通过在显示面板（10）中增加辅助电极线（152、1373），在公共电信号的传输过程中，公共电极（180）与辅助电极线（152、1373）并联，并联后的总电阻远小于公共电极（180）的电阻，在电流相同的情况下，压降减小，降低了显示面板（10）公共电极（180）线路上的压降，进而改善了显示面板（10）的亮度均匀性，同时降低了显示面板（10）的功耗。

Description

显示面板及显示装置 技术领域
本申请涉及显示领域，尤其涉及一种显示面板及显示装置。
 背景技术
显示面板的亮度均匀性作为显示效果的重要判定标准，是显示器件的制造过程中需要严格考虑和控制的。
然而，在显示面板的设计中，由于线路中压降的存在，尤其是公共电极线路压降的存在，影响了显示面板的亮度均匀性，同时也增加显示面板的功耗。
因此，现有显示面板存在线路压降过大的问题，需要解决。
 技术问题
本申请提供一种显示面板及显示装置，以缓解现有显示面板存在线路压降过大的问题。
 技术解决方案
本申请提供一种显示面板，其包括：
公共电极层，形成公共电极；
辅助电极层，图案化形成辅助电极线，所述辅助电极线的两端连接所述公共电极。
在本申请提供的显示面板中，所述辅助电极层为像素电极层，所述像素电极层图案化形成辅助电极线。
在本申请提供的显示面板中，所述辅助电极线为折线型走线，像素电极位于相邻所述折线型走线之间的区域内。
在本申请提供的显示面板中，所述辅助电极线为网格型走线，像素电极位于所述网格型走线围成的区域内。
在本申请提供的显示面板中，所述辅助电极线通过条形过槽与公共电极层连接。
在本申请提供的显示面板中，所述辅助电极线在线的两端，分别和与所述辅助电极线方向垂直的辅助总线连接。
在本申请提供的显示面板中，所述辅助电极线在至少两个对边与辅助总线连接。
在本申请提供的显示面板中，所述辅助电极层包括第一辅助电极层和第二辅助电极层，所述第一辅助电极层为像素电极层，所述第二辅助电极层为源漏极层。
在本申请提供的显示面板中，所述辅助电极层包括第一辅助电极层和第二辅助电极层，所述第一辅助电极层为像素电极层，所述第二辅助电极层为源漏极层。
在本申请提供的显示面板中，所述像素电极层图案化形成第一辅助电极线，所述源漏极层图案化形成第二辅助电极线。
在本申请提供的显示面板中，所述第一辅助电极线为横向折线型走线，所述第二辅助电极线为与数据线平行的竖向走线。
在本申请提供的显示面板中，所述第一辅助电极线为竖向折线型走线，所述第二辅助电极线为与数据线平行的竖向走线。
在本申请提供的显示面板中，所述第一辅助电极线为网格型走线，所述第二辅助电极线为与数据线平行的竖向走线。
在本申请提供的显示面板中，所述第一辅助电极线与所述第二辅助电极线在空间内的交叉位置，通过过孔相互连接。
在本申请提供的显示面板中，所述第一辅助电极线的端点通过过孔与所述公共电极层连接。
在本申请提供的显示面板中，所述第一辅助电极线在线的两端，分别和与所述第一辅助电极线方向垂直的辅助总线连接。
在本申请提供的显示面板中，所述第一辅助电极线在至少两个对边与辅助总线连接。
在本申请提供的显示面板中，所述辅助总线通过条形过槽与所述公共电极层连接。
在本申请提供的显示面板中，所述辅助电极线与像素电极之间的距离大于2um。
同时，本申请还提供一种显示装置，其包括一种显示面板，该显示面板包括：
公共电极层，形成公共电极；
辅助电极层，图案化形成辅助电极线，所述辅助电极线的两端连接所述公共电极。
 有益效果
本申请提供一种显示面板及装置，该显示面板包括公共电极层和辅助电极层，公共电极层形成公共电极，辅助电极层图案化形成辅助电极线，辅助电极线的两端连接公共电极；通过在显示面板中增加辅助电极线，使公共电信号从公共电极的一端流入辅助电极线，流过辅助电极线后，再从另一端流出公共电极，因而公共电信号的传输过程中，可以视为公共电极与辅助电极线并联，又由于辅助电极线的片电阻远小于公共电极的片电阻，因此公共电极与辅助电极线并联后的总电阻远小于公共电极的电阻，在电流相同的情况下，电阻减小，压降减小，即本申请实施例降低了显示面板公共电极线路上的压降，进而改善了显示面板的亮度均匀性，同时降低了显示面板的功耗。
 附图说明
图1为本发明实施例提供的显示面板的第一种膜层结构的剖面示意图。
图2中（a）为本发明实施例提供的显示面板的第一种结构的公共电极层的俯视示意简图。
图2中（b）为本发明实施例提供的显示面板的第一种结构的像素电极层的俯视示意简图。
图2中（c）为本发明实施例提供的显示面板的第一种结构的公共电极层和像素电极层的俯视叠加示意简图。
图3中（a）为本发明实施例提供的显示面板的第二种结构的公共电极层的俯视示意简图。
图3中（b）为本发明实施例提供的显示面板的第二种结构的像素电极层的俯视示意简图。
图3中（c）为本发明实施例提供的显示面板的第二种结构的公共电极层和像素电极层的俯视叠加示意简图。
图4中（a）为图2中（c）11区的局部放大示意图。
图4中（b）为图2中（c）12区的局部放大示意图。
图4中（c）为图3中（c）13区的局部放大示意图。
图5中（a）为本发明实施例提供的显示面板的第三种结构的公共电极层的俯视示意简图。
图5中（b）为本发明实施例提供的显示面板的第三种结构的像素电极层的俯视示意简图。
图5中（c）为本发明实施例提供的显示面板的第三种结构的公共电极层和像素电极层的俯视叠加示意简图。
图6中（a）为本发明实施例提供的显示面板的第四种结构的公共电极层的俯视示意简图。
图6中（b）为本发明实施例提供的显示面板的第四种结构的像素电极层的俯视示意简图。
图6中（c）为本发明实施例提供的显示面板的第四种结构的公共电极层和像素电极层的俯视叠加示意简图。
图7中（a）为本发明实施例提供的显示面板的第五种结构的公共电极层的俯视示意简图。
图7中（b）为本发明实施例提供的显示面板的第五种结构的像素电极层的俯视示意简图。
图7中（c）为本发明实施例提供的显示面板的第五种结构的公共电极层和像素电极层的俯视叠加示意简图。
图8中（a）为本发明实施例提供的显示面板的第六种结构的公共电极层的俯视示意简图。
图8中（b）为本发明实施例提供的显示面板的第六种结构的像素电极层的俯视示意简图。
图8中（c）为本发明实施例提供的显示面板的第六种结构的公共电极层和像素电极层的俯视叠加示意简图。
图9为本发明实施例提供的显示面板的第二种膜层结构的剖面示意图。
图10中（a）为本发明实施例提供的显示面板的第七种结构的公共电极层的俯视示意简图。
图10中（b）为本发明实施例提供的显示面板的第七种结构的像素电极层的俯视示意简图。
图10中（c）为本发明实施例提供的显示面板的第七种结构的源漏极层的俯视示意简图。
图10中（d）为本发明实施例提供的显示面板的第七种结构的公共电极层、像素电极层和源漏极层的俯视叠加示意简图。
图11中（a）为本发明实施例提供的显示面板的第八种结构的公共电极层的俯视示意简图。
图11中（b）为本发明实施例提供的显示面板的第八种结构的像素电极层的俯视示意简图。
图11中（c）为本发明实施例提供的显示面板的第八种结构的源漏极层的俯视示意简图。
图11中（d）为本发明实施例提供的显示面板的第八种结构的公共电极层、像素电极层和源漏极层的俯视叠加示意简图。
图12中（a）为图10中（d）14区的局部放大示意图。
图12中（b）为图10中（d）15区的局部放大示意图。
图12中（c）为图11中（d）16区的局部放大示意图。
图13中（a）为本发明实施例提供的显示面板的第九种结构的公共电极层的俯视示意简图。
图13中（b）为本发明实施例提供的显示面板的第九种结构的像素电极层的俯视示意简图。
图13中（c）为本发明实施例提供的显示面板的第九种结构的源漏极层的俯视示意简图。
图13中（d）为本发明实施例提供的显示面板的第九种结构的公共电极层、像素电极层和源漏极层的俯视叠加示意简图。
图14中（a）为本发明实施例提供的显示面板的第十种结构的公共电极层的俯视示意简图。
图14中（b）为本发明实施例提供的显示面板的第十种结构的像素电极层的俯视示意简图。
图14中（c）为本发明实施例提供的显示面板的第十种结构的源漏极层的俯视示意简图。
图14中（d）为本发明实施例提供的显示面板的第十种结构的公共电极层、像素电极层和源漏极层的俯视叠加示意简图。
图15中（a）为图13中（d）17区的局部放大示意图。
图15中（b）为图13中（d）18区的局部放大示意图。
图15中（c）为图14中（d）19区的局部放大示意图。
图16中（a）为本发明实施例提供的显示面板的第十一种结构的公共电极层的俯视示意简图。
图16中（b）为本发明实施例提供的显示面板的第十一种结构的像素电极层的俯视示意简图。
图16中（c）为本发明实施例提供的显示面板的第十一种结构的源漏极层的俯视示意简图。
图16中（d）为本发明实施例提供的显示面板的第十一种结构的公共电极层、像素电极层和源漏极层的俯视叠加示意简图。
 本发明的实施方式
针对现有显示面板存在阴极线路压降过大的问题，本申请提供一种显示面板及显示装置。
在一种实施例中，本申请提供的显示面板包括：
公共电极层，形成公共电极；
辅助电极层，图案化形成辅助电极线，所述辅助电极线的两端连接所述公共电极。
本申请实施例通过在显示面板中增加辅助电极线，使公共电信号从公共电极的一端流入辅助电极线，流过辅助电极线后，再从另一端流出公共电极，因而公共电信号的传输过程中，可以视为公共电极与辅助电极线并联，又由于辅助电极线的片电阻远小于公共电极的片电阻，因此公共电极与辅助电极线并联后的总电阻远小于公共电极的电阻，在电流相同的情况下，电阻减小，压降减小，即本申请实施例有效降低了显示面板公共电极线路上的压降，进而改善了显示面板的亮度均匀性，同时降低了显示面板的功耗。
在一种实施例中，本申请实施例中提供的显示面板可以是OLED显示面板，也可以是LCD显示面板，在此不做限定。在下面的实施例中，将以OLED显示面板为例，对本申请实施例提供的显示面板做进一步的解释说明。
在一种实施例中，本申请提供的显示面板为OLED显示面板，如图1所示，所述OLED显示面板10包括：
衬底110，包括玻璃衬底和柔性衬底，玻璃衬底为刚性的玻璃材料制成，在于显示面板的最下方；柔性衬底一般为聚酰亚胺、聚对苯二甲酸乙二醇酯等有机聚合物材料，形成于玻璃衬底上。
缓冲层120，用于阻隔水氧进入显示面板10，避免降低显示面板的使用寿命；同时防止杂质粒子扩散到薄膜晶体管中，避免降低漏电流。缓冲层一般采用氮化硅（SiN x）和氧化硅（SiO x）的叠层结构，氮化硅具有较强的离子阻隔能力和很好的水氧隔绝能力，氧化硅与多晶硅的界面润湿性较好，能更好的作为形成有源层的基底材料。
薄膜晶体光层130，包括：有源层，图案化形成有源区131，有源区131掺杂形成有沟道区和掺杂区，有源层的材料一般为非晶硅或多晶硅；第一栅极绝缘层132，覆盖缓冲层120和有源层；第一栅极层，形成于第一栅极绝缘层132上，图案化形成有第一栅极133以及栅极扫描线（未画出）；第二栅极绝缘层134，覆盖第一栅极绝缘层132和第一栅极层；第二栅极层，形成于第二栅极绝缘层134上，图案形成有第二栅极135；层间绝缘层136，覆盖第二栅极绝缘层134和第二栅极层；源漏极层137，形成于层间绝缘层136上，图案化形成有漏极1371、源极1372、数据线（未画出）和电源线（未画出），源漏极层137一般为金属钛/铝/钛（Ti/Al/Ti）的叠层结构，其片电阻为0.04~0.06Ω/□；钝化层138，覆盖层间绝缘层136和源漏极层137。薄膜晶体管层130内的有源层、第一栅极层、第二栅极层、源漏极层共同构成了显示面板的驱动电路。
平坦化层140，形成于钝化层138之上，用于平坦化薄膜晶体管层130，为后续像素电极的制备提供平坦的基底，其材料为有机物。
像素电极层150，形成于平坦化层140上，图案化形成有像素电极151，像素电极151通过平坦化层140和钝化层138内的过孔与源极1372连接；像素电极151一般为氧化铟锡/银/氧化铟锡（ITO/Ag/ITO）的叠层结构，其片电阻为0.1~0.2Ω/□。
像素定义层160，形成于平坦化层140和像素电极层150上，图案化形成有的发光区域，发光区域用于限定像素区域。
发光材料层170，形成于像素定义层160定义的发光区域内，一般包括空穴注入层、空穴传输层、发光层、电子传输层、以及电子注入层。
公共电极层，形成于像素定义层160上且覆盖发光材料层170，公共电极层一般为整面蒸镀在像素定义层160和发光材料层170上，整面蒸镀的公共电极层形成了显示面板的公共电极180；公共电极180的材料为低功函数的金属或合金，最常用的是镁铝合金，其片电阻为5~30Ω/□。
本实施例中的OLED显示面板可以是如图1所示的顶栅结构，也可以是底栅结构；可以是如图3所示的双栅结构，也可以是单栅结构；像素电极可以是连接源极，也可以是连接漏极，在此不做限定。
由于像素电极层150的片电阻为0.1~0.2Ω/□，源漏极层137的片电阻为0.04~0.06Ω/□，均小于公共电极层的片电阻5~30Ω/□。因此，可将像素电极层150、源漏极层137或第一栅极层、第二栅极层同时作为辅助电极层，在所述辅助电极层内增设辅助电极，辅助电极与公共电极并联，用于辅助公共电极传输公共电信号，降低公共电信号传输路径上的电阻，从而降低公共电信号传输过程中在公共电极线路上的压降，进而改善了显示面板的亮度均匀性，同时降低了显示面板的功耗。辅助电极的设置方式不同，辅助电极与公共电极并联后的总电阻不同，从而对显示面板公共电极线路上压降的降低效果也会不同。在以下的实施例中，像素的排列方式为钻石排列；在其他实施例中，像素的排列也可以是其他方式，在此不做限定。
在一种实施例中，辅助电极层为像素电极层，如图1所示，像素电极层还图案化形成辅助电极线152。在下述图2至图8所述的实施例中，像素电极层作为辅助电极层，同时图案化形成有像素电极151和辅助电极线152，为了确保辅助电极线152与像素电极151之间不出现短路的情况，需要设置辅助电极线152与像素电极151之间的距离大于阈值，该阈值一般为2um。
在一种实施例中，如图2至图4所示，辅助电极线152为横向折线型走线，即辅助电极线152为折线型走线，且所述折线型走线的走向为沿显示面板短边的方向，即显示面板中数据线的设置方向；像素电极151位于相邻横向折线型走线之间的区域内。
在一种实施例中，如图2和图4中（b）所示，辅助电极线152在横向折线的两个端点，分别通过过孔101与公共电极180连接，从而达到与公共电极180并联的效果，公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
在另一种实施例中，如图3和图4中（c）所示，辅助电极线152在横向折线的两端，分别和与所述横向折线方向垂直的辅助总线153连接，辅助总线153再通过与辅助总线153平行的条形过槽102与公共电极180连接，从而达到辅助电极线152与公共电极180并联的效果。公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
相比与图2所示的实施例，本实施例通过辅助总线先分别与辅助电极线的两端连接，再通过条形过槽与公共电极连接，确保了辅助电极线与公共电极的连接，避免了辅助电极线与公共电极由于过孔原因造成断接的现象；同时，辅助总线的片电阻小于公共电极的片电阻，辅助总线的设置进一步减小了公共电极线路上的总电阻，进一步降低了显示面板公共电极线路上的压降，进一步改善了显示面板的亮度均匀性，进一步降低显示面板功耗的效果。
在另一种实施例中，如图5和图6所示，辅助电极线152为竖向折线型走线，即辅助电极线152为折线型走线，且所述折线型走线的走向为沿显示面板短边的方向，即显示面板中数据线的设置方向；像素电极151位于相邻所述竖向折线型走线之间的区域内。
在一种实施例中，如图5所示，辅助电极线152在竖向折线的两个端点，分别通过过孔101与公共电极180连接，具体方式可参照图4中（b）所示，从而达到与公共电极180并联的效果，公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
在另一种实施例中，如图6所示，辅助电极线152在竖向折线的两端，分别和与所述竖向折线方向垂直的辅助总线153连接，辅助总线153再通过与辅助总线153平行的条形过槽102与公共电极180连接，具体连接方式可参照图4中（c）所示，从而达到辅助电极线152与公共电极180并联的效果。公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
相比与图5所示的实施例，本实施例通过辅助总线先分别与辅助电极线的两端连接，再通过条形过槽与公共电极连接，确保了辅助电极线与公共电极的连接，避免了辅助电极线与公共电极由于过孔原因造成断接的现象；同时，辅助总线的片电阻小于公共电极的片电阻，辅助总线的设置进一步减小了公共电极线路上的总电阻，进一步降低了显示面板公共电极线路上的压降，进一步改善了显示面板的亮度均匀性，进一步降低显示面板功耗的效果。
在又一种实施例中，如图7和图8所示，辅助电极线152为网格型走线，像素电极151位于网格型走线围成的区域内。
在一种实施例中，如图7所示，辅助电极线152在至少两个对边，其端点通过过孔101与公共电极180连接，具体方式可参照图4中（b）所示，从而达到与公共电极180并联的效果。所述的对边可以是如图7所示的两个横向对边，也可以是两个竖向对边，还可以是两个竖向对边和两个横向对边，在此不做限定。公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
在另一种实施例中，如图8所示，辅助电极线152在至少两个对边，与辅助总线153连接，辅助总线153再通过与辅助总线153平行的条形过槽102与公共电极180连接，具体连接方式可参照图4中（c）所示，从而达到辅助电极线152与公共电极180并联的效果。所述的对边可以是如图8所示的两个竖向对边，也可以是两个横向对边，还可以是两个竖向对边和两个横向对边，在此不做限定。公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
相比与图7所示的实施例，本实施例通过辅助总线先分别与辅助电极线的两端连接，再通过条形过槽与公共电极连接，确保了辅助电极线与公共电极的连接，避免了辅助电极线与公共电极由于过孔原因造成断接的现象；同时，辅助总线的片电阻小于公共电极的片电阻，辅助总线的设置进一步减小了公共电极线路上的总电阻，进一步降低了显示面板公共电极线路上的压降，进一步改善了显示面板的亮度均匀性，进一步降低显示面板功耗的效果。
在一种实施例中，辅助电极层包括第一辅助电极层和第二辅助电极层。第一辅助电极层为像素电极层，第二辅助电极层为源漏极层。如图9所示，像素电极层图案化形成第一辅助电极线152，源漏极层图案化形成第二辅助电极线1273。在下述图9至图16所述的实施例中，像素电极层作为第一辅助电极层，同时图案化形成有像素电极151和辅助电极线152，为了确保辅助电极线152与像素电极151之间不出现短路的情况，需要设置辅助电极线152与像素电极151之间的距离大于阈值，该阈值一般为2um。源漏极层作为第二辅助电极，同时图案化形成有漏极1371、源极1372、第二辅助电极1373、以及数据线和电源线（未画出），由于数据线和电源线均为竖向走线，因此第二辅助电极线1373为与数据线、电源线平行的竖向走线，与数据线、电源线绝缘。
在一种实施例中，如图10至12所示，第一辅助电极线152为横向折线型走线，像素电极151位于相邻横向折线型走线之间的区域内。如图12中（a）所示，第一辅助电极线152与第二辅助电极线1373在空间内的交叉位置，通过过孔103相互连接，使得第一辅助电极152与第二辅助电极1373并联。
在一种实施例中，如图10和图12中（b）所示，第一辅助电极线152在横向折线的两个端点，分别通过过孔101与公共电极180连接，从而使得第一辅助电极152、第二辅助电极1373和公共电极180同时并联，第一辅助电极152、第二辅助电极1373和公共电极180同时并联之后总的片电阻将小于第二辅助电极1373的片电阻0.04~0.06Ω/□，远远小于公共电极180的片电阻5~30Ω/□，降低了公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
与上文中仅以像素电极层作为辅助电极层相比，本实施例以像素电极层作为第一辅助电极层，源漏极层作为第二辅助电极层，依靠源漏极层材料更小的片电阻，将第一辅助电极、第二辅助电极和公共电极同时并联，更进一步降低公共电极线路上的电阻，更进一步降低了显示面板公共电极线路上的压降，改善了显示面板的亮度均匀性，降低了显示面板功耗的效果。
在另一种实施例中，如图11和图12中（c）所示，第一辅助电极线152在横向折线的两端，和与所述横向折线方向垂直的辅助总线153连接，辅助总线153再通过与辅助总线153平行的条形过槽102与公共电极180连接，从而使得第一辅助电极152、第二辅助电极1373和公共电极180同时并联，第一辅助电极152、第二辅助电极1373和公共电极180同时并联之后总的片电阻将小于第二辅助电极1373的片电阻0.04~0.06Ω/□，远远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
相比与图10所示的实施例，本实施例通过辅助总线先分别与第一辅助电极线的两端连接，再通过条形过槽与公共电极连接，确保了第一辅助电极线与公共电极的连接，避免了第一辅助电极线与公共电极由于过孔原因造成断接的现象；同时，辅助总线的片电阻小于公共电极的片电阻，辅助总线的设置进一步减小了公共电极线路上的总电阻，进一步降低了显示面板公共电极线路上的压降，进一步改善了显示面板的亮度均匀性，进一步降低显示面板功耗的效果。
在另一种实施例中，如图13至15所示，第一辅助电极线152为竖向折线型走线，像素电极151位于相邻竖向折线型走线之间的区域内。如图15中（a）所示，第一辅助电极线152与第二辅助电极线1373在空间内的交叉位置，通过过孔103相互连接，使得第一辅助电极152与第二辅助电极1373并联。
在一种实施例中，如图13和图15中（b）所示，第一辅助电极线152在竖向折线的两个端点，分别通过过孔101与公共电极180连接，从而使得第一辅助电极152、第二辅助电极1373和公共电极180同时并联，第一辅助电极152、第二辅助电极1373和公共电极180同时并联之后总的片电阻将小于第二辅助电极1373的片电阻0.04~0.06Ω/□，远远小于公共电极180的片电阻5~30Ω/□，降低了公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
在另一种实施例中，如图14和图15中（c）所示，第一辅助电极线152在竖向折线的两端，和与所述竖向折线方向垂直的辅助总线153连接，辅助总线153再通过与辅助总线153平行的条形过槽102与公共电极180连接，从而使得第一辅助电极152、第二辅助电极1373和公共电极180同时并联，第一辅助电极152、第二辅助电极1373和公共电极180同时并联之后总的片电阻将小于第二辅助电极1373的片电阻0.04~0.06Ω/□，远远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
相比与图13所示的实施例，本实施例通过辅助总线先分别与第一辅助电极线的两端连接，再通过条形过槽与公共电极连接，确保了第一辅助电极线与公共电极的连接，避免了第一辅助电极线与公共电极由于过孔原因造成断接的现象；同时，辅助总线的片电阻小于公共电极的片电阻，辅助总线的设置进一步减小了公共电极线路上的总电阻，进一步降低了显示面板公共电极线路上的压降，进一步改善了显示面板的亮度均匀性，进一步降低显示面板功耗的效果。
在又一种实施例中，如图16所示，第一辅助电极线152为网格型走线，像素电极151位于网格型走线围成的区域内。第一辅助电极线152与第二辅助电极线1373在空间内的交叉位置，通过过孔103相互连接，使得第一辅助电极152与第二辅助电极1373并联。
在在一种实施例中，第一辅助电极线152在至少两个对边，其端点通过过孔与公共电极180连接，具体方式可参照图12中（b）和图15中（b）所示，从而达到与公共电极180并联的效果。所述的对边可以是两个竖向对边，也可以是两个横向对边，还可以是两个竖向对边和两个横向对边，在此不做限定。公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
在另一种实施例中，第一辅助电极线152在至少两个对边，与辅助总线153连接，辅助总线153再通过与辅助总线153平行的条形过槽102与公共电极180连接，具体方式可参照图12中（c）和图15中（c）所示，从而达到与公共电极180并联的效果。所述的对边可以是两个竖向对边，也可以是两个横向对边，还可以是两个竖向对边和两个横向对边，在此不做限定。公共电极180和辅助电极线152并联之后总的片电阻将小于辅助电极线152的片电阻0.1~0.2Ω/□，远小于公共电极180的片电阻5~30Ω/□，降低公共电极线路上的电阻，进而达到了降低显示面板公共电极线路上的压降，改善显示面板的亮度均匀性，同时降低显示面板功耗的效果。
同时，本申请实施例还提供一种显示装置，其包括上述实施例中任一所述的显示面板，该显示面板包括公共电极层和辅助电极层，公共电极层形成公共电极，辅助电极层图案化形成辅助电极线，辅助电极线的两端连接公共电极。
本申请实施例提供一种显示装置，其包括显示面板，该显示面板通过增加辅助电极线，使公共电信号从公共电极的一端流入辅助电极线，流过辅助电极线后，再从另一端流出公共电极，因而公共电信号的传输过程中，可以视为公共电极与辅助电极线并联，又由于辅助电极线的片电阻远小于公共电极的片电阻，因此公共电极与辅助电极线并联后的总电阻远小于公共电极的电阻，在电流相同的情况下，电阻减小，压降减小，即本申请实施例降低了显示面板公共电极线路上的压降，进而改善了显示面板的亮度均匀性，同时降低了显示面板的功耗。
在一种实施例中，辅助电极层为像素电极层。
在一种实施例中，像素电极层图案化形成辅助电极线，辅助电极线为横向折线型走线，像素电极位于相邻横向折线型走线之间的区域内。
在一种实施例中，像素电极层图案化形成辅助电极线，辅助电极线为竖向折线型走线，像素电极位于相邻所述竖向折线型走线之间的区域内。
在一种实施例中，像素电极层图案化形成辅助电极线，辅助电极线为网格型走线，像素电极位于网格型走线围成的区域内。
在一种实施例中，辅助电极线与所述像素电极之间的距离大于阈值。
在一种实施例中，阈值为2um。
在一种实施例中，辅助电极线的端点通过过孔与公共电极层连接。
在一种实施例中，辅助电极线在线的两端，分别和与辅助电极线方向垂直的辅助总线连接。
在一种实施例中，辅助电极线在至少两个对边与辅助总线连接。
在一种实施例中，辅助总线通过与辅助总线平行的条形过槽与公共电极层连接。
在一种实施例中，两个对边为横向的两个对边。
在一种实施例中，两个对边为竖向的两个对边。
在一种实施例中，辅助电极层包括第一辅助电极层和第二辅助电极层。
在一种实施例中，第一辅助电极层为像素电极层，第二辅助电极层为源漏极层。
在一种实施例中，像素电极层图案化形成第一辅助电极线，源漏极层图案化形成第二辅助电极线。
在一种实施例中，第一辅助电极线与第二辅助电极线在空间内的交叉位置，通过过孔相互连接。
在一种实施例中，第一辅助电极线为横向折线型走线，第二辅助电极线为与数据线平行的竖向走线。
在一种实施例中，第一辅助电极线为竖向折线型走线，第二辅助电极线为与数据线平行的竖向走线。
在一种实施例中，第一辅助电极线为网格型走线，第二辅助电极线为与数据线平行的竖向走线。
在一种实施例中，第一辅助电极线的端点通过过孔与公共电极层连接。
在一种实施例中，第一辅助电极线在线的两端，分别和与第一辅助电极线方向垂直的辅助总线连接。
在一种实施例中，第一辅助电极线在至少两个对边与辅助总线连接。
在一种实施例中，辅助总线通过与辅助总线平行的条形过槽与公共电极层连接。
根据上述实施例可知：
本申请提供一种显示面板及装置，该显示面板包括公共电极层和辅助电极层，公共电极层形成公共电极，辅助电极层图案化形成辅助电极线，辅助电极线的两端连接公共电极；通过在显示面板中增加辅助电极线，使公共电信号从公共电极的一端流入辅助电极线，流过辅助电极线后，再从另一端流出公共电极，因而公共电信号的传输过程中，可以视为公共电极与辅助电极线并联，又由于辅助电极线的片电阻远小于公共电极的片电阻，因此公共电极与辅助电极线并联后的总电阻远小于公共电极的电阻，在电流相同的情况下，电阻减小，压降减小，即本申请实施例降低了显示面板公共电极线路上的压降，进而改善了显示面板的亮度均匀性，同时降低了显示面板的功耗。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：
    公共电极层，形成公共电极；
    辅助电极层，图案化形成辅助电极线，所述辅助电极线的两端连接所述公共电极。
  2. 如权利要求1所述的显示面板，其中，所述辅助电极层为像素电极层，所述像素电极层图案化形成辅助电极线。
  3. 如权利要求2所述的显示面板，其中，所述辅助电极线为折线型走线，像素电极位于相邻所述折线型走线之间的区域内。
  4. 如权利要求2所述的显示面板，其中，所述辅助电极线为网格型走线，像素电极位于所述网格型走线围成的区域内。
  5. 如权利要求2所述的显示面板，其中，所述辅助电极线的端点通过过孔与公共电极层连接。
  6. 如权利要求3所述的显示面板，其中，所述辅助电极线在线的两端，分别和与所述辅助电极线方向垂直的辅助总线连接。
  7. 如权利要求4所述的显示面板，其中，所述辅助电极线在至少两个对边与辅助总线连接。
  8. 如权利要求2所述的显示面板，其中，所述辅助电总线通过条形过槽与公共电极层连接。
  9. 如权利要求1所述的显示面板，其中，所述辅助电极层包括第一辅助电极层和第二辅助电极层，所述第一辅助电极层为像素电极层，所述第二辅助电极层为源漏极层。
  10. 如权利要求9所述的显示面板，其中，所述像素电极层图案化形成第一辅助电极线，所述源漏极层图案化形成第二辅助电极线。
  11. 如权利要求10所述的显示面板，其中，所述第一辅助电极线为横向折线型走线，所述第二辅助电极线为与数据线平行的竖向走线。
  12. 如权利要求10所述的显示面板，其中，所述第一辅助电极线为竖向折线型走线，所述第二辅助电极线为与数据线平行的竖向走线。
  13. 如权利要求10所述的显示面板，其中，所述第一辅助电极线为网格型走线，所述第二辅助电极线为与数据线平行的竖向走线。
  14. 如权利要求10所述的显示面板，其中，所述第一辅助电极线与所述第二辅助电极线在空间内的交叉位置，通过过孔相互连接。
  15. 如权利要求10所述的显示面板，其中，所述第一辅助电极线的端点通过过孔与所述公共电极层连接。
  16. 如权利要求10所述的显示面板，其中，所述第一辅助电极线在线的两端，分别和与所述第一辅助电极线方向垂直的辅助总线连接。
  17. 如权利要求13所述的显示面板，其中，所述第一辅助电极线在至少两个对边与辅助总线连接。
  18. 如权利要求16所述的显示面板，其中，所述辅助总线通过条形过槽与所述公共电极层连接。
  19. 如权利要求1所述的显示面板，其中，所述辅助电极线与像素电极之间的距离大于2um。
  20. 一种显示装置，包括显示面板，所述显示面板包括：
    公共电极层，形成公共电极；
    辅助电极层，图案化形成辅助电极线，所述辅助电极线的两端连接所述公共电极。
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