WO2021180122A1 - 半导体结构及其形成方法、激光熔丝的熔断方法 - Google Patents

半导体结构及其形成方法、激光熔丝的熔断方法 Download PDF

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WO2021180122A1
WO2021180122A1 PCT/CN2021/079973 CN2021079973W WO2021180122A1 WO 2021180122 A1 WO2021180122 A1 WO 2021180122A1 CN 2021079973 W CN2021079973 W CN 2021079973W WO 2021180122 A1 WO2021180122 A1 WO 2021180122A1
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layer
metal
laser fuse
laser
fuse
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PCT/CN2021/079973
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English (en)
French (fr)
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吴桐
徐亚超
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长鑫存储技术有限公司
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Priority to EP21768396.0A priority Critical patent/EP4089727A4/en
Priority to KR1020227028936A priority patent/KR20220131383A/ko
Priority to JP2022551008A priority patent/JP2023515550A/ja
Priority to US17/443,820 priority patent/US20210358846A1/en
Publication of WO2021180122A1 publication Critical patent/WO2021180122A1/zh

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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its forming method, and a method for fusing a laser fuse.
  • a DRAM chip manufactured by a semiconductor process will inevitably produce defective memory cells, and a DRAM chip usually has redundant memory cells.
  • the redundant memory cells are used to permanently replace the defective memory cells to repair the DRAM chip.
  • the common method is to form some fusible connection lines in the integrated circuit, that is, the fuse structure.
  • the fuse structure When the chip production is completed, if some of the memory cells or circuits have functional problems, they can be selectively fused. (Or destroy) the fuse structure related to the defective circuit, and at the same time activate the redundant memory cell to form a new circuit for replacement, achieving the purpose of repair.
  • the laser fuse is a commonly used fuse structure.
  • the fuse is blown by a laser beam, which changes the circuit structure.
  • it is necessary to accurately locate the position of the fuse.
  • the technical problem to be solved by this application is to provide a semiconductor structure and a method for forming the semiconductor structure and a method for fusing laser fuse to reduce laser alignment deviation during laser fusing.
  • the present application provides a semiconductor structure, including: a semiconductor substrate; an interlayer dielectric layer located above the semiconductor substrate, and at least two metal interconnection layers located in the interlayer dielectric layer;
  • the laser fuse is located in any metal interconnection layer above the underlying metal interconnection layer; metal islands are located in the metal interconnection layers below the laser fuse, and metal islands in different metal interconnection layers pass between
  • the conductive contact holes are connected to form two conductive paths, the laser fuse is connected in series with the two conductive paths through the conductive contact hole; the alignment mark is located in the same metal interconnection layer as the laser fuse, as The marking of laser alignment when the laser fuse is fused.
  • the conductive contact hole and the metal island are critical for the cross-section of the conductive contact hole and the metal island in a direction parallel to the surface of the semiconductor substrate.
  • the size increases layer by layer.
  • the projection of any layer of conductive contact holes/metal islands on the semiconductor substrate is located within the projection of the upper layer of conductive contact holes/metal islands on the semiconductor substrate.
  • the interlayer dielectric layer has a first barrier layer flush with the top surface of the metal island.
  • the interlayer dielectric layer further has a second barrier layer located on the surface of the first barrier layer surrounding the bottom of the conductive contact hole.
  • the surface of the laser fuse and the alignment mark is covered with a protective layer.
  • it further includes: a top dielectric layer covering the interlayer dielectric layer, a fuse window located above the laser fuse and the alignment mark is formed in the top dielectric layer, and the bottom of the fuse window is connected to A dielectric material with a partial thickness between the laser fuse and the alignment mark surface serves as the protective layer on the laser fuse and the alignment mark surface.
  • the protective layer includes at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • the thickness of the protective layer is 20 nm to 200 nm.
  • the laser fuse is connected to a single metal island through one or more conductive contact holes.
  • the technical solution of the present application also provides a method for forming a semiconductor structure, including: providing a semiconductor substrate; forming an interlayer dielectric layer above the semiconductor substrate and at least two metal interconnections located in the interlayer dielectric layer
  • the layer includes: forming a laser fuse in any metal interconnection layer above the underlying metal interconnection layer, and metal islands located in each metal interconnection layer below the laser fuse, and different metal interconnection layers
  • the metal islands are connected by conductive contact holes to form two conductive paths.
  • the laser fuse is connected in series with the two conductive paths through the conductive contact hole; and the laser fuse is also formed in the same metal interconnection layer as the laser fuse.
  • the alignment mark is used as a laser alignment mark when the laser fuse is blown.
  • the conductive contact hole and the metal island are critical for the cross-section of the conductive contact hole and the metal island in a direction parallel to the surface of the semiconductor substrate.
  • the size increases layer by layer.
  • the projection of any layer of conductive contact holes/metal islands on the semiconductor substrate is located within the projection of the upper layer of conductive contact holes/metal islands on the semiconductor substrate.
  • the interlayer dielectric layer has a first barrier layer flush with the top surface of the metal island as an etch stop layer for forming the through hole of the conductive contact hole in the upper layer; the interlayer dielectric The layer also has a second barrier layer disposed on the surface of the first barrier layer around the bottom of the conductive contact hole.
  • the method further includes: forming a top dielectric layer covering the interlayer dielectric layer; etching the top dielectric layer to form a fuse window located above the laser fuse and the alignment mark, the fuse window A dielectric material with a partial thickness between the bottom, the laser fuse and the alignment mark surface serves as the protective layer covering the laser fuse and the alignment mark surface.
  • one or more conductive contact holes are formed between the laser fuse and a single metal island.
  • the technical solution of the present application also provides a method for fusing a laser fuse in a semiconductor structure.
  • the semiconductor structure is as described in any one of the above, including: using the alignment mark to align the laser to the fusing position, and using the laser
  • the laser fuse is fused to disconnect the two conductive paths, wherein, during the fusing process, the laser fuse and the metal islands and conductive contact holes in the conductive path below are all laser fused .
  • the alignment mark and the laser fuse are formed in the same metal interconnection layer, and the fuse window used for laser fusing will not expose the alignment mark, thereby avoiding the exposure of the alignment mark.
  • the deformation and other problems of the laser beam can avoid or reduce the deviation of the laser alignment.
  • the critical dimensions of the conductive contact hole and the metal island along the cross section in a direction parallel to the surface of the semiconductor substrate Increased layer by layer, so that the projection of any layer of conductive contact hole/metal island on the semiconductor substrate is located within the projection of the upper conductive contact hole/metal island on the semiconductor substrate; during the fusing process, laser alignment can be reduced It is difficult, and during the fusing process, there is no dielectric material between the metal layers, which can reduce the required laser energy, thereby reducing power consumption.
  • FIG. 1 is a schematic diagram of a laser fuse structure according to an embodiment of the application
  • FIGS. 2a to 2d are structural schematic diagrams of a semiconductor structure according to an embodiment of the application.
  • 3a to 3c are structural schematic diagrams of a semiconductor structure according to an embodiment of the application.
  • 4a to 4b are schematic structural diagrams of a semiconductor structure according to an embodiment of the application.
  • the laser alignment deviation often occurs during the fusing process of the laser fuse, which leads to the failure of the fuse fusing, and the problem that the circuit repair fails.
  • the inventor found that the reason for the deviation of laser alignment is that the alignment mark cannot be accurately marked due to corrosion due to exposure to the air. The specific explanation is as follows:
  • FIG. 1 is a schematic diagram of a laser fuse structure according to an embodiment of the application.
  • the laser fuse 101 is located in the first metal interconnection layer above the semiconductor substrate, and the alignment mark 102 is located in the second metal interconnection layer.
  • the first metal interconnection layer is a bottom metal interconnection layer formed on the surface or inside of the interlayer dielectric layer 120 above the semiconductor substrate (not shown in the figure), and is formed by directly connecting to the semiconductor substrate through a conductive contact (CT) 121 Of semiconductor devices.
  • CT conductive contact
  • a laser fuse is formed in the first metal interconnection layer, so that the connection line between the laser fuse 101 and the semiconductor device is the shortest, and the resistance is low. After fusing, the connection circuit between different devices can be significantly changed, so that the fuse programming The effect is better.
  • the alignment mark 102 is formed in the second metal interconnection layer, or may also be formed in the upper metal interconnection layer.
  • the laser fuse 101 In order to laser fuse the laser fuse 101, it is necessary to form a fuse window 110 on the surface of the laser fuse 101, and the bottom of the fuse window 110 needs to stay above the metal fuse 101, and only a small thickness is retained above the metal fuse 101. ⁇ 111 ⁇ Layer protection layer 111.
  • the fuse window 110 When the fuse window 110 is formed, the surface of the alignment mark 102 in the second metal interconnection layer is exposed.
  • the second metal interconnection layer and the above metal interconnection layers are all made of Cu process. Because Cu is exposed to the air, it is prone to corrosion and serious corrosion. At this time, the alignment mark 102 pattern will be deformed or unclear, which will cause the laser alignment to shift.
  • the inventor proposes a new semiconductor structure and its forming method and a method of fusing a laser fuse to solve the above-mentioned problems.
  • the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
  • FIGS. 2a to 2d are schematic cross-sectional side views of the formation process of the semiconductor structure according to an embodiment of the application. Specifically, only a single laser fuse structure in the laser fuse structure array is shown in the semiconductor structure.
  • a semiconductor substrate (not shown in the figure) is provided, a first dielectric layer 201 is formed on the surface of the semiconductor substrate, and a semiconductor device connected to the semiconductor substrate is formed in the first dielectric layer 201
  • the conductive plug 2011 may be metal materials such as tungsten, copper, or silver.
  • a second dielectric layer 202 is formed on the first dielectric layer 201, and a metal island 2021 located in the second dielectric layer 202 is formed.
  • the metal island 2021 may be formed by a single damascene process. In fact, this step forms a bottom metal interconnection layer in the second dielectric layer 202, and the bottom metal layer is used to directly form an electrical connection with the device in the semiconductor substrate through the conductive plug 2011, and the metal The island 2021 is a part of the bottom metal layer. In other positions of the second dielectric layer 202, structures such as metal interconnection lines are also formed.
  • the bottom metal layer can be formed by a single damascene process, or after forming a metal material layer covering the first dielectric layer 201, patterning the metal material layer to form the bottom metal interconnection layer, and then Then, a dielectric material is formed on the first dielectric layer 201 and planarized to form a second dielectric layer 202 that is flush with the surface of the metal island 2021.
  • the cross section of the metal island 2021 may be a plane figure such as a rectangle, a circle, and a polygon.
  • a barrier layer 2022 and a third dielectric layer 203 covering the barrier layer 2022 are formed on the surface of the second dielectric layer 202; conductive contact holes 2032 are formed in the third dielectric layer 203 and located in the The laser fuse 2031 on the conductive contact hole 2032.
  • the bottom of the conductive contact hole 2032 penetrates the barrier layer 2022 and is located on the surface of the metal island 2021, and connects the metal island 2021 and the laser fuse 2031.
  • the laser fuse 2031 connects two metals through the conductive contact hole 2032.
  • the island 2021 connects the two conductive paths where the two metal islands 2021 are located. The two conductive paths can be disconnected by laser fusing the laser fuse 2031.
  • the laser fuse 2031 is located in the second metal interconnection layer above the bottom metal interconnection layer, and other metal interconnections may also be formed in the second metal interconnection layer at the same time.
  • an alignment mark 2033 is also formed in the second-level metal interconnection layer. The alignment mark 2033 is used to mark the position of the laser fuse 2031, and is used in the process of laser fusing. Realize the alignment of the laser fuse position.
  • the laser fuse 2031 and the conductive contact hole 2031 may be formed by a double damascene process. Specifically, a through hole and a groove located above the through hole are formed in the second dielectric layer 203, and then the Through holes and grooves, the conductive contact holes 2031 are formed in the through holes, and the laser fuse 2031 is formed in the grooves.
  • the alignment mark may be formed by a single damascene process.
  • the laser fuse 2031, the conductive contact hole 2032, and the alignment mark 2033 can be made of metal materials such as tungsten, copper, or silver.
  • a metal barrier layer may be formed between the laser fuse 2031, the conductive contact hole 2032, the alignment mark 2033 and the second dielectric layer 203 to avoid the diffusion of atoms in the metal material.
  • the material of the metal barrier layer may be at least one of TiN and TaN.
  • the conductive contact hole 2032 is located on the surface of the metal island 2021, and the cross-sectional size is smaller than the size of the top surface of the metal island 2021.
  • the barrier layer 2022 also covers part of the surface of the metal island 2021, which can avoid the metal island 2021.
  • the material of 2021 undergoes electromigration in the contact surface between the metal island 2021 and the second dielectric layer 203 or diffuses into the second dielectric layer 203.
  • the material of the barrier layer 2022 may be SiN, SiON, SiCN, etc.
  • the material of the first dielectric layer 201, the second dielectric layer 202, and the third dielectric layer 203 may be silicon oxide, oxynitride, etc.
  • Silicon and silicon oxycarbide are commonly used interlayer dielectric materials in integrated circuit support, or they can also be low-K dielectric materials such as amorphous carbon and porous silicon oxide.
  • the conductive contact hole 2032 and the conductive plug 2011 overlap in the vertical direction.
  • the conductive contact hole 2032 and the conductive plug 2011 are shown at the same time. It clearly indicates the conductive path formed by the conductive contact hole 2032, the metal island 2021, and the conductive plug 2011, but does not limit the conductive contact hole 2032 and the conductive plug 2011 to overlap in the vertical direction.
  • the positions of the conductive contact holes 2032 and the conductive plugs 2011 may be staggered, so that the conductive contact holes 2032 and the conductive plugs 2011 cannot appear in the same schematic cross-sectional view. Inside.
  • the conductive contact holes all refer to vertical interconnection structures used to connect the upper and lower metal interconnection layers, and the conductive plugs are the vertical interconnections connecting the first metal interconnection layer and the semiconductor substrate.
  • the connection structure, the conductive contact hole and the conductive plug are usually columnar. Although the names of the two are different, they both refer to a vertical interconnection structure.
  • FIG. 3a is a schematic diagram of the projection of each part of the laser fuse structure of the semiconductor structure on the surface of the semiconductor substrate in another embodiment; also refer to FIG. 3B, which shows the laser fuse structure along the line A- in FIG. 3a A schematic cross-sectional view in the direction of A'; FIG. 3c is a schematic cross-sectional view of the laser fuse structure along the direction B-B' in FIG. 3a.
  • FIGS. 3a to 3c only the laser fuse in the semiconductor structure and the conductive path connected thereto are shown, and the interlayer dielectric layer surrounding the conductive path is omitted.
  • the laser fuse structure includes a conductive plug 3011, a metal island 3021, a conductive contact hole 3032, and a laser fuse 3031.
  • the conductive contact hole 3032 and the conductive plug 3011 are staggered in the vertical direction, and there is no overlap.
  • a barrier layer 2041 covering the second dielectric layer 203 and a fourth dielectric layer 204 on the surface of the barrier layer 2041 are sequentially formed; the fourth dielectric layer 204 is etched to form the laser
  • the fuse 2031 and the fuse window 2042 above the alignment mark 2033, the bottom of the fuse window 2042 and the laser fuse 2031 and the surface of the alignment mark 2033 have a partial thickness of a dielectric material that covers the The protective layer on the surface of the laser fuse 2031 and the alignment mark 2033.
  • the protective layer can protect the laser fuse 2031 and the alignment mark 2033.
  • the laser fuse 2031 needs to be blown, the laser fuse 2031 is blown directly through the fuse window 2042.
  • the thickness of the protective layer on the surface of the laser fuse 2031 is small, so that the protective layer is in a transparent state.
  • the laser fuse 2031 can be aligned through the alignment mark 2033. Since the surface of the alignment mark 2033 is covered with a protective layer, the alignment mark 2033 can be prevented from being oxidized or damaged and deformed, thereby avoiding the problem of laser beam deviation when the laser is fused.
  • the protective layer includes a barrier layer 2041 and a dielectric layer of a part of the thickness remaining after etching the fourth dielectric layer 204 on the barrier layer 2041.
  • the barrier layer 2041 may be used as an etch stop layer, so that the laser fuse 2031 and the alignment mark 2033 are only covered with the barrier layer 2041 as a protective layer .
  • the timing of stopping the etching of the fourth dielectric layer 204 is easier to control, and the thickness of the protective layer is only determined by the thickness of the barrier layer 2041.
  • Two different materials can be selected as the barrier layer 2041 and the fourth dielectric layer 204, so that during the etching process of the dielectric layer 204, the fourth dielectric layer 204 and the barrier layer 2041 have a higher etching selection ratio.
  • the barrier layer 2041 is also used to prevent the materials of the laser fuse 2031 and the alignment mark 2033 from diffusing into the fourth dielectric layer 204.
  • the material of the barrier layer 2041 may be silicon nitride, silicon carbonitride, etc.
  • the material of the fourth dielectric layer 204 may be silicon oxide, silicon oxynitride, silicon oxycarbide, or other integrated circuit support.
  • the commonly used interlayer dielectric layer material in the film may also be low-K dielectric materials such as amorphous carbon, porous silicon oxide, etc.
  • the first dielectric layer 201, the second dielectric layer 202, the third dielectric layer 203, the fourth dielectric layer 204, and the barrier layers 2041, 2022 are all used as interlayer dielectric layers or interlayers above the semiconductor substrate. A part of the dielectric layer is used to isolate the metal layers and the interlayer interconnection structure.
  • the laser fuse 2031 and the single metal island 2021 are only connected by a single conductive contact hole 2032; in other embodiments, the area of the laser fuse and the metal island is larger.
  • the number of conductive contact holes can be increased, so that the laser fuse and a single metal island are connected through two or more conductive contact holes to reduce the connection resistance between the laser fuse and the metal island , When the laser fuse is blown, the resistance between the two conductive paths changes more significantly.
  • a single metal island 2021 and the devices or circuits in the underlying semiconductor substrate may be connected in a form-fitting manner through two or more conductive plugs, so as to reduce the connection resistance.
  • the laser fuse is formed in the second metal interconnection layer above the semiconductor substrate, and the metal island is formed in the first metal interconnection layer above the semiconductor substrate; and in other embodiments, the The laser fuse can be formed in the second layer above the semiconductor substrate or in any metal layer above the second layer, and metal islands are formed in the multilayer metal layers below the laser fuse layer, through conductive contact holes A conductive path connected in series is formed.
  • the fuse window used for laser fusing will not expose the alignment mark, which can avoid problems such as deformation caused by the exposure of the alignment mark, and avoid Or reduce the deviation of laser alignment.
  • the metal splash generated during the fusing process or the metal diffusion and migration caused by the high temperature may still cause the two conductive paths connected by the laser fuse Short circuit occurs, especially, more and more porous dielectric materials are used as the dielectric layer material between the metal layers.
  • the entire conductive path is usually blown vertically, and the metal on the conductive path is laser fused, so that the metal is completely vaporized at high temperatures. discharge.
  • the inventor has proposed a new semiconductor structure and its forming method.
  • FIG. 4a to FIG. 4b for structural schematic diagrams of the formation process of the semiconductor structure according to another embodiment of the application.
  • a semiconductor substrate (not shown in the figure) is provided.
  • a first dielectric layer 401 is formed on the surface of the semiconductor substrate;
  • a second dielectric layer 402 is formed on the first dielectric layer 401 to cover the The first barrier layer 4021 of the second dielectric layer 402, and the metal island 4022 located in the second dielectric layer 402, the surface of the metal island 4022 is flush with the surface of the first barrier layer 4021;
  • a second barrier layer 4031, a third dielectric layer 403, and a first barrier layer 4032 are sequentially formed on the surface of the first barrier layer 4021 and the metal island 4022.
  • Conductive plugs 4011 connecting semiconductor devices in the semiconductor substrate are formed in the first dielectric layer 401.
  • the material of the conductive plug 4011 may be metal materials such as tungsten, copper, or silver.
  • the formation of a laser fuse structure is taken as an example. Therefore, the first dielectric layer 401 is used as an example to form two conductive plugs 4011, which are respectively used to form two different conductive paths.
  • the metal island 4022 may be formed by a single damascene process, including: after forming the second dielectric layer 402 and the first barrier layer 4021, etching the first barrier layer 4021 and the second dielectric layer 402 to form a groove , Filling the groove with a metal material and performing a planarization treatment to form the metal island 4022. In fact, this step is also used to form a bottom metal interconnection layer in the second dielectric layer 402, and the bottom metal layer is used to directly form electrical connections with the devices in the semiconductor substrate through the conductive plugs 4011.
  • the metal island 4022 is a part of the bottom metal layer, and at other positions of the second dielectric layer 402, structures such as metal interconnection lines are also formed.
  • the second barrier layer 4031 can prevent the metal atoms in the metal island 4022 from diffusing upward to the third dielectric layer 403. In other embodiments, the second barrier layer 4031 may not be formed.
  • the cross-sectional size of the metal island 4022 is larger than the cross-sectional size of the conductive plug 4011, so that the projection of the conductive plug 4011 on the surface of the semiconductor substrate Located in the projection of the metal island 4022 on the semiconductor substrate.
  • a second barrier layer 4031 and a third dielectric layer 403 covering the surface of the first barrier layer 4021 and the metal island 4022 are sequentially formed; a conductive contact hole 4033 is formed in the third dielectric layer 403 and located at the The laser fuse 4032 above the conductive contact hole 4033.
  • the two ends of the laser fuse 4032 are respectively connected to the conductive contact hole 4033, and are connected to the metal island 4022 below through the conductive contact hole 4033.
  • a double damascene process may be used to form the conductive contact hole 4033 and the laser fuse 4032.
  • the cross-sectional size of the conductive contact hole 4033 is larger than the size of the metal island 4022, so that the projection of the metal island 4022 on the surface of the semiconductor substrate is within the projection of the conductive contact hole 4033 on the surface of the semiconductor substrate.
  • the first barrier layer 4021 is used as an etching barrier layer in the process of forming the through hole for forming the conductive contact hole 4033. , Stop the etching process in time to avoid over-etching the second dielectric layer 402.
  • the first barrier layer 4021 and the second barrier layer 4031 are arranged around the top of the metal island 4022 and the bottom of the conductive contact hole 4033, respectively, so as to prevent the metal island 4022 and the conductive contact hole 4033 from being in place. Electromigration or diffusion problems occur at the interface between the second dielectric layer 402 and the third dielectric layer 403.
  • the first barrier layer 4021, 4032 and the second barrier layer 4031 are made of different materials, so that the second barrier layer 4031 and the first barrier layer 4021 have a higher etching selection ratio.
  • the material of the first barrier layer 4021 may be SiN, SiON, SiCN, etc.
  • the material of the second barrier layer 4031 may be SiN, SiON, SiCN, or the like.
  • the laser fuse 4033 is located in the second metal interconnection layer above the semiconductor substrate. In the embodiment of the present application, it further includes an alignment mark 4034 formed in the same layer as the laser fuse 4033.
  • the laser fuse may also be located in the third or higher metal interconnection layer.
  • the conductive connection structure in each conductive path includes a conductive plug, a metal island, and a conductive contact hole, and each conductive connection structure runs in a direction parallel to the surface of the semiconductor substrate.
  • the key dimensions of the upper cross-section increase layer by layer, so that the projection of the conductive connection structure of the lower layer on the semiconductor substrate is within the projection of the conductive connection structure of the upper layer on the semiconductor substrate.
  • any layer is conductive.
  • the projection of the contact hole/metal island on the semiconductor substrate is within the projection of the upper conductive contact hole/metal island on the semiconductor substrate.
  • the critical dimension is the smallest characteristic dimension of the cross section of the conductive connection structure.
  • the critical dimension is the diameter of the cross section; if the cross section is In the case of a rectangle, the key dimension is the width of the graphic.
  • the cross-sectional size of the conductive plug 4011, the metal island 4022, and the conductive contact portion 4033 becomes larger and larger.
  • Subsequent steps may further include forming a protective layer covering the laser fuse 4032, the alignment mark 4034, and the third dielectric layer 403.
  • the method for forming the protective layer includes: forming a top dielectric layer covering the third dielectric layer 403; The top dielectric layer is etched to form a fusing window located above the laser fuse 4032 and the alignment mark 4034, between the bottom of the fusing window and the surface of the laser fuse 4032 and the alignment mark 4034 A dielectric material with a partial thickness is used as the protective layer covering the surface of the laser fuse 4032 and the alignment mark 4034.
  • the sizes of the conductive connection structures such as conductive plugs, metal islands, and conductive contact holes in the conductive path, gradually increase from the bottom up, so that the conductive connection structures overlap each other on the conductive path. In the vertical direction, it is all metal materials.
  • the difficulty of laser alignment can be reduced, and during the fusing process, there is no dielectric material between the metal layers, which can reduce the required laser energy, thereby reducing power consumption.
  • the embodiment of the present application also provides a semiconductor structure, including: a semiconductor substrate; an interlayer dielectric layer located above the semiconductor substrate and at least two metal interconnection layers located in the interlayer dielectric layer; laser melting Wires are located in any metal interconnection layer above the underlying metal interconnection layer, metal islands are located in the metal interconnection layers of the lower layer of the laser fuse, and metal islands in different metal interconnection layers are in conductive contact Holes are connected to form two conductive paths, the laser fuse is connected in series with the two conductive paths through the conductive contact hole; the alignment mark, which is located in the same metal interconnection layer as the laser fuse, serves as the The laser alignment mark when the wire is fused.
  • the protective layer at the bottom of the fuse window formed above the laser fuse and the alignment mark can simultaneously cover the laser fuse and the laser fuse. Alignment marks to avoid exposure, oxidation or damage of alignment marks.
  • FIG. 2d is a schematic cross-sectional structure diagram of a semiconductor structure according to an embodiment of the application.
  • the semiconductor structure includes: a semiconductor substrate (not shown in the figure), a first dielectric layer 201 is formed on the surface of the semiconductor substrate, and a first dielectric layer 201 is formed in the first dielectric layer 201 to connect the semiconductor Conductive plug 2011 of the semiconductor device in the substrate.
  • a second dielectric layer 202 is formed on the first dielectric layer 201, and a metal island 2021 located in the second dielectric layer 202, the metal island 2021 is connected to the conductive plug 2011; the second dielectric A barrier layer 2022 and a third dielectric layer 203 covering the barrier layer 2022 are formed on the surface of the layer 202; a conductive contact hole 2032 and a laser fuse located on the conductive contact hole 2032 are formed in the third dielectric layer 203 2031.
  • the bottom of the conductive contact hole 2032 penetrates the barrier layer 2022 and is located on the surface of the metal island 2021, and connects the metal island 2021 and the laser fuse 2031.
  • the laser fuse 2031 connects the two through the conductive contact hole 2032.
  • the fuse window 2042 located above the laser fuse 2031 and the alignment mark 2033, a dielectric material with a partial thickness between the bottom of the fuse window 2042 and the laser fuse 2031 and the surface of the alignment mark 2033 ,
  • the protective layer covering the surface of the laser fuse 2031 and the alignment mark 2033.
  • the protective layer can protect the laser fuse 2031 and the alignment mark 2033.
  • the laser fuse 2031 needs to be blown, the laser fuse 2031 is blown directly through the fuse window 2031
  • the metal island 2021 is located in the bottom metal interconnection layer on the surface of the semiconductor substrate, and the laser fuse 2031 and the alignment mark 2033 are located in the second layer metal interconnection above the bottom metal interconnection layer. Within the layer.
  • the laser fuse may also be formed in the third layer or any metal interconnection layer above the third layer, underneath the laser fuse through multiple metal islands and conductive contacts between layers The part is connected to the device or circuit in the semiconductor substrate.
  • the conductive plug 2011 and the conductive contact hole 2032 overlap in a direction perpendicular to the surface of the semiconductor substrate; in other embodiments, the conductive plug and the conductive contact hole above it
  • the contact holes or the conductive contact parts of different layers can also be staggered in the vertical direction.
  • the conductive plug 3011 and the conductive contact hole 3032 are staggered in the vertical direction.
  • the protective layer at the bottom of the fuse window 2042 may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • the thickness of the protective layer may be 20 nm to 200 nm.
  • the laser fuse 2031 and the single metal island 2021 are only connected by a single conductive contact hole 2032; in other embodiments, when the laser fuse and the metal island are larger in area , The number of conductive contact holes can be increased, so that the laser fuse and a single metal island can be connected through two or more conductive contact holes to reduce the connection resistance between the laser fuse and the metal island. After the wire is fused, the resistance between the two conductive paths changes more significantly.
  • a single metal island 2021 and the devices or circuits in the underlying semiconductor substrate may be connected in a form-fitting manner through two or more conductive plugs, so as to reduce the connection resistance.
  • FIG. 4b is a schematic diagram of a semiconductor structure according to another embodiment of the application.
  • the semiconductor structure includes: a semiconductor substrate (not shown in the figure), a first dielectric layer 401 is formed on the surface of the semiconductor substrate; a second dielectric layer is formed on the first dielectric layer 401 Layer 402, a first barrier layer 4021 covering the second dielectric layer 402, and a metal island 4022 located in the second dielectric layer 402, the surface of the metal island 4022 is flush with the surface of the first barrier layer 4021 Flat; a second barrier layer 4031 covering the surface of the first barrier layer 4021 and the metal island 4022, a third dielectric layer 403 located on the surface of the second barrier layer 4031, and a third dielectric layer 403 located on the surface
  • Conductive plugs 4011 connecting semiconductor devices in the semiconductor substrate are formed in the first dielectric layer 401.
  • the material of the conductive plug 4011 may be metal materials such as tungsten, copper, or silver.
  • the formation of a laser fuse structure is taken as an example. Therefore, the first dielectric layer 401 is illustrated as having two conductive plugs 4011, which are respectively used to form two different conductive paths.
  • the metal island 4022 is located in the bottom metal layer and is used to directly form an electrical connection with the device in the semiconductor substrate through the conductive plug 4011.
  • the metal island 4022 is a part of the bottom metal layer and is used in the second dielectric At other positions of the layer 402, structures such as metal interconnections are also formed.
  • the second barrier layer 4031 can prevent the metal atoms in the metal island 4022 from diffusing upward to the third dielectric layer 403. In other embodiments, the second barrier layer 4031 may not be provided.
  • the cross-sectional size of the metal island 4022 is larger than the cross-sectional size of the conductive plug 4011, so that the projection of the conductive plug 4011 on the surface of the semiconductor substrate Located in the projection of the metal island 4022 on the semiconductor substrate.
  • the cross-sectional size of the conductive contact hole 4033 is larger than the size of the metal island 4022, so that the projection of the metal island 4022 on the surface of the semiconductor substrate is within the projection of the conductive contact hole 4033 on the surface of the semiconductor substrate.
  • the first barrier layer 4021 is used as an etching barrier layer in the process of forming the through hole for forming the conductive contact hole 4033. , Stop the etching process in time to avoid over-etching the second dielectric layer 402.
  • the first barrier layer 4021 and the second barrier layer 4031 are arranged around the top of the metal island 4022 and the bottom of the conductive contact hole 4033, respectively, so as to prevent the metal island 4022 and the conductive contact hole 4033 from being in place. Electromigration or diffusion problems occur at the interface between the second dielectric layer 402 and the third dielectric layer 403.
  • the laser fuse 4033 is located in the second metal interconnection layer above the semiconductor substrate, and the alignment mark 4034 and the laser fuse 4033 are located in the same metal interconnection layer.
  • the laser fuse and the alignment mark may also be located in the third or higher metal interconnection layer.
  • the key dimensions of the conductive contact hole and the metal island along the cross section parallel to the surface of the semiconductor substrate increase layer by layer. Large, so that the projection of any layer of conductive contact holes/metal islands on the semiconductor substrate is within the projection of the upper layer of conductive contact holes/metal islands on the semiconductor substrate.
  • the semiconductor structure may further include a protective layer covering the laser fuse 4032, the alignment mark 4034, and the third dielectric layer 403, and a fuse window is located above the protective layer.
  • the sizes of the conductive connection structures gradually increase from the bottom up, so that in the conductive path, the conductive connection structures overlap each other.
  • all are metal materials.
  • the embodiment of the present application also provides a method for fusing a laser fuse in a semiconductor structure, which specifically includes: using an alignment mark located in the same metal interconnection layer as the laser fuse to align the laser to the fusing position, and using the laser The laser fuse is blown to disconnect the two conductive paths.
  • the laser fuse and the metal islands and conductive contact holes in the two conductive paths below are both performed. Laser fusing, so that the metal on the conductive path is completely vaporized and discharged at high temperature, improving the fusing effect.
  • the position of the laser beam can be adjusted so that it is always aligned with the metal in the conductive path.
  • the various conductive connection structures overlap each other in the conductive path, all of them are metal materials in the vertical direction. Therefore, the difficulty of laser alignment can be reduced, along the dotted line in Figure 4b.
  • almost no or only a slight movement of the laser beam can cause the metal in the entire conductive path to be fused, and since there is no dielectric material in the on-off path, the required laser energy can be reduced, thereby reducing power consumption.

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Abstract

一种半导体结构及其形成方法，以及激光熔丝熔断方法，所述半导体结构包括：半导体衬底；位于所述半导体衬底上方的层间介质层以及位于所述层间介质层内的至少两层金属互连层；激光熔丝，位于底层金属互连层上方的任一金属互连层内，金属岛，位于所述激光熔丝下层的各金属互连层内，不同金属互连层内的金属岛之间通过导电接触孔连接，形成两条导电通路，所述激光熔丝通过导电接触孔串联所述两条导电通路；对准标记，与所述激光熔丝位于同一金属互连层内，作为对所述激光熔丝进行熔断时的激光对准的标记。所述对准标记与所述激光熔丝位于同一金属互连层内，能够提高激光对准效果。

Description

半导体结构及其形成方法、激光熔丝的熔断方法
相关申请引用说明
本申请要求于2020年03月13日递交的中国专利申请号202010174314.9，申请名为“半导体结构及其形成方法、激光熔丝的熔断方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法、激光熔丝的熔断方法。
背景技术
随着半导体工艺水平的改进以及集成电路复杂度的提高，芯片内器件数量不断增加，而单个元器件如晶体管或存储单元的失效，往往会导致整个集成电路的功能失效。
例如，采用半导体制程制造的DRAM芯片会不可避免的产生缺陷的存储单元，而DRAM芯片上通常会形成有冗余存储单元，利用冗余存储单元去永久替换缺陷存储单元，即可修复DRAM芯片。常见的方法是在集成电路中形成一些可以熔断的连接线，也就是熔丝(fuse)结构，在芯片生产完成时，若其中有部分存储单元或电路出现功能问题，就可以通过选择性地熔断(或破坏)与缺陷电路相关的熔丝结构，同时激活冗余的存储单元以形成新的电路来替换，实现修复的目的。
激光熔丝是一种常用的熔丝结构，通过激光束熔断熔丝，使得电路结构发生变化。在熔断熔丝过程中，需要准确定位熔丝的位置。在芯片上会存在对准标记，通过激光器扫描对准标记从而在芯片上获得熔丝位置的指示。
而现有技术中，激光束经常会出现对准偏差，导致电路修复失败。
发明内容
本申请所要解决的技术问题是，提供一种半导体结构及其形成方法以及激 光熔丝的熔断方法，减少激光熔断过程中的激光对准偏差。
为了解决上述问题，本申请提供了一种半导体结构，包括：半导体衬底；位于所述半导体衬底上方的层间介质层以及位于所述层间介质层内的至少两层金属互连层；激光熔丝，位于底层金属互连层上方的任一金属互连层内；金属岛，位于所述激光熔丝下层的各金属互连层内，不同金属互连层内的金属岛之间通过导电接触孔连接，形成两条导电通路，所述激光熔丝通过导电接触孔串联所述两条导电通路；对准标记，与所述激光熔丝位于同一金属互连层内，作为对所述激光熔丝进行熔断时的激光对准的标记。
可选的，自半导体衬底向上至所述激光熔丝方向上，每一导电通路内，所述导电接触孔及所述金属岛沿平行于所述半导体衬底表面方向上的横截面的关键尺寸逐层增大。
可选的，任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内。
可选的，所述层间介质层内具有与所述金属岛的顶部表面齐平的第一阻挡层。
可选的，所述层间介质层内还具有位于所述第一阻挡层表面环绕导电接触孔底部的第二阻挡层。
可选的，所述激光熔丝和所述对准标记表面覆盖有保护层。
可选的，还包括：覆盖所述层间介质层的顶部介质层，所述顶部介质层内形成有位于所述激光熔丝与所述对准标记上方的熔断窗口，所述熔断窗口底部与所述激光熔丝、所述对准标记表面之间具有部分厚度的介质材料，作为所述激光熔丝和所述对准标记表面的所述保护层。
可选的，所述保护层包括氧化硅层、氮化硅层或氮氧化硅层中的至少一层。
可选的，所述保护层的厚度为20nm～200nm。
可选的，所述激光熔丝与单个金属岛之间通过一个或两个以上的导电接触孔连接。
本申请的技术方案还提供一种半导体结构的形成方法，包括：提供半导体衬底；在所述半导体衬底上方形成层间介质层以及位于所述层间介质层内的至少两层金属互连层，包括：在底层金属互连层上方的任一金属互连层内形成激 光熔丝，以及位于所述激光熔丝下层的各金属互连层内的金属岛，不同金属互连层内的金属岛之间通过导电接触孔连接，形成两条导电通路，所述激光熔丝通过导电接触孔串联所述两条导电通路；还包括形成与所述激光熔丝位于同一金属互连层内的对准标记，所述对准标记作为对所述激光熔丝进行熔断时的激光对准的标记。
可选的，自半导体衬底向上至所述激光熔丝方向上，每一导电通路内，所述导电接触孔及所述金属岛沿平行于所述半导体衬底表面方向上的横截面的关键尺寸逐层增大。
可选的，任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内。
可选的，所述层间介质层内具有与所述金属岛的顶部表面齐平的第一阻挡层，作为形成位于上层的导电接触孔的通孔的刻蚀停止层；所述层间介质层内还具有位于所述第一阻挡层表面环绕导电接触孔底部设置的第二阻挡层。
可选的，还包括：形成覆盖所述层间介质层的顶部介质层；刻蚀所述顶部介质层，形成位于所述激光熔丝与所述对准标记上方的熔断窗口，所述熔断窗口底部与所述激光熔丝、所述对准标记表面之间具有部分厚度的介质材料，作为覆盖所述激光熔丝和所述对准标记表面的所述保护层。
可选的，在所述激光熔丝与单个金属岛之间形成一个或两个以上的导电接触孔。
本申请的技术方案还提供一种半导体结构内的激光熔丝的熔断方法，所述半导体结构如上述任一项所述，包括：利用所述对准标记将激光对准至熔断位置，采用激光对所述激光熔丝进行熔断，以使所述两个导电通路之间断路，其中，所述熔断过程中，将激光熔丝及下方的导电通路内的金属岛及导电接触孔均进行激光熔断。
本申请的半导体结构中，对准标记与激光熔丝形成于同一金属互连层内，用于激光熔断的熔断窗口不会将所述对准标记暴露，从而可以避免由于对准标记暴露而导致的形变等问题，避免或减少激光对准发生偏移。
进一步的，自半导体衬底向上至所述激光熔丝方向上，每一导电通路内，所述导电接触孔及所述金属岛沿平行于所述半导体衬底表面方向上的横截面 的关键尺寸逐层增大，使得任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内；熔断过程中，可以减少激光对准的难度，并且熔断过程中，各金属层之间不夹杂介质材料，能够降低需要的激光能量，从而降低功耗。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例的一种激光熔丝结构的示意图；
图2a至图2d为本申请一实施例的半导体结构的结构示意图；
图3a至图3c为本申请一实施例的半导体结构的结构示意图；
图4a至图4b为本申请一实施例的半导体结构的结构示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如背景技术中所述，激光熔丝熔断过程中经常会出现激光对准偏移而导致熔丝熔断失败，使得电路修复失败的问题。发明人研究发现，出现激光对准偏差的原因，是由于对准标记由于被暴露在空气中发生腐蚀，而无法起到准确的标记作用，具体解释如下：
请参考图1，为本申请一实施例的一种激光熔丝结构的示意图。
该半导体结构中，激光熔丝101位于半导体衬底上方的第一层金属互连层内，而对准标记102则位于第二层金属互连层内。第一金属互连层是半导体衬底(图中未示出)上方的层间介质层120表面或内部形成的底层金属互连层，通过导电接触(CT)121直接连接至半导体衬底内形成的半导体器件。在第一 层金属互连层内形成激光熔丝，使得激光熔丝101与半导体器件之间的连接线路最短，电阻较低，在熔断后能够显著改变不同器件之间的连接电路，使得熔断编程效果较佳。
由于第一层金属互连层内的线宽要求通常较高，金属线排布密度较大，而由于对准的对准标记通常要求尺寸较大，才能够实现较高的对准效果，因此，通常会将对准标记102形成在第二层金属互连层内，或者还可以形成在更上层的金属互连层内。
为了对激光熔丝101进行激光熔断，需要在激光熔丝101表面形成熔断窗口110，所述熔断窗口110底部需要停留在金属熔丝101上方，仅在金属熔丝101上方保留较小厚度的一层保护层111。在形成熔断窗口110的同时，会暴露出第二层金属互连层内的对准标记102表面。在半导体先进制程工艺中，为了降低电阻，提高集成电路的计算效率，第二层金属互连层及以上的金属互连层均采用Cu制程，由于Cu暴露在空气中极易发生腐蚀，腐蚀严重时，会导致对准标记102图形会发生变形或不清晰，从而造成激光对准偏移。
发明人提出了一种新的半导体结构及其形成方法以及激光熔丝的熔断方法，来解决上述问题。下面结合附图对本申请的实施例做详细说明。
请参考图2a至图2d，为本申请一实施例的半导体结构的形成过程的剖面侧视示意图。具体的，所述半导体结构内仅示出了激光熔丝结构阵列内的单个激光熔丝结构。
请参考图2a，提供半导体衬底(图中未示出)，所述半导体衬底表面形成有第一介质层201，所述第一介质层201内形成有连接所述半导体衬底内半导体器件的导电插塞2011。所述导电插塞2011的材料可以为钨、铜或银等金属材料。
请参考图2b，在所述第一介质层201上形成第二介质层202，以及位于所述第二介质层202内的金属岛2021。所述金属岛2021可以采用单大马士革工艺形成。实际上，该步骤在所述第二介质层202内形成底层金属互连层，所述底层金属层用于通过所述导电插塞2011直接与半导体衬底内的器件形成电连接，所述金属岛2021为所述底层金属层的一部分，在第二介质层202的其他位置处，还形成有金属互连线等结构。所述底层金属层可以通过单大马士革工 艺形成，也可以通过形成覆盖所述第一介质层201的金属材料层后，对所述金属材料层进行图形化而形成所述底层金属互连层，然后再在所述第一介质层201上形成介质材料，并进行平坦化处理，形成表面与所述金属岛2021表面齐平第二介质层202。所述金属岛2021的横截面可以为矩形、圆形、多边形等平面图形。
请参考图2c，在所述第二介质层202表面形成阻挡层2022以及覆盖所述阻挡层2022的第三介质层203；在所述第三介质层203内形成导电接触孔2032以及位于所述导电接触孔2032上的激光熔丝2031。
所述导电接触孔2032底部贯穿所述阻挡层2022位于所述金属岛2021表面，连接所述金属岛2021和所述激光熔丝2031，所述激光熔丝2031通过导电接触孔2032连接两个金属岛2021，使得两个所述金属岛2021所在的两个导电通路之间连接。通过激光熔断所述激光熔丝2031即可断开所述两个导电通路。
所述激光熔丝2031位于底层金属互连层上方的第二层金属互连层内，所述第二金属互连层内还可以同时形成有其他金属互连线。该实施例中，在所述第二层金属互连层内还形成有对准标记2033，所述对准标记2033用于标识激光熔丝2031的位置，用于在进行激光熔断的过程中，实现激光熔断位置的对准。
所述激光熔丝2031和所述导电接触孔2031可以通过双大马士革工艺形成，具体的，在所述第二介质层203内形成通孔及位于所述通孔上方的凹槽，然后填充所述通孔和凹槽，在通孔内形成所述导电接触孔2031，在所述凹槽内形成激光熔丝2031。所述对准标记可以通过单大马士革工艺形成。
所述激光熔丝2031、导电接触孔2032以及所述对准标记2033可以采用钨、铜或银等金属材料。较佳的，在所述激光熔丝2031、导电接触孔2032以及所述对准标记2033与所述第二介质层203之间还可以形成有金属阻挡层，以避免金属材料内原子的扩散。所述金属阻挡层的材料可以为TiN、TaN中的至少一种。
所述导电接触孔2032位于所述金属岛2021表面，横截面尺寸小于所述金属岛2021的顶部表面尺寸，所述阻挡层2022还覆盖部分所述金属岛2021的表面，可以避免所述金属岛2021的材料在所述金属岛2021与所述第二介质层 203的接触面内发生电迁移或向所述第二介质层203内发生扩散。
在一些实施例中，所述阻挡层2022的材料可以为SiN、SiON或SiCN等，所述第一介质层201、第二介质层202以及第三介质层203的材料可以为氧化硅、氮氧化硅、碳氧化硅等集成电路支撑中常用的层间介质层材料，或者还可以为无定型碳、多孔氧化硅等等低K介电材料。
该实施例中，所述导电接触孔2032和所述导电插塞2011在竖直方向上有重叠，图2c的剖面示意图内，同时示出了所述导电接触孔2032以及导电插塞2011，以清楚的示意导电接触孔2032、金属岛2021以及导电插塞2011形成的导电通路，但并不限制所述导电接触孔2032以及导电插塞2011在竖直方向上有重叠。在一些实施例中，由于布线规则的限制，所述导电接触孔2032和所述导电插塞2011的位置可能交错分布，使得所述导电接触孔2032以及导电插塞2011无法出现于同一个剖面示意图内。
在本申请的实施例中，导电接触孔均指用于连接上下层金属互连层内的垂直互连结构，所述导电插塞为连接第一层金属互连层与半导体衬底的垂直互连结构，所述导电接触孔和所述导电插塞通常为柱状，虽然两者的命名不同，但是均是指竖直的互连结构。
请参考图3a，为另一实施例中，半导体结构的激光熔丝结构内各个部分在半导体衬底表面的投影示意图；同时参考图3B，为所述激光熔丝结构的沿图3a中A-A’方向的剖面示意图；图3c为所述激光熔丝结构沿图3a中B-B’方向的剖面示意图。图3a至图3c中，仅示出了半导体结构中的激光熔丝及其连接的导电通路，省略了包围所述导电通路的层间介质层。
所述激光熔丝结构包括导电插塞3011、金属岛3021、导电接触孔3032以及激光熔丝3031。所述导电接触孔3032与所述导电插塞3011在竖直方向上相互错开，无重叠。
请继续参考图2d，依次形成覆盖所述第二介质层203的阻挡层2041以及位于所述阻挡层2041表面的第四介质层204；刻蚀所述第四介质层204，形成位于所述激光熔丝2031与所述对准标记2033上方的熔断窗口2042，所述熔断窗口2042底部与所述激光熔丝2031、所述对准标记2033表面之间具有部分厚度的介质材料，作为覆盖所述激光熔丝2031和所述对准标记2033表面的所述 保护层。当不需要对所述激光熔丝2031进行熔断时，所述保护层能够保护所述激光熔丝2031及所述对准标记2033。当需要对所述激光熔丝2031进行熔断时，直接通过所述熔断窗口2042对激光熔丝2031进行熔断。
所述激光熔丝2031表面的保护层的厚度较小，使得所述保护层为透明状态，在进行激光熔断时，能够通过所述对准标记2033对所述激光熔丝2031进行对准。由于所述对准标记2033表面覆盖有保护层，能够避免所述对准标记2033被氧化或受到损伤而产生变形，从而能够避免激光熔断时，激光束发生偏移的问题。
该实施例中，所述保护层包括阻挡层2041和位于所述阻挡层2041上的刻蚀所述第四介质层204后剩余的部分厚度的介质层。
在其他实施例中，在形成熔断窗口2042的过程中，可以以所述阻挡层2041作为刻蚀停止层，使得所述激光熔丝2031以及对准标记2033上仅覆盖有阻挡层2041作为保护层。该实施例中，刻蚀所述第四介质层204的停止时机较容易控制，保护层的厚度仅由所述阻挡层2041的厚度决定。可以选择两种不同的材料作为阻挡层2041和第四介质层204，使得刻蚀所述介质层204的过程中，对第四介质层204和阻挡层2041具有较高的刻蚀选择比。所述阻挡层2041还用于阻挡所述激光熔丝2031以及对准标记2033的材料向所述第四介质层204内扩散。在一些实施例中，所述阻挡层2041的材料可以为氮化硅、碳氮化硅等，所述第四介质层204的材料可以为氧化硅、氮氧化硅、碳氧化硅等集成电路支撑中常用的层间介质层材料，或者还可以为无定型碳、多孔氧化硅等等低K介电材料。
上述实施例中，所述第一介质层201、第二介质层202、第三介质层203、第四介质层204以及阻挡层2041、2022均作为半导体衬底上方的层间介质层或层间介质层内的一部分，用于隔离各金属层及层间互连结构。
在本申请的上述实施例中，所述激光熔丝2031与单个金属岛2021之间仅通过当个导电接触孔2032进行连接；在其他实施例中，在所述激光熔丝以及金属岛面积较大的情况下，可以提高导电接触孔的数量，使得激光熔丝与单个金属岛之间通过两个或两个以上的导电接触孔进行连接，以降低激光熔丝与金属岛之间的连接电阻，当激光熔丝被熔断后，两个导电通路之间的电阻变化更 加显著。同样，也可以使得单个金属岛2021与下方的半导体衬底内的器件或者电路之间通过两个或两个以上的导电插塞进形连接，以降低连接电阻。
上述实施例中，激光熔丝形成于半导体衬底上方的第二层金属互连层内，金属岛形成于半导体衬底上方的第一层金属互连层内；而在其他实施例中，所述激光熔丝可以形成于所述半导体衬底上方的第二层或者第二层上方的任一层金属层内，激光熔丝层下方的多层金属层内均形成金属岛，通过导电接触孔形成上下串联的导电通路。只要对准标记与激光熔丝形成于同一金属层内，那么用于激光熔断的熔断窗口就不会将所述对准标记暴露，从而可以避免由于对准标记暴露而导致的形变等问题，避免或减少激光对准发生偏移。
在激光熔断过程中，如果仅仅是将所述激光熔丝熔断，熔断过程中产生的金属飞溅或设高温导致的金属扩散迁移，依然有可能使得所述激光熔丝连接的两个导电通路之间发生短路，尤其是，越来越多的采用多孔介电材料，作为各金属层间的介质层材料。为了能够使得所述激光熔丝连接的两个导电通路之间彻底断开，通常会将整个导电通路进行垂直熔断，将导电通路上的金属均进行激光融断，使得金属在高温下彻底被汽化排出。虽然，上述实施例解决的激光对准偏移的问题，但是，将激光熔丝设置与第一层或更上层的金属互连层内，会导致激光熔丝与半导体衬底之间的距离增大，激光熔丝连接的导电通路上的导电接触孔、金属岛的数量增加，使得激光熔断需要消耗能量更大；进一步的，由于导电接触孔以及导电插塞的尺寸通常小于金属岛的尺寸，在竖直的激光熔断路径上，各层金属岛之间还存在介质层，而介质层需要消耗更多的激光能量。如于图3b所示的半导体结构，在导电接触孔之间，或者导电接触孔与导电插塞之间位置有偏移的情况下，单一竖直的激光熔断路径无法将导电通路上的金属完全熔断，还需要调整激光光束的位置，使得整个激光熔断过程消耗更多能量，操作也可能更为复杂。
为了进一步改进上述问题，发明人又提出了一种新的半导体结构及其形成方法。
请参考图4a至图4b为本申请另一实施例的半导体结构的形成过程的结构示意图。
请参考图4a，提供半导体衬底(图中未示出)，所述半导体衬底表面形成 有第一介质层401；在所述第一介质层401上形成第二介质层402、覆盖所述第二介质层402的第一阻挡层4021，以及位于所述第二介质层402内的金属岛4022，所述金属岛4022表面与所述第一阻挡层4021的表面齐平；然后，再在所述第一阻挡层4021及所述金属岛4022表面依次形成第二阻挡层4031和第三介质层403以及第一阻挡层4032。
所述第一介质层401内形成有连接所述半导体衬底内半导体器件的导电插塞4011。所述导电插塞4011的材料可以为钨、铜或银等金属材料。该实施例中，以形成一个激光熔丝结构作为示例，因此，所述第一介质层401以形成两个导电插塞4011作为示意，分别用于形成两路不同的导电通路。
所述金属岛4022可以采用单大马士革工艺形成，包括：形成所述第二介质层402和第一阻挡层4021后，刻蚀所述第一阻挡层4021和所述第二介质层402形成凹槽，在所述凹槽内填充金属材料并进行平坦化处理，形成所述金属岛4022。实际上，该步骤同时用于在所述第二介质层402内形成底层金属互连层，所述底层金属层用于通过所述导电插塞4011直接与半导体衬底内的器件形成电连接，所述金属岛4022为所述底层金属层的一部分，在第二介质层402的其他位置处，还形成有金属互连线等结构。
所述第二阻挡层4031能够阻挡所述金属岛4022内的金属原子向上扩散至第三介质层403。在其他实施例中，也可以不形成所述第二阻挡层4031。
该实施例中，在平行于半导体衬底表面的方向上，所述金属岛4022横截面尺寸大于所述导电插塞4011的横截面尺寸，使得所述导电插塞4011在半导体衬底表面的投影位于所述金属岛4022在半导体衬底上的投影内。
请参考图4b，依次形成覆盖所述第一阻挡层4021以及金属岛4022表面的第二阻挡层4031以及第三介质层403；在所述第三介质层403内形成导电接触孔4033以及位于所述导电接触孔4033上方的激光熔丝4032。所述激光熔丝4032两端分别与所述导电接触孔4033连接，通过所述导电接触孔4033连接至下方的金属岛4022。
具体的，可以采用双大马士革工艺，形成所述导电接触孔4033以及所述激光熔丝4032。所述导电接触孔4033的横截面尺寸大于所述金属岛4022的尺寸，使得所述金属岛4022在半导体衬底表面的投影位于所述导电接触孔4033 在半导体衬底表面的投影内。
由于所述导电接触孔4033的尺寸大于所述金属岛4022的尺寸，在刻蚀形成用于形成所述导电接触孔4033的通孔过程中，以所述第一阻挡层4021作为刻蚀阻挡层，及时停止刻蚀的进程，避免对所述第二介质层402造成过刻蚀。所述第一阻挡层4021和所述第二阻挡层4031分别环绕所述金属岛4022的顶部以及所述导电接触孔4033的底部设置，避免所述金属岛4022和所述导电接触孔4033在所述第二介质层402和所述第三介质层403的界面上发生电迁移或扩散问题。
所述第一阻挡层4021、4032和所述第二阻挡层4031采用不同的材料，使得所述第二阻挡层4031和所述第一阻挡层4021之间具有较高的刻蚀选择比。较佳的，所述第一阻挡层4021的材料可以为SiN、SiON或SiCN等，所述第二阻挡层4031的材料可以为SiN、SiON或SiCN等。
所述激光熔丝4033位于半导体衬底上方的第二层金属互连层内，本申请的实施例中，还包括形成与所述激光熔丝4033位于同一层内的对准标记4034。
在其他实施例中，所述激光熔丝还可以位于第三层或者更上层的金属互连层内。
自半导体衬底向上至所述激光熔丝方向上，每一导电通路内的导电连接结结构包括导电插塞、金属岛、导电接触孔，各导电连接结构沿平行于所述半导体衬底表面方向上的横截面的关键尺寸逐层增大，使得下层的导电连接结构在半导体衬底上的投影位于上层导电连接结构在半导体衬底上的投影内，例如，该实施例中，任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内。所述关键尺寸(Critical Dimension)为所述导电连接结构的横截面的最小特征尺寸，例如导电连接结构的横截面为圆形时，所述关键尺寸为横截面的直径；若所述横截面为矩形时，则所述关键尺寸为图形的宽度。如图4b所示，自底部向上，所述导电插塞4011、金属岛4022、导电接触部4033的横截面尺寸越来越大。
后续还可以包括形成覆盖所述激光熔丝4032、对准标记4034以及第三介质层403的保护层，所述保护层的形成方法包括：形成覆盖所述第三介质层403的顶部介质层；刻蚀所述顶部介质层，形成位于所述激光熔丝4032与所述对 准标记4034上方的熔断窗口，所述熔断窗口底部与所述激光熔丝4032、所述对准标记4034表面之间具有部分厚度的介质材料，作为覆盖所述激光熔丝4032和所述对准标记4034表面的所述保护层。
上述实施例中，由于导电通路内，各导电连接结构，例如导电插塞、金属岛、导电接触孔的尺寸自底部向上逐步增大，使得在导电通路上，各个导电连接结构之间相互重叠，在竖直方向上，全部为金属材料，熔断过程中，可以减少激光对准的难度，并且熔断过程中，各金属层之间不夹杂介质材料，能够降低需要的激光能量，从而降低功耗。
本申请的实施例还提供一种半导体结构，包括：半导体衬底；位于所述半导体衬底上方的层间介质层以及位于所述层间介质层内的至少两层金属互连层；激光熔丝，位于底层金属互连层上方的任一金属互连层内，金属岛，位于所述激光熔丝下层的各金属互连层内，不同金属互连层内的金属岛之间通过导电接触孔连接，形成两条导电通路，所述激光熔丝通过导电接触孔串联所述两条导电通路；对准标记，与所述激光熔丝位于同一金属互连层内，作为对所述激光熔丝进行熔断时的激光对准的标记。
由于所述对准标记与所述激光熔丝位于同一金属互连层内，因此在所述激光熔丝和对准标记上方形成的熔断窗口底部的保护层可以同时覆盖所述激光熔丝和对准标记，避免对准标记暴露，被氧化或受到损伤。
请参考图2d，为本申请一实施例的半导体结构的剖面结构示意图。
该实施例中，所述半导体结构包括：半导体衬底(图中未示出)，所述半导体衬底表面形成有第一介质层201，所述第一介质层201内形成有连接所述半导体衬底内半导体器件的导电插塞2011。所述第一介质层201上形成有第二介质层202，以及位于所述第二介质层202内的金属岛2021，所述金属岛2021与所述导电插塞2011连接；所述第二介质层202表面形成有阻挡层2022以及覆盖所述阻挡层2022的第三介质层203；在所述第三介质层203内形成有导电接触孔2032以及位于所述导电接触孔2032上的激光熔丝2031，所述导电接触孔2032底部贯穿所述阻挡层2022位于所述金属岛2021表面，连接所述金属岛2021和所述激光熔丝2031，所述激光熔丝2031通过导电接触孔2032连接两个金属岛2021，使得两个所述金属岛2021所在的两个导电通路之间连接； 覆盖所述第二介质层203表面的阻挡层2041以及位于所述阻挡层2041表面的第四介质层204，位于所述激光熔丝2031与所述对准标记2033上方的熔断窗口2042，所述熔断窗口2042底部与所述激光熔丝2031、所述对准标记2033表面之间具有部分厚度的介质材料，作为覆盖所述激光熔丝2031和所述对准标记2033表面的所述保护层。当不需要对所述激光熔丝2031进行熔断时，所述保护层能够保护所述激光熔丝2031及所述对准标记2033。当需要对所述激光熔丝2031进行熔断时，直接通过所述熔断窗口2042对激光熔丝2031进行熔断。
该实施例中，所述金属岛2021位于半导体衬底表面的底层金属互连层内，所述激光熔丝2031和对准标记2033位于所述底层金属互连层上方的第二层金属互连层内。
在其他实施例中，所述激光熔丝还可以形成于第三层或者第三层以上的任一层金属互连层内，所述激光熔丝下方通过多层金属岛以及层间的导电接触部连接至半导体衬底内的器件或电路。
图2d所示的实施例中，所述导电插塞2011与所述导电接触孔2032在垂直于半导体衬底表面方向上有重叠；在其他实施例中，所述导电插插塞与其上方的导电接触孔或者不同层的导电接触部之间，在竖直方向上也可以交错分布。请参考图3b，导电插塞3011与所述导电接触孔3032在竖直方向上相互错开。
请继续参考图2d，熔断窗口2042底部的保护层可以包括氧化硅层、氮化硅层或氮氧化硅层中的至少一层。所述保护层的厚度可以为20nm～200nm。
该实施例中，所述激光熔丝2031与单个金属岛2021之间仅通过当个导电接触孔2032进行连接；在其他实施例中，在所述激光熔丝以及金属岛面积较大的情况下，可以提高导电接触孔的数量，使得激光熔丝与单个金属岛之间通过两个或两个以上的导电接触孔进行连接，以降低激光熔丝与金属岛之间的连接电阻，当激光熔丝被熔断后，两个导电通路之间的电阻变化更加显著。同样，也可以使得单个金属岛2021与下方的半导体衬底内的器件或者电路之间通过两个或两个以上的导电插塞进形连接，以降低连接电阻。
请参考图4b，为本申请另一实施例的半导体结构的示意图。
该实施例中，所述半导体结构包括：半导体衬底(图中未示出)，所述半导体衬底表面形成有第一介质层401；在所述第一介质层401上形成有第二介质层402、覆盖所述第二介质层402的第一阻挡层4021，以及位于所述第二介质层402内的金属岛4022，所述金属岛4022表面与所述第一阻挡层4021的表面齐平；覆盖所述第一阻挡层4021及所述金属岛4022表面的第二阻挡层4031、位于所述第二阻挡层4031表面的第三介质层403以及位于所述第三介质层403表面的第一阻挡层4032；覆盖所述第一阻挡层4021以及金属岛4022表面的第二阻挡层4031和位于所述第二阻挡层4031表面的第三介质层403；位于所述第三介质层403内的导电接触孔4033以及位于所述导电接触孔4033上方的激光熔丝4032。所述激光熔丝4032两端分别与所述导电接触孔4033连接，通过所述导电接触孔4033连接至下方的金属岛4022。
所述第一介质层401内形成有连接所述半导体衬底内半导体器件的导电插塞4011。所述导电插塞4011的材料可以为钨、铜或银等金属材料。该实施例中，以形成一个激光熔丝结构作为示例，因此，所述第一介质层401以形成有两个导电插塞4011作为示意，分别用于形成两路不同的导电通路。
所述金属岛4022位于底层金属层内，用于通过所述导电插塞4011直接与半导体衬底内的器件形成电连接，所述金属岛4022为所述底层金属层的一部分，在第二介质层402的其他位置处，还形成有金属互连线等结构。
所述第二阻挡层4031能够阻挡所述金属岛4022内的金属原子向上扩散至第三介质层403。在其他实施例中，也可以没有所述第二阻挡层4031。
该实施例中，在平行于半导体衬底表面的方向上，所述金属岛4022横截面尺寸大于所述导电插塞4011的横截面尺寸，使得所述导电插塞4011在半导体衬底表面的投影位于所述金属岛4022在半导体衬底上的投影内。
所述导电接触孔4033的横截面尺寸大于所述金属岛4022的尺寸，使得所述金属岛4022在半导体衬底表面的投影位于所述导电接触孔4033在半导体衬底表面的投影内。
由于所述导电接触孔4033的尺寸大于所述金属岛4022的尺寸，在刻蚀形成用于形成所述导电接触孔4033的通孔过程中，以所述第一阻挡层4021作为刻蚀阻挡层，及时停止刻蚀的进程，避免对所述第二介质层402造成过刻蚀。 所述第一阻挡层4021和所述第二阻挡层4031分别环绕所述金属岛4022的顶部以及所述导电接触孔4033的底部设置，避免所述金属岛4022和所述导电接触孔4033在所述第二介质层402和所述第三介质层403的界面上发生电迁移或扩散问题。
所述激光熔丝4033位于半导体衬底上方的第二层金属互连层内，所述对准标记4034与所述激光熔丝4033位于同一层金属互连层内。
在其他实施例中，所述激光熔丝和对准标记还可以位于第三层或者更上层的金属互连层内。
自半导体衬底向上至所述激光熔丝方向上，每一导电通路内，所述导电接触孔及所述金属岛沿平行于所述半导体衬底表面方向上的横截面的关键尺寸逐层增大，使得任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内。
所述半导体结构还可以包括覆盖所述激光熔丝4032、对准标记4034以及第三介质层403的保护层，所述保护层上方为熔断窗口。
由于上述半导体结构的导电通路内，各导电连接结构，例如导电插塞、金属岛、导电接触孔的尺寸自底部向上逐步增大，使得在导电通路上，各个导电连接结构之间相互重叠，在竖直方向上，全部为金属材料，熔断过程中，可以减少激光对准的难度，并且熔断路径(如图4b中虚线所示)上，各金属层之间不夹杂介质材料，能够降低需要的激光能量，从而降低功耗。
本申请的实施例还提供一种半导体结构内的激光熔丝的熔断方法，具体包括：利用与激光熔丝位于同一金属互连层内的对准标记，将激光对准至熔断位置，采用激光对所述激光熔丝进行熔断，以使所述两个导电通路之间断路，其中，所述熔断过程中，将激光熔丝及下方的两个导电通路内的金属岛及导电接触孔均进行激光熔断，使得导电通路上的金属在高温下彻底被汽化排出，提高熔断效果。
熔断过程中，可以通过调整激光光束位置，使其始终对准导电通路内的金属。如图4b所示的结构，由于在导电通路上，各个导电连接结构之间相互重叠，在竖直方向上，全部为金属材料，因此，可以减少激光对准的难度，沿图4b中虚线方向进行熔断，几乎不用或者仅需稍微移动激光光束，就能够使得整 个导电通路内的金属均被熔断，且由于通断路径上不夹杂介质材料，能够降低需要的激光能量，从而降低功耗。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (17)

  1. 一种半导体结构，其中，包括：
    半导体衬底；
    位于所述半导体衬底上方的层间介质层以及位于所述层间介质层内的至少两层金属互连层；
    激光熔丝，位于底层金属互连层上方的任一金属互连层内；
    金属岛，位于所述激光熔丝下层的各金属互连层内，不同金属互连层内的金属岛之间通过导电接触孔连接，形成两条导电通路，所述激光熔丝通过导电接触孔串联所述两条导电通路；
    对准标记，与所述激光熔丝位于同一金属互连层内，作为对所述激光熔丝进行熔断时的激光对准的标记。
  2. 根据权利要求1所述的半导体结构，其中，自半导体衬底向上至所述激光熔丝方向上，每一导电通路内，所述导电接触孔及所述金属岛沿平行于所述半导体衬底表面方向上的横截面的关键尺寸逐层增大。
  3. 根据权利要求1所述的半导体结构，其中，任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内。
  4. 根据权利要求1所述的半导体结构，其中，所述层间介质层内具有与所述金属岛的顶部表面齐平的第一阻挡层。
  5. 根据权利要求4所述的半导体结构，其中，所述层间介质层内还具有位于所述第一阻挡层表面环绕导电接触孔底部的第二阻挡层。
  6. 根据权利要求1所述的半导体结构，其中，所述激光熔丝和所述对准标记表面覆盖有保护层。
  7. 根据权利要求6所述的半导体结构，其中，还包括：覆盖所述层间介质层的顶部介质层，所述顶部介质层内形成有位于所述激光熔丝与所述对准标记上方的熔断窗口，所述熔断窗口底部与所述激光熔丝、所述对准标记表面之间具有部分厚度的介质材料，作为所述激光熔丝和所述对准标记表面的所述保护层。
  8. 根据权利要求6所述的半导体结构，其中，所述保护层包括氧化硅层、氮化硅层或氮氧化硅层中的至少一层。
  9. 根据权利要求6所述的半导体结构，其中，所述保护层的厚度为20nm～200nm。
  10. 根据权利要求1所述的半导体结构，其中，所述激光熔丝与单个金属岛之间通过一个或两个以上的导电接触孔连接。
  11. 一种半导体结构的形成方法，其中，包括：
    提供半导体衬底；
    在所述半导体衬底上方形成层间介质层以及位于所述层间介质层内的至少两层金属互连层，包括：
    在底层金属互连层上方的任一金属互连层内形成激光熔丝，以及位于所述激光熔丝下层的各金属互连层内的金属岛，不同金属互连层内的金属岛之间通过导电接触孔连接，形成两条导电通路，所述激光熔丝通过导电接触孔串联所述两条导电通路；
    还包括形成与所述激光熔丝位于同一金属互连层内的对准标记，所述对准标记作为对所述激光熔丝进行熔断时的激光对准的标记。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，自半导体衬底向上至所述激光熔丝方向上，每一导电通路内，所述导电接触孔及所述金属岛沿平行于所述半导体衬底表面方向上的横截面的关键尺寸逐层增大。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，任一层导电接触孔/金属岛在半导体衬底上的投影位于上层的导电接触孔/金属岛在半导体衬底上的投影内。
  14. 根据权利要求11所述的半导体结构的形成方法，其中，所述层间介质层内具有与所述金属岛的顶部表面齐平的第一阻挡层，作为形成位于上层的导电接触孔的通孔的刻蚀停止层；所述层间介质层内还具有位于所述第一阻挡层表面环绕导电接触孔底部设置的第二阻挡层。
  15. 根据权利要求11所述的半导体结构的形成方法，其中，还包括：形成覆盖所述层间介质层的顶部介质层；刻蚀所述顶部介质层，形成位于所述激光 熔丝与所述对准标记上方的熔断窗口，所述熔断窗口底部与所述激光熔丝、所述对准标记表面之间具有部分厚度的介质材料，作为覆盖所述激光熔丝和所述对准标记表面的所述保护层。
  16. 根据权利要求11所述的半导体结构的形成方法，其中，在所述激光熔丝与单个金属岛之间形成一个或两个以上的导电接触孔。
  17. 一种半导体结构内的激光熔丝的熔断方法，所述半导体结构如权利要求1所述，其中，包括：
    利用所述对准标记将激光对准至熔断位置，采用激光对所述激光熔丝进行熔断，以使所述两个导电通路之间断路，其中，所述熔断过程中，将激光熔丝及下方的导电通路内的金属岛及导电接触孔均进行激光熔断。
PCT/CN2021/079973 2020-03-13 2021-03-10 半导体结构及其形成方法、激光熔丝的熔断方法 WO2021180122A1 (zh)

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JP2022551008A JP2023515550A (ja) 2020-03-13 2021-03-10 半導体構造及びその形成方法、レーザヒューズの溶断方法
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