WO2021179934A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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WO2021179934A1
WO2021179934A1 PCT/CN2021/078514 CN2021078514W WO2021179934A1 WO 2021179934 A1 WO2021179934 A1 WO 2021179934A1 CN 2021078514 W CN2021078514 W CN 2021078514W WO 2021179934 A1 WO2021179934 A1 WO 2021179934A1
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ion implantation
semiconductor device
layer
oxide layer
fluorine ion
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PCT/CN2021/078514
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English (en)
French (fr)
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张燕杰
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长鑫存储技术有限公司
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Priority to US17/371,079 priority Critical patent/US20210336014A1/en
Publication of WO2021179934A1 publication Critical patent/WO2021179934A1/zh

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Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor device and a manufacturing method thereof.
  • Negative bias temperature instability (NBTI) effect is a common phenomenon that occurs in PMOS devices.
  • device parameters such as threshold voltage, saturation current, and transconductance will be unstable. Phenomenon.
  • the gate electric field of the semiconductor structure increases, and the operating temperature of the integrated circuit rises. This NBTI effect, which leads to the degradation of device performance, becomes more prominent.
  • the formation of the Si-SiO 2 interface state of the gate oxide layer is the main factor leading to the NBTI effect.
  • the negative pressure will form a high electric field on the gate, and the Si-H bond formed by tempering in the H 2 atmosphere is easy to be Interruption, forming positively charged interface states and traps, resulting in the NBTI effect of integrated circuit devices.
  • fluorine ion doping is carried out in the gate oxide layer interface area to repair the unbonded floating bonds and form Si-F bonds with higher energy and more difficult to break than Si-H; at the same time, the introduction of fluorine can Suppress the defects caused by the source/drain doped boron penetrating the gate oxide layer, thereby reducing the NBTI effect.
  • the purpose of the embodiments of the present application is to provide a semiconductor device and a manufacturing method thereof, so as to improve the negative bias voltage instability effect of the semiconductor device and improve the reliability of the semiconductor device.
  • an embodiment of the present application provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate; sequentially forming a stacked gate oxide layer and a gate polysilicon layer on the semiconductor substrate; After the gate polysilicon layer, fluorine ion implantation is performed at a preset temperature, and annealing is performed after ion implantation to form Si-F bonds at the interface between the gate oxide layer and the semiconductor substrate; the preset temperature Between -100°C and -10°C.
  • the embodiments of the present application also provide a semiconductor device, which is manufactured by the above-mentioned semiconductor device manufacturing method.
  • the embodiment of the present application performs a fluorine ion implantation process on the semiconductor structure under low temperature conditions to repair the unbonded floating bonds between the gate oxide layer and the semiconductor substrate interface, and form Si with higher energy. -F bond, thereby greatly reducing the NBTI effect; and the crystal lattice is in a lower energy state under low temperature conditions, and the atoms are relatively inactive. Under this condition, fluoride ion implantation can reduce the damage to the crystal lattice by ion implantation. Lower range end defects, thereby reducing leakage and improving the yield and reliability of semiconductor devices.
  • the forming the stacked gate oxide layer and the gate polysilicon layer includes: sequentially forming a stacked initial oxide layer and an initial polysilicon layer on the first surface of the semiconductor substrate; etching the initial oxide layer and the initial polysilicon layer Layer to form a patterned gate oxide layer and a gate polysilicon layer.
  • the method before performing the low-temperature fluorine ion implantation process, the method further includes: before the performing the fluorine ion implantation at a preset temperature, the method further includes: forming a first mask layer on the first surface of the semiconductor substrate, The first mask layer covers the exposed first surface of the semiconductor substrate; and after the fluorine ion implantation at a preset temperature, the method further includes: removing the first mask layer.
  • a first mask layer covering the exposed first surface of the semiconductor substrate is formed to cover the source and drain regions on the semiconductor substrate, to prevent the implanted fluorine ions from damaging the source and drain region lattices, and to avoid subsequent source and drain regions. The effect of ion doping.
  • the first mask layer is photoresist.
  • the use of photoresist as the first mask layer for protecting the semiconductor substrate is easy to form and easy to remove, and can reduce the process difficulty and manufacturing cost of the semiconductor device.
  • the performing fluorine ion implantation at a preset temperature specifically includes: performing fluorine ion implantation through the gate polysilicon layer in a vertical direction.
  • the method further includes: forming sidewall spacers of the dielectric layer adjacent to the gate oxide layer and the gate polysilicon layer, and forming the gate spacer on the semiconductor substrate.
  • Lightly doped drain regions on both sides of the oxide layer; the performing fluorine ion implantation at a preset temperature specifically includes: performing oblique fluorine ion implantation through the lightly doped drain region.
  • the method before the ion implantation at the preset temperature, after forming the dielectric layer sidewall spacers, the method further includes: forming a second mask layer located above the gate polysilicon layer away from the semiconductor substrate After the fluorine ion implantation at a preset temperature, the method further includes: removing the second mask layer.
  • the performing fluorine ion implantation at a preset temperature specifically includes: implanting a fluorine ion source in a direction that forms an angle ⁇ with the first surface, and the angle ⁇ is between 30 degrees and 90 degrees.
  • Choosing a proper fluoride ion implantation angle according to the gate size can accurately control the fluoride ion implantation to the target position, obtain a high-quality amorphous layer, and reduce the influence of fluoride ions on the source doped region and the drain doped region, and then Improve the stability and service life of semiconductor devices.
  • the fluorine ion source used for performing fluorine ion implantation at a preset temperature includes boron fluoride gas.
  • the implantation energy used for the fluorine ion implantation at the preset temperature is 0.5KeV-15KeV, and the implantation dose is 5E11/cm 2 -1E13/cm 2 .
  • the temperature of the annealing process is between 900°C and 1100°C.
  • An annealing temperature that is too high will easily cause the injected fluoride ions to diffuse rapidly and cause fluoride ion leakage. If the annealing temperature is too low, the effect of ion damage repair is poor, and the Si-F bond formation rate between the gate oxide layer and the semiconductor substrate interface is low. , which in turn makes the improvement effect of the negative bias instability effect of the semiconductor device unsatisfactory.
  • Using the above annealing temperature can avoid the above drawbacks, thereby forming a stable Si-F bond between the gate oxide layer and the interface of the semiconductor substrate, and improving the negative bias instability effect of the semiconductor.
  • FIG. 1 to 3 are schematic structural diagrams corresponding to each step of a semiconductor device manufacturing method provided by an embodiment of the present application;
  • 4 and 5 are schematic structural diagrams corresponding to each step of a semiconductor device manufacturing method provided by another embodiment of the present application.
  • the first implementation of the present application provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate; sequentially forming a stacked gate oxide layer and a gate polysilicon layer on the semiconductor substrate; Perform fluorine ion implantation at a set temperature, and perform annealing after ion implantation to form Si-F bonds at the interface between the gate oxide layer and the semiconductor substrate; the preset temperature is between -100°C and -10°C.
  • FIGS. 1 to 3 are schematic diagrams of the semiconductor structure obtained in each step of the method for manufacturing a semiconductor device provided by an embodiment of the application.
  • the method for manufacturing the semiconductor device provided by this embodiment will be described in detail below with reference to FIGS. 1 to 3.
  • the material of the semiconductor substrate 100 in this embodiment is silicon.
  • the material of the semiconductor substrate may also be silicon-on-insulator (SOI), germanium, silicon germanium, or arsenide. Gallium etc.
  • SOI silicon-on-insulator
  • germanium germanium
  • silicon germanium silicon germanium
  • arsenide arsenide
  • Gallium etc.
  • Several epitaxial interface layers or strained layers may also be formed on the surface of the semiconductor substrate 100 to improve the electrical performance of the semiconductor device.
  • An isolation structure may also be formed in the semiconductor substrate 100.
  • the existing isolation structure usually adopts a shallow trench isolation structure.
  • the filling material of the shallow trench isolation structure may be silicon oxide, silicon nitride, or silicon oxynitride. One or a mixture of several.
  • the shallow trench isolation structure is mainly used to isolate the first region (not identified) and the second region (not identified) to prevent electrical connection between different semiconductor devices.
  • an initial oxide layer 11 and an initial polysilicon layer 12 are sequentially formed on the first surface A of the semiconductor substrate 100 through a deposition process.
  • the initial polysilicon layer 12 is located on the surface of the initial oxide layer 11 away from the semiconductor substrate 100.
  • Low Pressure Chemical Vapor Deposition LPCVD
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • thermal oxidation or in-situ water vapor oxidation ISSG
  • a stacked initial silicon oxide layer 11 and an initial polysilicon layer 12 are sequentially formed on the first surface A of the semiconductor substrate 100.
  • the reaction gases H2 and O2 directly react with the silicon material on the surface of the semiconductor substrate 100 to form the initial oxide layer 11, and a large amount of oxidizing gas-phase activity is generated during the reaction.
  • Free radicals include active oxygen atoms, water molecules, and OH groups. Because active oxygen atoms have a strong oxidizing effect, the resulting initial oxide layer 11 has fewer defects, and the semiconductor substrate 100 and the initial oxide layer The charge and the interface state at the interface between 11 are reduced, and therefore, the problem of instability of the negative bias voltage of the semiconductor device can be improved.
  • a thermal oxidation process When a thermal oxidation process is used to form the initial oxide layer, it may be formed by oxidizing the silicon substrate at 800-1000 degrees Celsius in an oxygen vapor environment. The thermal oxidation process can make close contact between the oxide layer and the substrate, have good interface performance between the two, and prevent the generation of interface defects.
  • the substrate temperature is usually maintained at about 350°C to obtain a good SiO x film, with a fast deposition rate and good film quality.
  • the initial oxide layer and the initial polysilicon layer may be formed by other deposition processes, and the formation process of the initial oxide layer and the initial polysilicon layer is not specifically limited herein.
  • the initial oxide layer 11 and the initial polysilicon layer 12 are etched to form a patterned gate oxide layer 101 and a gate polysilicon layer 102.
  • the material of the gate oxide layer 101 is silicon oxide.
  • the material of the gate oxide layer may also be SiON, a stack of SiO and SiON, or other high-K dielectric materials.
  • the high-K dielectric material refers to a material with a relative dielectric constant greater than that of silicon oxide.
  • the high-K dielectric material is HfSiO, HfO2, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 or Al 2 O 3 .
  • a patterned mask layer (not marked) for defining the gate is formed on the surface of the initial polysilicon layer 12 away from the semiconductor substrate 100, and the initial oxide layer 11 and the initial oxide layer 11 and the initial oxide layer are etched through a dry or wet etching process.
  • the polysilicon layer 12 forms a gate oxide layer 101 and a gate polysilicon layer 102.
  • the patterned mask layer on the surface of the gate polysilicon layer 102 is removed.
  • the initial polysilicon layer may be removed by a dry or wet etching process, leaving the initial oxide layer, or a patterned gate oxide layer and gate electrode may be directly formed on the first surface of the semiconductor substrate Polysilicon layer.
  • this embodiment further includes: A first mask layer 103 is formed on the surface A, and the first mask layer 103 covers the exposed first surface A of the semiconductor substrate 100.
  • the first surface area exposed by the semiconductor substrate 100 is the area on the first surface A of the semiconductor substrate 100 except for the gate oxide layer 101.
  • the first mask layer 103, the gate oxide layer 101 and the gate polysilicon are formed.
  • the sidewalls of layer 102 are next to each other.
  • the first mask layer 103 covers the source doped region and the drain doped region on the semiconductor substrate 100, thereby avoiding the influence of the fluorine ion doping process on the subsequent ion doping of the source and drain regions.
  • step S103 is performed.
  • the material of the first mask layer 103 is photoresist.
  • photoresist as the first mask layer 103 has simple formation and removal processes and low price. While protecting the semiconductor substrate 100 from fluoride ion erosion, the manufacturing process cost of the semiconductor device can be greatly reduced.
  • the first mask layer may also be other mask materials.
  • the preset temperature of the fluoride ion implantation process in this embodiment is between -100°C and -10°C. Under low temperature conditions, the crystal lattice is in a lower energy state, and the atoms in the crystal lattice are relatively inactive. During ion implantation, the crystal lattice is relatively difficult to be destroyed. Therefore, using low-temperature ion implantation to implant fluorine ion into the semiconductor structure can reduce the damage of ion implantation to the crystal lattice and obtain lower range end defects, thereby reducing leakage and improving the yield of semiconductor devices.
  • the temperature of the low-temperature fluoride ion implantation process is -90°C, -80°C, -70°C, -60°C, -50°C, -40°C, -30°C, or -20°C.
  • Performing fluorine ion implantation under the above-mentioned temperature conditions can improve the stability of the negative bias voltage of the semiconductor device, further reduce the defects of the range end, and improve the yield of the semiconductor device.
  • performing fluorine ion implantation at a preset temperature specifically includes: implanting a fluorine ion source through the gate polysilicon layer 102 in a vertical direction.
  • the gate polysilicon layer 102 is subjected to low-temperature fluorine ion implantation along a direction perpendicular to the surface of the gate polysilicon layer 102, and the resultant semiconductor structure after ion implantation is annealed to perform low-temperature fluorine ion implantation on the gate oxide layer 101. Ion implantation and annealing the gate oxide layer 101 after ion implantation. In this way, fluorine ions can be diffused into the gate oxide layer 101 through the gate polysilicon layer 102, and Si-F bonds are formed at the interface between the gate oxide layer 101 and the semiconductor substrate 100, thereby preventing the semiconductor device from being biased or negatively biased on the gate. Unstable phenomenon under high temperature conditions.
  • the low-temperature fluorine ion implantation process can form a smoother amorphous interface and fewer range end defects in the gate polysilicon layer 102, and reduce the implantation of fluorine ions into the semiconductor through the gate polysilicon layer 102 and the gate oxide layer 101. Damage to the surface of the semiconductor substrate 100 caused by the surface of the substrate 100, and in the subsequent annealing process, the implanted fluorine ions reach a higher activation level and relatively less diffusion, thereby greatly reducing the NBTI effect and improving the semiconductor device’s performance. Reliability and service life.
  • the gate polysilicon layer may be implanted with low-temperature fluorine ions in a direction that forms a certain angle with the first surface.
  • the fluorine ion source includes boron fluoride gas.
  • the implantation energy for the fluorine ion implantation process at a preset temperature is 0.5KeV-15KeV, and the implantation dose is 5E11/cm2 ⁇ 1E13/cm2.
  • the injection energy is 1KeV, 2KeV, 3KeV, 4KeV, 5KeV, 6KeV, 7KeV, 8KeV, 9KeV, 10KeV, 11KeV, 12KeV, 13KeV or 14KeV
  • the injection dose is 6E11/cm2, 8E11/cm2, 1E12/cm2, 2E12/cm2 , 4E12/cm2, 5E12/cm2, 6E12/cm2 or 8E12/cm2.
  • this embodiment only lists the implantation energy and implantation dose combinations with better ion implantation effects.
  • other implantation energy values and implantation dose values may also be used.
  • the fluoride ion source may also be an HF solution or the like.
  • the annealing process adopts a high-temperature rapid tempering process, and the temperature of the annealing process is between 900°C and 1100°C.
  • the annealing temperature is 950°C, 1000°C, or 1050°C.
  • An annealing temperature that is too high will easily cause the injected fluoride ions to diffuse rapidly and cause fluoride ion leakage. If the annealing temperature is too low, the effect of ion damage repair is poor, and the Si-F bond formation rate between the gate oxide layer and the semiconductor substrate interface is low. , Which in turn makes the improvement effect of the negative bias instability effect of the semiconductor device unsatisfactory.
  • Using the above annealing temperature can avoid the above drawbacks, thereby forming a stable Si-F bond between the gate oxide layer and the interface of the semiconductor substrate, and improving the negative bias instability effect of the semiconductor.
  • the first mask layer 103 on the semiconductor substrate 100 is removed first.
  • a wet etching process is used to remove the first mask layer 103, for example, a mixed solution of an etching liquid, sulfuric acid and hydrogen peroxide is used to etch the first mask layer 103 whose material is photoresist.
  • a mixed solution of ammonia and hydrogen peroxide is cleaned.
  • the first mask layer may also use other commonly used mask layer materials.
  • the first mask layer may also be removed by a process such as etching after performing an annealing process.
  • the initial polysilicon layer 12 is implanted with a fluorine ion source along a direction perpendicular to the initial polysilicon layer 12, and After the low-temperature fluorine ion implantation process, the initial oxide layer 11 and the initial polysilicon layer 12 are etched to form a patterned gate oxide layer 101 and a gate polysilicon layer 102, and the ion implanted gate oxide layer 101 and gate polysilicon layer The layer 102 undergoes an annealing process to diffuse fluorine ions from the gate polysilicon layer 102 to the gate oxide layer 101, and form Si-F bonds at the interface between the semiconductor substrate 100 and the gate oxide layer 101.
  • a gate metal layer and an insulating dielectric layer are further formed on the semiconductor substrate 100, and source doped regions and regions on both sides of the gate oxide layer 101 are formed. Drain doped area.
  • the semiconductor device manufacturing method provided in this embodiment uses a fluorine ion implantation process on the semiconductor structure under low temperature conditions to repair the unbonded floating bonds between the gate oxide layer and the semiconductor substrate interface, thereby greatly reducing the semiconductor device NBTI effect; and the lattice is in a lower energy state under low temperature conditions, and the atoms are relatively inactive. Under this condition, fluoride ion implantation can reduce the damage of ion implantation to the lattice and obtain lower range end defects, thereby Reduce the leakage phenomenon, improve the yield and reliability of semiconductor devices.
  • Another embodiment of the present application relates to a method of manufacturing a semiconductor device.
  • Another embodiment is roughly the same as the above-mentioned embodiment, the main difference is: before the low-temperature fluorine ion implantation process, it also includes: forming sidewalls of the dielectric layer adjacent to the gate oxide layer and the gate polysilicon layer, and on the semiconductor substrate Forming lightly doped drain regions on both sides of the gate oxide layer; performing fluorine ion implantation at a preset temperature specifically includes: performing inclined fluoride ion implantation on the gate oxide layer through the lightly doped drain region.
  • FIGS. 4 and 5 are schematic structural diagrams corresponding to a semiconductor device manufacturing method provided by another embodiment of the application.
  • FIG. 4 and 5 are schematic structural diagrams corresponding to a semiconductor device manufacturing method provided by another embodiment of the application.
  • details that are the same as or similar to the foregoing embodiment please refer to the detailed description in the previous embodiment, which will not be repeated here.
  • S201 Provide a semiconductor substrate 200.
  • the dielectric layer spacer 204 in this embodiment includes a first dielectric layer spacer 23 and a second dielectric layer spacer 24.
  • the material of the first dielectric layer spacer 23 is silicon nitride, and the second dielectric layer spacer
  • the material of 24 is silicon oxide.
  • the material of the sidewall spacer of the first dielectric layer may also be other high-K dielectric materials.
  • a gate metal layer (not marked) and an insulating dielectric layer (not marked) located on the gate polysilicon layer 202 away from the surface of the semiconductor substrate 200 are also formed.
  • the stacked gate oxide layer 201, the gate polysilicon layer 202, the gate metal layer and the insulating dielectric layer form a gate structure, and the dielectric layer sidewall spacers 204 are located on both sides of the gate structure.
  • forming the sidewall spacer 204 of the dielectric layer adjacent to the gate structure includes: after the gate structure is formed, an atomic deposition process or a chemical vapor deposition process with higher step coverage is used to sequentially deposit and cover the formed semiconductor structure A silicon nitride layer and a silicon oxide layer on the surface; the silicon oxide layer and silicon nitride layer formed are etched by a dry etching process with a directional etching effect.
  • the cover is removed The first surface A of the semiconductor substrate 200 and the silicon oxide layer and the silicon nitride layer covering the insulating dielectric layer, leaving only the silicon nitride layer and silicon oxide layer on both sides of the gate structure to form the first dielectric layer side The wall 23 and the side wall 24 of the second dielectric layer.
  • the Halo doped regions are formed on the semiconductor substrate 200 through the N-type Halo doping process, and the N-type Halo doped regions are formed on the semiconductor substrate 200.
  • a P-type lightly doped drain region 206 is formed on the semiconductor substrate 200 on both sides of the gate oxide layer 201.
  • the Light Dope Drain (LDD) structure is a structure adopted by the MOSFET to weaken the electric field in the drain region and improve the hot carrier injection effect. That is, a low doping is placed near the drain in the channel.
  • the low-doped drain region allows the low-doped drain region to withstand part of the voltage.
  • This structure can prevent the hot carrier injection effect.
  • the hot carrier effect is an important failure principle of MOS (metal-oxide-semiconductor) devices. As the size of MOS devices shrinks, the hot carrier injection effect of the device becomes more and more serious.
  • the holes in the channel are accelerated under the action of the high lateral electric field between the source and the drain to form high-energy carriers, which collide with the silicon lattice to generate ionized electron-hole pairs. Electrons are collected by the substrate to form a substrate current. Most of the holes generated by the collision flow to the drain, but some holes are injected into the gate under the action of the vertical electric field to form a gate current. This phenomenon is called It is Hot Carrier Injection.
  • Hot carriers will cause the break of the bond energy at the interface between the silicon substrate and the gate oxide layer, resulting in an interface state at the interface between the silicon substrate and the gate oxide layer, resulting in device performance, such as threshold voltage, transconductance, and linear/saturation zone
  • device performance such as threshold voltage, transconductance, and linear/saturation zone
  • the degradation of the current will eventually cause the MOS device to fail.
  • Device failure usually occurs at the drain terminal first. This is because carriers are accelerated through the electric field of the entire channel. After reaching the drain terminal, the energy of the carriers reaches the maximum value, so the hot carrier injection phenomenon at the drain terminal is more serious.
  • Hot carriers affect the performance of the device in two aspects: crossing the Si-SiO 2 barrier, being injected into the oxide layer, and accumulating, changing the threshold voltage, affecting the lifetime; colliding with the crystal lattice in the depletion region near the drain region An electron-hole pair is generated.
  • the electrons generated by the collision form an additional leakage current, and the holes are collected by the substrate to form a substrate current, making the total current the sum of the saturation leakage current and the substrate current.
  • the greater the substrate current the greater the number of collisions in the channel, and the more serious the corresponding hot carrier effect.
  • the hot carrier effect is one of the basic factors that limit the maximum operating voltage of the device.
  • the second mask layer 205 is photoresist.
  • performing fluorine ion implantation at a preset temperature specifically includes: implanting a fluorine ion source in a direction that forms an angle ⁇ with the first surface A, and the angle ⁇ is between 30 degrees and 90 degrees. For example, it is 40 degrees, 50 degrees, 60 degrees, 70 degrees, or 80 degrees.
  • the angle of fluorine ion implantation is related to the size of the gate structure.
  • a suitable fluorine ion implantation angle is selected according to the gate size, and low-temperature fluorine ion is applied to the gate oxide layer 201 through the semiconductor substrate 200 regions on both sides of the gate oxide layer 201.
  • the ion implantation process can accurately control the implantation of fluoride ions to the target position, obtain a high-quality amorphous layer, and reduce the influence of fluoride ions on the source and drain doped regions, thereby improving the stability and use of semiconductor devices life.
  • the photoresist layer on the gate polysilicon layer 202 away from the semiconductor substrate 200 is removed, and a high-temperature rapid tempering process is used for annealing.
  • the semiconductor device manufacturing method provided in this embodiment uses low-temperature ion implantation to dope the gate oxide layer 201 interface region with fluoride ions through the semiconductor substrate 200 regions on both sides of the gate oxide layer 201.
  • fluorine ion implantation can reduce the damage of ion implantation to the crystal lattice and obtain lower range end defects, thereby reducing leakage and improving the yield and quality of semiconductor devices. reliability.
  • yet another embodiment of the present application further provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method in the foregoing embodiment.
  • the semiconductor device in this embodiment is, for example, a PMOS tube, a logic circuit, a dynamic random access memory, and the like.

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Abstract

一种半导体器件及其制造方法，半导体器件制造方法包括，提供半导体衬底(100)；在所述半导体衬底(100)上依次形成层叠的栅氧化层(101)和栅极多晶硅层(102)；在形成所述栅极多晶硅层(102)之后，在预设温度下进行氟离子注入，并在离子注入后进行退火，以在所述栅氧化层(101)和所述半导体衬底(100)的界面形成Si-F键；所述预设温度在-100℃至-10℃之间。通过低温离子注入的方式对栅极氧化层(101)界面区域进行氟离子掺杂，可以得到更平整的非晶界面以及更少的射程端缺陷，从而极大降低半导体器件的NBTI效应，提高半导体器件的可靠性和使用寿命。

Description

一种半导体器件及其制造方法
交叉引用
本申请引用于2020年3月9日递交的名称为“一种半导体器件及其制造方法”的第202010157194.1号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体器件及其制造方法。
背景技术
负偏压温度不稳定性(NBTI)效应为发生在PMOS器件中的常见现象，在栅极负偏压和较高温度工作时，会导致器件参数如阈值电压、饱和电流和跨导等不稳定现象。随着尺寸微缩，半导体结构的栅电场增加，集成电路工作温度升高，这种导致器件性能衰退的NBTI效应表现得更加显著。
栅氧化层Si-SiO 2界面态的形成是导致NBTI效应的主要因素，在器件工作时负压会在栅极上形成高电场，在H 2气氛中回火形成的Si-H键就容易被打断，形成带正电的界面态以及陷阱，从而导致集成电路器件的NBTI效应。相关技术中通过在栅极氧化层界面区域进行氟离子掺杂，修复未键结的悬浮键并形成能量更高且较Si-H更难被打断的Si-F键；同时氟的引入可以抑制源/漏极掺杂硼穿透栅氧化层造成的缺陷，从而降低NBTI效应。
然而，为了极大地降低NBTI效应以提高半导体器件的可靠性，现有的氟离子掺杂工艺仍有待提高。
发明内容
本申请实施例的目的在于提供一种半导体器件及其制造方法，以改善半 导体器件负偏压不稳定性效应、提高半导体器件的可靠性。
为解决上述技术问题，本申请实施例提供了一种半导体器件制造方法，包括：提供半导体衬底；在所述半导体衬底上依次形成层叠的栅氧化层和栅极多晶硅层；在形成所述栅极多晶硅层之后，在预设温度下进行氟离子注入，并在离子注入后进行退火，以在所述栅氧化层和所述半导体衬底的界面形成Si-F键；所述预设温度在-100℃至-10℃之间。
本申请实施例还提供了一种半导体器件，所述半导体器件通过上述半导体器件制造方法所制造而成。
本申请实施例相对于相关技术而言，通过在低温条件下对半导体结构进行氟离子注入工艺，以修复栅氧化层和半导体衬底界面之间未键合的悬浮键，形成能量更高的Si-F键，从而极大降低NBTI效应；并且低温条件下晶格处于较低的能量状态，原子相对不活跃，在此条件下进行氟离子注入，可以减小离子注入对晶格的损伤，得到较低的射程端缺陷，从而减小漏电现象，提高半导体器件的良率和可靠性。
另外，所述形成层叠的栅氧化层和栅极多晶硅层包括：在所述半导体衬底的第一表面上依次形成层叠的初始氧化层和初始多晶硅层；刻蚀所述初始氧化层和初始多晶硅层以形成图形化的栅氧化层和栅极多晶硅层。
另外，在进行所述低温氟离子注入工艺之前还包括：在所述在预设温度下进行氟离子注入之前还包括：在所述半导体衬底的所述第一表面形成第一掩模层，所述第一掩模层覆盖所述半导体衬底暴露出的所述第一表面；且在所述在预设温度下进行氟离子注入之后还包括：去除所述第一掩模层。形成覆盖半导体衬底暴露出的第一表面的第一掩模层，以覆盖半导体衬底上的源漏区域， 防止注入的氟离子对源漏区晶格的损伤，以及避免对后续源漏区离子掺杂的影响。
另外，所述第一掩模层为光刻胶。采用光刻胶作为保护半导体衬底的第一掩模层，便于形成以及方便去除，可以降低半导体器件的工艺难度以及制造成本。
另外，所述在预设温度下进行氟离子注入具体包括：沿竖直方向经由所述栅极多晶硅层进行氟离子注入。
另外，在所述在预设温度下进行氟离子注入之前，还包括：形成紧邻所述栅氧化层和栅极多晶硅层的介质层侧墙，并在所述半导体衬底上形成位于所述栅氧化层两侧的轻掺杂漏区；所述在预设温度下进行氟离子注入具体包括：经由所述轻掺杂漏区进行倾斜氟离子注入。
另外，在所述在预设温度下进行离子注入之前，在形成所述介质层侧墙之后，还包括：形成位于所述栅极多晶硅层远离所述半导体衬底的上方的第二掩模层；在所述在预设温度下进行氟离子注入之后还包括：去除所述第二掩模层。
另外，所述在预设温度下进行氟离子注入具体包括：以与所述第一表面形成夹角θ的方向注入氟离子源，所述夹角θ在30度～90度之间。根据栅极尺寸选择合适的氟离子注入角度，可以精确控制氟离子注入到目标位置，获得高质量的非晶层，并减少氟离子对源极掺杂区和漏极掺杂区的影响，进而提升半导体器件的稳定性和使用寿命。
另外，所述在预设温度下进行氟离子注入所采用的氟离子源包括氟化硼气体。
另外，所述在预设温度下进行氟离子注入所采用的注入能量为0.5KeV～15KeV，注入剂量为5E11/cm 2～1E13/cm 2。
另外，所述退火工艺的温度在900℃～1100℃之间。退火温度太高容易导致注入的氟离子迅速扩散进而导致造成氟离子泄露，而退火温度太低离子损伤修复效果较差，栅氧化层与半导体衬底界面之间的Si-F键形成率较低，进而使得半导体器件的负偏压不稳定性效应改善效果不理想。采用上述退火温度，可以避免上述弊端，从而在栅氧化层与半导体衬底界面之间形成稳定的Si-F键，改善半导体的负偏压不稳定性效应。
附图说明
图1至图3是本申请一实施例提供的半导体器件制造方法各步骤对应的结构示意图；
图4和图5是本申请另一实施例提供的半导体器件制造方法各步骤对应的结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
本申请的第一实施提供一种半导体器件的制造方法，包括：提供半导体 衬底；在半导体衬底上依次形成层叠的栅氧化层和栅极多晶硅层；在形成栅极多晶硅层之后，在预设温度下进行氟离子注入，并在离子注入后进行退火，以在栅氧化层和半导体衬底的界面形成Si-F键；预设温度在-100℃至-10℃之间。
图1至图3为本申请一实施例提供的半导体器件的制造方法各步骤所获得的半导体结构示意图，以下将结合图1至图3对本实施例提供的半导体器件的制造方法进行详细说明。
S101、提供半导体衬底100。
参考图1，本实施例中半导体衬底100的材料为硅，在其他实施例中半导体衬底的材料还可以是绝缘体上硅(Silicon-on-insulator，SOI)、锗、锗硅或砷化镓等。半导体衬底100表面还可以形成若干外延界面层或应变层以提高半导体器件的电学性能。
在半导体衬底100内还可以形成隔离结构(未标识)，现有的隔离结构通常采用浅沟槽隔离结构，浅沟槽隔离结构的填充材料可以为氧化硅、氮化硅、氮氧化硅中的一种或几种的混合物。浅沟槽隔离结构主要用于隔离第一区域(未标识)和第二区域(未标识)，防止不同半导体器件之间电学连接。
S102、在半导体衬底100上依次形成层叠的栅氧化层101和栅极多晶硅层102。
继续参考图1，通过沉积工艺在半导体衬底100的第一表面A上依次形成初始氧化层11和初始多晶硅层12，初始多晶硅层12位于初始氧化层11远离半导体衬底100的表面。本实施例中通过低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)、等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、热氧化或原位水汽氧 化法(In-Situ Steam Generation，ISSG)在半导体衬底100的第一表面A上依次形成层叠的初始氧化硅层11和初始多晶硅层12。
在采用原位水汽氧化法形成初始氧化层11的过程中，反应气体H2和O2直接与半导体衬底100表面的硅材料发生反应而形成初始氧化层11，反应中产生大量具有氧化性的气相活性自由基，这些自由基包括活性氧原子、水分子以及OH基团等，由于活性氧原子具有极强的氧化作用，使得最终得到的初始氧化层11的缺陷减少，半导体衬底100与初始氧化层11之间的界面处的电荷和界面态减少，因此能够改善半导体器件的负偏压不稳定问题。
采用热氧化工艺形成初始氧化层时，可以是在氧蒸汽环境中在800～1000摄氏度下将硅衬底氧化而成。热氧化工艺可以使得氧化层和衬底之间紧密接触，两者之间具有良好得界面性能，防止界面缺陷的产生。
在PECVD工艺中，衬底温度通常保持在350℃左右就可以得到良好的SiO x薄膜，沉积速率快，且成膜质量好。
在其他实施例中，还可以是通过其它沉积工艺形成初始氧化层和初始多晶硅层，在此不对初始氧化层和初始多晶硅层的形成工艺做具体限定。
参考图2，刻蚀初始氧化层11和初始多晶硅层12以形成图形化的栅氧化层101和栅极多晶硅层102。本实施例中栅氧化层101的材料为氧化硅。在其它实施例中，栅氧化层的材料还可以是SiON、SiO与SiON叠层或其它高K介质材料。其中，高K介质材料指的是相对介电常数大于氧化硅相对介电常数的材料，例如高K介质材料为HfSiO、HfO2、HfSiON、HfTaO、HfTiO、HfZrO、ZrO 2或Al 2O 3。
具体来说，在初始多晶硅层12远离半导体衬底100的表面形成用以定义 栅极的图形化掩模层(未标识)，通过干法或湿法刻蚀工艺刻蚀初始氧化层11和初始多晶硅层12，以形成栅氧化层101和栅极多晶硅层102，刻蚀工艺完成后去除栅极多晶硅层102表面上的图形化掩模层。在其它实施例中，还可以是通过干法或湿法刻蚀工艺去除初始多晶硅层，保留初始氧化层，或者是在半导体衬底的第一表面上直接形成图形化的栅氧化层和栅极多晶硅层。
需要说明的是，氟离子注入会损伤源漏区的晶格，同时也会影响后续源漏区离子掺杂的分布，为了避免后续氟离子注入工艺对半导体衬底源极掺杂区(未标识)和漏极掺杂区(未标识)造成的影响，参考图3，本实施例在形成图形化的栅氧化层101和栅极多晶硅层102之后，还包括：在半导体衬底100的第一表面A形成第一掩模层103，第一掩模层103覆盖半导体衬底100暴露出的第一表面A。
半导体衬底100暴露出的第一表面区域为半导体衬底100第一表面A上除栅极氧化层101之外的区域，所形成的第一掩模层103与栅氧化层101以及栅极多晶硅层102的侧壁相紧邻。第一掩模层103覆盖半导体衬底100上的源极掺杂区和漏极掺杂区，从而可以避免氟离子掺杂工艺对后续源漏区离子掺杂的影响。
可以理解的是，形成紧邻栅氧化层101和栅极多晶硅层102的第一掩模层103并非本实施例的必需步骤，参考图2，在其他实施例中，还可以是在形成图形化的栅氧化层101和栅极多晶硅层102之后，执行步骤S103。
在本实施例中，第一掩模层103的材料为光刻胶。采用光刻胶作为第一掩模层103，其形成工艺以及去除工艺简单，且价格低廉，在保护半导体衬底100不受氟离子侵蚀的同时，可以极大降低半导器件的制造工艺成本。在其他 实施例中第一掩模层还可以是其他掩模材料。
S103、在预设温度下进行氟离子注入，并在离子注入后进行退火，以在栅氧化层101和半导体衬底100的界面形成Si-F键。
本实施例中氟离子注入工艺的预设温度在-100℃至-10℃之间。在低温条件下，晶格处于较低的能量状态，晶格内的原子相对不会很活跃，在离子注入时，晶格相对不易被破坏。因此采用低温离子注入的方式，对半导体结构进行氟离子注入，可以减小离子注入对晶格的损伤，得到较低的射程端缺陷，从而减少漏电现象，提高半导体器件的良率。
进一步地，低温氟离子注入工艺的温度为-90℃、-80℃、-70℃、-60℃、-50℃、-40℃、-30℃或-20℃。在上述温度条件下进行氟离子注入，可以在改善半导体器件负偏压稳定性的同时，进一步降低射程端缺陷，提高半导体器件的良率。
需要说明的是，在本实施例中，在预设温度下进行氟离子注入具体包括：沿竖直方向经由栅极多晶硅层102注入氟离子源。
参考图3，沿垂直于栅极多晶硅层102表面的方向对栅极多晶硅层102进行低温氟离子注入，并对离子注入后的所得到的半导体结构进行退火，以对栅氧化层101进行低温氟离子注入并对离子注入后的栅氧化层101进行退火。如此，可以使得氟离子经由栅极多晶硅层102向栅氧化层101进行扩散，并在栅氧化层101和半导体衬底100的界面形成Si-F键，从而避免半导体器件在栅极负偏压或高温情形下产生的不稳定现象。并且采用低温氟离子注入工艺可以在栅极多晶硅层102内形成更平整的非晶界面以及更少的射程端缺陷，减小由氟离子穿过栅极多晶硅层102和栅氧化层101注入到半导体衬底100表面所造 成的半导体衬底100面的损伤，并在随后退火工艺中使注入的氟离子达到较高的活化水平和相对较少的扩散，从而极大降低NBTI效应，提高半导体器件的可靠性和使用寿命。
可以理解的是，在其他实施例中，还可以是以与第一表面成一定夹角的方向，对栅极多晶硅层进行低温氟离子注入。
本实施例中氟离子源包括氟化硼气体，在预设温度下进行氟离子注入工艺的注入能量为0.5KeV～15KeV，注入剂量为5E11/cm2～1E13/cm2。例如注入能量为1KeV、2KeV、3KeV、4KeV、5KeV、6KeV、7KeV、8KeV、9KeV、10KeV、11KeV、12KeV、13KeV或14KeV，注入剂量为6E11/cm2、8E11/cm2、1E12/cm2、2E12/cm2、4E12/cm2、5E12/cm2、6E12/cm2或8E12/cm2。
需要说明的是，本实施例仅列举具有较优离子注入效果的注入能量和注入剂量组合，在其他实施例中，还可以是采用其他注入能量值和注入剂量值。此外，在其他实施例中，氟离子源还可以是HF溶液等。
本实施例中退火工艺采用高温快速回火工艺，退火工艺的温度在900℃～1100℃之间。例如退火温度为950℃、1000℃或1050℃。退火温度太高容易导致注入的氟离子迅速扩散进而导致造成氟离子泄露，而退火温度太低离子损伤修复效果较差，栅氧化层与半导体衬底界面之间的Si-F键形成率较低，进而使得半导体器件的负偏压不稳定性效应改善效果不理想。采用上述退火温度，可以避免上述弊端，从而在栅氧化层与半导体衬底界面之间形成稳定的Si-F键，改善半导体的负偏压不稳定性效应。
需要说明的是，由于光刻胶不耐高温，本实施例中，在进行退火工艺之前，先去除半导体衬底100上的第一掩模层103。具体来说，采用湿法刻蚀工 艺去除第一掩模层103，例如采用刻蚀液体未硫酸和双氧水的混合溶液来刻蚀去除材料为光刻胶的第一掩模层103，接着，采用氨水和双氧水的混合溶液进行清洗处理。
在其他实施例中，第一掩模层还可以采用其他常用的掩模层材料，此时还可以是在进行退火工艺之后通过刻蚀等工艺去除第一掩模层。
在其他实施例中，参考图1，还可以是在形成图形化的栅氧化层101和栅极多晶硅层102之前，沿垂直于初始多晶硅层12的方向对初始多晶硅层12注入氟离子源，并在低温氟离子注入工艺后对初始氧化层11和初始多晶硅层12进行刻蚀以形成图形化的栅氧化层101和栅极多晶硅层102，并对离子注入后的栅氧化层101和栅极多晶硅层102进行退火工艺，以使氟离子从栅极多晶硅层102向栅氧化层101扩散，并在半导体衬底100和栅氧化层101的界面形成Si-F键。
在对氟离子注入后的栅氧化层101进行退火工艺后，还继续在半导体衬底100上形成栅金属层和绝缘介质层，以及形成位于栅极氧化层101两侧的源极掺杂区和漏极掺杂区。
本实施例提供的半导体器件制造方法，通过在低温条件下对半导体结构进行氟离子注入工艺，以修复栅氧化层和半导体衬底界面之间未键结的悬浮键，从而极大降低半导体器件的NBTI效应；并且低温条件下晶格处于较低的能量状态，原子相对不活跃，在此条件下进行氟离子注入，可以减小离子注入对晶格的损伤，得到较低的射程端缺陷，从而减小漏电现象，提高半导体器件的良率和可靠性。
本申请的另一实施例涉及一种半导体器件制造方法。另一实施例与上述 实施例大致相同，主要区别之处在于：进行低温氟离子注入工艺之前，还包括：形成紧邻栅氧化层和栅极多晶硅层的介质层侧墙，并在半导体衬底上形成位于栅氧化层两侧的轻掺杂漏区；在预设温度下进行氟离子注入具体包括：经由轻掺杂漏区对栅氧化层进行倾斜氟离子注入。
图4和图5为本申请另一实施例提供的半导体器件制造方法对应的结构示意图，与上述实施例相同或相似的细节请参考上一实施例中的详细描述，在此不再赘述。
S201、提供半导体衬底200。
S202、在半导体衬底200上依次形成层叠的栅氧化层201和栅极多晶硅层202。
S203、形成紧邻栅氧化层201和栅极多晶硅层202的介质层侧墙204，并在半导体衬底200上形成位于栅氧化层201两侧的轻掺杂漏区206。
参考图4，本实施例中介质层侧墙204包括第一介质层侧墙23和第二介质层侧墙24，第一介质层侧墙23的材料为氮化硅，第二介质层侧墙24的材料为氧化硅。在其他实施例中，第一介质层侧墙的材料还可以是其它的高K介质材料。
可以理解的是，本实施例中在形成介质层侧墙204之前，还形成位于栅极多晶硅层202远离半导体衬底200表面的栅金属层(未标识)和绝缘介质层(未标识)，依次层叠的栅氧化层201、栅极多晶硅层202、栅金属层和绝缘介质层形成栅极结构，介质层侧墙204位于栅极结构的两侧。
具体来说，形成紧邻栅极结构的介质层侧墙204包括：在形成栅极结构后，采用具有较高台阶覆盖性的原子沉积工艺或化学气相沉积工艺，依次沉积 形成覆盖所形成的半导体结构表面的一层氮化硅层和一层氧化硅层；采用具有定向刻蚀效果的干法刻蚀工艺对形成的氧化硅层和氮化硅层进行刻蚀，经过刻蚀之后，去除了覆盖半导体衬底200第一表面A以及覆盖于绝缘介质层之上的氧化硅层和氮化硅层，仅仅保留处于栅极结构两侧的氮化硅层和氧化硅层以形成第一介质层侧墙23和第二介质层侧墙24。
为了在半导体衬底200上形成源/漏极掺杂区，在形成介质层侧墙204后，通过N型Halo掺杂工艺在半导体衬底200上形成Halo掺杂区，并在进行N型Halo掺杂工艺后，在栅氧化层201两侧的半导体衬底200上形成P型轻掺杂漏区206。
轻掺杂漏区(Light Dope Drain，LDD)结构是MOSFET为了减弱漏区电场、以改进热载流子注入效应所采取的一种结构，即在沟道中靠近漏极的附近设置一个低掺杂的漏区，让该低掺杂的漏区也承受部分电压，这种结构可以防止热载流子注入效应。热载流子效应是MOS(金属-氧化物-半导体)器件的一个重要失效原理，随着MOS器件尺寸的日益缩小，器件的热载流子注入效应越来越严重。以PMOS器件为例，沟道中的空穴，在源漏之间高横向电场的作用下被加速，形成高能载流子，高能载流子与硅晶格碰撞，产生电离的电子空穴对，电子由衬底收集，形成衬底电流，大部分碰撞产生的空穴流向漏极，但还有部分空穴，在纵向电场的作用下，注入到栅极中形成栅极电流，这种现象称为热载流子注入(Hot Carrier Injection)。
热载流子会造成硅衬底与栅氧化层界面处键能的断裂，在硅衬底和栅氧化层界面处产生界面态，导致器件性能，如阈值电压、跨导以及线性区/饱和区电流的退化，最终造成MOS器件失效。器件失效通常首先发生在漏端，这是 由于载流子通过整个沟道的电场加速，在到达漏端后，载流子的能量到达最大值，因此漏端的热载流子注入现象比较严重。
随着器件尺寸进入亚微米沟长范围，器件内部的电场强度随器件尺寸的减小而增强，特别在漏端附近存在强电场，载流子在这一强电场中获得较高的能量，成为热载流子。热载流子在两个方面影响器件性能：越过Si-SiO 2势垒，注入到氧化层中，不断积累，改变阈值电压，影响期间寿命；在漏区附近的耗尽区中与晶格碰撞产生电子空穴对，对NMOS管，碰撞产生的电子形成附加的漏电流，空穴则被衬底收集，形成衬底电流，使总电流成为饱和漏电流和衬底电流之和。衬底电流越大，说明沟道中发生的碰撞次数越多，相应的热载流子效应越严重。热载流子效应是限制器件最高工作电压的基本因素之一。
需要说明的是，为了避免后续低温氟离子注入工艺对栅极结构的影响，参考图5，在形成介质层侧墙204后，还包括形成位于栅极多晶硅层202远离半导体衬底200的上方的第二掩模层205。本实施例中第二掩模层205为光刻胶。
S204、在预设温度下，经由P型轻掺杂漏区206进行倾斜氟离子注入，并在氟离子注入后进行退火，以在栅氧化层201和半导体衬底200的界面形成Si-F键。
在本实施例中，在预设温度下进行氟离子注入具体包括：以与第一表面A形成夹角θ的方向注入氟离子源，所述夹角θ在30度～90度之间。例如为40度、50度、60度、70度或80度。
具体来说，氟离子注入的角度与栅极结构的尺寸相关，根据栅极尺寸选择合适的氟离子注入角度，经由栅氧化层201两侧的半导体衬底200区域向栅 氧化层201进行低温氟离子注入工艺，可以精确控制氟离子注入到目标位置，获得高质量的非晶层，并减少氟离子对源极掺杂区和漏极掺杂区的影响，进而提升半导体器件的稳定性和使用寿命。
在预设温度下进行氟离子注入工艺后，去除栅极多晶硅层202远离半导体衬底200上方的光刻胶层，并采用高温快速回火工艺进行退火。
与相关技术相比，本实施例提供的半导体器件制造方法，通过低温离子注入的方式经由栅极氧化层201两侧的半导体衬底200区域对栅极氧化层201界面区域进行氟离子掺杂，以修复栅氧化层和半导体衬底界面之间未键结的悬浮键，并键合成能量更高的Si-F键，从而极大降低半导体器件的NBTI效应；并且低温条件下晶格处于较低的能量状态，原子相对不活跃，在此条件下进行氟离子注入，可以减小离子注入对晶格的损伤，得到较低的射程端缺陷，从而减小漏电现象，提高半导体器件的良率和可靠性。
相应的，本申请又一实施例还提供一种半导体器件，半导体器件通过上述实施例中的半导体器件制造方法所制造而成。
本实施例中的半导体器件例如为PMOS管、逻辑电路、动态随机存储器等。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (12)

  1. 一种半导体器件制造方法，其中，包括：
    提供半导体衬底；
    在所述半导体衬底上依次形成层叠的栅氧化层和栅极多晶硅层；
    在形成所述栅极多晶硅层之后，在预设温度下进行氟离子注入，并在离子注入后进行退火，以在所述栅氧化层和所述半导体衬底的界面形成Si-F键；
    所述预设温度在-100℃至-10℃之间。
  2. 根据权利要求1所述的半导体器件制造方法，其中，所述形成层叠的栅氧化层和栅极多晶硅层包括：在所述半导体衬底的第一表面上依次形成层叠的初始氧化层和初始多晶硅层；刻蚀所述初始氧化层和初始多晶硅层以形成图形化的栅氧化层和栅极多晶硅层。
  3. 根据权利要求2所述的半导体器件制造方法，其中，在所述在预设温度下进行氟离子注入之前还包括：在所述半导体衬底的所述第一表面形成第一掩模层，所述第一掩模层覆盖所述半导体衬底暴露出的所述第一表面；且在所述在预设温度下进行氟离子注入之后还包括：去除所述第一掩模层。
  4. 根据权利要求3所述的半导体器件制造方法，其中，所述第一掩模层为光刻胶。
  5. 根据权利要求1～4中任一项所述的半导体器件制造方法，其中，所述在预设温度下进行氟离子注入具体包括：沿竖直方向经由所述栅极多晶硅层进行氟离子注入。
  6. 根据权利要求1所述的半导体器件制造方法，其中，在所述在预设温度下进行氟离子注入之前，还包括：形成紧邻所述栅氧化层和栅极多晶硅层的介质层 侧墙，并在所述半导体衬底上形成位于所述栅氧化层两侧的轻掺杂漏区；所述在预设温度下进行氟离子注入具体包括：经由所述轻掺杂漏区进行倾斜氟离子注入。
  7. 根据权利要求6所述的半导体器件制造方法，其中，在所述在预设温度下进行离子注入之前，在形成所述介质层侧墙之后，还包括：形成位于所述栅极多晶硅层远离所述半导体衬底的上方的第二掩模层；在所述在预设温度下进行氟离子注入之后还包括：去除所述第二掩模层。
  8. 根据权利要求6或7所述的半导体器件制造方法，其中，所述在预设温度下进行氟离子注入具体包括：以与第一表面形成夹角θ的方向注入氟离子源，所述夹角θ在30度～90度之间。
  9. 根据权利要求1所述的半导体器件制造方法，其中，所述在预设温度下进行氟离子注入所采用的氟离子源包括氟化硼气体。
  10. 根据权利要求1所述的半导体器件制造方法，其中，所述在预设温度下进行氟离子注入所采用的注入能量为0.5KeV～15KeV，注入剂量为5E11/cm 2～1E13/cm 2。
  11. 根据权利要求1所述的半导体器件制造方法，其中，所述退火工艺的温度在900℃～1100℃之间。
  12. 一种半导体器件，其中，所述半导体器件通过上述权利要求1～11中任一项所述的半导体器件制造方法所制造而成。
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