WO2021179382A1 - 一种像素电路及显示面板 - Google Patents

一种像素电路及显示面板 Download PDF

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Publication number
WO2021179382A1
WO2021179382A1 PCT/CN2020/083571 CN2020083571W WO2021179382A1 WO 2021179382 A1 WO2021179382 A1 WO 2021179382A1 CN 2020083571 W CN2020083571 W CN 2020083571W WO 2021179382 A1 WO2021179382 A1 WO 2021179382A1
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Prior art keywords
thin film
film transistor
signal
unit
light
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PCT/CN2020/083571
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English (en)
French (fr)
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郑园
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武汉华星光电半导体显示技术有限公司
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Priority to US16/767,127 priority Critical patent/US11322085B1/en
Publication of WO2021179382A1 publication Critical patent/WO2021179382A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Definitions

  • This application relates to the field of display technology, in particular to the field of higher frequency display technology, and in particular to a pixel circuit and a display panel.
  • the current main display modes are: LCD (Liquid Crystal Display) display mode and OLED (Organic Light-Emitting Diode, organic light-emitting semiconductor) display mode.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode, organic light-emitting semiconductor
  • the two have different difficulties in higher frequency driving.
  • the current-driven display represented by the OLED display mode is more difficult to achieve higher frequency driving than the LCD display mode.
  • most of the compensation circuit design is adopted, and the working time limit of the compensation circuit makes the application of higher frequency driving difficult.
  • the scanning time of each pixel (Pixel) is compressed, and the compensation time is compressed at the same time, causing the compensation effect to decrease, and the display quality is poor.
  • the present application provides a pixel circuit, which solves the problem that the threshold voltage compensation of the pixel circuit in higher frequency applications is limited by the line scan time, which causes the threshold voltage compensation effect to decrease.
  • the present application provides a pixel circuit including a switch unit, a driving unit, a first light emission control unit, a second light emission control unit, a light emission unit, a storage unit, a voltage divider unit, a reset unit, and a compensation unit; a switch unit , Used to output the connected data signal according to the control of the scan signal; the driving unit, connected to the output terminal of the switch unit, used to connect and drive the pixels according to the data signal; the first light-emitting control unit, and the drive unit
  • the input terminal is connected to output the positive signal of the connected power supply according to the control of the first lighting control signal;
  • the second lighting control unit is connected to the output terminal of the driving unit and is used to output power according to the control of the second lighting control signal Positive signal; light-emitting unit, connected with the output terminal of the second light-emitting control unit and the negative signal of the power supply, for pixel display; storage unit, connected with the output terminal of the switch unit and the output terminal of the drive unit, used to store the
  • the switch unit includes a first thin film transistor; the drain of the first thin film transistor is connected to the data signal; the gate of the first thin film transistor is connected to the scan signal; The source of a thin film transistor is connected to the driving unit.
  • the driving unit includes a second thin film transistor; the gate of the second thin film transistor is connected to the source of the first thin film transistor; and second The drain of the thin film transistor is connected to the output terminal of the first light emitting control unit; the source of the second thin film transistor is connected to the input terminal of the second light emitting control unit.
  • the first light emission control unit includes a third thin film transistor; the drain of the third thin film transistor is connected to the positive signal of the power supply; and the third thin film The gate of the transistor is connected with the first light emission control signal; the source of the third thin film transistor is connected with the drain of the second thin film transistor.
  • the second light emission control unit includes a fourth thin film transistor; the drain of the fourth thin film transistor is connected to the source of the second thin film transistor ; The gate of the fourth thin film transistor is connected with the second light-emitting control signal; the source of the fourth thin film transistor is connected with the input terminal of the light-emitting unit.
  • the light emitting unit includes a light emitting device; the input terminal of the light emitting device is connected to the source of the fourth thin film transistor; the output terminal of the light emitting device is connected to Power negative signal connection.
  • the memory unit includes a first capacitor; the first terminal of the first capacitor is connected to the gate of the second thin film transistor; the first capacitor The second end of is connected to the source of the second thin film transistor.
  • the voltage dividing unit includes a second capacitor; the first end of the second capacitor is connected to the positive signal of the power supply; The terminal is connected to the second terminal of the first capacitor.
  • the compensation unit includes a fifth thin film transistor; the drain of the fifth thin film transistor is connected to the first reference signal; The gate is connected with the compensation signal; the source of the fifth thin film transistor is connected with the first end of the first capacitor.
  • the present application provides a display panel, which includes the pixel circuit in any of the above embodiments.
  • the compensation unit can independently compensate the threshold voltage of the driving unit during the work cycle of the compensation signal. It is not limited to the work cycle of the switch unit, and can improve the compensation effect of the threshold voltage. Higher frequency pixel driving is in progress.
  • Fig. 1 is a schematic circuit diagram of a pixel circuit in a conventional technical solution.
  • FIG. 2 is a timing diagram of the pixel circuit in FIG. 1.
  • FIG. 3 is a schematic diagram of the first structure of a pixel circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic circuit diagram of the pixel circuit in FIG. 3.
  • FIG. 5 is a timing diagram of the pixel circuit in FIG. 4.
  • FIG. 6 is a timing diagram of the multi-line operation of the pixel circuit in FIG. 4.
  • the pixel circuit is a commonly used 7T1C topology, and its working process can be divided into the following three stages:
  • Reset stage the N-1 level scan signal SCAN (N-1) is low, the transistor NT6 is turned on, the low potential signal VI is connected to the pixel circuit, and the capacitor C starts to discharge.
  • the Nth level scan signal SCAN(N) is low, the transistor NT3 and the transistor NT1 are turned on, the source and drain of the transistor NT2 are short-circuited, and the transistor NT2 acts as a diode until the gate potential of the transistor NT2 changes
  • the voltage Vdata of the data signal is the absolute value of the threshold voltage of the transistor NT2, it is turned off; at the same time, the transistor NT7 is turned on to reset the light-emitting device L.
  • Light-emitting stage the light-emitting control signal EM(N) is at a low level, the transistor NT4 and the transistor NT5 are turned on, and the light-emitting device L performs pixel display.
  • the data writing and the threshold voltage compensation of the transistor NT2 are performed at the same time, that is, the threshold voltage compensation is limited by the time period of data writing; therefore, when driving at higher frequencies , The time period of data writing will be shortened, correspondingly, the time period of threshold voltage compensation will be shortened accordingly, reducing the effect of threshold voltage compensation.
  • the compensation unit can independently compensate the threshold voltage of the driving unit during the work cycle of the compensation signal, which is not limited to the work cycle of the switch unit, and can improve the compensation effect of the threshold voltage. In the higher frequency pixel drive.
  • this embodiment provides a pixel circuit, which includes a switch unit 10, a driving unit 20, a first light-emitting control unit 30, a second light-emitting control unit 40, a light-emitting unit 50, a storage unit 60, and a voltage divider.
  • the pixels are driven according to the data signal DATA;
  • the first light-emitting control unit 30 is connected to the input end of the driving unit 20 and is used to output the connected power supply positive signal VDD according to the control of the first light-emitting control signal EM1;
  • the second light-emitting control The unit 40 is connected to the output terminal of the driving unit 20 and is used to output a positive power signal VDD according to the control of the second light-emitting control signal EM2;
  • the light-emitting unit 50 is connected to the output terminal of the second light-emitting control unit 40 and the negative power signal VSS , Used for pixel display; storage unit 60, connected to the output end of the switch unit 10 and the output end of the drive unit 20, used to store the threshold
  • the switch unit 10 and the compensation unit 80 are configured as two independent modules, both of which can adjust the storage unit 60 and sequentially control the scan signal SCAN and the compensation signal COMP of the two units. Therefore, the threshold voltage of the driving unit 20 stored in the storage unit 60 by the compensation unit 80 may not be limited to the working period of the switching unit 10, and therefore, the threshold voltage of the driving unit 20 can be better compensated. At the same time, the compensation time and value can be controlled, which is suitable for higher frequency pixel driving.
  • the switch unit 10 includes a first thin film transistor T1; the drain of the first thin film transistor T1 is connected to the data signal DATA; the gate of the first thin film transistor T1 is connected to the scan signal SCAN ; The source of the first thin film transistor T1 is connected to the driving unit 20.
  • the driving unit 20 includes a second thin film transistor T2; the gate of the second thin film transistor T2 and the gate of the first thin film transistor T1 The source is connected; the drain of the second thin film transistor T2 is connected to the output terminal of the first light emitting control unit 30; the source of the second thin film transistor T2 is connected to the input terminal of the second light emitting control unit 40.
  • the first light emission control unit 30 includes a third thin film transistor T3; the drain of the third thin film transistor T3 is connected to the positive power signal VDD; the gate of the third thin film transistor T3 is connected to The first light emission control signal EM1 is connected; the source of the third thin film transistor T3 is connected to the drain of the second thin film transistor T2.
  • the second light emission control unit 40 includes a fourth thin film transistor T4; the drain of the fourth thin film transistor T4 is connected to the source of the second thin film transistor T2; and the fourth thin film transistor T4
  • the gate of T4 is connected to the second light emission control signal EM2; the source of the fourth thin film transistor T4 is connected to the input end of the light emitting unit 50.
  • the light-emitting unit 50 includes a light-emitting device D; the input terminal of the light-emitting device D is connected to the source of the fourth thin film transistor T4; the output terminal of the light-emitting device D is connected to the negative power signal VSS .
  • the light-emitting device D may be, but is not limited to, an OLED, and may also be a self-luminous element such as an LED.
  • the memory unit 60 includes a first capacitor C1; a first terminal of the first capacitor C1 is connected to the gate of the second thin film transistor T2; and a second terminal of the first capacitor C1 is connected to the gate of the second thin film transistor T2.
  • the source of the second thin film transistor T2 is connected.
  • the voltage dividing unit 70 includes a second capacitor C2; the first end of the second capacitor C2 is connected to the positive power signal VDD; the second end of the second capacitor C2 is connected to the first capacitor The second end of C1 is connected.
  • the compensation unit 80 includes a fifth thin film transistor T5; the drain of the fifth thin film transistor T5 is connected to the first reference signal VREF1; the gate of the fifth thin film transistor T5 is connected to the compensation signal COMP is connected; the source of the fifth thin film transistor T5 is connected to the first end of the first capacitor C1.
  • the reset unit 90 includes a sixth thin film transistor T6; the drain of the sixth thin film transistor T6 is connected to the second reference signal VREF2; the gate of the sixth thin film transistor T6 is connected to the reset signal RST is connected; the source of the sixth thin film transistor T6 is connected to the second end of the second capacitor C2.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are all N-type thin film transistor.
  • the working process of the pixel circuit in this embodiment includes the following stages:
  • the reset signal RST, the second light emission control signal EM2, and the compensation signal COMP are all high-potential signals.
  • the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned on to prevent the second capacitor C2, and The light emitting device D is reset; the fifth thin film transistor T5 resets point Q to the potential of the first reference signal VREF1, and the sixth thin film transistor T6 resets the second terminal of the memory cell 60 to the potential of the second reference signal VREF2; at the same time, the first The four thin film transistors T4 reset the input terminal of the light emitting device D to the potential of the second reference signal VREF2.
  • the compensation signal COMP and the first light emission control signal EM1 are both high potential signals
  • the second thin film transistor T2, the third thin film transistor T3 and the fifth thin film transistor T5 are all turned on, and the first capacitor C1 and the second capacitor C2 are Charged
  • the first capacitor C1 stores the threshold voltage Vth of the second thin film transistor T2
  • point Q maintains the potential of the first reference signal VREF1
  • the potential at point A is the difference between the potential of the first reference signal VREF1 and the threshold voltage, that is, VREF1-Vth .
  • the scanning signal SCAN is at a high potential
  • the first thin film transistor T1 is turned on, and the data signal DATA is written to the first capacitor C1.
  • point Q is the potential of the data signal DATA, that is, VDATA
  • VA is the source potential of the second thin film transistor T2
  • the expression of VA is as follows:
  • Light emitting stage the first light emitting control signal EM1 and the second light emitting control signal EM2 are both high potential signals, the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the light emitting device D starts to emit light.
  • the expression of the current flowing through the light-emitting device D is as follows:
  • ⁇ is the carrier mobility
  • C 0x is the oxide capacitance per unit area
  • W/L is the width-to-length ratio of the second thin film transistor T2 channel
  • Vth is the threshold voltage of the second thin film transistor T2
  • VREF1 is the first The potential of the reference signal
  • VDATA is the potential of the data signal
  • C1 is the capacity of the first capacitor
  • C2 is the capacity of the second capacitor.
  • the present embodiment provides a display panel, which is applied to the self-luminous display field.
  • the display panel may include multiple rows of pixel circuits in the above-mentioned embodiments arranged in an array, and each row includes multiple pixel circuits, such as As shown in FIG. 6, the pixel circuit of the Nth row receives the first emission control signal EM1(N) of the Nth row, the second emission control signal EM2(N) of the Nth row, the compensation signal COMP(N) of the Nth row, and the Nth row of pixel circuits.
  • the row reset signal RST(N), the Nth row scan signal SCAN(N) and the data signal DATA are controlled.
  • the compensation phase and the write phase are independent of each other, and the compensation phase is not subject to the cycle limit of the write phase; similarly, the Nth The pixel circuit of the +1 row receives the first emission control signal EM1(N+1) of the N+1th row, the second emission control signal EM2(N+1) of the N+1th row, and the compensation signal COMP(N+1) of the N+1th row.
  • the compensation phase and the write phase are independent of each other, and the compensation phase is parallel It is not limited by the cycle of the writing phase; and the pixel circuits in the Nth row and the pixel circuits in the N+1th row can also be carried out at the same time without mutual influence. Therefore, the display panel provided in this example is also suitable for higher In the application of frequency drive, it has a better compensation effect.

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Abstract

一种像素电路，其包括开关单元（10）、驱动单元（20）、第一发光控制单元（30）、第二发光控制单元（40）、发光单元（50）、存储单元（60）、分压单元（70）、复位单元（90）以及补偿单元（80），补偿单元（80）在补偿信号（COMP）的工作周期中能够对驱动单元（20）的阈值电压（Vth）进行独立补偿，其并不受限于开关单元（10）的工作周期，适用于更高频像素驱动中。

Description

一种像素电路及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及更高频显示技术领域，具体涉及一种像素电路及显示面板。
背景技术
当前，显示产业发展日新月异，显示应用也已融入到人们生活的方方面面，但产品同质化日趋严重；而消费者是对高品质的显示需求也越来越高。因此，更高频显示在高端显示领域一直受消费者追捧，其中，更高频显示早期主要集中于专业级以及游戏应用等领域；现在手机应用更高频的需求也在提高，相应的，更高频显示可以带来更流畅的使用体验。
当前主要的显示模式有：LCD(Liquid Crystal Display，液晶显示器)显示模式和OLED(Organic Light-Emitting Diode，有机发光半导体)显示模式，两者在更高频驱动方面的难点各不相同。而以OLED显示模式为代表的电流驱动型显示较LCD显示模式实现更高频驱动有更高的难度。当前OLED显示为保证显示品质，大多采用补偿电路设计，而补偿电路的工作时间限制导致更高频驱动的应用困难。在更高频驱动应用中，压缩了每行像素(Pixel)的扫描时间，同时导致补偿时间被压缩，引起补偿效果下降，造成显示品质不良。
技术问题
本申请提供一种像素电路，解决了像素电路在更高频应用中，其阈值电压补偿受限于行扫描时间，导致的阈值电压补偿效果下降的问题。
技术解决方案
第一方面，本申请提供一种像素电路，其包括开关单元、驱动单元、第一发光控制单元、第二发光控制单元、发光单元、存储单元、分压单元、复位单元以及补偿单元；开关单元，用于根据扫描信号的控制，输出接入的数据信号；驱动单元，与开关单元的输出端连接，用于接入并根据数据信号，以驱动像素；第一发光控制单元，与驱动单元的输入端连接，用于根据第一发光控制信号的控制，输出接入的电源正信号；第二发光控制单元，与驱动单元的输出端连接， 用于根据第二发光控制信号的控制，输出电源正信号；发光单元，与第二发光控制单元的输出端和电源负信号连接，用于像素显示；存储单元，与开关单元的输出端和驱动单元的输出端连接，用于存储驱动单元的阈值电压；分压单元，与电源正信号和驱动单元的输出端连接，用于对存储单元进行分压；复位单元，与驱动单元的输出端连接，用于根据复位信号的控制，拉低驱动单元的输出端电位至第一参考信号的电位；以及补偿单元，与开关单元的输出端连接，用于根据补偿信号输出接入的第二参考信号，以补偿阈值电压；其中，扫描信号的工作周期与补偿信号的工作周期位于不同的时序区间。
基于第一方面，在第一方面的第一种实施方式中，开关单元包括第一薄膜晶体管；第一薄膜晶体管的漏极与数据信号连接；第一薄膜晶体管的栅极与扫描信号连接；第一薄膜晶体管的源极与驱动单元连接。
基于第一方面的第一种实施方式，在第一方面的第二种实施方式中，驱动单元包括第二薄膜晶体管；第二薄膜晶体管的栅极与第一薄膜晶体管的源极连接；第二薄膜晶体管的漏极与第一发光控制单元的输出端连接；第二薄膜晶体管的源极与第二发光控制单元的输入端连接。
基于第一方面的第二种实施方式，在第一方面的第三种实施方式中，第一发光控制单元包括第三薄膜晶体管；第三薄膜晶体管的漏极与电源正信号连接；第三薄膜晶体管的栅极与第一发光控制信号连接；第三薄膜晶体管的源极与第二薄膜晶体管的漏极连接。
基于第一方面的第三种实施方式，在第一方面的第四种实施方式中，第二发光控制单元包括第四薄膜晶体管；第四薄膜晶体管的漏极与第二薄膜晶体管的源极连接；第四薄膜晶体管的栅极与第二发光控制信号连接；第四薄膜晶体管的源极与发光单元的输入端连接。
基于第一方面的第四种实施方式，在第一方面的第五种实施方式中，发光单元包括发光器件；发光器件的输入端与第四薄膜晶体管的源极连接；发光器件的输出端与电源负信号连接。
基于第一方面的第五种实施方式，在第一方面的第六种实施方式中，存储单元包括第一电容；第一电容的第一端与第二薄膜晶体管的栅极连接；第一电容的第二端与第二薄膜晶体管的源极连接。
基于第一方面的第六种实施方式，在第一方面的第七种实施方式中，分压单元包括第二电容；第二电容的第一端与电源正信号连接；第二电容的第二端与第一电容的第二端连接。
基于第一方面的第七种实施方式，在第一方面的第八种实施方式中，补偿单元包括第五薄膜晶体管；第五薄膜晶体管的漏极与第一参考信号连接；第五薄膜晶体管的栅极与补偿信号连接；第五薄膜晶体管的源极与第一电容的第一端连接。
第二方面，本申请提供了一种显示面板，其包括上述任一实施方式中的像素电路。
有益效果
本申请提供的像素电路，补偿单元在补偿信号的工作周期中能够对驱动单元的阈值电压进行独立补偿，其并不受限于开关单元的工作周期，可以提高其阈值电压的补偿效果，适用于更高频像素驱动中。
附图说明
图1为传统技术方案中像素电路的电路原理图。
图2为图1中像素电路的时序示意图。
图3为本申请实施例提供的像素电路的第一种结构示意图。
图4为图3中像素电路的电路原理图。
图5为图4中像素电路的时序示意图。
图6为图4中像素电路的多行工作的时序示意图。
本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
为了更好地理解本申请的发明意图，现结合图1和图2对传统技术方案中的像素电路进行分析如下：
该像素电路为常用的7T1C拓扑结构，其工作过程可以分为以下三个阶段：
复位阶段：第N-1级扫描信号SCAN(N-1)为低电平，晶体管NT6打开， 低电位信号VI接入该像素电路，电容C开始放电。
数据写入阶段：第N级扫描信号SCAN(N)为低电平，晶体管NT3和晶体管NT1打开，晶体管NT2的源极和漏极短接，晶体管NT2作为二极管，直至晶体管NT2的栅极电位变为数据信号的电压Vdata与晶体管NT2的阈值电压绝对值时截止；同时，晶体管NT7打开，复位发光器件L。
发光阶段：发光控制信号EM(N)为低电平，晶体管NT4和晶体管NT5打开，发光器件L进行像素显示。
综上可知，该7T1C拓扑结构的像素电路中数据写入和晶体管NT2的阈值电压补偿是同时进行的，即其阈值电压补偿受限于数据写入的时间周期；因此，在更高频率驱动时，数据写入的时间周期会缩短，对应地，阈值电压补偿的时间周期随之缩短，降低了阈值电压补偿的效果。
而本申请提供的像素电路，补偿单元在补偿信号的工作周期中能够对驱动单元的阈值电压进行独立补偿，其并不受限于开关单元的工作周期，可以提高其阈值电压的补偿效果，适用于更高频像素驱动中。下面将结合实施例进行如下分析：
如图3所示，本实施例提供了一种像素电路，其包括开关单元10、驱动单元20、第一发光控制单元30、第二发光控制单元40、发光单元50、存储单元60、分压单元70、复位单元90以及补偿单元80；开关单元10，用于根据扫描信号SCAN的控制，输出接入的数据信号DATA；驱动单元20，与开关单元10的输出端连接，用于接入并根据数据信号DATA，以驱动像素；第一发光控制单元30，与驱动单元20的输入端连接，用于根据第一发光控制信号EM1的控制，输出接入的电源正信号VDD；第二发光控制单元40，与驱动单元20的输出端连接，用于根据第二发光控制信号EM2的控制，输出电源正信号VDD；发光单元50，与第二发光控制单元40的输出端和电源负信号VSS连接，用于像素显示；存储单元60，与开关单元10的输出端和驱动单元20的输出端连接，用于存储驱动单元20的阈值电压；分压单元70，与电源正信号VDD和驱动单元20的输出端连接，用于对存储单元60进行分压；复位单元90，与驱动单元20的输出端连接，用于根据复位信号RST的控制，拉低驱动单元20的输出端电位至第一参考信号VREF1的电位；以及补偿单元80， 与开关单元10的输出端连接，用于根据补偿信号COMP输出接入的第二参考信号VREF2，以补偿阈值电压；其中，扫描信号SCAN的工作周期与补偿信号COMP的工作周期位于不同的时序区间。
需要说明的是，开关单元10和补偿单元80被配置为两个相互独立的模块，均可以对存储单元60进行调节，且依次控制该两个单元的扫描信号SCAN和补偿信号COMP的工作周期并不相同，因此，补偿单元80对存储单元60中存储的驱动单元20的阈值电压可以不受限于开关单元10的工作周期，因此，可以更好地实现对驱动单元20的阈值电压的补偿，同时也可以控制补偿的时间和数值，适用于更高频像素驱动中。
如图4所示，在其中一个实施例中，开关单元10包括第一薄膜晶体管T1；第一薄膜晶体管T1的漏极与数据信号DATA连接；第一薄膜晶体管T1的栅极与扫描信号SCAN连接；第一薄膜晶体管T1的源极与驱动单元20连接。
如图4所示，在其中一个实施例中，在第一方面的第二种实施方式中，驱动单元20包括第二薄膜晶体管T2；第二薄膜晶体管T2的栅极与第一薄膜晶体管T1的源极连接；第二薄膜晶体管T2的漏极与第一发光控制单元30的输出端连接；第二薄膜晶体管T2的源极与第二发光控制单元40的输入端连接。
如图4所示，在其中一个实施例中，第一发光控制单元30包括第三薄膜晶体管T3；第三薄膜晶体管T3的漏极与电源正信号VDD连接；第三薄膜晶体管T3的栅极与第一发光控制信号EM1连接；第三薄膜晶体管T3的源极与第二薄膜晶体管T2的漏极连接。
如图4所示，在其中一个实施例中，第二发光控制单元40包括第四薄膜晶体管T4；第四薄膜晶体管T4的漏极与第二薄膜晶体管T2的源极连接；第四薄膜晶体管T4的栅极与第二发光控制信号EM2连接；第四薄膜晶体管T4的源极与发光单元50的输入端连接。
如图4所示，在其中一个实施例中，发光单元50包括发光器件D；发光器件D的输入端与第四薄膜晶体管T4的源极连接；发光器件D的输出端与电源负信号VSS连接。
需要说明的是，发光器件D可以但不限于为OLED，也可以为LED等自发光型元器件。
如图4所示，在其中一个实施例中，存储单元60包括第一电容C1；第一电容C1的第一端与第二薄膜晶体管T2的栅极连接；第一电容C1的第二端与第二薄膜晶体管T2的源极连接。
如图4所示，在其中一个实施例中，分压单元70包括第二电容C2；第二电容C2的第一端与电源正信号VDD连接；第二电容C2的第二端与第一电容C1的第二端连接。
如图4所示，在其中一个实施例中，补偿单元80包括第五薄膜晶体管T5；第五薄膜晶体管T5的漏极与第一参考信号VREF1连接；第五薄膜晶体管T5的栅极与补偿信号COMP连接；第五薄膜晶体管T5的源极与第一电容C1的第一端连接。
如图4所示，在其中一个实施例中，复位单元90包括第六薄膜晶体管T6；第六薄膜晶体管T6的漏极与第二参考信号VREF2连接；第六薄膜晶体管T6的栅极与复位信号RST连接；第六薄膜晶体管T6的源极与第二电容C2的第二端连接。
如图4所示，在其中一个实施例中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5以及第六薄膜晶体管T6均为N型薄膜晶体管。
如图5所示，本实施例中像素电路的工作过程包括以下几个阶段：
复位阶段：复位信号RST、第二发光控制信号EM2以及补偿信号COMP均为高电位信号，第四薄膜晶体管T4、第五薄膜晶体管T5以及第六薄膜晶体管T6开启，以对第二电容C2、和发光器件D进行复位；第五薄膜晶体管T5将Q点复位至第一参考信号VREF1的电位，第六薄膜晶体管T6将存储单元60的第二端复位至第二参考信号VREF2的电位；同时，第四薄膜晶体管T4将发光器件D的输入端复位至第二参考信号VREF2的电位。
补偿阶段：补偿信号COMP和第一发光控制信号EM1均为高电位信号，第二薄膜晶体管T2、第三薄膜晶体管T3以及第五薄膜晶体管T5均开启，对第一电容C1和第二电容C2进行充电，第一电容C1存储第二薄膜晶体管T2的阈值电压Vth，Q点保持第一参考信号VREF1的电位，A点的电位为第一参考信号VREF1的电位与阈值电压之差，即VREF1-Vth。
写入阶段：扫描信号SCAN为高电位，第一薄膜晶体管T1开启，将数据信号DATA写入到第一电容C1，此时，Q点为数据信号DATA的电位，即VDATA，A点电位变为VA，即为第二薄膜晶体管T2的源极电位，VA的表达式如下：
Figure PCTCN2020083571-appb-000001
发光阶段：第一发光控制信号EM1和第二发光控制信号EM2均为高电位信号，第二薄膜晶体管T2和第三薄膜晶体管T3开启，发光器件D开始发光。
流过发光器件D的电流的表达式如下：
Figure PCTCN2020083571-appb-000002
将Q点电位VDATA和A点电位即表达式一带入表达式二中，得出如下所示的表达式三：
Figure PCTCN2020083571-appb-000003
对表达式三进行简化，得到如下的表达式四：
Figure PCTCN2020083571-appb-000004
其中，μ为载流子迁移率；C 0x为单位面积氧化层电容；W/L为第二薄膜晶体管T2沟道的宽长比；Vth为第二薄膜晶体管T2的阈值电压；VREF1为第一参考信号的电位；VDATA为数据信号的电位；C1为第一电容的容量；C2为第二电容的容量。
在其中一个实施例中，本实施提供一种显示面板，其应用于自发光显示领域，显示面板可以包括阵列分布的多行上述实施例中的像素电路，每行包括多个该像素电路，如图6所示，其中第N行像素电路受第N行第一发光控制信号EM1(N)、第N行第二发光控制信号EM2(N)、第N行补偿信号COMP(N)、第N行复位信号RST(N)、第N行扫描信号SCAN(N)以及数据信号DATA的控制，补偿阶段与写入阶段相互独立，补偿阶段并不受写入阶段的周期限制；同理，第N+1行像素电路受第N+1行第一发光控制信号EM1(N+1)、第N+1行第二发光控制信号EM2(N+1)、第N+1行补偿信号COMP(N+1)、第N+1行复位信号RST(N+1)、第N+1行扫描信号SCAN(N+1)以及数据信号DATA的控制，补偿阶段与写入阶段相互独立，补偿阶段并不受写入阶段的周期限制；且第N行像素电路与第N+1行像素电路之间也可以同时进行，并不产生相互 影响，因此，本实例提供的显示面板，同样适合于更高频驱动的应用中，具有较好的补偿效果。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，其中，包括：
    开关单元，用于根据扫描信号的控制，输出接入的数据信号；
    驱动单元，与所述开关单元的输出端连接，用于接入并根据所述数据信号，以驱动像素；
    第一发光控制单元，与所述驱动单元的输入端连接，用于根据第一发光控制信号的控制，输出接入的电源正信号；
    第二发光控制单元，与所述驱动单元的输出端连接，用于根据第二发光控制信号的控制，输出所述电源正信号；
    发光单元，与所述第二发光控制单元的输出端和电源负信号连接，用于所述像素显示；
    存储单元，与所述开关单元的输出端和所述驱动单元的输出端连接，用于存储所述驱动单元的阈值电压；
    分压单元，与所述电源正信号和所述驱动单元的输出端连接，用于对所述存储单元进行分压；
    复位单元，与所述驱动单元的输出端连接，用于根据复位信号的控制，拉低所述驱动单元的输出端电位至第一参考信号的电位；以及
    补偿单元，与所述开关单元的输出端连接，用于根据补偿信号输出接入的第二参考信号，以补偿所述阈值电压；
    其中，所述复位单元包括第六薄膜晶体管；所述第六薄膜晶体管的漏极与第二参考信号连接；所述第六薄膜晶体管的栅极与所述复位信号连接；所述第六薄膜晶体管的源极与所述分压单元连接；
    所述扫描信号的工作周期与所述补偿信号的工作周期位于不同的时序区间。
  2. 根据权利要求1所述的像素电路，其中，所述开关单元包括第一薄膜晶体管；
    所述第一薄膜晶体管的漏极与所述数据信号连接；所述第一薄膜晶体管的栅极与所述扫描信号连接；所述第一薄膜晶体管的源极与所述驱动单元连接。
  3. 根据权利要求2所述的像素电路，其中，所述驱动单元包括第二薄膜 晶体管；
    所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的源极连接；所述第二薄膜晶体管的漏极与所述第一发光控制单元的输出端连接；所述第二薄膜晶体管的源极与所述第二发光控制单元的输入端连接。
  4. 根据权利要求3所述的像素电路，其中，所述第一发光控制单元包括第三薄膜晶体管；
    所述第三薄膜晶体管的漏极与所述电源正信号连接；所述第三薄膜晶体管的栅极与所述第一发光控制信号连接；所述第三薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接。
  5. 根据权利要求4所述的像素电路，其中，所述第二发光控制单元包括第四薄膜晶体管；
    所述第四薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接；所述第四薄膜晶体管的栅极与所述第二发光控制信号连接；所述第四薄膜晶体管的源极与所述发光单元的输入端连接。
  6. 根据权利要求5所述的像素电路，其中，所述发光单元包括发光器件；
    所述发光器件的输入端与所述第四薄膜晶体管的源极连接；所述发光器件的输出端与所述电源负信号连接。
  7. 根据权利要求6所述的像素电路，其中，所述存储单元包括第一电容；
    所述第一电容的第一端与所述第二薄膜晶体管的栅极连接；所述第一电容的第二端与所述第二薄膜晶体管的源极连接。
  8. 根据权利要求7所述的像素电路，其中，所述分压单元包括第二电容；
    所述第二电容的第一端与所述电源正信号连接；所述第二电容的第二端与所述第一电容的第二端连接。
  9. 根据权利要求8所述的像素电路，其中，所述补偿单元包括第五薄膜晶体管；
    所述第五薄膜晶体管的漏极与所述第一参考信号连接；所述第五薄膜晶体管的栅极与所述补偿信号连接；所述第五薄膜晶体管的源极与所述第一电容的第一端连接。
  10. 根据权利要求9所述的像素电路，其中，所述第一薄膜晶体管、所述 第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管均为N型薄膜晶体管。
  11. 一种像素电路，其中，包括：
    开关单元，用于根据扫描信号的控制，输出接入的数据信号；
    驱动单元，与所述开关单元的输出端连接，用于接入并根据所述数据信号，以驱动像素；
    第一发光控制单元，与所述驱动单元的输入端连接，用于根据第一发光控制信号的控制，输出接入的电源正信号；
    第二发光控制单元，与所述驱动单元的输出端连接，用于根据第二发光控制信号的控制，输出所述电源正信号；
    发光单元，与所述第二发光控制单元的输出端和电源负信号连接，用于所述像素显示；
    存储单元，与所述开关单元的输出端和所述驱动单元的输出端连接，用于存储所述驱动单元的阈值电压；
    分压单元，与所述电源正信号和所述驱动单元的输出端连接，用于对所述存储单元进行分压；
    复位单元，与所述驱动单元的输出端连接，用于根据复位信号的控制，拉低所述驱动单元的输出端电位至第一参考信号的电位；以及
    补偿单元，与所述开关单元的输出端连接，用于根据补偿信号输出接入的第二参考信号，以补偿所述阈值电压；
    其中，所述扫描信号的工作周期与所述补偿信号的工作周期位于不同的时序区间。
  12. 根据权利要求11所述的像素电路，其中，所述开关单元包括第一薄膜晶体管；
    所述第一薄膜晶体管的漏极与所述数据信号连接；所述第一薄膜晶体管的栅极与所述扫描信号连接；所述第一薄膜晶体管的源极与所述驱动单元连接。
  13. 根据权利要求12所述的像素电路，其中，所述驱动单元包括第二薄膜晶体管；
    所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的源极连接；所述第二 薄膜晶体管的漏极与所述第一发光控制单元的输出端连接；所述第二薄膜晶体管的源极与所述第二发光控制单元的输入端连接。
  14. 根据权利要求13所述的像素电路，其中，所述第一发光控制单元包括第三薄膜晶体管；
    所述第三薄膜晶体管的漏极与所述电源正信号连接；所述第三薄膜晶体管的栅极与所述第一发光控制信号连接；所述第三薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接。
  15. 根据权利要求14所述的像素电路，其中，所述第二发光控制单元包括第四薄膜晶体管；
    所述第四薄膜晶体管的漏极与所述第二薄膜晶体管的源极连接；所述第四薄膜晶体管的栅极与所述第二发光控制信号连接；所述第四薄膜晶体管的源极与所述发光单元的输入端连接。
  16. 根据权利要求15所述的像素电路，其中，所述发光单元包括发光器件；
    所述发光器件的输入端与所述第四薄膜晶体管的源极连接；所述发光器件的输出端与所述电源负信号连接。
  17. 根据权利要求16所述的像素电路，其中，所述存储单元包括第一电容；
    所述第一电容的第一端与所述第二薄膜晶体管的栅极连接；所述第一电容的第二端与所述第二薄膜晶体管的源极连接。
  18. 根据权利要求17所述的像素电路，其中，所述分压单元包括第二电容；
    所述第二电容的第一端与所述电源正信号连接；所述第二电容的第二端与所述第一电容的第二端连接。
  19. 根据权利要求18所述的像素电路，其中，所述补偿单元包括第五薄膜晶体管；
    所述第五薄膜晶体管的漏极与所述第一参考信号连接；所述第五薄膜晶体管的栅极与所述补偿信号连接；所述第五薄膜晶体管的源极与所述第一电容的第一端连接。
  20. 一种显示面板，其中，包括如权利要求11所述的像素电路。
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