WO2024036751A1 - 像素驱动电路和显示面板 - Google Patents

像素驱动电路和显示面板 Download PDF

Info

Publication number
WO2024036751A1
WO2024036751A1 PCT/CN2022/128122 CN2022128122W WO2024036751A1 WO 2024036751 A1 WO2024036751 A1 WO 2024036751A1 CN 2022128122 W CN2022128122 W CN 2022128122W WO 2024036751 A1 WO2024036751 A1 WO 2024036751A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
transistor
light
initialization
signal input
Prior art date
Application number
PCT/CN2022/128122
Other languages
English (en)
French (fr)
Inventor
鲁建军
张兵
米磊
Original Assignee
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Publication of WO2024036751A1 publication Critical patent/WO2024036751A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the technical field of display, and in particular, to a pixel driving circuit and a display panel.
  • AMOLED Active-matrix organic light emitting diode
  • display panels support display modes with multiple refresh frequencies to meet people's needs for display panels in different application scenarios.
  • the display panel can be applied to a low refresh frequency display mode to reduce the power consumption of the display panel while meeting the display requirements.
  • the display panel can be applied to a high refresh frequency display mode to meet display requirements.
  • the refresh frequency of the display panel is relatively high, the one frame time of the pixel driving circuit is relatively short.
  • the duration of the threshold compensation stage is relatively short, which easily leads to insufficient threshold compensation time of the pixel driving circuit, resulting in poor threshold compensation effect of the pixel driving circuit, which in turn leads to the failure of the display panel.
  • the brightness uniformity is relatively poor.
  • This application provides a pixel driving circuit and a display panel to improve the threshold compensation effect of the pixel driving circuit and improve the brightness uniformity of the display panel.
  • embodiments of the present application provide a pixel driving circuit, including a driving module, a light-emitting module, a first initialization module, a data writing module, a threshold compensation module, a storage module, a compensation continuation module, a light-emitting control module and a second initialization module;
  • the first initialization module is connected to the light-emitting module, and the first initialization module is used to initialize the light-emitting module in the initialization phase;
  • the second initialization module is connected to the control end of the driving module, and the The second initialization module is used to initialize the control end of the driving module during the initialization phase;
  • the data writing module is connected to the second end of the driving module and the compensation continuation module, and the threshold compensation module Connected between the first end of the driving module and the control end, the data writing module is used to write the data voltage into the control end of the driving module and the control end of the driving module through the threshold compensation module during the data writing stage.
  • the storage module is connected between the control end of the driving module and the first initialization module, and the storage module is used to store the control end potential of the driving module; the first initialization module also is used to clamp the potential of the storage module; the compensation continuation module is used to perform threshold compensation on the control end of the driving module during the compensation continuation stage; the lighting control module is connected to the first power signal input end and the Between the light-emitting modules, the light-emitting control module is used to conduct the path between the first power signal input terminal and the light-emitting module during the light-emitting stage; the driving module is used to illuminate the light-emitting module during the light-emitting stage.
  • the module provides a driving current, and the light-emitting module emits light in response to the driving current.
  • the compensation continuation module includes a first storage capacitor
  • the first pole of the first storage capacitor is connected to the first voltage input terminal, and the second pole of the first storage capacitor is connected to the second terminal of the driving module;
  • the first power signal input terminal is multiplexed as the first voltage input terminal.
  • the data writing module includes a first transistor
  • the threshold compensation module includes a second transistor
  • the driving module includes a driving transistor
  • the first initialization module includes a third transistor
  • the first pole of the first transistor is connected to the data signal input end, and the second pole of the first transistor is connected to the second pole of the driving transistor and the second end of the compensation continuation module.
  • the gate electrode is connected to the first scan signal input terminal, the first electrode of the second transistor is connected to the first electrode of the driving transistor, the second electrode of the second transistor is connected to the gate electrode of the driving transistor and the first electrode of the driving transistor.
  • the first end of the memory module is connected, the gate of the second transistor is connected to the second scan signal input end, the first pole of the third transistor is connected to the first initialization signal input end, and the gate electrode of the third transistor is connected to the first initialization signal input end.
  • the second electrode is connected to the second end of the memory module and the anode of the light-emitting module, the gate of the third transistor is connected to the third scan signal input end; the second scan signal input end provides a second The effective level of the scanning signal is longer than the effective level of the first scanning signal provided by the first scanning signal input terminal.
  • the lighting control module includes a fourth transistor and a fifth transistor;
  • the first pole of the fourth transistor is connected to the first power signal input terminal
  • the second pole of the fourth transistor is connected to the first pole of the driving module
  • the gate of the fourth transistor is connected to the first power signal input terminal.
  • a light-emitting control signal input terminal is connected
  • the first pole of the fifth transistor is connected to the second pole of the driving module
  • the second pole of the fifth transistor is connected to the anode of the light-emitting module
  • the fifth transistor is connected to the anode of the light-emitting module.
  • the gate of the transistor is connected to the second light-emitting control signal input terminal, and the cathode of the light-emitting module is connected to the second power signal input terminal;
  • the first lighting control signal provided by the first lighting control signal input terminal controls the fourth transistor to be turned on during the lighting phase
  • the second lighting control signal provided by the second lighting control signal input terminal controls the conduction of the fourth transistor during the lighting phase.
  • the initialization phase and the light-emitting phase control the fifth transistor to be turned on.
  • the pixel driving circuit further includes a third initialization module
  • the third initialization module is connected to the second end of the driving module, and is used to initialize the second end of the driving module during the initialization phase.
  • the third initialization module includes a sixth transistor, a first pole of the sixth transistor is connected to the second initialization signal input terminal, and a second pole of the sixth transistor is connected to the second terminal of the driving module.
  • the gate electrode of the sixth transistor is connected to the fourth scan signal input terminal.
  • the pixel driving circuit further includes a seventh transistor
  • the first electrode of the seventh transistor is connected to the anode of the light-emitting module, the second electrode of the seventh transistor is connected to the third initialization signal input terminal, and the gate electrode of the seventh transistor is connected to the fourth scanning Signal input terminal connection.
  • the second initialization signal input terminal is multiplexed as the third initialization signal input terminal.
  • the second initialization module includes an eighth transistor, the first pole of the eighth transistor is connected to the fourth initialization signal input terminal, and the second pole of the eighth transistor is connected to the control terminal of the driving module. connected, the gate of the eighth transistor is connected to the fifth scan signal input terminal.
  • embodiments of the present application further provide a display panel, including the pixel driving circuit described in the first aspect.
  • the technical solution of the embodiment of the present application uses the data writing module to write the data voltage to the driving module and the compensation continuation module in the data writing stage, and then in the compensation continuation stage, the compensation continuation module can continue to write the data voltage to the driving module, Therefore, when the pixel driving circuit operates at a high refresh frequency, the threshold compensation time of the pixel driving circuit can be increased without affecting the duration of the data writing phase, thereby improving the threshold compensation effect of the pixel driving circuit and improving the performance of the display panel. brightness uniformity.
  • Figure 1 is a schematic structural diagram of a pixel driving circuit provided by the prior art
  • Figure 2 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 5 is a timing diagram corresponding to the pixel driving circuit provided in Figure 4.
  • Figure 6 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 7 is a timing diagram corresponding to the pixel driving circuit provided in Figure 6;
  • Figure 8 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 10 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • Figure 11 is a timing diagram corresponding to the pixel driving circuit provided in Figure 10;
  • FIG. 12 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by the prior art.
  • the pixel driving circuit includes a driving transistor Mdr, a data writing transistor M1, a threshold compensation transistor M2, a first light emitting control transistor M3, a second light emitting control transistor M4, an anode initialization transistor M5, a storage capacitor Cst and a light emitting transistor.
  • Device D1 The driving transistor Mdr, the data writing transistor M1, the threshold compensation transistor M2, the first light emission control transistor M3, the second light emission control transistor M4, and the anode initialization transistor M5 are exemplarily shown to be N-type transistors, and their specific connection relationships are as follows As shown in Figure 1.
  • the threshold compensation transistor M2 the first light emission control transistor M3 and the anode initialization transistor M5 are turned on, and the first voltage provided by the first voltage input terminal Vdd is written through the threshold compensation transistor M2
  • the gate of the driving transistor Mdr realizes the gate initialization of the driving transistor Mdr, so that the driving transistor Mdr is turned on.
  • the initialization voltage is written into the anode of the light-emitting device D1 through the anode initialization transistor M5, thereby realizing the anode initialization of the light-emitting device D1.
  • the driving transistor Mdr In the data writing phase, the driving transistor Mdr is in the on state, the data writing transistor M1, the threshold compensation transistor M2 and the anode initialization transistor M5 are in the on state, and the data voltage vdata passes through the data writing transistor M1, the driving transistor Mdr and the threshold compensation
  • the transistor M2 writes to the gate of the driving transistor Mdr to realize the writing of the data voltage vdata and the threshold compensation of the driving transistor Mdr.
  • the storage capacitor Cst maintains the gate potential of the driving transistor Mdr. At the same time, the other end of the storage capacitor Cst maintains the initialization voltage.
  • the first light-emitting control transistor M3 and the second light-emitting control transistor M4 are turned on, and the driving transistor Mdr forms a driving current according to the first voltage and the gate potential provided by the first voltage input terminal Vdd, and passes through the second light-emitting control transistor M4 is transmitted to the anode of the light-emitting device D1, driving the light-emitting device D1 to emit light.
  • the data writing stage of the pixel driving circuit In the data writing stage of the pixel driving circuit, it takes a relatively long time to complete the threshold compensation of the driving transistor Mdr.
  • the time of each stage of the pixel driving circuit is relatively short, so that the length of the data writing stage of the pixel driving circuit cannot meet the time required for threshold compensation of the driving transistor Mdr, resulting in pixel driving
  • the threshold compensation effect of the circuit is relatively poor, which leads to poor brightness uniformity of the display panel.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit includes a driving module 10, a light emitting module 20, a first initialization module 30, a data writing module 40, a threshold compensation module 50, a storage module 60, a compensation continuation module 70, a light emitting control module 80 and The second initialization module 90;
  • the first initialization module 30 is connected to the light-emitting module 20, and the first initialization module 30 is used to initialize the light-emitting module 20 during the initialization phase;
  • the second initialization module 90 is connected to the control end of the driving module 10, and the second initialization module 90 is connected to the control end of the driving module 10.
  • the initialization module 90 is used to initialize the control end of the drive module 10 during the initialization phase; the data writing module 40 is connected to the second end of the drive module 10 and the compensation continuation module 70 , and the threshold compensation module 50 is connected to the first end of the drive module 10 Between the terminal and the control terminal, the data writing module 40 is used to write the data voltage into the control terminal of the driving module 10 and the compensation continuation module 70 through the threshold compensation module 50 during the data writing phase; the storage module 60 is connected to the driving module 10 Between the control terminal and the first initialization module 30, the storage module 60 is used to store the control terminal potential of the drive module 10; the first initialization module 30 is also used to clamp the potential of the storage module 60; the compensation continuation module 70 is used to compensate for the continuation.
  • threshold compensation is performed on the control terminal of the driving module 10; the lighting control module 80 is connected between the first power signal input terminal VDD and the lighting module 20, and the lighting control module 80 is used to conduct the first power signal input terminal VDD during the lighting stage. and the light-emitting module 20; the driving module 10 is used to provide driving current to the light-emitting module 20 during the light-emitting stage, and the light-emitting module 20 emits light in response to the driving current.
  • the first initialization module 30 is connected to the light-emitting module 20.
  • the first initialization module 30 can receive the first initialization signal.
  • the first initialization module 30 transmits the first initialization signal to the light-emitting module 20.
  • the module 20 initializes the light-emitting module 20 to avoid the problem of "stealing brightness" of the pixel driving circuit during the initialization stage and the image afterimage phenomenon when driving the light-emitting module 20 to emit light.
  • the first initialization signal may be a fixed potential signal.
  • the first initialization module 30 is connected to the second end of the memory module 60.
  • the second initialization module 90 is connected to the control end of the drive module 10.
  • the second initialization module 90 can receive an initialization signal and transmit the initialization signal to the control end of the drive module 10 when the second initialization module 90 is in the pass state.
  • the control end of the driving module 10 is initialized to improve the impact of the data voltage of the previous frame on the current frame, and at the same time, the driving module 10 is in a conductive state.
  • the data writing module 40 is connected to the second end of the driving module 10 and the second end of the compensation continuation module 70 , the first end of the compensation continuation module 70 is connected to a fixed potential, and the threshold compensation module 50 is connected to the first end of the driving module 10 Between the storage module 60 and the control end, the first end of the storage module 60 is connected to the control end of the driving module 10 .
  • the data writing module 40 and the threshold compensation module 50 are in a pass state, the data writing module 40 writes the data voltage into the compensation continuation module 70, and the compensation continuation module 70 stores the data voltage.
  • the data voltage is written into the control terminal of the driving module 10 through the driving module 10 and the threshold compensation module 50 to realize the writing of the data voltage and the threshold compensation of the driving module 10 .
  • the data writing module 40 is in an off-circuit state, so that the data writing phase meets the operating frequency requirements of the pixel driving circuit, the threshold compensation module 50 maintains the path state, and the data voltage stored in the compensation continuation module 70 passes through the driving module 10 and the threshold
  • the compensation module 50 continues to write to the control terminal of the driving module 10, which can continue the writing of data voltage and the threshold compensation of the driving module 10, increasing the threshold compensation time of the driving module 10, so that the pixel driving circuit can operate at a high refresh frequency.
  • the threshold compensation time of the pixel driving circuit is increased, thereby improving the threshold compensation effect of the pixel driving circuit and improving the brightness uniformity of the display panel.
  • the storage module 60 stores the potential difference between the two ends.
  • the light-emitting control module 80 is connected between the first power signal input terminal VDD and the light-emitting module 20. During the light-emitting phase, the light-emitting control module 80 conducts the path between the first power signal input terminal VDD and the light-emitting module 20, so that the driving module 10
  • the driving current formed according to the potential difference across the memory module 60 is transmitted to the light-emitting module 20 , and the light-emitting module 20 emits light in response to the driving current.
  • the technical solution of this embodiment uses the data writing module to write the data voltage to the driving module and the compensation continuation module in the data writing phase. Then in the compensation continuation phase, the compensation continuation module can continue to write the data voltage to the driving module, so that When the pixel drive circuit operates at a high refresh frequency, the threshold compensation time of the pixel drive circuit can be increased without affecting the duration of the data writing phase, thereby improving the threshold compensation effect of the pixel drive circuit and improving the performance of the display panel. Brightness uniformity.
  • FIG. 3 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the compensation continuation module 70 includes a first storage capacitor C1; the first pole of the first storage capacitor C1 is connected to the first voltage input terminal V1, and the second pole of the first storage capacitor C1 is connected to the third pole of the driving module 10. Two-terminal connection.
  • the first voltage V1 provided by the first voltage input terminal V1 may be a voltage signal with a fixed potential.
  • the first pole of the first storage capacitor C1 is connected to the first voltage input terminal V1, so that the potential of the first pole of the first storage capacitor C1 is fixed.
  • the second pole of the first storage capacitor C1 is connected to the second terminal of the driving module 10 , that is, connected to the data writing module 40 .
  • the data voltage provided by the data writing module 40 is written into the second pole of the first storage capacitor C1 so that the first storage capacitor C1 can store the data voltage.
  • the data writing module 40 is in an off-circuit state, so that the data writing phase meets the operating frequency requirements of the pixel driving circuit, and at the same time, the threshold compensation module 50 maintains the path state, and the data voltage stored in the first storage capacitor C1 passes through the driving module 10 and the threshold compensation module 50 continue to write to the control end of the driving module 10, and the writing of the data voltage and the threshold compensation of the driving module 10 can be continued, increasing the threshold compensation time of the driving module 10, so that the pixel driving circuit can work at high When refreshing the frequency, the threshold compensation time of the pixel driving circuit is increased without affecting the length of the data writing phase, thereby improving the threshold compensation effect of the pixel driving circuit and improving the brightness uniformity of the display panel.
  • FIG. 3 exemplarily shows that the compensation continuation module 70 includes the first storage capacitor C1.
  • the compensation continuation module 70 may also include multiple capacitors to meet the capacitance value required for data voltage storage.
  • the compensation continuation module 70 may also include other components with storage functions, which are not limited here.
  • the first power signal input terminal VDD is multiplexed as the first voltage input terminal V1.
  • the first power signal provided by the first power signal input terminal VDD is a signal with a fixed potential.
  • the first power signal input terminal VDD By setting the first power signal input terminal VDD to be multiplexed as the first voltage input terminal V1, on the basis that the first power signal provided by the first power signal input terminal VDD can fix the first pole potential of the first storage capacitor C1, Avoiding the additional setting of the first voltage input terminal V1 can avoid setting additional wiring on the display panel for transmitting the first voltage, which is beneficial to simplifying the wiring design on the display panel.
  • the display panel is also provided with an initialization signal line, with To provide initialization signal.
  • the initialization signal has a fixed potential.
  • the initialization signal line can be used to provide a fixed potential for the first voltage input terminal V1, which is not limited here.
  • FIG. 4 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the data writing module 40 includes a first transistor T1
  • the threshold compensation module 50 includes a second transistor T2
  • the driving module 10 includes a driving transistor Tdr
  • the first initialization module 30 includes a third transistor T3; the first transistor T1
  • the first electrode of the first transistor T1 is connected to the data signal input terminal VDATA
  • the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor Tdr and the second end of the compensation continuation module 70
  • the gate electrode of the first transistor T1 is connected to the first scanning
  • the signal input terminal S1 is connected
  • the first pole of the second transistor T2 is connected to the first pole of the driving transistor Tdr
  • the second pole of the second transistor T2 is connected to the gate of the driving transistor Tdr and the first terminal of the memory module 60
  • the The gate of the second transistor T2 is connected to the second scan signal input terminal S2, the first electrode of the third transistor
  • the gate of the third transistor T3 is connected to the third scanning signal input terminal S3; the effective level of the second scanning signal provided by the second scanning signal input terminal S2 is longer than the first scanning signal input terminal.
  • FIG. 4 exemplarily shows that the first transistor T1, the second transistor T2, the third transistor T3 and the driving transistor Tdr are all N-type transistors.
  • the first transistor T1 When the first scan signal provided by the first scan signal input terminal S1 is high level, the first transistor T1 is turned on.
  • the second scan signal provided by the second scan signal input terminal S2 is high level, the second transistor T2 is turned on.
  • the third scan signal provided by the third scan signal input terminal S3 is high level, the third transistor T3 is turned on.
  • the first terminal of the compensation continuation module 70 is connected to the first voltage input terminal V1 , and the first voltage provided by the first voltage input terminal V1 fixes the potential of the first terminal of the compensation continuation module 70 .
  • the storage module 60 may include a second storage capacitor C2.
  • the first end of the memory module 60 is connected to the gate of the driving transistor Tdr, and is used to store the potential of the gate of the driving transistor Tdr.
  • the light-emitting module 20 may be a light-emitting device E1.
  • FIG. 5 is a timing diagram corresponding to the pixel driving circuit provided in FIG. 4 . Wherein, s1 is a timing sequence of the first scanning signal, s2 is a timing sequence of the second scanning signal, and s3 is a timing sequence of the third scanning signal. The working process of the pixel driving circuit will be described below with reference to Figures 4 and 5.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is high level
  • the first transistor T1 and the second transistor T2 are turned off
  • the third transistor T3 is turned on.
  • the first initialization signal provided by the first initialization signal input terminal VREF1 is transmitted to the second end of the memory module 60 and the anode of the light-emitting module 20 through the third transistor T3 to initialize the light-emitting module 20 and fix the second terminal of the memory module 60 terminal potential.
  • the second initialization module 90 initializes the control end of the driving module 10 .
  • the first scanning signal is high level
  • the second scanning signal is high level
  • the third scanning signal is high level
  • the first transistor T1, the second transistor T2 and the third transistor T3 are turned on.
  • the data voltage provided by the data signal input terminal VDATA is written into the second end of the compensation continuation module 70 through the first transistor T1
  • the compensation continuation module 70 stores the data voltage.
  • the first transistor T1 writes the data voltage into the gate of the driving transistor Tdr through the driving transistor Tdr and the second transistor T2, thereby realizing the writing of the data voltage and the threshold compensation of the driving transistor Tdr.
  • the memory module 60 stores the gate potential of the drive transistor Tdr. Since the potential of the second terminal of the memory module 60 is the first initialization signal, that is, the potential of the second terminal of the memory module 60 is fixed, the accuracy of the gate potential of the storage drive transistor Tdr of the memory module 60 can be ensured.
  • the first scan signal is low level
  • the second scan signal is high level
  • the third scan signal is high level.
  • the first transistor T1 is turned off, and the second transistor T2 and the third transistor T3 are turned on.
  • the first transistor T1 stops providing the data voltage, so that the process of writing the data voltage to the pixel driving circuit is only completed during the data writing phase, meeting the time requirement of the data writing phase of the pixel driving circuit working at a high refresh frequency.
  • the second transistor T2 is turned on, so that the data voltage stored in the compensation continuation module 70 is written into the gate of the driving transistor Tdr through the driving transistor Tdr and the second transistor T2, and the data voltage can be continuously written into the gate of the driving transistor Tdr, and the driving
  • the threshold compensation process of the transistor Tdr increases the threshold compensation time of the driving transistor Tdr, thereby increasing the threshold compensation of the pixel driving circuit without affecting the length of the data writing phase when the pixel driving circuit operates at a high refresh frequency. time, thereby improving the threshold compensation effect of the pixel driving circuit and improving the brightness uniformity of the display panel.
  • a transition phase is also included.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is high level
  • the first transistor T1 and the second transistor T2 are turned off
  • the third transistor T3 is turned on.
  • the data writing phase and compensation continuation phase are completed.
  • the third transistor T3 is turned on to keep the anode of the light-emitting module 20 initialized
  • the potential of the second terminal of the memory module 60 is the first initialization signal, that is, the potential of the second terminal of the memory module 60 is fixed.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is low level.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are turned off.
  • the first terminal of the second storage capacitor C2 is in a floating state.
  • the light-emitting control module 80 turns on the path between the first power signal input terminal VDD and the light-emitting module 20
  • the potential of the second end of the second storage capacitor C2 changes, and drives the second storage device according to the coupling effect of the second storage capacitor C2.
  • the potential of the first terminal of the capacitor C2 changes so that the potential difference between the two terminals of the second storage capacitor C2 remains unchanged.
  • the driving current formed by the driving transistor Tdr according to the potential difference across the second storage capacitor C2 is transmitted to the light-emitting device E1, and the light-emitting device E1 emits light in response to the driving current.
  • the lighting control module 80 may include a fourth transistor T4 and a fifth transistor T5 .
  • the first electrode of the fourth transistor T4 is connected to the first power signal input terminal VDD, and the second electrode of the fourth transistor T4 is connected to the first power signal input terminal VDD.
  • the first pole of the fifth transistor T5 is connected to the first pole of the driving transistor Tdr, the first pole of the fifth transistor T5 is connected to the second pole of the driving transistor Tdr, the second pole of the fifth transistor T5 is connected to the anode of the light-emitting module 20, the fourth transistor T4 and The gate of the fifth transistor T5 is connected to the light-emitting control signal input terminal EM, and the cathode of the light-emitting module 20 is connected to the second power signal input terminal VSS.
  • FIG. 4 exemplarily shows that the fourth transistor T4 and the fifth transistor T5 are N-type transistors.
  • the light-emitting control signal em provided by the light-emitting control signal input terminal EM is at a high level, controlling the fourth transistor T4 and the fifth transistor T5 to turn on, so that the second storage capacitor C2
  • the potential of the two terminals changes, and drives the potential of the first terminal of the second storage capacitor C2 to change according to the coupling effect of the second storage capacitor C2, maintaining the potential difference between the two terminals of the second storage capacitor C2 unchanged.
  • the driving transistor Tdr forms a driving current according to the potential difference of the second storage capacitor C2, and transmits it to the anode of the light-emitting device E1 through the fifth transistor T5, and the light-emitting device E1 emits light according to the driving current.
  • FIG. 4 exemplarily shows that the first transistor T1, the second transistor T2, the third transistor T3 and the driving transistor Tdr are all N-type transistors.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the driving transistor Tdr may also be P-type transistors, in which case the first scanning signal, the second scanning signal and the third scanning signal are adaptively adjusted. The timing is not limited here.
  • FIG. 6 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the lighting control module includes a fourth transistor T4 and a fifth transistor T5; the first pole of the fourth transistor T4 is connected to the first power signal input terminal VDD, and the second pole of the fourth transistor T4 is connected to the driving module 10
  • the first electrode of the fourth transistor T4 is connected to the first lighting control signal input terminal EM1
  • the first electrode of the fifth transistor T5 is connected to the second electrode of the driving module 10
  • the second electrode of the fifth transistor T5 The anode of the light-emitting module 20 is connected, the gate of the fifth transistor T5 is connected to the second light-emitting control signal input terminal EM2, and the cathode of the light-emitting module 20 is connected to the second power signal input terminal VSS;
  • the first light-emitting control signal input terminal EM1 provides The first light-emitting control signal controls the fourth transistor T4 to turn on during the light-emitting phase, and the
  • FIG. 6 exemplarily shows that the fourth transistor T4 and the fifth transistor T5 are N-type transistors.
  • the fourth transistor T4 When the first lighting control signal provided by the first lighting control signal input terminal EM1 is at a high level, the fourth transistor T4 is turned on.
  • the fourth transistor T4 When the second lighting control signal provided by the second lighting control signal input terminal EM2 is at a high level, the fourth transistor T4 is turned on. Five transistors T5 are turned on.
  • the third scan signal is high level
  • the second light emission control signal is high level
  • the third transistor T3 and the fifth transistor T5 are turned on
  • the first initialization signal is transmitted through the third transistor T3 and the fifth transistor T5
  • the second end of the driving module 10 can be initialized, and the driving module 10 can be further reset, which is beneficial to further improving the image sticking phenomenon when the pixel driving circuit drives the light-emitting module 20 to emit light.
  • the first scanning signal, the second scanning signal and the third scanning signal are low level
  • the first light-emitting control signal is high level
  • the second light-emitting control signal is high level
  • the first transistor T1 and the second light-emitting control signal are high level.
  • the transistor T2 and the third transistor T3 are turned off, and the first terminal of the second storage capacitor C2 is in a floating state.
  • the fourth transistor T4 and the fifth transistor T5 are both turned on, and the potential of the second terminal of the second storage capacitor C2 changes, and drives the potential of the first terminal of the second storage capacitor C2 to change according to the coupling effect of the second storage capacitor C2, so that the potential of the second storage capacitor C2 changes.
  • the potential difference across the storage capacitor C2 remains unchanged.
  • the driving transistor Tdr forms a driving current based on the potential difference across the second storage capacitor C2 and transmits it to the anode of the light-emitting module 20 through the fifth transistor T5.
  • the light-emitting module 20 emits light according to the driving current.
  • the light-emitting module 20 may be a light-emitting device E1.
  • the display panel is provided with a light-emitting control drive circuit and a multi-row pixel drive circuit.
  • the light-emitting control drive circuit includes a multi-stage cascaded shift register. Each stage of the shift register outputs a level of light-emitting control signal in turn for driving one row of pixels.
  • the circuit provides lighting control signals.
  • the second light-emitting control signal corresponding to the row of pixel driving circuits can be the light-emitting control signal output by the lower-level shift register, so that the second light-emitting control signal is effective
  • the level sequence lags the effective level sequence of the first light-emitting control signal, that is, the high level of the second light-emitting control signal lags the high level of the first light-emitting control signal, so that in the initialization stage, the second light-emitting control signal is an effective level. (that is, high level), the fifth transistor T5 is controlled to be turned on, and the second terminal of the driving module 10 is initialized.
  • FIG. 7 is a timing diagram corresponding to the pixel driving circuit provided in FIG. 6 .
  • s1 is a timing sequence of the first scanning signal
  • s2 is a timing sequence of the second scanning signal
  • s3 is a timing sequence of the third scanning signal
  • em1 is the first lighting signal provided by the first lighting control signal input terminal EM1.
  • a timing sequence of the control signal, em2 is a timing sequence of the second lighting control signal provided by the second lighting control signal input terminal EM2.
  • the working process of the pixel driving circuit will be described below with reference to Figures 6 and 7.
  • the first scanning signal is low level
  • the second scanning signal is low level
  • the third scanning signal is high level
  • the first lighting control signal is low level
  • the second lighting control signal is high level. level
  • the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off
  • the third transistor T3 and the fifth transistor T5 are turned on
  • the first initialization signal provided by the first initialization signal input terminal VREF1 is transmitted through the third transistor T3 to the second end of the memory module 60 and the anode of the light-emitting module 20 to initialize the anode of the light-emitting module 20 and fix the potential of the second end of the memory module 60 .
  • the first initialization signal is transmitted to the second end of the driving module 10 through the third transistor T3 and the fifth transistor T5.
  • the second end of the driving module 10 can be initialized, and the driving module 10 can be further reset, which is beneficial to further The image sticking phenomenon when the pixel driving circuit drives the light-emitting module 20 to emit light is improved.
  • the second initialization module 90 initializes the control end of the driving module 10 .
  • the first scanning signal is high level
  • the second scanning signal is high level
  • the third scanning signal is high level
  • the first lighting control signal is low level
  • the second lighting control signal is Low level
  • the first transistor T1, the second transistor T2 and the third transistor T3 are turned on
  • the fourth transistor T4 and the fifth transistor T5 are turned off
  • the data voltage provided by the data signal input terminal VDATA is written and compensated through the first transistor T1
  • the compensation continuation module 70 stores the data voltage.
  • the first transistor T1 writes the data voltage into the gate of the driving transistor Tdr through the driving transistor Tdr and the second transistor T2, thereby realizing the writing of the data voltage and the threshold compensation of the driving transistor Tdr.
  • the memory module 60 stores the gate potential of the drive transistor Tdr. Since the potential of the second terminal of the memory module 60 is the first initialization signal, that is, the potential of the second terminal of the memory module 60 is fixed, the accuracy of the gate potential of the storage drive transistor Tdr of the memory module 60 can be ensured.
  • the first scanning signal is low level
  • the second scanning signal is high level
  • the third scanning signal is high level
  • the first lighting control signal is low level
  • the second lighting control signal is low level
  • the first transistor T1, the fourth transistor T4 and the fifth transistor T5 are turned off
  • the second transistor T2 and the third transistor T3 are turned on
  • the first transistor T1 stops providing the data voltage, causing the data voltage to be written into the pixel driving circuit.
  • the process is only completed in the data writing phase, which meets the time requirements of the data writing phase of the pixel drive circuit working at a high refresh frequency.
  • the second transistor T2 is turned on, so that the data voltage stored in the compensation continuation module 70 is written into the gate of the driving transistor Tdr through the driving transistor Tdr and the second transistor T2, and the data voltage can be continuously written into the gate of the driving transistor Tdr, and the driving
  • the threshold compensation process of the transistor Tdr increases the threshold compensation time of the driving transistor Tdr, thereby increasing the threshold compensation of the pixel driving circuit without affecting the length of the data writing phase when the pixel driving circuit operates at a high refresh frequency. time, thereby improving the threshold compensation effect of the pixel driving circuit and improving the brightness uniformity of the display panel.
  • a transition phase is also included.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is high level
  • the first transistor T1 and the second transistor T2 are turned off
  • the third transistor T3 is turned on.
  • the data writing phase and compensation continuation phase are completed.
  • the third transistor T3 is turned on to keep the anode of the light-emitting module 20 initialized
  • the potential of the second terminal of the memory module 60 is the first initialization signal, that is, the potential of the second terminal of the memory module 60 is fixed.
  • the first scanning signal is low level
  • the second scanning signal is low level
  • the third scanning signal is low level
  • the first lighting control signal is high level
  • the second lighting control signal is high level
  • the second lighting control signal is high level.
  • the first transistor T1, the second transistor T2 and the third transistor T3 are turned off, and the first end of the second storage capacitor C2 is in a floating state.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the potential of the second terminal of the second storage capacitor C2 changes, and drives the potential of the first terminal of the second storage capacitor C2 to change according to the coupling effect of the second storage capacitor C2, so that the second terminal of the second storage capacitor C2 changes.
  • the potential difference across storage capacitor C2 remains unchanged.
  • the driving transistor Tdr forms a driving current based on the potential difference across the second storage capacitor C2 and transmits it to the anode of the light-emitting module 20 through the fifth transistor T5.
  • the light-emitting module 20 emits light according to the driving current.
  • the light-emitting module 20 may be a light-emitting device E1.
  • FIG. 8 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit also includes a third initialization module 100; the third initialization module 100 is connected to the second end of the driving module 10, and the third initialization module 100 is used to configure the second end of the driving module 10 during the initialization phase. Perform initialization.
  • FIG. 8 exemplarily shows that the light-emitting control module 80 is only used to conduct the path between the first power signal input terminal VDD and the light-emitting module 20 during the light-emitting phase, so that the driving transistor Tdr is configured according to the voltage across the memory module 60 .
  • the driving current formed by the potential difference is transmitted to the light-emitting module 20, and the light-emitting module 20 emits light in response to the driving current.
  • the light emission control module 80 may include a fourth transistor T4 and a fifth transistor T5, the gates of the fourth transistor T4 and the fifth transistor T5 are connected to the light emission control signal input terminal EM.
  • the pixel driving circuit can be configured to include a third initialization module 100.
  • the third initialization module 100 can receive the second initialization signal.
  • the third initialization module 100 is in the pass state, and the third initialization module 100 converts the second initialization signal to the pass state.
  • Initializing the signal to transmit the second end of the driving module 10 and initializing the second end of the driving module 10 can further reset the driving module 10, which is conducive to further improving the afterimage phenomenon when the pixel driving circuit drives the light-emitting module 20 to emit light. . It can be seen from this that by using only one lighting control signal input terminal EM to control the state of the lighting control module 80 , the control signal of the lighting control module 80 can be simplified. Then, the second end of the driving module 10 is initialized through the third initialization module 100 to ensure the effect of the pixel driving circuit driving the light-emitting module 20 to emit light.
  • one frame time is the time required for the display panel to refresh once, that is, the time required for scanning from the first row of pixel driving circuits to the last row of pixel driving circuits on the display panel.
  • Different refresh frequencies correspond to different frame times. For example, when the refresh frequency is 10HZ, the scanning time from the first line to the last line of the display panel is 100ms, that is, one frame time is 100ms. When the refresh frequency is 120HZ, the scanning time from the first line of the display panel to the last line is about 8.3ms, that is, one frame time is 8.3ms.
  • one frame time during which the pixel driving circuit operates may include one subframe.
  • one frame time of the pixel driving circuit operation may include multiple subframes.
  • the multiple subframes are divided into writing frames and at least one holding frame.
  • Each subframe corresponds to one frame duration of the basic refresh frequency.
  • the basic refresh frequency is 120HZ
  • one frame time when the pixel drive circuit works at 10HZ can include 12 subframes, the first subframe is used as a write frame, and the remaining 11 subframes as holding frames.
  • the third initialization module 100 By arranging the third initialization module 100 to initialize the second end of the driving module 10 during the initialization stage of writing frames and holding frames, the afterimage phenomenon of the light-emitting module 20 when emitting light is improved, and at the same time, it is possible to initialize the writing frames and holding frames.
  • the characteristics of the driving module 10 are adjusted in stages, thereby reducing the impact of the characteristics of the driving module 10 on the luminous brightness of the light-emitting module 20, improving the brightness difference of the pixel driving circuit within one frame, thereby improving the flickering phenomenon of the display panel.
  • the third initialization module 100 includes a sixth transistor T6 .
  • the first pole of the sixth transistor T6 is connected to the second initialization signal input terminal VREF2 .
  • the second pole of the sixth transistor T6 is connected to the second terminal of the driving module 10 .
  • connection, the gate of the sixth transistor T6 is connected to the fourth scan signal input terminal S4.
  • FIG. 8 exemplarily shows that the sixth transistor T6 is an N-type transistor.
  • the sixth transistor T6 is turned on, and the second initialization signal provided by the second initialization signal input terminal VREF2 is written to the driving transistor Tdr through the sixth transistor T6
  • the second pole of the drive transistor Tdr is initialized, and the drive transistor Tdr can be further reset, which is beneficial to further improving the image sticking phenomenon when the pixel drive circuit drives the light-emitting module 20 to emit light.
  • the fourth scan signal provided by the fourth scan signal input terminal S4 is high level, and the sixth transistor T6 is turned on,
  • the second initialization signal provided by the second initialization signal input terminal VREF2 is transmitted to the second pole of the driving transistor Tdr through the sixth transistor T6 to initialize the second pole of the driving transistor Tdr.
  • the fourth scanning signal is low level and the sixth transistor T6 is turned off.
  • the fourth scan signal is high level, the sixth transistor T6 is turned on, and the second initialization signal is transmitted to the second pole of the drive transistor Tdr through the sixth transistor T6, and the third pole of the drive transistor Tdr is The two poles are initialized.
  • FIG. 9 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit also includes a seventh transistor T7; the first electrode of the seventh transistor T7 is connected to the anode of the light-emitting module 20, and the second electrode of the seventh transistor T7 is connected to the third initialization signal input terminal VREF3.
  • the gate of the seventh transistor T7 is connected to the fourth scan signal input terminal S4.
  • FIG. 9 exemplarily shows that the seventh transistor T7 is an N-type transistor.
  • the seventh transistor T7 and the sixth transistor T6 have the same conduction state.
  • the fourth scan signal provided by the fourth scan signal input terminal S4 is high level
  • the seventh transistor T7 is turned on at the same time
  • the third initialization signal provided by the third initialization signal input terminal VREF3 The seventh transistor T7 is transmitted to the anode of the light-emitting module 20 to initialize the anode of the light-emitting module 20 , which can improve the image sticking phenomenon when the pixel driving circuit drives the light-emitting module 20 to emit light.
  • the second initialization signal input terminal VREF2 is multiplexed into the third initialization signal input terminal VREF3.
  • the light-emitting control module 80 connects the path between the driving module 10 and the light-emitting module 20 so that the potential of the second end of the driving module 10 is the same as the anode potential of the light-emitting module 20 .
  • the second initialization signal input terminal VREF2 is multiplexed as the third initialization signal input terminal VREF3, so that the initial potential of the anode of the light-emitting module 20 is the same as the initial potential of the second terminal of the driving module 10, while ensuring the normal operation of the pixel driving circuit.
  • the settings of the initialization signal input terminal can be reduced, which in turn can reduce the wiring settings used to provide the initialization signal on the display panel, which is conducive to simplifying the wiring design on the display panel.
  • FIG. 10 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present application. As shown in Figure 10,
  • the second initialization module 90 includes an eighth transistor T8.
  • the first pole of the eighth transistor T8 is connected to the fourth initialization signal input terminal VREF4.
  • the second pole of the eighth transistor T8 is connected to the control terminal of the driving module 10.
  • the eighth transistor T8 The gate is connected to the fifth scan signal input terminal S5.
  • FIG. 10 exemplarily shows that the eighth transistor T8 is an N-type transistor.
  • the eighth transistor T8 is turned on, and the fourth initialization signal provided by the fourth initialization signal input terminal VREF4 is transmitted to the driving module 10 through the eighth transistor T8
  • the control end initializes the control end of the drive module 10 .
  • FIG. 10 exemplarily shows that the lighting control module 80 includes a fourth transistor T4 and a fifth transistor T5, and the gate electrode of the fourth transistor T4 and the gate electrode of the fifth transistor T5 are both connected to the lighting control signal input terminal EM.
  • FIG. 11 is a timing diagram corresponding to the pixel driving circuit provided in FIG. 10 .
  • s1 is a timing sequence of the first scanning signal
  • s2 is a timing sequence of the second scanning signal
  • s3 is a timing sequence of the third scanning signal
  • s4 is a timing sequence of the fourth scanning signal
  • s5 is a timing sequence of the fifth scanning signal.
  • a timing of the scanning signal, em is a timing of the lighting control signal provided by the lighting control signal input terminal EM.
  • the first scanning signal is low level
  • the second scanning signal is low level
  • the third scanning signal is high level
  • the fourth scanning signal is high level
  • the fifth scanning signal is High level
  • the light-emitting control signal is low level
  • the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off
  • the third transistor T3, the sixth transistor T6, the seventh transistor T7 and the third transistor T7 are turned off.
  • the eight transistor T8 is turned on, and the first initialization signal provided by the first initialization signal input terminal VREF1 is transmitted to the second end of the memory module 60 and the anode of the light-emitting module 20 through the third transistor T3 to initialize the light-emitting module 20 and fix the storage.
  • the second terminal potential of module 60 The second terminal potential of module 60.
  • the third initialization signal provided by the third initialization signal input terminal VREF3 is also transmitted to the anode of the light-emitting module 20 through the seventh transistor T7 to initialize the anode of the light-emitting module 20 .
  • the second initialization signal provided by the second initialization signal input terminal VREF2 is transmitted to the second pole of the driving transistor Tdr through the sixth transistor T6 to initialize the second pole of the driving transistor Tdr.
  • the fourth initialization signal provided by the fourth initialization signal input terminal REF4 is transmitted to the gate of the driving transistor Tdr through the eighth transistor T8 to initialize the gate of the driving transistor Tdr.
  • the first scanning signal is high level
  • the second scanning signal is high level
  • the third scanning signal is high level
  • the fourth scanning signal is low level
  • the fifth scanning signal is high level.
  • the signal is low level
  • the light emission control signal is low level
  • the first transistor T1, the second transistor T2 and the third transistor T3 are turned on
  • the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 and the eighth transistor T8 is turned off
  • the data voltage provided by the data signal input terminal VDATA is written into the second end of the compensation continuation module 70 through the first transistor T1, and the compensation continuation module 70 stores the data voltage.
  • the first transistor T1 writes the data voltage into the gate of the driving transistor Tdr through the driving transistor Tdr and the second transistor T2, thereby realizing the writing of the data voltage and the threshold compensation of the driving transistor Tdr.
  • the memory module 60 stores the gate potential of the drive transistor Tdr. Since the potential of the second terminal of the memory module 60 is the first initialization signal, that is, the potential of the second terminal of the memory module 60 is fixed, the accuracy of the gate potential of the storage drive transistor Tdr of the memory module 60 can be ensured.
  • the first scanning signal is low level
  • the second scanning signal is high level
  • the third scanning signal is high level
  • the fourth scanning signal is low level
  • the fifth scanning signal is low level
  • the light emission control signal is low level
  • the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off
  • the third transistor T3 is turned on, and the first transistor T1 stops providing the data voltage, so that the process of writing the data voltage to the pixel driving circuit is only completed during the data writing phase, which meets the time required for the pixel driving circuit to work in the data writing phase at a high refresh frequency. need.
  • the second transistor T2 is turned on, so that the data voltage stored in the compensation continuation module 70 is written into the gate of the driving transistor Tdr through the driving transistor Tdr and the second transistor T2, and the data voltage can be continuously written into the gate of the driving transistor Tdr, and the driving
  • the threshold compensation process of the transistor Tdr increases the threshold compensation time of the driving transistor Tdr, thereby increasing the threshold compensation of the pixel driving circuit without affecting the length of the data writing phase when the pixel driving circuit operates at a high refresh frequency. time, thereby improving the threshold compensation effect of the pixel driving circuit and improving the brightness uniformity of the display panel.
  • a transition phase is also included.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is high level
  • the first transistor T1 and the second transistor T2 are turned off
  • the third transistor T3 is turned on.
  • the data writing phase and compensation continuation phase are completed.
  • the third transistor T3 is turned on to keep the anode of the light-emitting module 20 initialized
  • the potential of the second terminal of the memory module 60 is the first initialization signal, that is, the potential of the second terminal of the memory module 60 is fixed.
  • the first scanning signal is low level
  • the second scanning signal is low level
  • the third scanning signal is low level
  • the fourth scanning signal is low level
  • the fifth scanning signal is Low level
  • the light emission control signal is high level
  • the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off
  • the second storage capacitor C2 The first end is floating.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the potential of the second terminal of the second storage capacitor C2 changes, and drives the potential of the first terminal of the second storage capacitor C2 to change according to the coupling effect of the second storage capacitor C2, so that the second terminal of the second storage capacitor C2 changes.
  • the potential difference across storage capacitor C2 remains unchanged.
  • the driving transistor Tdr forms a driving current based on the potential difference across the second storage capacitor C2 and transmits it to the anode of the light-emitting module 20 through the fifth transistor T5.
  • the light-emitting module 20 emits light according to the driving current.
  • the light-emitting module 20 may be a light-emitting device E1.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is low level
  • the fourth scan signal is high level
  • the fifth scan signal is low level. level
  • the light-emitting control signal is low level
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 are turned off
  • the sixth transistor T6 and the seventh transistor are turned off.
  • the transistor T7 is turned on, and the second initialization signal provided by the second initialization signal input terminal VREF2 is transmitted to the second pole of the driving transistor Tdr through the sixth transistor T6 to initialize the second pole of the driving transistor Tdr.
  • the third initialization signal provided by the third initialization signal input terminal VREF3 is transmitted to the anode of the light-emitting module 20 through the seventh transistor T7 to initialize the anode of the light-emitting module 20 .
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is low level
  • the fourth scan signal is low level
  • the fifth scan signal is low level. level
  • the light emission control signal is low level
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are all turned off, maintaining the current state of the pixel drive circuit.
  • the first scan signal is low level
  • the second scan signal is low level
  • the third scan signal is low level
  • the fourth scan signal is low level
  • the fifth scan signal is low level. level
  • the light-emitting control signal is high level
  • the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off, and the second storage capacitor C2 One end is floating.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the potential of the second terminal of the second storage capacitor C2 changes, and drives the potential of the first terminal of the second storage capacitor C2 to change according to the coupling effect of the second storage capacitor C2, so that the second terminal of the second storage capacitor C2 changes.
  • the potential difference across storage capacitor C2 remains unchanged.
  • the driving transistor Tdr forms a driving current based on the potential difference across the second storage capacitor C2 and transmits it to the anode of the light-emitting module 20 through the fifth transistor T5.
  • the light-emitting module 20 emits light according to the driving current.
  • FIG. 12 is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 12 , the display panel includes the pixel driving circuit 101 provided in any embodiment of the present application.
  • the display panel includes a display area AA.
  • the display area AA is provided with a plurality of pixel units P.
  • Each pixel unit P includes a pixel driving circuit 101 and a light-emitting device E1 provided in any embodiment of the present application.
  • the pixel driving circuit 101 is a light-emitting device.
  • E1 provides a driving current to drive the light-emitting device E1 to emit light. Since the display panel includes the pixel driving circuit 101 provided in any embodiment of the present application, it has the same beneficial effects as the pixel driving circuit 101, which will not be described again here.

Abstract

一种像素驱动电路和显示面板，在像素驱动电路中，第一初始化模块（30）用于在初始化阶段对发光模块（20）进行初始化；第二初始化模块（90）用于在初始化阶段对驱动模块（10）的控制端进行初始化；数据写入模块（40）用于在数据写入阶段将数据电压通过阈值补偿模块（50）写入驱动模块（10）的控制端和补偿延续模块（70）；存储模块（60）用于存储驱动模块（10）的控制端电位；第一初始化模块（30）还用于钳位存储模块（60）的电位；补偿延续模块（70）用于在补偿延续阶段对驱动模块（10）的控制端进行阈值补偿；发光控制模块（80）用于在发光阶段导通第一电源信号输入端（VDD）和发光模块（20）之间的通路；驱动模块（10）用于在发光阶段向发光模块（20）提供驱动电流，发光模块（20）响应驱动电流发光。改善了像素驱动电路的阈值补偿效果和显示面板的亮度均一性。

Description

像素驱动电路和显示面板
本申请要求于2022年08月15日提交中国专利局、申请号为202210977072.6、申请名称为“像素驱动电路和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示的技术领域，尤其涉及一种像素驱动电路和显示面板。
背景技术
有源矩阵有机发光二极管(Active-matrix organic light emitting diode，AMOLED)显示面板由于在显示色彩饱和度、功耗和弯折等方面优胜于液晶显示面板，已经广泛应用于显示领域。在AMOLED显示面板显示的过程中，像素驱动电路驱动发光器件发光。
随着显示技术的发展，显示面板支持多种刷新频率的显示模式，以满足人们对显示面板在不同应用场景下的需求。例如，在息屏和电子书等应用场景下，显示面板可以应用于低刷新频率的显示模式，以在满足显示的需求的基础上降低显示面板的耗电量。在游戏和影视的等动态画面显示的应用场景下，显示面板可以应用于高刷新频率的显示模式，以满足显示的需求。当显示面板的刷新频率比较高时，像素驱动电路的一帧时间比较短。当像素驱动电路的一帧时间包括阈值补偿阶段时，使得阈值补偿阶段的时长比较短，容易导致像素驱动电路的阈值补偿时间不足，使得像素驱动电路的阈值补偿效果不佳，进而导致显示面板的亮度均一性比较差。
发明内容
本申请提供一种像素驱动电路和显示面板，以提高像素驱动电路的阈值补偿效果，提高显示面板的亮度均一性。
第一方面，本申请实施例提供了一种像素驱动电路，包括驱动模块、发光模块、第一初始化模块、数据写入模块、阈值补偿模块、存储模块、补偿延续模块、发光控制模块和第二初始化模块；
所述第一初始化模块与所述发光模块连接，所述第一初始化模块用于在初始化阶段对所述发光模块进行初始化；所述第二初始化模块与所述驱动模块的控制端连接，所述第二初始化模块用于在所述初始化阶段对所述驱动模块的控制端进行初始化；所述数据写入模块与所述驱动模块的第二端和所述补偿延续模块连接，所述阈值补偿模块连接于所述驱动模块的第一端和控制端之间，所述数据写入模块用于在数据写入阶段将数据电压通过所述阈值补偿模块写入所述驱动模块的控制端和所述补偿延续模块；所述存储模块连接于所述驱动模块的控制端和所述第一初始化模块之间，所述存储模块用于存储所述驱动模块的控制端电位；所述第一初始化模块还用于钳位所述存储模块的电位；所述补偿延续模块用于在补偿延续阶段对所述驱动模块的控制端进行阈值补偿；所述发光控制模块连接于第一电源信号输入端和所述发光模块之间，所述发光控制模块用于在发光阶段导通所述第一电源信号输入端和所述发光模块之间的通路；所述驱动模块用于在所述发光阶段向所述发光模块提供驱动电流，所述发光模块响应所述驱动电流发光。
可选地，所述补偿延续模块包括第一存储电容；
所述第一存储电容的第一极与第一电压输入端连接，所述第一存储电容的第二极与所述驱动模块的第二端连接；
优选地，所述第一电源信号输入端复用为所述第一电压输入端。
可选地，所述数据写入模块包括第一晶体管，所述阈值补偿模块包括第二晶体管，所述驱动模块包括驱动晶体管，所述第一初始化模块包括第三晶体管；
所述第一晶体管的第一极与数据信号输入端连接，所述第一晶体管的第二极与驱动晶体管的第二极和所述补偿延续模块的第二端连接，所述第一晶体管的栅极与第一扫描信号输入端连接，所述第二晶体管的第一极与所述驱动晶体管的第一极连接，所述第二晶体管的第二极与所述驱动晶体管的栅极和所述存储模块的第一端连接，所述第二晶体管的栅极与第二扫描信号输入端连接，所述第三晶体管的第一极与第一初 始化信号输入端连接，所述第三晶体管的第二极与所述存储模块的第二端和所述发光模块的阳极连接，所述第三晶体管的栅极与第三扫描信号输入端连接；所述第二扫描信号输入端提供的第二扫描信号的有效电平时长大于所述第一扫描信号输入端提供的第一扫描信号的有效电平时长。
可选地，所述发光控制模块包括第四晶体管和第五晶体管；
所述第四晶体管的第一极与所述第一电源信号输入端连接，所述第四晶体管的第二极与所述驱动模块的第一极连接，所述第四晶体管的栅极与第一发光控制信号输入端连接，所述第五晶体管的第一极与所述驱动模块的第二极连接，所述第五晶体管的第二极与所述发光模块的阳极连接，所述第五晶体管的栅极与第二发光控制信号输入端连接，所述发光模块的阴极与第二电源信号输入端连接；
优选地，所述第一发光控制信号输入端提供的第一发光控制信号在所述发光阶段控制所述第四晶体管导通，所述第二发光控制信号输入端提供的第二发光控制信号在所述初始化阶段和所述发光阶段控制所述第五晶体管导通。
可选地，像素驱动电路还包括第三初始化模块；
所述第三初始化模块与所述驱动模块的第二端连接，所述第三初始化模块用于在初始化阶段对所述驱动模块的第二端进行初始化。
可选地，所述第三初始化模块包括第六晶体管，所述第六晶体管的第一极与第二初始化信号输入端连接，所述第六晶体管的第二极与所述驱动模块的第二端连接，所述第六晶体管的栅极与第四扫描信号输入端连接。
可选地，像素驱动电路还包括第七晶体管；
所述第七晶体管的第一极与所述发光模块的阳极连接，所述第七晶体管的第二极与第三初始化信号输入端连接，所述第七晶体管的栅极与所述第四扫描信号输入端连接。
可选地，所述第二初始化信号输入端复用为所述第三初始化信号输入端。
可选地，所述第二初始化模块包括第八晶体管，所述第八晶体管的第一极与第四初始化信号输入端连接，所述第八晶体管的第二极与所述驱动模块的控制端连接，所述第八晶体管的栅极与第五扫描信号输入端连接。
第二方面，本申请实施例还提供了一种显示面板，包括第一方面所述的像素驱动电路。
本申请实施例的技术方案，通过数据写入模块在数据写入阶段将数据电压写入至驱动模块和补偿延续模块，然后在补偿延续阶段，补偿延续模块可以将数据电压继续写入驱动模块，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。
附图说明
图1为现有技术提供的一种像素驱动电路的结构示意图；
图2为本申请实施例提供的一种像素驱动电路的结构示意图；
图3为本申请实施例提供的另一种像素驱动电路的结构示意图；
图4为本申请实施例提供的另一种像素驱动电路的结构示意图；
图5为图4提供的像素驱动电路对应的一种时序图；
图6为本申请实施例提供的另一种像素驱动电路的结构示意图；
图7为图6提供的像素驱动电路对应的一种时序图；
图8为本申请实施例提供的另一种像素驱动电路的结构示意图；
图9为本申请实施例提供的另一种像素驱动电路的结构示意图；
图10为本申请实施例提供的另一种像素驱动电路的结构示意图；
图11为图10提供的像素驱动电路对应的一种时序图；
图12为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。
图1为现有技术提供的一种像素驱动电路的结构示意图。如图1所示，该像素驱动电路包括驱动晶体管Mdr、数据写入晶体管M1、阈值补偿晶体管M2、第一发光控制晶体管M3、第二发光控制晶体管M4、阳极初始化晶体管M5、存储电容Cst和发光器件D1。驱动晶体管Mdr、数据写入晶体管M1、阈值补偿晶体管M2、第一发光控制晶体管M3、第二发光控制晶体管M4、阳极初始化晶体管M5示例性地示出了均为N型晶体管，其具体连接关系如图1所示。在像素驱动电路工作的过程中，在初始化阶段，阈值补偿晶体管M2、第一发光控制晶体管M3和阳极初始化晶体管M5导通，第一电压输入端Vdd提供的第一电压通过阈值补偿晶体管M2写入驱动晶体管Mdr的栅极，实现驱动晶体管Mdr的栅极初始化，使得驱动晶体管Mdr导通。同时初始化电压通过阳极初始化晶体管M5写入发光器件D1的阳极，实现发光器件D1的阳极初始化。在数据写入阶段，驱动晶体管Mdr为导通状态，数据写入晶体管M1、阈值补偿晶体管M2和阳极初始化晶体管M5为导通状态，数据电压vdata通过数据写入晶体管M1、驱动晶体管Mdr和阈值补偿晶体管M2写入驱动晶体管Mdr的栅极，实现数据电压vdata的写入以及驱动晶体管Mdr的阈值补偿，存储电容Cst维持驱动晶体管Mdr的栅极电位。同时存储电容Cst的另一端维持初始化电压。在发光阶段，第一发光控制晶体管M3和第二发光控制晶体管M4导通，驱动晶体管Mdr根据第一电压输入端Vdd提供的第一电压和栅极电位形成驱动电流，并通过第二发光控制晶体管M4传输至发光器件D1的阳极，驱动发光器件D1发光。
在像素驱动电路的数据写入阶段，需要比较长的时间以完成驱动晶体管Mdr的阈值补偿。当像素驱动电路工作在高刷新频率时，像素驱动电路工作的各个阶段的时间比较短，使得像素驱动电路的数据写入阶段的时长无法满足驱动晶体管Mdr的阈值补偿所需的时间，导致像素驱动电路的阈值补偿效果比较差，进而导致显示面板的亮度均一性比较差。
针对上述技术问题，本申请实施例提供了一种像素驱动电路。图2为本申请实施例提供的一种像素驱动电路的结构示意图。如图2所示，该像素驱动电路包括驱动模块10、发光模块20、第一初始化模块30、数据写入模块40、阈值补偿模块50、存储模块60、补偿延续模块70、发光控制模块80和第二初始化模块90；第一初始化模块30与发光模块20连接，第一初始化模块30用于在初始化阶段对发光模块20进行初始化；第二初始化模块90与驱动模块10的控制端连接，第二初始化模块90用于在初始化阶段对驱动模块10的控制端进行初始化；数据写入模块40与驱动模块10的第二端和补偿延续模块70连接，阈值补偿模块50连接于驱动模块10的第一端和控制端之间，数据写入模块40用于在数据写入阶段将数据电压通过阈值补偿模块50写入驱动模块10的控制端和补偿延续模块70；存储模块60连接于驱动模块10的控制端和第一初始化模块30之间，存储模块60用于存储驱动模块10的控制端电位；第一初始化模块30还用于钳位存储模块60的电位；补偿延续模块70用于在补偿延续阶段对驱动模块10的控制端进行阈值补偿；发光控制模块80连接于第一电源信号输入端VDD和发光模块20之间，发光控制模块80用于在发光阶段导通第一电源信号输入端VDD和发光模块20之间的通路；驱动模块10用于在发光阶段向发光模块20提供驱动电流，发光模块20响应驱动电流发光。
具体地，第一初始化模块30与发光模块20连接，第一初始化模块30可以接收第一初始化信号，在第一初始化模块30为通路状态下，第一初始化模块30将第一初始化信号传输至发光模块20，对发光模块20进行初始化，避免了像素驱动电路在初始化阶段的“偷亮”问题以及驱动发光模块20发光时的残影现象。同时，第一初始化信号可以为固定电位的信号。第一初始化模块30与存储模块60的第二端连接，当第一初始化模块30输出第一初始化信号时，可以固定存储模块60的第二端电位，有利于存储模块60在像素驱动电路的后续工作过程中保证阈值补偿的准确性。第二初始化模块90与驱动模块10的控制端连接，第二初始化模块90可以接收一初始化信号，在第二初始化模块90为通路状态下，将该初始化信号传输至驱动模块10的控制端，对驱动模块10的控制端进行初始化，改善上一帧的数据电压对当前帧的影响，同时使得驱动模块10处于导通状态。数据写入模块40与驱动模块10的第二端和补偿延续模块70的第二端连接，补偿延续模块70的第一端接入固定电位，阈值补偿模块50连接于驱动模块10的第一端和控制端 之间，存储模块60的第一端与驱动模块10的控制端连接。在数据写入阶段，数据写入模块40和阈值补偿模块50处于通路状态，数据写入模块40将数据电压写入补偿延续模块70，补偿延续模块70存储数据电压。同时将数据电压通过驱动模块10和阈值补偿模块50写入驱动模块10的控制端，实现数据电压的写入和驱动模块10的阈值补偿。在补偿延续阶段，数据写入模块40处于断路状态，使得数据写入阶段满足像素驱动电路的工作频率要求，阈值补偿模块50维持通路状态，补偿延续模块70存储的数据电压通过驱动模块10和阈值补偿模块50继续写入驱动模块10的控制端，可以持续数据电压的写入和驱动模块10的阈值补偿，增加了驱动模块10的阈值补偿时间，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。同时存储模块60存储两端的电位差。发光控制模块80连接于第一电源信号输入端VDD和发光模块20之间，在发光阶段，发光控制模块80导通第一电源信号输入端VDD和发光模块20之间的通路，使得驱动模块10根据存储模块60两端的电位差形成的驱动电流传输至发光模块20，发光模块20响应驱动电流发光。
本实施例的技术方案，通过数据写入模块在数据写入阶段将数据电压写入至驱动模块和补偿延续模块，然后在补偿延续阶段，补偿延续模块可以将数据电压继续写入驱动模块，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。
图3为本申请实施例提供的另一种像素驱动电路的结构示意图。如图3所示，补偿延续模块70包括第一存储电容C1；第一存储电容C1的第一极与第一电压输入端V1连接，第一存储电容C1的第二极与驱动模块10的第二端连接。
具体地，第一电压输入端V1提供的第一电压V1可以为具有固定电位的电压信号。第一存储电容C1的第一极与第一电压输入端V1连接，使得第一存储电容C1的第一极电位固定。第一存储电容C1的第二极与驱动模块10的第二端连接，即与数据写入模块40连接。在数据写入阶段，数据写入模块40提供的数据电压写入第一存储电容C1的第二极，使得第一存储电容C1可以存储数据电压。然后在补偿延续阶段，数据写入模块40处于断路状态，使得数据写入阶段满足像素驱动电路的工作频率要求，同时阈值补偿模块50维持通路状态，第一存储电容C1存储的数据电压通过驱动模块10和阈值补偿模块50继续写入驱动模块10的控制端，可以持续数据电压的写入和驱动模块10的阈值补偿，增加了驱动模块10的阈值补偿时间，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。
需要说明的是，图3中示例性地示出了补偿延续模块70包括第一存储电容C1。在其他实施例中，补偿延续模块70还可以包括多个电容，以满足数据电压存储所需的电容值。或者，在其他实施例中，补偿延续模块70还可以包括其他具有存储功能的元件，此处不做限定。
可选地，继续参考图3，第一电源信号输入端VDD复用为所述第一电压输入端V1。
具体地，第一电源信号输入端VDD提供的第一电源信号为电位固定的信号。通过设置第一电源信号输入端VDD复用为第一电压输入端V1，在第一电源信号输入端VDD提供的第一电源信号可以固定第一存储电容C1的第一极电位的基础上，可以避免额外设置第一电压输入端V1，从而可以避免在显示面板上额外设置走线用于传输第一电压，有利于简化显示面板上的布线设计。
需要说明的是，在其他实施例中，还可以采用显示面板上其他具有固定电位的常规走线用于提供电压至第一电压输入端V1，例如，显示面板上还设置有初始化信号线，用于提供初始化信号。该初始化信号具有固定电位，此时初始化信号线可以用于为第一电压输入端V1提供固定电位，此处不做限定。
图4为本申请实施例提供的另一种像素驱动电路的结构示意图。如图4所示，数据写入模块40包括第一晶体管T1，阈值补偿模块50包括第二晶体管T2，驱动模块10包括驱动晶体管Tdr，第一初始化模块30包括第三晶体管T3；第一晶体管T1的第一极与数据信号输入端VDATA连接，第一晶体管T1的第二极与驱动晶体管Tdr的第二极和补偿延续模块70的第二端连接，第一晶体管T1的栅极与第一扫描信号输入端S1连接，第二晶体管T2的第一极与驱动晶体管Tdr的第一极连接，第二晶体管T2的第二极与驱动晶体管Tdr的栅极和存储模块60的第一端连接，第二晶体管T2的栅极与第二扫描信号输入端S2连接， 第三晶体管T3的第一极与第一初始化信号输入端VREF1连接，第三晶体管T3的第二极与存储模块60的第二端和发光模块20的阳极连接，第三晶体管T3的栅极与第三扫描信号输入端S3连接；第二扫描信号输入端S2提供的第二扫描信号的有效电平时长大于第一扫描信号输入端S1提供的第一扫描信号的有效电平时长。
具体地，图4中示例性地示出了第一晶体管T1、第二晶体管T2、第三晶体管T3和驱动晶体管Tdr均为N型晶体管。当第一扫描信号输入端S1提供的第一扫描信号为高电平时，第一晶体管T1导通。同理，当第二扫描信号输入端S2提供的第二扫描信号为高电平时，第二晶体管T2导通。第三扫描信号输入端S3提供的第三扫描信号为高电平时，第三晶体管T3导通。继续参考图4，补偿延续模块70的第一端与第一电压输入端V1连接，第一电压输入端V1提供的第一电压固定补偿延续模块70的第一端电位。存储模块60可以包括第二存储电容C2。存储模块60的第一端与驱动晶体管Tdr的栅极连接，用于存储驱动晶体管Tdr栅极的电位。发光模块20可以为发光器件E1。图5为图4提供的像素驱动电路对应的一种时序图。其中，s1为第一扫描信号的一种时序，s2为第二扫描信号的一种时序，s3为第三扫描信号的一种时序。以下结合图4和图5说明像素驱动电路的工作过程。
在初始化阶段t11，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为高电平，第一晶体管T1和第二晶体管T2关断，第三晶体管T3导通，第一初始化信号输入端VREF1提供的第一初始化信号通过第三晶体管T3传输至存储模块60的第二端和发光模块20的阳极，对发光模块20进行初始化，以及固定存储模块60的第二端电位。同时，第二初始化模块90对驱动模块10的控制端进行初始化。
在数据写入阶段t12，第一扫描信号为高电平，第二扫描信号为高电平，第三扫描信号为高电平，第一晶体管T1、第二晶体管T2和第三晶体管T3导通，数据信号输入端VDATA提供的数据电压通过第一晶体管T1写入补偿延续模块70的第二端，补偿延续模块70存储数据电压。同时第一晶体管T1将数据电压通过驱动晶体管Tdr和第二晶体管T2写入驱动晶体管Tdr的栅极，实现数据电压的写入和驱动晶体管Tdr的阈值补偿。存储模块60存储驱动晶体管Tdr的栅极电位。由于存储模块60的第二端电位为第一初始化信号，即存储模块60的第二端电位固定，可以保证存储模块60存储驱动晶体管Tdr的栅极电位准确性。
在补偿延续阶段t13，第一扫描信号为低电平，第二扫描信号为高电平，第三扫描信号为高电平，第一晶体管T1关断，第二晶体管T2和第三晶体管T3导通，第一晶体管T1停止提供数据电压，使得数据电压写入像素驱动电路的过程只在数据写入阶段完成，满足像素驱动电路工作在高刷新频率中数据写入阶段的时间需求。同时第二晶体管T2导通，使得补偿延续模块70存储的数据电压通过驱动晶体管Tdr和第二晶体管T2写入驱动晶体管Tdr的栅极，可以持续数据电压写入驱动晶体管Tdr的栅极，以及驱动晶体管Tdr的阈值补偿过程，增加了驱动晶体管Tdr的阈值补偿时间，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。
另外，继续参考图5，在补偿延续阶段t13之后，还包括过渡阶段。在过渡阶段，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为高电平，第一晶体管T1和第二晶体管T2关断，第三晶体管T3导通，数据写入阶段和补偿延续阶段完成。同时第三晶体管T3导通，保持发光模块20的阳极初始化，以及存储模块60的第二端电位为第一初始化信号，即存储模块60的第二端电位固定。
在发光阶段t14，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为低电平，第一晶体管T1、第二晶体管T2和第三晶体管T3关断，第二存储电容C2的第一端为浮动状态。当发光控制模块80导通第一电源信号输入端VDD和发光模块20之间的通路时，第二存储电容C2的第二端电位变化，并根据第二存储电容C2的耦合作用带动第二存储电容C2的第一端电位变化，使得第二存储电容C2两端的电位差保持不变。从而使得驱动晶体管Tdr根据第二存储电容C2两端的电位差形成的驱动电流传输至发光器件E1，发光器件E1响应驱动电流发光。
示例性地，继续参考图4，发光控制模块80可以包括第四晶体管T4和第五晶体管T5，第四晶体管T4的第一极与第一电源信号输入端VDD连接，第四晶体管T4的第二极与驱动晶体管Tdr的第一极连接，第五晶体管T5的第一极与驱动晶体管Tdr的第二极连接，第五晶体管T5的第二极与发光模块20的阳极连接，第四晶体管T4和第五晶体管T5的栅极与发光控制信号输入端EM连接，发光模块20的阴极与第 二电源信号输入端VSS连接。图4中示例性地示出了第四晶体管T4和第五晶体管T5为N型晶体管。参考图4和图5，在发光阶段t14，发光控制信号输入端EM提供的发光控制信号em为高电平，控制第四晶体管T4和第五晶体管T5导通，使得第二存储电容C2的第二端电位变化，并根据第二存储电容C2的耦合作用带动第二存储电容C2的第一端电位变化，维持第二存储电容C2两端的电位差保持不变。从而使得驱动晶体管Tdr根据第二存储电容C2的电位差形成驱动电流，并通过第五晶体管T5传输至发光器件E1的阳极，发光器件E1根据驱动电流发光。
需要说明的是，图4中示例性地示出了第一晶体管T1、第二晶体管T2、第三晶体管T3和驱动晶体管Tdr均为N型晶体管。在其他实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3和驱动晶体管Tdr还可以为P型晶体管，此时适应性调整第一扫描信号、第二扫描信号和第三扫描信号的时序，此处不做限定。
图6为本申请实施例提供的另一种像素驱动电路的结构示意图。如图6所示，发光控制模块包括第四晶体管T4和第五晶体管T5；第四晶体管T4的第一极与第一电源信号输入端VDD连接，第四晶体管T4的第二极与驱动模块10的第一极连接，第四晶体管T4的栅极与第一发光控制信号输入端EM1连接，第五晶体管T5的第一极与驱动模块10的第二极连接，第五晶体管T5的第二极与发光模块20的阳极连接，第五晶体管T5的栅极与第二发光控制信号输入端EM2连接，发光模块20的阴极与第二电源信号输入端VSS连接；第一发光控制信号输入端EM1提供的第一发光控制信号在发光阶段控制第四晶体管T4导通，第二发光控制信号输入端EM2提供的第二发光控制信号在初始化阶段和发光阶段控制第五晶体管T5导通。
具体地，图6中示例性地示出了第四晶体管T4和第五晶体管T5为N型晶体管。当第一发光控制信号输入端EM1提供的第一发光控制信号为高电平时，第四晶体管T4导通，当第二发光控制信号输入端EM2提供的第二发光控制信号为高电平时，第五晶体管T5导通。在初始化阶段，第三扫描信号为高电平，第二发光控制信号为高电平，第三晶体管T3和第五晶体管T5导通，第一初始化信号通过第三晶体管T3和第五晶体管T5传输至驱动模块10的第二端，可以对驱动模块10的第二端进行初始化，可以进一步地对驱动模块10进行复位，有利于进一步地改善像素驱动电路驱动发光模块20发光时的残影现象。在发光阶段，第一扫描信号、第二扫描信号和第三扫描信号为低电平，第一发光控制信号为高电平，第二发光控制信号为高电平，第一晶体管T1、第二晶体管T2和第三晶体管T3关断，第二存储电容C2的第一端为浮动状态。第四晶体管T4和第五晶体管T5均导通，第二存储电容C2的第二端电位变化，并根据第二存储电容C2的耦合作用带动第二存储电容C2的第一端电位变化，使得第二存储电容C2两端的电位差保持不变。驱动晶体管Tdr根据第二存储电容C2两端的电位差形成驱动电流，并通过第五晶体管T5传输至发光模块20的阳极，发光模块20根据驱动电流发光。其中，发光模块20可以为发光器件E1。
其中，显示面板上设置发光控制驱动电路和多行像素驱动电路，发光控制驱动电路包括多级级联的移位寄存器，每级移位寄存器依次输出一级发光控制信号，用于为一行像素驱动电路提供发光控制信号。当一行像素驱动电路对应的发光控制信号为第一发光控制信号时，该行像素驱动电路对应的第二发光控制信号可以为下级移位寄存器输出的发光控制信号，使得第二发光控制信号的有效电平时序滞后第一发光控制信号的有效电平时序，即第二发光控制信号的高电平滞后第一发光控制信号的高电平，从而在初始化阶段，第二发光控制信号为有效电平(即为高电平)，控制第五晶体管T5导通，实现对驱动模块10的第二端的初始化。
示例性地，图7为图6提供的像素驱动电路对应的一种时序图。其中，s1为第一扫描信号的一种时序，s2为第二扫描信号的一种时序，s3为第三扫描信号的一种时序，em1为第一发光控制信号输入端EM1提供的第一发光控制信号的一种时序，em2为第二发光控制信号输入端EM2提供的第二发光控制信号的一种时序。以下结合图6和图7说明像素驱动电路的工作过程。
在初始化阶段t21，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为高电平，第一发光控制信号为低电平，第二发光控制信号为高电平，第一晶体管T1、第二晶体管T2和第四晶体管T4关断，第三晶体管T3和第五晶体管T5导通，第一初始化信号输入端VREF1提供的第一初始化信号通过第三晶体管T3传输至存储模块60的第二端和发光模块20的阳极，对发光模块20的阳极进行初始化，以及固定存储模块60的第二端电位。第一初始化信号通过第三晶体管T3和第五晶体管T5传输至驱动模块 10的第二端，可以对驱动模块10的第二端进行初始化，可以进一步地对驱动模块10进行复位，有利于进一步地改善像素驱动电路驱动发光模块20发光时的残影现象。同时，第二初始化模块90对驱动模块10的控制端进行初始化。
在数据写入阶段t22，第一扫描信号为高电平，第二扫描信号为高电平，第三扫描信号为高电平，第一发光控制信号为低电平，第二发光控制信号为低电平，第一晶体管T1、第二晶体管T2和第三晶体管T3导通，第四晶体管T4和第五晶体管T5关断，数据信号输入端VDATA提供的数据电压通过第一晶体管T1写入补偿延续模块70的第二端，补偿延续模块70存储数据电压。同时第一晶体管T1将数据电压通过驱动晶体管Tdr和第二晶体管T2写入驱动晶体管Tdr的栅极，实现数据电压的写入和驱动晶体管Tdr的阈值补偿。存储模块60存储驱动晶体管Tdr的栅极电位。由于存储模块60的第二端电位为第一初始化信号，即存储模块60的第二端电位固定，可以保证存储模块60存储驱动晶体管Tdr的栅极电位准确性。
在补偿延续阶段t23，第一扫描信号为低电平，第二扫描信号为高电平，第三扫描信号为高电平，第一发光控制信号为低电平，第二发光控制信号为低电平，第一晶体管T1、第四晶体管T4和第五晶体管T5关断，第二晶体管T2和第三晶体管T3导通，第一晶体管T1停止提供数据电压，使得数据电压写入像素驱动电路的过程只在数据写入阶段完成，满足像素驱动电路工作在高刷新频率中数据写入阶段的时间需求。同时第二晶体管T2导通，使得补偿延续模块70存储的数据电压通过驱动晶体管Tdr和第二晶体管T2写入驱动晶体管Tdr的栅极，可以持续数据电压写入驱动晶体管Tdr的栅极，以及驱动晶体管Tdr的阈值补偿过程，增加了驱动晶体管Tdr的阈值补偿时间，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。
另外，继续参考图7，在补偿延续阶段t23之后，还包括过渡阶段。在过渡阶段，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为高电平，第一晶体管T1和第二晶体管T2关断，第三晶体管T3导通，数据写入阶段和补偿延续阶段完成。同时第三晶体管T3导通，保持发光模块20的阳极初始化，以及存储模块60的第二端电位为第一初始化信号，即存储模块60的第二端电位固定。
在发光阶段t24，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为低电平，第一发光控制信号为高电平，第二发光控制信号为高电平，第一晶体管T1、第二晶体管T2和第三晶体管T3关断，第二存储电容C2的第一端为浮动状态。第四晶体管T4和第五晶体管T5导通，第二存储电容C2的第二端电位变化，并根据第二存储电容C2的耦合作用带动第二存储电容C2的第一端电位变化，使得第二存储电容C2两端的电位差保持不变。驱动晶体管Tdr根据第二存储电容C2两端的电位差形成驱动电流，并通过第五晶体管T5传输至发光模块20的阳极，发光模块20根据驱动电流发光。其中，发光模块20可以为发光器件E1。
图8为本申请实施例提供的另一种像素驱动电路的结构示意图。如图8所示，像素驱动电路还包括第三初始化模块100；第三初始化模块100与驱动模块10的第二端连接，第三初始化模块100用于在初始化阶段对驱动模块10的第二端进行初始化。
具体地，图8中示例性地示出了发光控制模块80仅用于在发光阶段导通第一电源信号输入端VDD和发光模块20之间的通路，使得驱动晶体管Tdr根据存储模块60两端的电位差形成的驱动电流传输至发光模块20，发光模块20响应驱动电流发光。示例性地，发光控制模块80可以包括第四晶体管T4和第五晶体管T5，第四晶体管T4和第五晶体管T5的栅极与发光控制信号输入端EM连接。在此基础上，可以设置像素驱动电路包括第三初始化模块100，第三初始化模块100可以接收第二初始化信号，在初始化阶段，第三初始化模块100为通路状态，第三初始化模块100将第二初始化信号传输驱动模块10的第二端，对驱动模块10的第二端进行初始化，可以进一步地对驱动模块10进行复位，有利于进一步地改善像素驱动电路驱动发光模块20发光时的残影现象。由此可知，通过仅用一个发光控制信号输入端EM控制发光控制模块80的状态，可以简化发光控制模块80的控制信号。然后通过第三初始化模块100对驱动模块10的第二端进行初始化，保证了像素驱动电路驱动发光模块20发光的效果。
另外，一帧时间为显示面板刷新一次所需的时间，即显示面板上从第一行像素驱动电路扫描至最后一行像素驱动电路所需的时间。不同的刷新频率对应的一帧时间不同。例如，当刷新频率为10HZ，从显示 面板的第一行扫描至最后一行的时长为100ms，即一帧时间为100ms。当刷新频率为120HZ时，从显示面板的第一行扫描至最后一行的时长大约为8.3ms，即一帧时间为8.3ms。当像素驱动电路工作在基础刷新频率时，像素驱动电路工作的一帧时间可以包括一个子帧。当像素驱动电路工作在低刷新频率时，像素驱动电路工作的一帧时间可以包括多个子帧，多个子帧分为写入帧和至少一个保持帧，每个子帧对应基础刷新频率的一帧时长。例如，当像素驱动电路工作在10HZ时，如果基础刷新频率为120HZ，则像素驱动电路工作在10HZ时的一帧时间内可以包括12个子帧，第一个子帧作为写入帧，剩余的11个子帧作为保持帧。通过设置第三初始化模块100在写入帧和保持帧的初始化阶段对驱动模块10的第二端进行初始化，改善发光模块20发光时的残影现象，同时可以在写入帧和保持帧的初始化阶段调节驱动模块10的特性，从而减小驱动模块10的特性对发光模块20的发光亮度的影响，改善像素驱动电路在一帧时间内的亮度差异，进而改善了显示面板的闪屏现象。
继续参考图8，第三初始化模块100包括第六晶体管T6，第六晶体管T6的第一极与第二初始化信号输入端VREF2连接，第六晶体管T6的第二极与驱动模块10的第二端连接，第六晶体管T6的栅极与第四扫描信号输入端S4连接。
具体地，图8中示例性地示出了第六晶体管T6为N型晶体管。当第四扫描信号输入端S4提供的第四扫描信号为高电平时，第六晶体管T6导通，第二初始化信号输入端VREF2提供的第二初始化信号通过第六晶体管T6写入至驱动晶体管Tdr的第二极，对驱动晶体管Tdr的第二极进行初始化，可以进一步地对驱动晶体管Tdr进行复位，有利于进一步地改善像素驱动电路驱动发光模块20发光时的残影现象。
示例性地，在像素驱动电路工作在低刷新频率时，在第一个子帧的初始化阶段，第四扫描信号输入端S4提供的第四扫描信号为高电平，第六晶体管T6导通，第二初始化信号输入端VREF2提供的第二初始化信号通过第六晶体管T6传输至驱动晶体管Tdr的第二极，对驱动晶体管Tdr的第二极进行初始化。在写入帧的数据写入阶段、补偿延续阶段和发光阶段，第四扫描信号为低电平，第六晶体管T6关断。然后在保持帧的初始化阶段，第四扫描信号为高电平，第六晶体管T6导通，将第二初始化信号通过第六晶体管T6传输至驱动晶体管Tdr的第二极，对驱动晶体管Tdr的第二极进行初始化。
图9为本申请实施例提供的另一种像素驱动电路的结构示意图。如图9所示，像素驱动电路还包括第七晶体管T7；第七晶体管T7的第一极与发光模块20的阳极连接，第七晶体管T7的第二极与第三初始化信号输入端VREF3连接，第七晶体管T7的栅极与第四扫描信号输入端S4连接。
具体地，图9中示例性地示出了第七晶体管T7为N型晶体管。第七晶体管T7与第六晶体管T6的导通状态相同。在写入帧和保持帧的初始化阶段，第四扫描信号输入端S4提供的第四扫描信号为高电平，第七晶体管T7同时导通，第三初始化信号输入端VREF3提供的第三初始化信号通过第七晶体管T7传输至发光模块20的阳极，对发光模块20的阳极进行初始化，可以改善像素驱动电路驱动发光模块20发光时的残影现象。
可选地，第二初始化信号输入端VREF2复用为第三初始化信号输入端VREF3。
具体地，在发光阶段，发光控制模块80导通驱动模块10与发光模块20之间的通路，使得驱动模块10的第二端电位与发光模块20的阳极电位相同。在初始化阶段，通过第二初始化信号输入端VREF2复用为第三初始化信号输入端VREF3，使得发光模块20的阳极初始电位与驱动模块10的第二端初始电位相同，在保证像素驱动电路正常工作的基础上，可以减少初始化信号输入端的设置，进而可以减少显示面板上用于提供初始化信号的走线设置，有利于简化显示面板上的布线设计。
图10为本申请实施例提供的另一种像素驱动电路的结构示意图。如图10所示，
第二初始化模块90包括第八晶体管T8，第八晶体管T8的第一极与第四初始化信号输入端VREF4连接，第八晶体管T8的第二极与驱动模块10的控制端连接，第八晶体管T8的栅极与第五扫描信号输入端S5连接。
具体地，图10中示例性地示出了第八晶体管T8为N型晶体管。当第五扫描信号输入端S5提供的第五扫描信号为高电平时，第八晶体管T8导通，第四初始化信号输入端VREF4提供的第四初始化信号通过第八晶体管T8传输至驱动模块10的控制端，对驱动模块10的控制端进行初始化。
图10中示例性地示出了发光控制模块80包括第四晶体管T4和第五晶体管T5，且第四晶体管T4的 栅极和第五晶体管T5的栅极均与发光控制信号输入端EM连接。图11为图10提供的像素驱动电路对应的一种时序图。其中，s1为第一扫描信号的一种时序，s2为第二扫描信号的一种时序，s3为第三扫描信号的一种时序，s4为第四扫描信号的一种时序，s5为第五扫描信号的一种时序，em为发光控制信号输入端EM提供的发光控制信号的一种时序。以下结合图10和图11说明像素驱动电路工作在低刷新频率的工作过程。
在写入帧的初始化阶段t31，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为高电平，第四扫描信号为高电平，第五扫描信号为高电平，发光控制信号为低电平，第一晶体管T1、第二晶体管T2、第四晶体管T4和第五晶体管T5关断，第三晶体管T3、第六晶体管T6、第七晶体管T7和第八晶体管T8导通，第一初始化信号输入端VREF1提供的第一初始化信号通过第三晶体管T3传输至存储模块60的第二端和发光模块20的阳极，对发光模块20进行初始化，以及固定存储模块60的第二端电位。同时第三初始化信号输入端VREF3提供的第三初始化信号同样通过第七晶体管T7传输至发光模块20的阳极，对发光模块20的阳极进行初始化。第二初始化信号输入端VREF2提供的第二初始化信号通过第六晶体管T6传输至驱动晶体管Tdr的第二极，对驱动晶体管Tdr的第二极进行初始化。第四初始化信号输入端REF4提供的第四初始化信号通过第八晶体管T8传输至驱动晶体管Tdr的栅极，对驱动晶体管Tdr的栅极进行初始化。
在写入帧的数据写入阶段t32，第一扫描信号为高电平，第二扫描信号为高电平，第三扫描信号为高电平，第四扫描信号为低电平，第五扫描信号为低电平，发光控制信号为低电平，第一晶体管T1、第二晶体管T2和第三晶体管T3导通，第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8关断，数据信号输入端VDATA提供的数据电压通过第一晶体管T1写入补偿延续模块70的第二端，补偿延续模块70存储数据电压。同时第一晶体管T1将数据电压通过驱动晶体管Tdr和第二晶体管T2写入驱动晶体管Tdr的栅极，实现数据电压的写入和驱动晶体管Tdr的阈值补偿。存储模块60存储驱动晶体管Tdr的栅极电位。由于存储模块60的第二端电位为第一初始化信号，即存储模块60的第二端电位固定，可以保证存储模块60存储驱动晶体管Tdr的栅极电位准确性。
在写入帧的补偿延续阶段t33，第一扫描信号为低电平，第二扫描信号为高电平，第三扫描信号为高电平，第四扫描信号为低电平，第五扫描信号为低电平，发光控制信号为低电平，第一晶体管T1、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8关断，第二晶体管T2和第三晶体管T3导通，第一晶体管T1停止提供数据电压，使得数据电压写入像素驱动电路的过程只在数据写入阶段完成，满足像素驱动电路工作在高刷新频率中数据写入阶段的时间需求。同时第二晶体管T2导通，使得补偿延续模块70存储的数据电压通过驱动晶体管Tdr和第二晶体管T2写入驱动晶体管Tdr的栅极，可以持续数据电压写入驱动晶体管Tdr的栅极，以及驱动晶体管Tdr的阈值补偿过程，增加了驱动晶体管Tdr的阈值补偿时间，从而可以在像素驱动电路工作在高刷新频率时，在不影响数据写入阶段时长的基础上，增加了像素驱动电路的阈值补偿时间，从而可以改善像素驱动电路的阈值补偿效果，提高了显示面板的亮度均一性。
继续参考图11，在写入帧的补偿延续阶段t33之后，还包括过渡阶段。在过渡阶段，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为高电平，第一晶体管T1和第二晶体管T2关断，第三晶体管T3导通，数据写入阶段和补偿延续阶段完成。同时第三晶体管T3导通，保持发光模块20的阳极初始化，以及存储模块60的第二端电位为第一初始化信号，即存储模块60的第二端电位固定。
在写入帧的发光阶段t34，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为低电平，第四扫描信号为低电平，第五扫描信号为低电平，发光控制信号为高电平，第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6、第七晶体管T7和第八晶体管T8关断，第二存储电容C2的第一端为浮动状态。第四晶体管T4和第五晶体管T5导通，第二存储电容C2的第二端电位变化，并根据第二存储电容C2的耦合作用带动第二存储电容C2的第一端电位变化，使得第二存储电容C2两端的电位差保持不变。驱动晶体管Tdr根据第二存储电容C2两端的电位差形成驱动电流，并通过第五晶体管T5传输至发光模块20的阳极，发光模块20根据驱动电流发光。其中，发光模块20可以为发光器件E1。
在保持帧的初始化阶段t35，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为低电 平，第四扫描信号为高电平，第五扫描信号为低电平，发光控制信号为低电平，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第八晶体管T8关断，第六晶体管T6和第七晶体管T7导通，第二初始化信号输入端VREF2提供的第二初始化信号通过第六晶体管T6传输至驱动晶体管Tdr的第二极，对驱动晶体管Tdr的第二极进行初始化。同时第三初始化信号输入端VREF3提供的第三初始化信号通过第七晶体管T7传输至发光模块20的阳极，对发光模块20的阳极进行初始化。
在保持帧的过渡阶段t36，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为低电平，第四扫描信号为低电平，第五扫描信号为低电平，发光控制信号为低电平，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和第八晶体管T8均关断，维持像素驱动电路的当前状态。
在保持帧的发光阶段t37，第一扫描信号为低电平，第二扫描信号为低电平，第三扫描信号为低电平，第四扫描信号为低电平，第五扫描信号为低电平，发光控制信号为高电平，第一晶体管T1、第二晶体管T2、第三晶体管T3、第六晶体管T6、第七晶体管T7和第八晶体管T8关断，第二存储电容C2的第一端为浮动状态。第四晶体管T4和第五晶体管T5导通，第二存储电容C2的第二端电位变化，并根据第二存储电容C2的耦合作用带动第二存储电容C2的第一端电位变化，使得第二存储电容C2两端的电位差保持不变。驱动晶体管Tdr根据第二存储电容C2两端的电位差形成驱动电流，并通过第五晶体管T5传输至发光模块20的阳极，发光模块20根据驱动电流发光。
本申请实施例还提供一种显示面板。图12为本申请实施例提供的一种显示面板的结构示意图。如图12所示，该显示面板包括本申请任意实施例提供的像素驱动电路101。
具体地，显示面板包括显示区AA，显示区AA设置有多个像素单元P，每个像素单元P包括本申请任意实施例提供的像素驱动电路101和发光器件E1，像素驱动电路101为发光器件E1提供驱动电流，驱动发光器件E1发光。由于显示面板包括本申请任意实施例提供的像素驱动电路101，因此具有像素驱动电路101相同的有益效果，此处不再赘述。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。

Claims (10)

  1. 一种像素驱动电路，包括驱动模块、发光模块、第一初始化模块、数据写入模块、阈值补偿模块、存储模块、补偿延续模块、发光控制模块和第二初始化模块；
    所述第一初始化模块与所述发光模块连接，所述第一初始化模块用于在初始化阶段对所述发光模块进行初始化；所述第二初始化模块与所述驱动模块的控制端连接，所述第二初始化模块用于在所述初始化阶段对所述驱动模块的控制端进行初始化；所述数据写入模块与所述驱动模块的第二端和所述补偿延续模块连接，所述阈值补偿模块连接于所述驱动模块的第一端和控制端之间，所述数据写入模块用于在数据写入阶段将数据电压通过所述阈值补偿模块写入所述驱动模块的控制端和所述补偿延续模块；所述存储模块连接于所述驱动模块的控制端和所述第一初始化模块之间，所述存储模块用于存储所述驱动模块的控制端电位；所述第一初始化模块还用于钳位所述存储模块的电位；所述补偿延续模块用于在补偿延续阶段对所述驱动模块的控制端进行阈值补偿；所述发光控制模块连接于第一电源信号输入端和所述发光模块之间，所述发光控制模块用于在发光阶段导通所述第一电源信号输入端和所述发光模块之间的通路；所述驱动模块用于在所述发光阶段向所述发光模块提供驱动电流，所述发光模块响应所述驱动电流发光。
  2. 根据权利要求1所述的像素驱动电路，其中，所述补偿延续模块包括第一存储电容；
    所述第一存储电容的第一极与第一电压输入端连接，所述第一存储电容的第二极与所述驱动模块的第二端连接；
    优选地，所述第一电源信号输入端复用为所述第一电压输入端。
  3. 根据权利要求1所述的像素驱动电路，其中，所述数据写入模块包括第一晶体管，所述阈值补偿模块包括第二晶体管，所述驱动模块包括驱动晶体管，所述第一初始化模块包括第三晶体管；
    所述第一晶体管的第一极与数据信号输入端连接，所述第一晶体管的第二极与驱动晶体管的第二极和所述补偿延续模块的第二端连接，所述第一晶体管的栅极与第一扫描信号输入端连接，所述第二晶体管的第一极与所述驱动晶体管的第一极连接，所述第二晶体管的第二极与所述驱动晶体管的栅极和所述存储模块的第一端连接，所述第二晶体管的栅极与第二扫描信号输入端连接，所述第三晶体管的第一极与第一初始化信号输入端连接，所述第三晶体管的第二极与所述存储模块的第二端和所述发光模块的阳极连接，所述第三晶体管的栅极与第三扫描信号输入端连接；所述第二扫描信号输入端提供的第二扫描信号的有效电平时长大于所述第一扫描信号输入端提供的第一扫描信号的有效电平时长。
  4. 根据权利要求1-3任一项所述的像素驱动电路，其中，所述发光控制模块包括第四晶体管和第五晶体管；
    所述第四晶体管的第一极与所述第一电源信号输入端连接，所述第四晶体管的第二极与所述驱动模块的第一极连接，所述第四晶体管的栅极与第一发光控制信号输入端连接，所述第五晶体管的第一极与所述驱动模块的第二极连接，所述第五晶体管的第二极与所述发光模块的阳极连接，所述第五晶体管的栅极与第二发光控制信号输入端连接，所述发光模块的阴极与第二电源信号输入端连接；
    优选地，所述第一发光控制信号输入端提供的第一发光控制信号在所述发光阶段控制所述第四晶体管导通，所述第二发光控制信号输入端提供的第二发光控制信号在所述初始化阶段和所述发光阶段控制所述第五晶体管导通。
  5. 根据权利要求1-3任一项所述的像素驱动电路，其中，还包括第三初始化模块；
    所述第三初始化模块与所述驱动模块的第二端连接，所述第三初始化模块用于在初始化阶段对所述驱动模块的第二端进行初始化。
  6. 根据权利要求5所述的像素驱动电路，其特征在于，所述第三初始化模块包括第六晶体管，所述第六晶体管的第一极与第二初始化信号输入端连接，所述第六晶体管的第二极与所述驱动模块的第二端连接，所述第六晶体管的栅极与第四扫描信号输入端连接。
  7. 根据权利要求6所述的像素驱动电路，其中，还包括第七晶体管；
    所述第七晶体管的第一极与所述发光模块的阳极连接，所述第七晶体管的第二极与第三初始化信号输入端连接，所述第七晶体管的栅极与所述第四扫描信号输入端连接。
  8. 根据权利要求7所述的像素驱动电路，其中，所述第二初始化信号输入端复用为所述第三初始化信号输入端。
  9. 根据权利要求1所述的像素驱动电路，其中，所述第二初始化模块包括第八晶体管，所述第八晶体管的第一极与第四初始化信号输入端连接，所述第八晶体管的第二极与所述驱动模块的控制端连接，所述第八晶体管的栅极与第五扫描信号输入端连接。
  10. 一种显示面板，包括权利要求1-9任一项所述的像素驱动电路。
PCT/CN2022/128122 2022-08-15 2022-10-28 像素驱动电路和显示面板 WO2024036751A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210977072.6A CN115223504A (zh) 2022-08-15 2022-08-15 像素驱动电路和显示面板
CN202210977072.6 2022-08-15

Publications (1)

Publication Number Publication Date
WO2024036751A1 true WO2024036751A1 (zh) 2024-02-22

Family

ID=83614895

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/128122 WO2024036751A1 (zh) 2022-08-15 2022-10-28 像素驱动电路和显示面板

Country Status (2)

Country Link
CN (1) CN115223504A (zh)
WO (1) WO2024036751A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115223504A (zh) * 2022-08-15 2022-10-21 昆山国显光电有限公司 像素驱动电路和显示面板

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102467876A (zh) * 2010-10-28 2012-05-23 三星移动显示器株式会社 像素和使用该像素的有机发光显示器
US20160133191A1 (en) * 2014-11-12 2016-05-12 Samsung Display Co., Ltd. Display apparatus and method of driving the same
CN108389549A (zh) * 2018-01-30 2018-08-10 上海天马微电子有限公司 像素电路及其驱动方法、显示面板及其驱动方法
CN111508422A (zh) * 2020-04-27 2020-08-07 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
CN111883043A (zh) * 2020-07-30 2020-11-03 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN111986612A (zh) * 2020-08-31 2020-11-24 云谷（固安）科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN112102782A (zh) * 2020-09-25 2020-12-18 云谷（固安）科技有限公司 像素驱动电路、显示面板和显示装置
US11114030B1 (en) * 2020-07-10 2021-09-07 Sharp Kabushiki Kaisha Fast data programming TFT pixel threshold voltage compensation circuit with improved compensation accuracy
CN113870781A (zh) * 2021-09-18 2021-12-31 云谷（固安）科技有限公司 像素电路及显示面板
WO2022016706A1 (zh) * 2020-07-21 2022-01-27 京东方科技集团股份有限公司 像素电路、其驱动方法及显示装置
CN114023259A (zh) * 2021-12-01 2022-02-08 合肥维信诺科技有限公司 一种像素驱动电路及其驱动方法
CN114023263A (zh) * 2021-11-25 2022-02-08 云谷（固安）科技有限公司 像素电路、像素电路的驱动方法和显示面板
CN114708832A (zh) * 2021-11-25 2022-07-05 云谷（固安）科技有限公司 像素电路及其驱动方法和显示面板
CN115223504A (zh) * 2022-08-15 2022-10-21 昆山国显光电有限公司 像素驱动电路和显示面板

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102467876A (zh) * 2010-10-28 2012-05-23 三星移动显示器株式会社 像素和使用该像素的有机发光显示器
US20160133191A1 (en) * 2014-11-12 2016-05-12 Samsung Display Co., Ltd. Display apparatus and method of driving the same
CN108389549A (zh) * 2018-01-30 2018-08-10 上海天马微电子有限公司 像素电路及其驱动方法、显示面板及其驱动方法
CN111508422A (zh) * 2020-04-27 2020-08-07 昆山国显光电有限公司 像素电路及其驱动方法、显示面板
US11114030B1 (en) * 2020-07-10 2021-09-07 Sharp Kabushiki Kaisha Fast data programming TFT pixel threshold voltage compensation circuit with improved compensation accuracy
WO2022016706A1 (zh) * 2020-07-21 2022-01-27 京东方科技集团股份有限公司 像素电路、其驱动方法及显示装置
CN111883043A (zh) * 2020-07-30 2020-11-03 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN111986612A (zh) * 2020-08-31 2020-11-24 云谷（固安）科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN112102782A (zh) * 2020-09-25 2020-12-18 云谷（固安）科技有限公司 像素驱动电路、显示面板和显示装置
CN113870781A (zh) * 2021-09-18 2021-12-31 云谷（固安）科技有限公司 像素电路及显示面板
CN114023263A (zh) * 2021-11-25 2022-02-08 云谷（固安）科技有限公司 像素电路、像素电路的驱动方法和显示面板
CN114708832A (zh) * 2021-11-25 2022-07-05 云谷（固安）科技有限公司 像素电路及其驱动方法和显示面板
CN114023259A (zh) * 2021-12-01 2022-02-08 合肥维信诺科技有限公司 一种像素驱动电路及其驱动方法
CN115223504A (zh) * 2022-08-15 2022-10-21 昆山国显光电有限公司 像素驱动电路和显示面板

Also Published As

Publication number Publication date
CN115223504A (zh) 2022-10-21

Similar Documents

Publication Publication Date Title
WO2023005621A1 (zh) 像素电路及其驱动方法、显示面板
WO2020186811A1 (zh) 像素电路及驱动方法、显示面板及驱动方法、显示装置
CN111508422B (zh) 像素电路及其驱动方法、显示面板
CN111354307B (zh) 一种像素驱动电路及驱动方法、有机发光显示面板
WO2021179383A1 (zh) 一种像素电路和显示面板
WO2021179382A1 (zh) 一种像素电路及显示面板
CN112382235A (zh) 一种像素电路及其控制方法、显示面板
WO2021057067A1 (zh) 扫描电路、显示面板和显示装置
US20160005359A1 (en) Scan driver and organic light emitting display device using the same
WO2023016138A1 (zh) 像素驱动电路及显示面板
CN114170959A (zh) 像素驱动电路及显示面板
US11322094B2 (en) Display panel and display device
CN109064973B (zh) 显示方法和显示装置
CN111354308A (zh) 一种像素驱动电路、有机发光显示面板及显示装置
CN112908245B (zh) 像素电路及其驱动方法、显示面板
US11538379B2 (en) Foldable display panel and driving method thereof, display device and electronic apparatus
CN112289269A (zh) 一种像素电路及其控制方法和显示面板
US11205389B2 (en) Scan driver and display device having same
CN114333700A (zh) 像素电路以及显示面板
WO2024036751A1 (zh) 像素驱动电路和显示面板
CN113270067B (zh) 像素电路及显示面板
CN111489703B (zh) 一种像素电路及其驱动方法和显示面板
CN113870780A (zh) 像素电路及显示面板
CN110992886A (zh) 一种像素驱动电路以及像素驱动电路的驱动方法
CN116363998A (zh) 一种显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22955523

Country of ref document: EP

Kind code of ref document: A1