WO2021168923A1 - 一种 goa 电路及 tft 基板 - Google Patents

一种 goa 电路及 tft 基板 Download PDF

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Publication number
WO2021168923A1
WO2021168923A1 PCT/CN2020/079465 CN2020079465W WO2021168923A1 WO 2021168923 A1 WO2021168923 A1 WO 2021168923A1 CN 2020079465 W CN2020079465 W CN 2020079465W WO 2021168923 A1 WO2021168923 A1 WO 2021168923A1
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WO
WIPO (PCT)
Prior art keywords
pull
switch tube
module
signal
switch
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PCT/CN2020/079465
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English (en)
French (fr)
Inventor
郑旭煌
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/652,433 priority Critical patent/US10977978B1/en
Publication of WO2021168923A1 publication Critical patent/WO2021168923A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the technical field of display panels, in particular to a GOA circuit and a TFT substrate.
  • Gate Driver On Array is to use the existing thin film transistor liquid crystal display array manufacturing process to fabricate the gate row scanning driving signal circuit on the array substrate to realize the driving mode of the gate progressive scan.
  • a capacitor is mounted between the pull-up control signal output by the pull-up control module and the scan signal output by the pull-up module.
  • the pull-up control is raised through the capacitor bootstrap The potential of the signal so that the high level output by the pull-up module during the scanning signal output period is sufficiently high.
  • only using capacitors for bootstrapping cannot flexibly control the bootstrapping conditions, resulting in a large capacitive load at the output terminal and reducing the load capacity of the GOA circuit output.
  • the embodiment of the present invention provides a GOA circuit and a TFT substrate to solve the problem of large capacitive load at the output end of the existing GOA circuit and poor load capacity.
  • the embodiment of the present invention provides a GOA circuit, which includes a plurality of cascaded GOA units, and each level of GOA unit includes:
  • the pull-up control module is used to output a high-potential pull-up control signal according to the first clock signal and the previous scan signal when scanning starts;
  • the pull-up module is configured to output a high-level scan signal of the current level according to the second clock signal and the pull-up control signal;
  • a pull-down module which is used to pull the pull-up control signal and the scan signal of the current level to a low level when the scan is completed;
  • a pull-down maintenance module configured to maintain the pull-up control signal and the current level scan signal at a low level
  • the switch module is used for turning off after a preset time delay when the pull-up module outputs a high-level scanning signal of the current level;
  • the bootstrap module is used to maintain the pull-up control signal at a high level according to the current-level scan signal of the high level within the preset time period of the switch module delay, and cut off the control signal when the switch module is disconnected.
  • the connection of the scan signal of the current level is used to maintain the pull-up control signal at a high level according to the current-level scan signal of the high level within the preset time period of the switch module delay, and cut off the control signal when the switch module is disconnected. The connection of the scan signal of the current level.
  • the switch module is specifically configured to be turned on when the pull-up control signal is at a low potential, continue to conduct when the pull-up control signal is converted from a low potential to a high potential, and turn on when the pull-up module When outputting a high-level scanning signal of this level, it is switched from on to off after a preset time delay.
  • the switch module includes a capacitor and a first switch tube
  • the switch module is specifically configured to charge the capacitor when the pull-up control signal is at a low potential and the first switch tube is turned on.
  • the first switch tube continues to be turned on through the capacitor, and when the pull-up module outputs a high-level scanning signal of the current level, it is switched from on to off after a preset time delay.
  • one end of the capacitor is connected to the pull-down maintenance module, the other end of the capacitor is connected to the gate of the first switch tube, the source of the first switch tube is connected to the bootstrap module, the The drain of the first switch tube is connected to the scan signal of this level.
  • the bootstrap module includes a bootstrap capacitor
  • One end of the bootstrap capacitor is connected to the pull-up control signal, and the other end of the bootstrap capacitor is connected to the source of the first switch tube.
  • the pull-up control module includes a second switch tube
  • the gate of the second switch tube is connected to the first clock signal, the source of the second switch tube is connected to the previous scan signal, and the drain of the second switch tube outputs a pull-up control signal.
  • the pull-up module includes a third switch tube
  • the gate of the third switch tube is connected to the pull-up control signal, the source of the third switch tube is connected to the second clock signal, and the drain of the third switch tube outputs the current stage Scan signal.
  • the pull-down module includes a fourth switch tube
  • the gate of the fourth switch tube is connected to the pull-down maintenance module, the source of the fourth switch tube is connected to the scan signal of the current level, and the drain of the fourth switch tube is connected to a low-level signal.
  • the pull-down maintenance module includes a fifth switch tube, a sixth switch tube, and a seventh switch tube;
  • the gate and drain of the fifth switch tube are connected to a high-potential signal, and the drain of the fifth switch tube is connected to the capacitor, the gate of the fourth switch tube, and the gate of the sixth switch tube.
  • the gate and the source of the seventh switch, the source of the sixth switch is connected to the pull-up control signal, the drain of the sixth switch is connected to a low potential signal, and the seventh
  • the gate of the switch tube is connected to the pull-up control signal, and the drain of the seventh switch tube is connected to a low potential signal.
  • An embodiment of the present invention also provides a TFT substrate, including the above-mentioned GOA circuit, the GOA circuit includes a plurality of cascaded GOA units, and each level of GOA unit includes:
  • the pull-up control module is used to output a high-potential pull-up control signal according to the first clock signal and the previous scan signal when scanning starts;
  • the pull-up module is configured to output a high-level scan signal of the current level according to the second clock signal and the pull-up control signal;
  • a pull-down module which is used to pull the pull-up control signal and the scan signal of the current level to a low level when the scan is completed;
  • a pull-down maintenance module configured to maintain the pull-up control signal and the current level scan signal at a low level
  • the switch module is used for turning off after a preset time delay when the pull-up module outputs a high-level scanning signal of the current level;
  • the bootstrap module is used to maintain the pull-up control signal at a high level according to the current-level scan signal of the high level within the preset time period of the switch module delay, and cut off the control signal when the switch module is disconnected.
  • the connection of the scan signal of the current level is used to maintain the pull-up control signal at a high level according to the current-level scan signal of the high level within the preset time period of the switch module delay, and cut off the control signal when the switch module is disconnected. The connection of the scan signal of the current level.
  • the switch module is specifically configured to be turned on when the pull-up control signal is at a low potential, continue to conduct when the pull-up control signal is converted from a low potential to a high potential, and turn on when the pull-up module When outputting a high-level scanning signal of this level, it is switched from on to off after a preset time delay.
  • the switch module includes a capacitor and a first switch tube
  • the switch module is specifically configured to charge the capacitor when the pull-up control signal is at a low potential and the first switch tube is turned on.
  • the first switch tube continues to be turned on through the capacitor, and when the pull-up module outputs a high-level scanning signal of the current level, it is switched from on to off after a preset time delay.
  • one end of the capacitor is connected to the pull-down maintenance module, the other end of the capacitor is connected to the gate of the first switch tube, the source of the first switch tube is connected to the bootstrap module, the The drain of the first switch tube is connected to the scan signal of this level.
  • the bootstrap module includes a bootstrap capacitor
  • One end of the bootstrap capacitor is connected to the pull-up control signal, and the other end of the bootstrap capacitor is connected to the source of the first switch tube.
  • the pull-up control module includes a second switch tube
  • the gate of the second switch tube is connected to the first clock signal, the source of the second switch tube is connected to the previous scan signal, and the drain of the second switch tube outputs a pull-up control signal.
  • the pull-up module includes a third switch tube
  • the gate of the third switch tube is connected to the pull-up control signal, the source of the third switch tube is connected to the second clock signal, and the drain of the third switch tube outputs the current stage Scan signal.
  • the pull-down module includes a fourth switch tube
  • the gate of the fourth switch tube is connected to the pull-down maintenance module, the source of the fourth switch tube is connected to the scan signal of the current level, and the drain of the fourth switch tube is connected to a low-level signal.
  • the pull-down maintenance module includes a fifth switch tube, a sixth switch tube, and a seventh switch tube;
  • the gate and drain of the fifth switch tube are connected to a high-potential signal, and the drain of the fifth switch tube is connected to the capacitor, the gate of the fourth switch tube, and the gate of the sixth switch tube.
  • the gate and the source of the seventh switch, the source of the sixth switch is connected to the pull-up control signal, the drain of the sixth switch is connected to a low potential signal, and the seventh
  • the gate of the switch tube is connected to the pull-up control signal, and the drain of the seventh switch tube is connected to a low potential signal.
  • a switch module is provided between the bootstrap module and the output terminal of the GOA circuit.
  • the pull-up module outputs a high-level scan signal of the current level
  • the switch module is turned on for a preset time and then turned off, so that The bootstrap module maintains the pull-up control signal at a high level for the preset time when the switch module is turned on, and cuts off the connection with the output terminal of the GOA circuit when the switch module is turned off, thereby reducing the load on the output terminal and increasing the load on the GOA circuit output ability.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present invention
  • FIG. 2 is a timing diagram of signals in a GOA circuit provided by an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the present invention.
  • the GOA circuit provided by the embodiment of the present invention includes a plurality of cascaded GOA units, and each level of GOA unit includes a pull-up control module 11, a pull-up module 12, a pull-down module 13, a pull-down maintenance module 14, a switch module 15, and a bootstrap module 16. .
  • the pull-up control module 11 is configured to output a high-level pull-up control signal Q according to the first clock signal CLK and the previous scan signal OUT (N-1) when scanning starts.
  • the pull-up control module 11 inputs the first clock signal CLK with a high potential and the previous scan signal OUT (N-1) with a high potential, and the pull-up control module 11 is turned on and outputs The high-level pull-up control signal Q; when the scan is completed, the pull-up control module 11 inputs the high-level first clock signal CLK and the low-level previous scan signal OUT (N-1), and the pull-up control module 11 conducts Turn on and output a low-level pull-up control signal Q.
  • the pull-up control signal Q can be used to control the opening and closing of the pull-up module 22.
  • the pull-up control module 11 includes a second switch tube T2;
  • the gate of the second switching tube T2 is connected to the first clock signal CLK, the source of the second switching tube T2 is connected to the previous scan signal OUT(N-1), and the second switching tube T2 The drain outputs the pull-up control signal Q.
  • the gate of the second switch tube T2 inputs the first clock signal CLK with a high potential, and the source of the second switch tube T2 inputs the previous scan signal OUT (N-1 ), the second switching tube T2 is turned on, and the drain of the second switching tube T2 outputs a high-potential pull-up control signal Q. Then, the gate of the second switching tube T2 inputs the first clock signal CLK with a low potential, the source of the second switching tube T2 inputs the previous scan signal OUT (N-1) with a low potential, and the second switching tube T2 is turned off. On, the pull-up control signal Q is in a floating state.
  • the gate of the second switch tube T2 inputs the first clock signal CLK with a high potential
  • the source of the second switch tube T2 inputs the previous scan signal OUT (N-1) with a low potential
  • the second switch The tube T2 is turned on, and the drain of the second switch tube T2 outputs a low-potential pull-up control signal Q.
  • the second switch tube T2 may be a thin film transistor.
  • the pull-up module 12 is connected to the pull-up control module 11, and is configured to output a high-level scan signal OUT(N) of the current level according to the second clock signal CLKB and the pull-up control signal Q.
  • the pull-up control signal Q output by the pull-up control module 11 is input to the pull-up module 12, while the pull-up module 12 inputs the second clock signal CLKB, so that the pull-up module 12 will input the first clock signal Q according to the pull-up control signal Q.
  • the second clock signal CLKB is output as the scan signal OUT(N) of the current stage.
  • the pull-up module 12 when the pull-up module 12 inputs a high-level pull-up control signal Q and a high-level second clock signal CLKB, the pull-up module 12 outputs a high-level scan signal OUT(N); When a high-level pull-up control signal Q and a low-level second clock signal CLKB are input, the pull-up module 12 outputs a low-level scan signal OUT(N) of the current level.
  • the second clock signal CLKB is opposite to the first clock signal CLK.
  • the pull-up module includes a third switch tube T3;
  • the gate of the third switch tube T3 is connected to the pull-up control signal Q, the source of the third switch tube T3 is connected to the second clock signal CLKB, and the drain of the third switch tube T3 Output the scan signal OUT(N) of the current level.
  • the gate of the third switch tube T3 inputs a high-level pull-up control signal Q
  • the source of the third switch tube T3 inputs a low-level second clock signal CLKB
  • the third switch tube T3 is turned on.
  • the drain of the three-switch tube T3 outputs the low-level scan signal OUT(N) of the current level.
  • the gate of the third switch tube T3 inputs the high-level pull-up control signal Q
  • the source of the third switch tube T3 inputs the high-level second clock signal CLKB
  • the third switch tube T3 is turned on
  • the third switch tube T3 is turned on.
  • the drain outputs the high-level scan signal OUT (N) of the current stage.
  • the third switch tube T3 may be a thin film transistor.
  • the port through which the third switch tube T3 outputs the scan signal OUT(N) of the current stage is the output terminal of the GOA circuit.
  • the pull-down module 13 is connected to the pull-up module 12 and the pull-down maintenance module 14 respectively, and is used to pull the pull-up control signal Q and the current-level scan signal OUT(N) to a low level when the scan is completed.
  • the pull-down module 13 is turned off; when the scan is completed, the pull-up control signal Q is pulled down to a low level, and the pull-down module 13 is turned on to pull the scan signal OUT(N) of the current level to a low level. .
  • the pull-down module 13 includes a fourth switch tube T4;
  • the gate of the fourth switching tube T4 is connected to the pull-down maintenance module 15, the source of the fourth switching tube T4 is connected to the scan signal OUT(N) of the current stage, and the drain of the fourth switching tube T4 is The pole is connected to the low potential signal VSS.
  • the pull-up control signal Q is at a high potential, and the gate of the fourth switch tube T4 inputs the control signal QB that is opposite to the pull-up control signal Q, that is, the gate of the fourth switch tube T4
  • the low-level control signal QB is input, and the fourth switch tube T4 is in the off state.
  • the pull-up control signal Q is pulled down to a low level, the gate of the fourth switch tube T4 inputs a high level control signal QB, and the source of the fourth switch tube T4 inputs the scan signal OUT(N) of the current stage.
  • the drain of the four switch tube T4 is connected to the low potential signal VSS, and the fourth switch tube T4 is turned on to pull the scan signal OUT(N) of the current stage to a low potential.
  • the fourth switch tube T4 may be a thin film transistor.
  • the pull-down maintenance module 14 is respectively connected to the pull-down module 13 and the pull-up control module 11, and is used to maintain the pull-up control signal Q and the current-level scan signal OUT(N) at a low level.
  • the pull-up control signal Q is at a high level
  • the pull-down maintaining module 14 outputs a low-level control signal QB to the pull-down module 13, so that the pull-down module 13 is in an off state
  • the pull-up The pull-up control signal Q is at a low level
  • the pull-down maintaining module 14 outputs a high-level control signal QB to the pull-down module 13 to turn on the pull-down module 13 to maintain the pull-up control signal Q and the scan signal OUT (N) of the current stage at low Potential.
  • the pull-down maintenance module 14 includes a fifth switch tube T5, a sixth switch tube T6, and a seventh switch tube T7;
  • the gate and drain of the fifth switch tube T5 are connected to a high-potential signal VGH, and the drain of the fifth switch tube T5 is connected to the switch module 15, the gate and the drain of the fourth switch tube T4, respectively.
  • the gate of the sixth switch tube T6 and the source of the seventh switch tube T7, the source of the sixth switch tube T6 is connected to the pull-up control signal Q, and the drain of the sixth switch tube T6
  • the pole is connected to the low potential signal VSS
  • the gate of the seventh switch tube T7 is connected to the pull-up control signal Q
  • the drain of the seventh switch tube T7 is connected to the low potential signal VSS.
  • the seventh switch tube T7 is turned on to pull the control signal QB to a low potential signal VSS, the sixth switch tube T6 is turned off, and the fourth switch tube T4 is turned off. open.
  • the pull-up control signal Q is at a low potential
  • the seventh switch tube T7 is turned off
  • the control signal QB is a high potential signal VGH
  • the sixth switch tube T6 is turned on to maintain the pull-up control signal Q at a low potential while controlling the first
  • the four-switch tube T4 is turned on and pulls down the scan signal OUT (N) of this stage and maintains it at a low potential.
  • the fifth switching tube T5, the sixth switching tube T6 and the seventh switching tube T7 are all thin film transistors.
  • the switch module 15 is respectively connected to the pull-down maintenance module 14, the bootstrap module 16 and the pull-up module 12, and is used to delay the preset time when the pull-up module 12 outputs the high-level scan signal OUT(N). open.
  • the switch module 15 is specifically configured to be turned on when the pull-up control signal Q is at a low potential, and continue to be turned on when the pull-up control signal Q is converted from a low potential to a high potential.
  • the pull-up module 12 outputs the high-level scanning signal OUT(N) of the current level, it is switched from on to off after a preset time delay.
  • the pull-up control signal Q before the start of the scan and after the completion of the scan, the pull-up control signal Q is at a low level, and the switch module 15 is in a conducting state.
  • the pull-up control module 11 outputs a high-potential pull-up control signal Q, that is, the pull-up control signal Q is converted from a low potential to a high potential at this time. Turning on is converted to turning off.
  • the pull-up module 12 outputs the high-level scan signal OUT(N) of the current level, that is, after the pull-up module 12 outputs the high-level scan signal OUT(N) of the current level, the switch module 15 is still delayed It is disconnected after a preset period of time. After the switch module 15 is disconnected, the pull-up control signal Q remains high.
  • the pull-up control signal Q is pulled down to a low potential, and the switch module 15 is turned into a conducting state.
  • the switch module 15 includes a capacitor C1 and a first switch tube T1;
  • the switch module 15 is specifically configured to charge the capacitor C1 when the pull-up control signal Q is at a low level, and the first switch tube T1 is turned on, when the pull-up control signal Q is switched from a low level When it is at a high potential, the first switch tube T1 continues to conduct through the capacitor C1, and when the pull-up module 12 outputs a high-level scan signal OUT(N) of the current level, it is turned on after a preset time delay. On is converted to off.
  • one end of the capacitor C1 is connected to the drain of the fifth switch tube T5, the other end of the capacitor C1 is connected to the gate of the first switch tube T1, and the source of the first switch tube T1 is connected to the In the bootstrap module 16, the drain of the first switch tube T1 is connected to the scan signal OUT(N) of the current stage.
  • the bootstrap module 16 is respectively connected to the output terminal of the pull-up control module 11 and the switch module 15, and is used to, within the preset time delay of the switch module 15, according to the high-level scan signal OUT(N) of the current level,
  • the pull-up control signal Q is maintained at a high potential, and when the switch module 15 is disconnected, the connection with the scan signal OUT(N) of the current stage is cut off.
  • the bootstrap module 16 includes a bootstrap capacitor C2;
  • One end of the bootstrap capacitor C2 is connected to the pull-up control signal Q, and the other end of the bootstrap capacitor C2 is connected to the source of the first switch tube T1.
  • one end of the bootstrap capacitor C2 is connected to the output end of the pull-up control module 11, and the other end is connected to the output end of the pull-up module 12 through the switch module 15.
  • the switch module 15 is still in the conducting state for a preset period of time, and both ends of the bootstrap capacitor C2 are connected to the high-level pull-up control signal Q and the high-level scan signal OUT (N) of the current stage maintain the pull-up control signal Q at a high level through bootstrapping.
  • the switch module 15 After delaying the preset time, the switch module 15 is disconnected, the bootstrap capacitor C2 is disconnected from the scan signal OUT(N) of the current stage, and the pull-up module 12 still outputs the scan signal OUT(N) of the current stage at a high level, thereby reducing
  • the capacitive load at the output of the GOA circuit improves the load capacity of the GOA circuit output.
  • the high-level first clock signal CLK and the previous scan signal OUT (N-1) are input to the second switch tube T2 together, and the second switch tube T2 is turned on and outputs a high-level pull-up control signal Q, the seventh switch tube T7 is turned on, and the control signal QB is pulled down to a low level.
  • the first switch tube T1 is still conducting through the capacitor C1, and the second clock signal CLKB with a low potential is input to the third switch tube T3.
  • the third switch tube T3 is turned on, and outputs the low-level scanning signal OUT(N) of the current level.
  • the low-level first clock signal CLK and the previous scan signal OUT (N-1) are input to the second switch tube T2, the second switch tube T2 is turned off, and the pull-up control signal Q is in a floating state.
  • the high-level second clock signal CLKB is input to the third switch tube T3 to pull up the scan signal OUT(N) of this level to a high level.
  • the first switch tube T1 is turned on through the capacitor C1, and the capacitor C1 will pull up the control.
  • the signal Q is maintained at a high potential, and the first switch tube T1 is disconnected after a preset period of time, and the connection between the capacitor C1 and the scanning signal OUT(N) of the current stage is cut off.
  • the first clock signal CLK with a high potential and the previous scan signal OUT (N-1) with a low potential are input to the second switch tube T2 together, and the second switch tube T2 is turned on to pull up the control signal Q Pulled down to a low potential, the seventh switch tube T7 is turned off, the sixth switch tube T6 is turned on, and the control signal QB is pulled up to a high potential.
  • the first switch tube T1 is turned on, and the fourth switch tube T4 is turned on to scan the current stage.
  • the signal OUT(N) is pulled down to a low level, and the pull-up control signal Q and the current level scan signal OUT(N) are maintained at a low level.
  • the high and low levels of the first clock signal CLK are respectively +20V and -10V
  • the high and low levels of the second clock signal CLKB are respectively +20V and -10V
  • the level of the low potential signal VSS is -10V.
  • the level of the high potential signal VGH is +20V.
  • the voltage of each signal can be evaluated and set according to the width-to-length ratio and process of each thin-film transistor, and the electrical parameters of the device.
  • the GOA circuit provided in this embodiment can provide a switch module between the bootstrap module and the output terminal of the GOA circuit.
  • the pull-up module outputs a high-level scan signal of the current level
  • the switch module is turned on for a preset period of time.
  • the bootstrap module maintains the pull-up control signal at a high level for the preset time period when the switch module is turned on.
  • the switch module is turned off, it cuts off the connection with the output terminal of the GOA circuit, thereby reducing the load on the output terminal and improving
  • the load capacity of GOA circuit output is extremely suitable for products with extremely high GOA output load such as ultra-high resolution and refresh rate.
  • This embodiment also provides a TFT substrate including the GOA circuit in the above-mentioned embodiment, which will not be described in detail here.
  • the TFT substrate provided in this embodiment reduces the load on the output terminal of the GOA circuit and improves the load capacity of the GOA circuit output, which is extremely suitable for products with extremely high GOA output loads such as ultra-high resolution and refresh rate.

Abstract

公开了一种GOA电路及TFT基板。该GOA电路包括上拉控制模块（11）；上拉模块（12）；下拉模块（12）；下拉维持模块（14）；开关模块（15），用于在上拉模块（12）输出高电位的本级扫描信号时，延迟预设时长后断开；自举模块（16），用于在开关模块（15）延迟的预设时长内，将上拉控制信号维持在高电位，在开关模块（15）断开时，切断与本级扫描信号的连接。

Description

一种GOA电路及TFT基板
本申请要求于2020年2月26日提交中国专利局、申请号为202010120563.X、发明名称为“一种GOA电路及TFT基板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示面板技术领域，尤其涉及一种GOA电路及TFT基板。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对栅极逐行扫描的驱动方式。
现有技术中的GOA电路，会在上拉控制模块输出的上拉控制信号与上拉模块输出的扫描信号之间挂载电容，在扫描信号为高电平时，通过电容自举抬升上拉控制信号的电位，以使上拉模块在扫描信号输出期间输出的高电平足够高。但是，仅采用电容进行自举，没法很灵活地控制自举状况，导致输出端的电容负载较大，降低GOA电路输出的带载能力。
 技术问题
本发明实施例提供一种GOA电路及TFT基板，以解决现有GOA电路输出端的电容负载较大，带载能力差的问题。
 技术解决方案
本发明实施例提供了一种GOA电路，包括多个级联的GOA单元，每级GOA单元包括：
上拉控制模块，用于在扫描开始时，根据第一时钟信号和上一级扫描信号，输出高电位的上拉控制信号；
上拉模块，用于根据第二时钟信号和所述上拉控制信号，输出高电位的本级扫描信号；
下拉模块，用于在扫描完成时，将所述上拉控制信号和所述本级扫描信号下拉至低电位；
下拉维持模块，用于将所述上拉控制信号和所述本级扫描信号维持在低电位；
开关模块，用于在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后断开；
自举模块，用于在所述开关模块延迟的预设时长内，根据高电位的本级扫描信号，将所述上拉控制信号维持在高电位，在所述开关模块断开时，切断与所述本级扫描信号的连接。
进一步地，所述开关模块具体用于在所述上拉控制信号为低电位时导通，在所述上拉控制信号由低电位转换为高电位时继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
进一步地，所述开关模块包括电容和第一开关管；
所述开关模块具体用于在所述上拉控制信号为低电位时，所述电容充电，且所述第一开关管导通，在所述上拉控制信号由低电位转换为高电位时，所述第一开关管通过所述电容继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
进一步地，所述电容的一端连接所述下拉维持模块，所述电容的另一端连接所述第一开关管的栅极，所述第一开关管的源极连接所述自举模块，所述第一开关管的漏极接入所述本级扫描信号。
进一步地，所述自举模块包括自举电容；
所述自举电容的一端接入所述上拉控制信号，所述自举电容的另一端连接所述第一开关管的源极。
进一步地，所述上拉控制模块包括第二开关管；
所述第二开关管的栅极接入第一时钟信号，所述第二开关管的源极接入上一级扫描信号，所述第二开关管的漏极输出上拉控制信号。
进一步地，所述上拉模块包括第三开关管；
所述第三开关管的栅极接入所述上拉控制信号，所述第三开关管的源极接入所述第二时钟信号，所述第三开关管的漏极输出所述本级扫描信号。
进一步地，所述下拉模块包括第四开关管；
所述第四开关管的栅极连接所述下拉维持模块，所述第四开关管的源极接入所述本级扫描信号，所述第四开关管的漏极接入低电位信号。
进一步地，所述下拉维持模块包括第五开关管、第六开关管和第七开关管；
所述第五开关管的栅极和漏极接入高电位信号，所述第五开关管的漏极分别连接所述电容、所述第四开关管的栅极、所述第六开关管的栅极和所述第七开关管的源极，所述第六开关管的源极接入所述上拉控制信号，所述第六开关管的漏极接入低电位信号，所述第七开关管的栅极接入所述上拉控制信号，所述第七开关管的漏极接入低电位信号。
本发明实施例还提供了一种TFT基板，包括上述GOA电路，所述GOA电路包括多个级联的GOA单元，每级GOA单元包括：
上拉控制模块，用于在扫描开始时，根据第一时钟信号和上一级扫描信号，输出高电位的上拉控制信号；
上拉模块，用于根据第二时钟信号和所述上拉控制信号，输出高电位的本级扫描信号；
下拉模块，用于在扫描完成时，将所述上拉控制信号和所述本级扫描信号下拉至低电位；
下拉维持模块，用于将所述上拉控制信号和所述本级扫描信号维持在低电位；
开关模块，用于在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后断开；
自举模块，用于在所述开关模块延迟的预设时长内，根据高电位的本级扫描信号，将所述上拉控制信号维持在高电位，在所述开关模块断开时，切断与所述本级扫描信号的连接。
进一步地，所述开关模块具体用于在所述上拉控制信号为低电位时导通，在所述上拉控制信号由低电位转换为高电位时继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
进一步地，所述开关模块包括电容和第一开关管；
所述开关模块具体用于在所述上拉控制信号为低电位时，所述电容充电，且所述第一开关管导通，在所述上拉控制信号由低电位转换为高电位时，所述第一开关管通过所述电容继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
进一步地，所述电容的一端连接所述下拉维持模块，所述电容的另一端连接所述第一开关管的栅极，所述第一开关管的源极连接所述自举模块，所述第一开关管的漏极接入所述本级扫描信号。
进一步地，所述自举模块包括自举电容；
所述自举电容的一端接入所述上拉控制信号，所述自举电容的另一端连接所述第一开关管的源极。
进一步地，所述上拉控制模块包括第二开关管；
所述第二开关管的栅极接入第一时钟信号，所述第二开关管的源极接入上一级扫描信号，所述第二开关管的漏极输出上拉控制信号。
进一步地，所述上拉模块包括第三开关管；
所述第三开关管的栅极接入所述上拉控制信号，所述第三开关管的源极接入所述第二时钟信号，所述第三开关管的漏极输出所述本级扫描信号。
进一步地，所述下拉模块包括第四开关管；
所述第四开关管的栅极连接所述下拉维持模块，所述第四开关管的源极接入所述本级扫描信号，所述第四开关管的漏极接入低电位信号。
进一步地，所述下拉维持模块包括第五开关管、第六开关管和第七开关管；
所述第五开关管的栅极和漏极接入高电位信号，所述第五开关管的漏极分别连接所述电容、所述第四开关管的栅极、所述第六开关管的栅极和所述第七开关管的源极，所述第六开关管的源极接入所述上拉控制信号，所述第六开关管的漏极接入低电位信号，所述第七开关管的栅极接入所述上拉控制信号，所述第七开关管的漏极接入低电位信号。
 有益效果
本发明的有益效果为：在自举模块和GOA电路的输出端之间设置开关模块，在上拉模块输出高电位的本级扫描信号时，开关模块导通预设时长后断开，以使自举模块在开关模块导通的预设时长内将上拉控制信号维持在高电位，在开关模块断开时切断与GOA电路输出端的连接，从而减少输出端的负载，提升GOA电路输出的带载能力。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的GOA电路的结构示意图；
图2为本发明实施例提供的GOA电路中的信号时序图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
参见图1，是本发明实施例提供的GOA电路的结构示意图。
本发明实施例提供的GOA电路包括多个级联的GOA单元，每级GOA单元包括上拉控制模块11、上拉模块12、下拉模块13、下拉维持模14、开关模块15和自举模块16。
上拉控制模块11用于在扫描开始时，根据第一时钟信号CLK和上一级扫描信号OUT（N-1），输出高电位的上拉控制信号Q。
本实施例中，在扫描开始时，上拉控制模块11输入高电位的第一时钟信号CLK和高电位的上一级扫描信号OUT（N-1），上拉控制模块11导通，并输出高电位的上拉控制信号Q；在扫描完成时，上拉控制模块11输入高电位的第一时钟信号CLK和低电位的上一级扫描信号OUT（N-1），上拉控制模块11导通，并输出低电位的上拉控制信号Q。其中，上拉控制信号Q可以用于控制上拉模块22的开启和关闭。
具体地，所述上拉控制模块11包括第二开关管T2；
所述第二开关管T2的栅极接入第一时钟信号CLK，所述第二开关管T2的源极接入上一级扫描信号OUT（N-1），所述第二开关管T2的漏极输出上拉控制信号Q。
需要说明的是，在扫描开始时，第二开关管T2的栅极输入高电位的第一时钟信号CLK，第二开关管T2的源极输入高电位的上一级扫描信号OUT（N-1），第二开关管T2导通，第二开关管T2的漏极输出高电位的上拉控制信号Q。然后，第二开关管T2的栅极输入低电位的第一时钟信号CLK，第二开关管T2的源极输入低电位的上一级扫描信号OUT（N-1），第二开关管T2断开，上拉控制信号Q处于悬浮状态。在扫描完成时，第二开关管T2的栅极输入高电位的第一时钟信号CLK，第二开关管T2的源极输入低电位的上一级扫描信号OUT（N-1），第二开关管T2导通，第二开关管T2的漏极输出低电位的上拉控制信号Q。其中，第二开关管T2可以为薄膜晶体管。
上拉模块12与上拉控制模块11连接，用于根据第二时钟信号CLKB和所述上拉控制信号Q，输出高电位的本级扫描信号OUT（N）。
本实施例中，上拉控制模块11输出的上拉控制信号Q输入至上拉模块12，同时上拉模块12输入第二时钟信号CLKB，使上拉模块12根据上拉控制信号Q将输入的第二时钟信号CLKB输出为本级扫描信号OUT（N）。具体地，在上拉模块12输入高电位的上拉控制信号Q和高电位的第二时钟信号CLKB时，上拉模块12输出高电位的本级扫描信号OUT（N）；在上拉模块12输入高电位的上拉控制信号Q和低电位的第二时钟信号CLKB时，上拉模块12输出低电位的本级扫描信号OUT（N）。其中，第二时钟信号CLKB与第一时钟信号CLK反向。
具体地，所述上拉模块包括第三开关管T3；
所述第三开关管T3的栅极接入所述上拉控制信号Q，所述第三开关管T3的源极接入所述第二时钟信号CLKB，所述第三开关管T3的漏极输出所述本级扫描信号OUT（N）。
需要说明的是，第三开关管T3的栅极输入高电位的上拉控制信号Q，第三开关管T3的源极输入低电位的第二时钟信号CLKB，第三开关管T3导通，第三开关管T3的漏极输出低电位的本级扫描信号OUT（N）。第三开关管T3的栅极输入高电位的上拉控制信号Q，第三开关管T3的源极输入高电位的第二时钟信号CLKB，第三开关管T3导通，第三开关管T3的漏极输出高电位的本级扫描信号OUT（N）。其中，第三开关管T3可以为薄膜晶体管。第三开关管T3输出本级扫描信号OUT（N）的端口即为所述GOA电路的输出端。
下拉模块13分别与上拉模块12、下拉维持模块14连接，用于在扫描完成时，将所述上拉控制信号Q和所述本级扫描信号OUT（N）下拉至低电位。
本实施例中，在扫描过程中，下拉模块13断开；在扫描完成时，上拉控制信号Q下拉至低电位，下拉模块13导通，将本级扫描信号OUT（N）下拉至低电位。
具体地，所述下拉模块13包括第四开关管T4；
所述第四开关管T4的栅极连接所述下拉维持模块15，所述第四开关管T4的源极接入所述本级扫描信号OUT（N），所述第四开关管T4的漏极接入低电位信号VSS。
需要说明的是，在扫描过程中，上拉控制信号Q为高电位，第四开关管T4的栅极输入与上拉控制信号Q反向的控制信号QB，即第四开关管T4的栅极输入低电位的控制信号QB，第四开关管T4处于断开状态。在扫描完成时，上拉控制信号Q下拉至低电位，第四开关管T4的栅极输入高电位的控制信号QB，第四开关管T4的源极输入本级扫描信号OUT（N），第四开关管T4的漏极接入低电位信号VSS，第四开关管T4导通，将本级扫描信号OUT（N）下拉至低电位。其中，第四开关管T4可以为薄膜晶体管。
下拉维持模块14分别与下拉模块13、上拉控制模块11连接，用于将所述上拉控制信号Q和所述本级扫描信号OUT（N）维持在低电位。
本实施例中，在扫描过程中，上拉控制信号Q为高电位，下拉维持模块14向下拉模块13输出低电位的控制信号QB，使下拉模块13处于断开状态；在扫描完成时，上拉控制信号Q为低电位，下拉维持模块14向下拉模块13输出高电位的控制信号QB，使下拉模块13导通，以将上拉控制信号Q和本级扫描信号OUT（N）维持在低电位。
具体地，所述下拉维持模块14包括第五开关管T5、第六开关管T6和第七开关管T7；
所述第五开关管T5的栅极和漏极接入高电位信号VGH，所述第五开关管T5的漏极分别连接所述开关模块15、所述第四开关管T4的栅极、所述第六开关管T6的栅极和所述第七开关管T7的源极，所述第六开关管T6的源极接入所述上拉控制信号Q，所述第六开关管T6的漏极接入低电位信号VSS，所述第七开关管T7的栅极接入所述上拉控制信号Q，所述第七开关管T7的漏极接入低电位信号VSS。
需要说明的是，在上拉控制信号Q为高电位时，第七开关管T7导通，以将控制信号QB下拉为低电位信号VSS，第六开关管T6断开，第四开关管T4断开。在上拉控制信号Q为低电位时，第七开关管T7断开，控制信号QB为高电位信号VGH，第六开关管T6导通，将上拉控制信号Q维持在低电位，同时控制第四开关管T4导通，将本级扫描信号OUT（N）下拉并维持在低电位。第五开关管T5、第六开关管T6和第七开关管T7均为薄膜晶体管。
开关模块15分别与下拉维持模块14、自举模块16和上拉模块12连接，用于在所述上拉模块12输出高电位的本级扫描信号OUT（N）时，延迟预设时长后断开。
具体地，所述开关模块15具体用于在所述上拉控制信号Q为低电位时导通，在所述上拉控制信号Q由低电位转换为高电位时继续导通，并在所述上拉模块12输出高电位的本级扫描信号OUT（N）时，延迟预设时长后由导通转换为断开。
本实施例中，在扫描开始之前和扫描完成之后，上拉控制信号Q为低电位，开关模块15处于导通状态。在扫描开始时，上拉控制模块11输出高电位上拉控制信号Q，即此时上拉控制信号Q由低电位转换为高电位，开关模块15未立即断开，而是延迟一定时间后由导通转换为断开。在延迟的这段时间内，上拉模块12输出高电位的本级扫描信号OUT（N），即在上拉模块12输出高电位的本级扫描信号OUT（N）后，开关模块15仍延迟预设时长后才断开，开关模块15断开后，上拉控制信号Q仍保持高电位。在扫描完成时，上拉控制信号Q下拉为低电位，开关模块15又转换为导通状态。
具体地，所述开关模块15包括电容C1和第一开关管T1；
所述开关模块15具体用于在所述上拉控制信号Q为低电位时，所述电容C1充电，且所述第一开关管T1导通，在所述上拉控制信号Q由低电位转换为高电位时，所述第一开关管T1通过所述电容C1继续导通，并在所述上拉模块12输出高电位的本级扫描信号OUT（N）时，延迟预设时长后由导通转换为断开。
其中，所述电容C1的一端连接第五开关管T5的漏极，所述电容C1的另一端连接所述第一开关管T1的栅极，所述第一开关管T1的源极连接所述自举模块16，所述第一开关管T1的漏极接入所述本级扫描信号OUT（N）。
自举模块16分别与所述上拉控制模块11的输出端、开关模块15连接，用于在所述开关模块15延迟的预设时长内，根据高电位的本级扫描信号OUT（N），将所述上拉控制信号Q维持在高电位，在所述开关模块15断开时，切断与所述本级扫描信号OUT（N）的连接。
具体地，所述自举模块16包括自举电容C2；
所述自举电容C2的一端接入所述上拉控制信号Q，所述自举电容C2的另一端连接所述第一开关管T1的源极。
本实施例中，自举电容C2的一端连接上拉控制模块11的输出端，另一端通过开关模块15连接上拉模块12的输出端。在上拉模块12的输出端输出高电位的本级扫描信号OUT（N）时，开关模块15在预设时长内仍处于导通状态，自举电容C2两端连接高电位的上拉控制信号Q和高电位的本级扫描信号OUT（N），通过自举将上拉控制信号Q维持在高电位。延迟预设时长后开关模块15断开，自举电容C2与本级扫描信号OUT（N）的连接断开，而上拉模块12仍输出高电位的本级扫描信号OUT（N），从而减少GOA电路输出端的电容负载，提高GOA电路输出的带载能力。
下面结合图1和图2对本发明实施例提供的GOA电路的工作原理进行详细说明。
在t1阶段，高电位的第一时钟信号CLK和上一级扫描信号OUT（N-1）一同输入至第二开关管T2，第二开关管T2导通，并输出高电位的上拉控制信号Q，第七开关管T7导通，将控制信号QB拉低至低电位，第一开关管T1通过电容C1仍处于导通状态，同时低电位的第二时钟信号CLKB输入至第三开关管T3，第三开关管T3导通，并输出低电位的本级扫描信号OUT（N）。
在t2阶段，低电位的第一时钟信号CLK和上一级扫描信号OUT（N-1）一同输入至第二开关管T2，第二开关管T2断开，上拉控制信号Q处于悬浮状态，同时高电位的第二时钟信号CLKB输入至第三开关管T3，以将本级扫描信号OUT（N）上拉为高电位，第一开关管T1通过电容C1导通，电容C1将上拉控制信号Q维持在高电位，预设时长后第一开关管T1断开，切断电容C1与本级扫描信号OUT（N）的连接。
在t3阶段，高电位的第一时钟信号CLK和低电位的上一级扫描信号OUT（N-1）一同输入至第二开关管T2，第二开关管T2导通，将上拉控制信号Q下拉至低电位，第七开关管T7断开，第六开关管T6导通，将控制信号QB上拉至高电位，第一开关管T1导通，第四开关管T4导通，将本级扫描信号OUT（N）下拉至低电位，并维持上拉控制信号Q和本级扫描信号OUT（N）在低电位。
在一个实施方式中，第一时钟信号CLK的高低电平分别为+20V和-10V，第二时钟信号CLKB的高低电平分别为+20V和-10V，低电位信号VSS的电平为-10V，高电位信号VGH的电平为+20V。实际应用中，各信号的电压可根据各个薄膜晶体管的宽长比和工艺、器件电性参数等进行评估和设定。
由上述可知，本实施例提供的GOA电路，能够在自举模块和GOA电路的输出端之间设置开关模块，在上拉模块输出高电位的本级扫描信号时，开关模块导通预设时长后断开，以使自举模块在开关模块导通的预设时长内将上拉控制信号维持在高电位，在开关模块断开时切断与GOA电路输出端的连接，从而减少输出端的负载，提升GOA电路输出的带载能力，极其适用于超高分辨率、刷新率等GOA输出负载极大的产品。
本实施例还提供一种TFT基板，包括上述实施例中的GOA电路，在此不再详细赘述。
本实施例提供的TFT基板，减少GOA电路输出端的负载，提升GOA电路输出的带载能力，极其适用于超高分辨率、刷新率等GOA输出负载极大的产品。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种GOA电路，其中，包括多个级联的GOA单元，每级GOA单元包括：
    上拉控制模块，用于在扫描开始时，根据第一时钟信号和上一级扫描信号，输出高电位的上拉控制信号；
    上拉模块，用于根据第二时钟信号和所述上拉控制信号，输出高电位的本级扫描信号；
    下拉模块，用于在扫描完成时，将所述上拉控制信号和所述本级扫描信号下拉至低电位；
    下拉维持模块，用于将所述上拉控制信号和所述本级扫描信号维持在低电位；
    开关模块，用于在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后断开；
    自举模块，用于在所述开关模块延迟的预设时长内，根据高电位的本级扫描信号，将所述上拉控制信号维持在高电位，在所述开关模块断开时，切断与所述本级扫描信号的连接。
  2. 根据权利要求1所述的GOA电路，其中，所述开关模块具体用于在所述上拉控制信号为低电位时导通，在所述上拉控制信号由低电位转换为高电位时继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
  3. 根据权利要求2所述的GOA电路，其中，所述开关模块包括电容和第一开关管；
    所述开关模块具体用于在所述上拉控制信号为低电位时，所述电容充电，且所述第一开关管导通，在所述上拉控制信号由低电位转换为高电位时，所述第一开关管通过所述电容继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
  4. 根据权利要求3所述的GOA电路，其中，所述电容的一端连接所述下拉维持模块，所述电容的另一端连接所述第一开关管的栅极，所述第一开关管的源极连接所述自举模块，所述第一开关管的漏极接入所述本级扫描信号。
  5. 根据权利要求4所述的GOA电路，其中，所述自举模块包括自举电容；
    所述自举电容的一端接入所述上拉控制信号，所述自举电容的另一端连接所述第一开关管的源极。
  6. 根据权利要求1所述的GOA电路，其中，所述上拉控制模块包括第二开关管；
    所述第二开关管的栅极接入所述第一时钟信号，所述第二开关管的源极接入所述上一级扫描信号，所述第二开关管的漏极输出所述上拉控制信号。
  7. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括第三开关管；
    所述第三开关管的栅极接入所述上拉控制信号，所述第三开关管的源极接入所述第二时钟信号，所述第三开关管的漏极输出所述本级扫描信号。
  8. 根据权利要求3所述的GOA电路，其中，所述下拉模块包括第四开关管；
    所述第四开关管的栅极连接所述下拉维持模块，所述第四开关管的源极接入所述本级扫描信号，所述第四开关管的漏极接入低电位信号。
  9. 根据权利要求8所述的GOA电路，其中，所述下拉维持模块包括第五开关管、第六开关管和第七开关管；
    所述第五开关管的栅极和漏极接入高电位信号，所述第五开关管的漏极分别连接所述电容、所述第四开关管的栅极、所述第六开关管的栅极和所述第七开关管的源极，所述第六开关管的源极接入所述上拉控制信号，所述第六开关管的漏极接入低电位信号，所述第七开关管的栅极接入所述上拉控制信号，所述第七开关管的漏极接入低电位信号。
  10. 一种TFT基板，其中，包括GOA电路，所述GOA电路包括多个级联的GOA单元，每级GOA单元包括：
    上拉控制模块，用于在扫描开始时，根据第一时钟信号和上一级扫描信号，输出高电位的上拉控制信号；
    上拉模块，用于根据第二时钟信号和所述上拉控制信号，输出高电位的本级扫描信号；
    下拉模块，用于在扫描完成时，将所述上拉控制信号和所述本级扫描信号下拉至低电位；
    下拉维持模块，用于将所述上拉控制信号和所述本级扫描信号维持在低电位；
    开关模块，用于在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后断开；
    自举模块，用于在所述开关模块延迟的预设时长内，根据高电位的本级扫描信号，将所述上拉控制信号维持在高电位，在所述开关模块断开时，切断与所述本级扫描信号的连接。
  11. 根据权利要求10所述的TFT基板，其中，所述开关模块具体用于在所述上拉控制信号为低电位时导通，在所述上拉控制信号由低电位转换为高电位时继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
  12. 根据权利要求11所述的TFT基板，其中，所述开关模块包括电容和第一开关管；
    所述开关模块具体用于在所述上拉控制信号为低电位时，所述电容充电，且所述第一开关管导通，在所述上拉控制信号由低电位转换为高电位时，所述第一开关管通过所述电容继续导通，并在所述上拉模块输出高电位的本级扫描信号时，延迟预设时长后由导通转换为断开。
  13. 根据权利要求12所述的TFT基板，其中，所述电容的一端连接所述下拉维持模块，所述电容的另一端连接所述第一开关管的栅极，所述第一开关管的源极连接所述自举模块，所述第一开关管的漏极接入所述本级扫描信号。
  14. 根据权利要求13所述的TFT基板，其中，所述自举模块包括自举电容；
    所述自举电容的一端接入所述上拉控制信号，所述自举电容的另一端连接所述第一开关管的源极。
  15. 根据权利要求10所述的TFT基板，其中，所述上拉控制模块包括第二开关管；
    所述第二开关管的栅极接入所述第一时钟信号，所述第二开关管的源极接入所述上一级扫描信号，所述第二开关管的漏极输出所述上拉控制信号。
  16. 根据权利要求10所述的TFT基板，其中，所述上拉模块包括第三开关管；
    所述第三开关管的栅极接入所述上拉控制信号，所述第三开关管的源极接入所述第二时钟信号，所述第三开关管的漏极输出所述本级扫描信号。
  17. 根据权利要求12所述的TFT基板，其中，所述下拉模块包括第四开关管；
    所述第四开关管的栅极连接所述下拉维持模块，所述第四开关管的源极接入所述本级扫描信号，所述第四开关管的漏极接入低电位信号。
  18. 根据权利要求17所述的TFT基板，其中，所述下拉维持模块包括第五开关管、第六开关管和第七开关管；
    所述第五开关管的栅极和漏极接入高电位信号，所述第五开关管的漏极分别连接所述电容、所述第四开关管的栅极、所述第六开关管的栅极和所述第七开关管的源极，所述第六开关管的源极接入所述上拉控制信号，所述第六开关管的漏极接入低电位信号，所述第七开关管的栅极接入所述上拉控制信号，所述第七开关管的漏极接入低电位信号。
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