WO2021164060A1 - 像素结构、像素电路及显示面板 - Google Patents

像素结构、像素电路及显示面板 Download PDF

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Publication number
WO2021164060A1
WO2021164060A1 PCT/CN2020/078106 CN2020078106W WO2021164060A1 WO 2021164060 A1 WO2021164060 A1 WO 2021164060A1 CN 2020078106 W CN2020078106 W CN 2020078106W WO 2021164060 A1 WO2021164060 A1 WO 2021164060A1
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Prior art keywords
thin film
film transistor
drain
metal layer
gate
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PCT/CN2020/078106
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English (en)
French (fr)
Inventor
赵玲
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Tcl华星光电技术有限公司
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Priority to US16/650,410 priority Critical patent/US20210405486A1/en
Publication of WO2021164060A1 publication Critical patent/WO2021164060A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode

Definitions

  • This application relates to the field of display, and in particular to a pixel structure, a pixel circuit and a display panel.
  • the vertical alignment type liquid crystal display panel has a very high contrast ratio compared to other types of liquid crystal display panels, and has a very wide range of applications in the field of large-size displays.
  • the current vertical alignment type liquid crystal display panel displays visual chromatic aberration or visual color shift at a large viewing angle.
  • the prior art adopts the pixel design of the 3T (three thin film transistor) structure on the side of the array substrate.
  • a pixel structure The main pixel area and the sub-pixel area are divided into two parts, and the voltage of the sub-pixel area is reduced by sharing the thin film transistor 101, thereby controlling the difference in the amount of liquid crystal rotation between the main pixel area and the sub-pixel area, and improving the display panel in a wide viewing angle.
  • Visual color cast phenomenon is a pixel design of the 3T (three thin film transistor) structure on the side of the array substrate.
  • the present application provides a pixel structure, a pixel circuit, and a display panel to improve the pixel structure of the existing liquid crystal display panel.
  • the existence of the shared electrode line affects the aperture ratio, produces white fog, is easy to short-circuit with the data line, and causes the entire column of pixels to be shared. A series of technical problems such as failure.
  • the present application provides a pixel structure, which includes:
  • the first metal layer includes a scan line, a gate of the first thin film transistor, a gate of a second thin film transistor, a gate of a third thin film transistor, and a gate common electrode line.
  • the gate common electrode line includes a first A grid common electrode line and a second grid common electrode line;
  • the second metal layer includes a data line, the source and drain of the first thin film transistor, the source and drain of the second thin film transistor, and the source and drain of the third thin film transistor;
  • a pixel electrode layer arranged on a side of the second metal layer away from the first metal layer, the pixel electrode layer including a main pixel electrode and a sub-pixel electrode;
  • the main pixel electrode is connected to the drain of the first thin film transistor
  • the sub-pixel electrode is connected to the drain of the second thin film transistor and the source of the third thin film transistor
  • the third The drain of the thin film transistor is connected to the common electrode line.
  • the drain of the third thin film transistor is connected to the first gate common electrode line.
  • the drain of the third thin film transistor is connected to the second gate common electrode line.
  • the scan line and the gate common electrode line are insulated from each other; the data line is connected to the source of the first thin film transistor and the source of the second thin film transistor.
  • the first metal layer further includes a first electrode plate of a first storage capacitor and a first electrode plate of a second storage capacitor
  • the second metal layer further includes a first electrode plate of the first storage capacitor.
  • the second electrode plate, the second electrode plate of the second storage capacitor; the drain electrode of the first thin film transistor is connected to the second electrode plate of the first storage capacitor, and the drain electrode of the second thin film transistor is connected to the second electrode plate of the first storage capacitor.
  • the second electrode plate of the second storage capacitor is connected.
  • the pixel structure further includes an active layer and an insulating layer, the active layer is disposed between the first metal layer and the second metal layer, and the insulating layer is disposed Between the first metal layer and the active layer.
  • a via hole is provided on the insulating layer, and the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • the pixel structure further includes an active layer, a first insulating layer, and a second insulating layer.
  • the active layer is disposed on the first metal layer away from the second metal layer.
  • the first insulating layer is disposed between the first metal layer and the active layer
  • the second insulating layer is disposed between the first metal layer and the second metal layer.
  • a via hole is provided on the second insulating layer, and the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • the application provides a pixel circuit, which includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a first storage capacitor, a first liquid crystal capacitor, a second storage capacitor, and a second liquid crystal capacitor;
  • the drain of the thin film transistor is connected to the first storage capacitor and the first liquid crystal capacitor, and the drain of the second thin film transistor is connected to the second storage capacitor, the second liquid crystal capacitor and the third thin film
  • the source of the transistor is connected; the gate of the first thin film transistor, the gate of the second thin film transistor, and the gate of the third thin film transistor are connected to the same scan line to access the same scan electrical signal; the first The source of a thin film transistor and the source of the second thin film transistor are connected to the same data line and connected to the same data electrical signal; the source of the third thin film transistor is connected to the gate common signal.
  • the present application also provides a display panel, which includes a pixel structure, and the pixel structure includes:
  • the first metal layer includes a scan line, a gate of the first thin film transistor, a gate of a second thin film transistor, a gate of a third thin film transistor, and a gate common electrode line.
  • the gate common electrode line includes a first A grid common electrode line and a second grid common electrode line;
  • the second metal layer includes a data line, the source and drain of the first thin film transistor, the source and drain of the second thin film transistor, and the source and drain of the third thin film transistor;
  • a pixel electrode layer arranged on a side of the second metal layer away from the first metal layer, the pixel electrode layer including a main pixel electrode and a sub-pixel electrode;
  • the main pixel electrode is connected to the drain of the first thin film transistor
  • the sub-pixel electrode is connected to the drain of the second thin film transistor and the source of the third thin film transistor
  • the third The drain of the thin film transistor is connected to the common electrode line.
  • the drain of the third thin film transistor is connected to the first gate common electrode line.
  • the drain of the third thin film transistor is connected to the second gate common electrode line.
  • the scan line and the gate common electrode line are insulated from each other; the data line is connected to the source of the first thin film transistor and the source of the second thin film transistor.
  • the first metal layer further includes the first electrode plate of the first storage capacitor and the first electrode plate of the second storage capacitor
  • the second metal layer further includes the first electrode plate of the first storage capacitor.
  • the second electrode plate, the second electrode plate of the second storage capacitor; the drain electrode of the first thin film transistor is connected to the second electrode plate of the first storage capacitor, and the drain electrode of the second thin film transistor is connected to the second electrode plate of the first storage capacitor.
  • the second electrode plate of the second storage capacitor is connected.
  • the pixel structure further includes an active layer and an insulating layer, the active layer is disposed between the first metal layer and the second metal layer, and the insulating layer is disposed Between the first metal layer and the active layer.
  • a via hole is provided on the insulating layer, and the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • the pixel structure further includes an active layer, a first insulating layer, and a second insulating layer.
  • the active layer is disposed on the first metal layer away from the second metal layer.
  • the first insulating layer is disposed between the first metal layer and the active layer
  • the second insulating layer is disposed between the first metal layer and the second metal layer.
  • a via hole is provided on the second insulating layer, and the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • the display panel further includes a pixel circuit
  • the pixel circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a first storage capacitor, a first liquid crystal capacitor, and a second A storage capacitor and a second liquid crystal capacitor; the drain of the first thin film transistor is connected to the first storage capacitor and the first liquid crystal capacitor, and the drain of the second thin film transistor is connected to the second storage capacitor
  • the second liquid crystal capacitor is connected to the source of the third thin film transistor; the gate of the first thin film transistor, the gate of the second thin film transistor, and the gate of the third thin film transistor are connected to the same
  • the scan line is connected to the same scanning electrical signal; the source of the first thin film transistor and the source of the second thin film transistor are connected to the same data line, and the same data electrical signal is connected; the source of the third thin film transistor Connect the grid common signal.
  • the present application provides a pixel structure, a pixel circuit, and a display panel.
  • the pixel structure includes a first metal layer.
  • the first metal layer includes a scan line, a gate of a first thin film transistor, a gate of a second thin film transistor, and a second thin film transistor.
  • the gate of the three thin film transistors and the gate common electrode line, the gate common electrode line includes a first gate common electrode line and a second gate common electrode line; a second metal layer, the second metal layer includes a data line, a second The source and drain of a thin film transistor, the source and drain of the second thin film transistor, the source and drain of the third thin film transistor; the pixel electrode layer is arranged on the side of the second metal layer away from the first metal layer ,
  • the pixel electrode layer includes a main pixel electrode and a sub-pixel electrode; wherein the main pixel electrode is connected to the drain of the first thin film transistor, the sub-pixel electrode is connected to the drain of the second thin film transistor and the source of the third thin film transistor.
  • the drain of the three thin film transistor is connected to the common electrode line through the via hole.
  • This pixel structure avoids a series of problems such as the existence of shared electrode lines in the existing pixel structure, affecting the aperture ratio, generating white fog, being easy to short-circuit with the data line, and being difficult to repair. At the same time, it further alleviates the existing pixel structure.
  • the drain of the third thin film transistor is connected to the common electrode line on the color film substrate, which affects the problem of the aperture ratio of the display panel.
  • FIG. 1 is a schematic plan view of a pixel structure in the prior art.
  • FIG. 2 is a schematic diagram of a first planar structure of a pixel structure provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a second type of planar structure of the pixel structure provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of a second type of planar structure of the pixel structure provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a first cross-sectional structure of a pixel structure provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a second cross-sectional structure of the pixel structure provided by an embodiment of the application.
  • FIG. 7 is a circuit diagram of a pixel provided by an embodiment of the application.
  • the present application provides a pixel structure that can alleviate this problem.
  • the pixel structure provided by the present application includes:
  • the first metal layer 210 includes the scan line 211, the gate of the first thin film transistor 241, the gate of the second thin film transistor 242, the gate of the third thin film transistor 243, and the gate common electrode line 212,
  • the gate common electrode line includes a first gate common electrode line 2121 and a second gate common electrode line 2122;
  • the second metal layer 220, the second metal layer includes the data line 221, the source and drain of the first thin film transistor 241, the source and drain of the second thin film transistor 242, and the source and drain of the third thin film transistor 243 ;
  • the pixel electrode layer 230 is arranged on a side of the second metal layer away from the first metal layer, and the pixel electrode layer includes a main pixel electrode 231 and a sub-pixel electrode 232;
  • the main pixel electrode 231 is connected to the drain of the first thin film transistor 241
  • the sub-pixel electrode 232 is connected to the drain of the second thin film transistor 242 and the source of the third thin film transistor 243
  • the drain of the third thin film transistor 243 passes through
  • the via 250 is connected to the common electrode line 212.
  • This embodiment provides a pixel structure that connects the drain of the third thin film transistor connected to the sub-pixel electrode with the gate common electrode line, so that the electrical signal flowing through the third thin film transistor passes through the gate common electrode line Leakage, thereby reducing the voltage of the sub-pixel area; avoiding a series of problems such as the shared electrode line in the existing pixel structure affecting the aperture ratio, generating white fog, being easy to short-circuit with the data line, and being difficult to repair; at the same time, it further alleviates the existing problems.
  • the pixel structure connects the drain electrode of the third thin film transistor with the common electrode line on the color filter substrate, which affects the problem of the aperture ratio of the display panel.
  • the drain of the third thin film transistor is connected to the first common electrode line.
  • the first metal layer 210 is patterned with scan lines 211, first gate common electrode lines 2121, and second gate common electrode lines 2122.
  • the scan line 211 is located between the first gate common electrode line 2121 and the second gate common electrode line 2122, and is insulated from the first gate common electrode line 2121 and the second gate common electrode line 2122; on the scan line 211 It includes the gate of the first thin film transistor 241, the gate of the second thin film transistor 242, and the gate of the third thin film transistor 243; the first gate common electrode line 2121 includes the first electrode plate of the first storage capacitor 244,
  • the two gate common electrode lines 213 include the first electrode plate of the second storage capacitor 245; the first gate common electrode line 2121 corresponds to the main pixel area, and the second gate common electrode line 2122 corresponds to the sub pixel area.
  • the second metal layer 220 is patterned to form the data line 221, the source and drain of the first thin film transistor 241, the source and drain of the second thin film transistor 242, the source and drain of the third thin film transistor 243, the first The second electrode plate of the storage capacitor 244 and the second electrode plate of the second storage capacitor 245.
  • the data line 221 is integrally arranged with the source of the first thin film transistor 241 and the source of the second thin film transistor 242, the drain of the first thin film transistor 241 and the second electrode plate of the first storage capacitor 244 are integrally arranged, and the second thin film transistor The drain of 242, the second electrode plate of the second storage capacitor 245, and the source of the third thin film transistor 243 are integrally arranged, and the drain of the third thin film transistor 243 is connected to the first gate common electrode line 2121 through the via 350.
  • the drain lead of the third thin film transistor is connected to the first gate common electrode line, so that the electrical signal flowing through the third thin film transistor leaks through the gate common electrode line, thereby reducing the voltage of the sub-pixel area;
  • a series of problems such as the shared electrode line in the existing pixel structure affecting the aperture ratio, white fog, easy to short-circuit with the data line, and difficult to repair; at the same time, it further alleviates the existing pixel structure to combine the drain and color of the third thin film transistor.
  • the common electrode line connection on the film substrate affects the aperture ratio of the display panel.
  • the drain of the third thin film transistor is connected to the second gate common electrode line.
  • the first metal layer 210 is patterned with scan lines 211, first gate common electrode lines 2121, and second gate common electrode lines 2122.
  • the scan line 211 is located between the first gate common electrode line 2121 and the second gate common electrode line 2122, and is insulated from the first gate common electrode line 2121 and the second gate common electrode line 2122; on the scan line 211 It includes the gate of the first thin film transistor 241, the gate of the second thin film transistor 242, and the gate of the third thin film transistor 243;
  • the first gate common electrode line 2121 includes the first electrode plate of the first storage capacitor 244,
  • the two gate common electrode lines 2122 include the first electrode plate of the second storage capacitor 245;
  • the first gate common electrode line 21211 corresponds to the main pixel area, and the second gate common electrode line 2122 corresponds to the sub pixel area.
  • the second metal layer 220 is patterned to form the data line 221, the source and drain of the first thin film transistor 241, the source and drain of the second thin film transistor 242, the source and drain of the third thin film transistor 243, the first The second electrode plate of the storage capacitor 244 and the second electrode plate of the second storage capacitor 245.
  • the data line 221 is integrally arranged with the source of the first thin film transistor 241 and the source of the second thin film transistor 242, the drain of the first thin film transistor 241 and the second electrode plate of the first storage capacitor 244 are integrally arranged, and the second thin film transistor
  • the drain electrode of 242, the second electrode plate of the second storage capacitor 245, and the source electrode of the third thin film transistor 243 are integrally arranged.
  • the two gate common electrode lines 2122 are connected.
  • the drain lead of the third thin film transistor is connected to the second gate common electrode line, so that the electrical signal flowing through the third thin film transistor leaks through the gate common electrode line, thereby reducing the voltage of the sub-pixel area;
  • the shared electrode line in the existing pixel structure affects a series of problems such as aperture ratio, white fog generation, and difficult maintenance; at the same time, it further relieves the existing pixel structure to connect the drain of the third thin film transistor to the common electrode line on the color film substrate , The problem that affects the aperture ratio of the display panel.
  • FIG. 5 is a schematic diagram of the first cross-sectional structure of the pixel structure provided by the embodiment of the application (part of the film structure is not shown).
  • the pixel structure includes a substrate 410, an active layer 420, a first insulating layer 430, a first metal layer 210, a second insulating layer 440, and a second metal layer 220.
  • the active layer 420 is disposed on the first metal layer 210 away from the first metal layer.
  • the first insulating layer 430 is disposed between the first metal layer 210 and the active layer 420
  • the second insulating layer 440 is disposed between the first metal layer 210 and the second metal layer 220.
  • the active layer 420 is patterned to form the active region of the third thin film transistor 243.
  • the active region includes a channel region and doped regions on both sides of the channel region.
  • the first metal layer 210 is patterned to form a third thin film transistor 243.
  • the second metal layer 220 is patterned to form the source 2432 and the drain 2433 of the third thin film transistor 243.
  • the source 2432 and the drain 2433 of the third thin film transistor 243 respectively pass through The vias penetrating through the first insulating layer 430 and the second insulating layer 440 are connected to the doped regions on both sides of the channel region.
  • the drain 2433 of the third thin film transistor 243 also passes through the vias penetrating the second insulating layer 440. It is connected to the gate common electrode line 212.
  • FIG. 6 is a schematic diagram of the second cross-sectional structure of the pixel structure provided by the embodiment of the application (part of the film structure is not shown).
  • the pixel structure includes a substrate 510, a first metal layer 210, an insulating layer 520, an active layer 530, and a second metal layer 220.
  • the active layer 530 is disposed between the first metal layer 210 and the second metal layer 220.
  • the second metal layer 220 partially covers the active layer 530, and the insulating layer 520 is disposed between the first metal layer 210 and the second metal layer 220 and the active layer 530.
  • the first metal layer 210 is patterned to form the gate 2431 of the third thin film transistor 243 and the gate common electrode line 212, and the active layer 530 is patterned to form the active region of the third thin film transistor 243.
  • the active region includes a channel.
  • the second metal layer 220 is patterned to form the source 2432 and the drain 2433 of the third thin film transistor 243, and the source 2432 and the drain 2433 of the third thin film transistor 243 cover the doped regions on both sides of the channel region.
  • the doped regions on both sides of the channel region are overlapped, and at the same time, the drain 2433 of the third thin film transistor 243 is also connected to the gate common electrode line 212 through the via hole penetrating the insulating layer 530.
  • the present application also provides a pixel circuit.
  • the pixel circuit includes a first thin film transistor 241, a second thin film transistor 242, a third thin film transistor 243, a first storage capacitor 244, a main liquid crystal capacitor 701, and a second The storage capacitor 245, the secondary liquid crystal capacitor 702, the drain of the first thin film transistor 241 is connected to the second electrode plate of the first storage capacitor 244 and the bottom plate of the main liquid crystal capacitor 701, and the drain of the second thin film transistor 242 is connected to the second electrode plate of the main liquid crystal capacitor 701.
  • the second electrode plate of the storage capacitor 245, the bottom plate of the secondary liquid crystal capacitor 702, and the source of the third thin film transistor 243 are connected; the gate of the first thin film transistor 241, the gate of the second thin film transistor 242, and the third thin film transistor 243 The gate is connected to the same gate line 211 to access the same gate signal; the source of the first thin film transistor 241 and the source of the second thin film transistor 242 are connected to the same data line 221 to access the same data signal, and the third The source of the thin film transistor 243 is connected to the gate common electrode line, and is connected to the gate common electrical signal.
  • the first thin film transistor 241 is a switch transistor that controls the main pixel area, and is used to control the conduction of the circuit in the main pixel area.
  • the first thin film transistor 241 is turned on, the data signal on the data line 221 passes through the first thin film transistor.
  • the second thin film transistor 242 is a switching transistor that controls the sub-pixel area
  • the third thin film transistor 243 is a shared thin film transistor
  • the third thin film transistor 243 lowers the potential of the sub-pixel area, so that the voltage of the sub-pixel area is different from the voltage lower than that of the main pixel area, and the deflection angles of liquid crystal molecules in the main pixel area and the sub-pixel area are also different.
  • the brightness of the area is lower than that of the main pixel area, so as to improve the large viewing angle deviation of the vertical alignment type liquid crystal display panel.
  • the present application also provides a display panel, including a pixel structure, and the pixel structure includes:
  • the first metal layer includes the scan line, the gate of the first thin film transistor, the gate of the second thin film transistor, the gate of the third thin film transistor, and the gate common electrode line, the gate common electrode line includes the first gate A common electrode line and a second grid common electrode line;
  • the second metal layer includes the data line, the source and drain of the first thin film transistor, the source and drain of the second thin film transistor, and the source and drain of the third thin film transistor;
  • the pixel electrode layer is arranged on a side of the second metal layer away from the first metal layer, and the pixel electrode layer includes a main pixel electrode and a sub-pixel electrode;
  • the main pixel electrode is connected to the drain of the first thin film transistor
  • the sub-pixel electrode is connected to the drain of the second thin film transistor and the source of the third thin film transistor
  • the drain of the third thin film transistor is connected to the common electrode line.
  • the drain of the third thin film transistor is connected to the first gate common electrode line.
  • the drain of the third thin film transistor is connected to the second gate common electrode line.
  • the scan line and the gate common electrode line are insulated from each other; the data line is connected to the source of the first thin film transistor and the source of the second thin film transistor.
  • the first metal layer further includes the first electrode plate of the first storage capacitor, the first electrode plate of the second storage capacitor, and the second metal layer further includes the second electrode plate of the first storage capacitor, and the second electrode plate of the first storage capacitor.
  • Two second electrode plates of the storage capacitor; the drain of the first thin film transistor is connected with the second electrode plate of the first storage capacitor, and the drain of the second thin film transistor is connected with the second electrode plate of the second storage capacitor.
  • the pixel structure further includes an active layer and an insulating layer, the active layer is disposed between the first metal layer and the second metal layer, and the insulating layer is disposed between the first metal layer and the active layer.
  • a via hole is provided on the insulating layer, and the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • the pixel structure further includes an active layer, a first insulating layer, and a second insulating layer.
  • the active layer is disposed on a side of the first metal layer away from the second metal layer, and the first insulating layer is disposed on Between the first metal layer and the active layer, the second insulating layer is provided between the first metal layer and the second metal layer.
  • a via hole is provided on the second insulating layer, and the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • the display panel further includes a pixel circuit.
  • the pixel circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a first storage capacitor, a first liquid crystal capacitor, a second storage capacitor, and a second storage capacitor.
  • the drain of the first thin film transistor is connected to the first storage capacitor and the first liquid crystal capacitor
  • the drain of the second thin film transistor is connected to the source of the second storage capacitor, the second liquid crystal capacitor and the third thin film transistor
  • the gate of a thin film transistor, the gate of the second thin film transistor, and the gate of the third thin film transistor are connected to the same scan line and access the same scanning electrical signal; the source of the first thin film transistor and the source of the second thin film transistor are connected The same data line is connected to the same data electrical signal; the source of the third thin film transistor is connected to the gate common signal.
  • the embodiments of the present application provide a pixel structure, a pixel circuit, and a display panel.
  • the pixel structure includes a first metal layer, the first metal layer includes a scan line, a gate of a first thin film transistor, and a gate of a second thin film transistor.
  • the gate of the third thin film transistor, and the gate common electrode line, the gate common electrode line includes a first gate common electrode line and a second gate common electrode line; a second metal layer, the second metal layer includes a data line , The source and drain of the first thin film transistor, the source and drain of the second thin film transistor, the source and drain of the third thin film transistor; the pixel electrode layer is arranged on the second metal layer away from the first metal layer On one side, the pixel electrode layer includes a main pixel electrode and a sub pixel electrode; wherein the main pixel electrode is connected to the drain of the first thin film transistor, and the sub pixel electrode is connected to the drain of the second thin film transistor and the source of the third thin film transistor.
  • the drain of the third thin film transistor is connected to the common electrode line through the via hole.
  • This pixel structure avoids a series of problems such as the existence of shared electrode lines in the existing pixel structure, affecting the aperture ratio, generating white fog, being easy to short-circuit with the data line, and being difficult to repair. At the same time, it further alleviates the existing pixel structure.
  • the drain of the third thin film transistor is connected to the common electrode line on the color film substrate, which affects the problem of the aperture ratio of the display panel.

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Abstract

一种避免现有像素结构中共享电极线(102)的存在，影响开口率、产生白雾、易与数据线(104)发生短接、不易检修等一系列问题的像素结构、像素电路及显示面板。像素结构包括：第一金属层(210)，包括扫描线(211)、第一薄膜晶体管(241)的栅极、第二薄膜晶体管(242)的栅极、第三薄膜晶体管(243)的栅极(2431)和栅极公共电极线(212)；第二金属层（220），包括数据线(221)、第一薄膜晶体管(241)的源极和漏极、第二薄膜晶体管(242)的源极和漏极、第三薄膜晶体管(243)的源极(2432)和漏极(2433)；第三薄膜晶体管(243)为共享薄膜晶体管，第三薄膜晶体管(243)的漏极(2433)与栅极公共电极线(212)连接。

Description

像素结构、像素电路及显示面板 技术领域
本申请涉及显示领域，尤其涉及一种像素结构、像素电路及显示面板。
 背景技术
垂直配向型液晶显示面板相对其他种类的液晶显示面板具有极高的对比度，在大尺寸显示领域具有非常广的应用。但是目前垂直配向型液晶显示面板在大视角下显示存在视觉色差或视觉色偏。
为了改善垂直配向型液晶显示面板在大视角下的视觉色差或视觉色偏，现有技术在阵列基板侧采用3T（三个薄膜晶体管）结构的像素设计，如图1所示，将一个像素结构分为主像素区和次像素区两部分，并通过共享薄膜晶体管101来降低次像素区的电压，从而控制主像素区和次像素区的液晶旋转量差，改善在显示面板在广视角下的视觉色偏现象。
降低的次像素电压通过共享电极线102漏出去的，然而共享电极线102的设置会使得位于其下的栅极公共电极线103线宽增加，降低显示面板的开口率；共享电极线102制备工艺的影响，使得显示面板极易产生白雾现象；共享电极线102与数据线104之间的距离较小，极易造成短接的风险；一条共享电极线102连接一列共享薄膜晶体管，不易检修，极容易造成整列像素共享失效的问题。
 技术问题
本申请提供一种像素结构、像素电路及显示面板，以改进现有液晶显示面板的像素结构中共享电极线的存在影响开口率、产生白雾、易与数据线发生短接、造成整列像素共享失效等一系列的技术问题。
 技术解决方案
为解决以上问题，本申请提供的技术方案如下：
本申请提供一种像素结构，其包括：
第一金属层，包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，所述栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；
第二金属层，包括数据线、所述第一薄膜晶体管的源极和漏极、所述第二薄膜晶体管的源极和漏极、所述第三薄膜晶体管的源极和漏极；
像素电极层，设置在所述第二金属层远离所述第一金属层的一侧，所述像素电极层包括主像素电极和次像素电极；
其中，所述主像素电极与所述第一薄膜晶体管的漏极连接，所述次像素电极与所述第二薄膜晶体管的漏极、所述第三薄膜晶体管的源极连接，所述第三薄膜晶体管的漏极与所述公共电极线连接。
在本申请提供的像素结构中，所述第三薄膜晶体管的漏极与所述第一栅极公共电极线连接。
在本申请提供的像素结构中，所述第三薄膜晶体管的漏极与所述第二栅极公共电极线连接。
在本申请提供的像素结构中，所述扫描线与所述栅极公共电极线彼此绝缘；所述数据线与所述第一薄膜晶体管的源极、第二薄膜晶体管的源极连接。
在本申请提供的像素结构中，所述第一金属层还包括第一存储电容的第一电极板、第二存储电容的第一电极板，所述第二金属层还包括第一存储电容的第二电极板、第二存储电容的第二电极板；所述第一薄膜晶体管的漏极与所述第一存储电容的第二电极板连接，所述第二薄膜晶体管的漏极与所述第二存储电容的第二电极板连接。
在本申请提供的像素结构中，所述像素结构还包括有源层、绝缘层，所述有源层设置在所述第一金属层和所述第二金属层之间，所述绝缘层设置在所述第一金属层和所述有源层之间。
在本申请提供的像素结构中，所述绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
在本申请提供的像素结构中，所述像素结构还包括有源层、第一绝缘层、第二绝缘层，所述有源层设置在所述第一金属层远离所述第二金属层的一侧，所述第一绝缘层设置在所述第一金属层和所述有源层之间，所述第二绝缘层设置在所述第一金属层和所述第二金属层之间。
在本申请提供的像素结构中，所述第二绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
本申请提供一种像素电路，其包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第一存储电容、第一液晶电容、第二存储电容、以及第二液晶电容；所述第一薄膜晶体管的漏极与所述第一存储电容、所述第一液晶电容连接，所述第二薄膜晶体管的漏极与所述第二存储电容、所述第二液晶电容和所述第三薄膜晶体管的源极连接；所述第一薄膜晶体管的栅极、所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极连接同一扫描线，接入同一扫描电信号；所述第一薄膜晶体管的源极、所述第二薄膜晶体管的源极连接同一数据线，接入同一数据电信号；所述第三薄膜晶体管的源极接入栅极公共信号。
同时，本申请还提供一种显示面板，其包括像素结构，所述像素结构包括：
第一金属层，包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，所述栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；
第二金属层，包括数据线、所述第一薄膜晶体管的源极和漏极、所述第二薄膜晶体管的源极和漏极、所述第三薄膜晶体管的源极和漏极；
像素电极层，设置在所述第二金属层远离所述第一金属层的一侧，所述像素电极层包括主像素电极和次像素电极；
其中，所述主像素电极与所述第一薄膜晶体管的漏极连接，所述次像素电极与所述第二薄膜晶体管的漏极、所述第三薄膜晶体管的源极连接，所述第三薄膜晶体管的漏极与所述公共电极线连接。
在本申请提供的显示面板中，所述第三薄膜晶体管的漏极与所述第一栅极公共电极线连接。
在本申请提供的显示面板中，所述第三薄膜晶体管的漏极与所述第二栅极公共电极线连接。
在本申请提供的显示面板中，所述扫描线与所述栅极公共电极线彼此绝缘；所述数据线与所述第一薄膜晶体管的源极、第二薄膜晶体管的源极连接。
在本申请提供的显示面板中，所述第一金属层还包括第一存储电容的第一电极板、第二存储电容的第一电极板，所述第二金属层还包括第一存储电容的第二电极板、第二存储电容的第二电极板；所述第一薄膜晶体管的漏极与所述第一存储电容的第二电极板连接，所述第二薄膜晶体管的漏极与所述第二存储电容的第二电极板连接。
在本申请提供的显示面板中，所述像素结构还包括有源层、绝缘层，所述有源层设置在所述第一金属层和所述第二金属层之间，所述绝缘层设置在所述第一金属层和所述有源层之间。
在本申请提供的显示面板中，所述绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
在本申请提供的显示面板中，所述像素结构还包括有源层、第一绝缘层、第二绝缘层，所述有源层设置在所述第一金属层远离所述第二金属层的一侧，所述第一绝缘层设置在所述第一金属层和所述有源层之间，所述第二绝缘层设置在所述第一金属层和所述第二金属层之间。
在本申请提供的显示面板中，所述第二绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
在本申请提供的显示面板中，所述显示面板还包括像素电路，所述像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第一存储电容、第一液晶电容、第二存储电容、以及第二液晶电容；所述第一薄膜晶体管的漏极与所述第一存储电容、所述第一液晶电容连接，所述第二薄膜晶体管的漏极与所述第二存储电容、所述第二液晶电容和所述第三薄膜晶体管的源极连接；所述第一薄膜晶体管的栅极、所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极连接同一扫描线，接入同一扫描电信号；所述第一薄膜晶体管的源极、所述第二薄膜晶体管的源极连接同一数据线，接入同一数据电信号；所述第三薄膜晶体管的源极接入栅极公共信号。
 有益效果
本申请提供了一种像素结构、像素电路及显示面板，该像素结构包括：第一金属层，第一金属层包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；第二金属层，第二金属层包括数据线、第一薄膜晶体管的源极和漏极、第二薄膜晶体管的源极和漏极、第三薄膜晶体管的源极和漏极；像素电极层，设置在第二金属层远离第一金属层的一侧，像素电极层包括主像素电极和次像素电极；其中，主像素电极与第一薄膜晶体管的漏极连接，次像素电极与第二薄膜晶体管的漏极、第三薄膜晶体管的源极连接，第三薄膜晶体管的漏极通过过孔与公共电极线连接。该像素结构避免了现有像素结构中共享电极线的存在，影响开口率、产生白雾、易与数据线发生短接、不易检修等一系列问题；同时进一步缓解了现有像素结构中，将第三薄膜晶体管的漏极与彩膜基板上的公共电极线连接，影响显示面板开口率的问题。
 附图说明
图1为现有技术的像素结构的平面结构示意图。
图2为本申请实施例提供的像素结构的第一种平面结构示意图。
图3为本申请实施例提供的像素结构的第二种平面结构示意图。
图4为本申请实施例提供的像素结构的第二种平面结构示意图。
图5为本申请实施例提供的像素结构的第一种剖面结构示意图。
图6为本申请实施例提供的像素结构的第二种剖面结构示意图。
图7为本申请实施例提供的像素电路图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有像素结构存在的共享电极线影响开口率、产生白雾、易与数据线发生短接、不易检修等一系列问题，本申请提供一种像素结构可以缓解这个问题。
在一种实施例中，如图2所示，本申请提供的像素结构包括：
第一金属层210，第一金属层包括扫描线211、第一薄膜晶体管241的栅极、第二薄膜晶体管242的栅极、第三薄膜晶体管243的栅极、以及栅极公共电极线212，栅极公共电极线包括第一栅极公共电极线2121和第二栅极公共电极线2122；
第二金属层220，第二金属层包括数据线221、第一薄膜晶体管241的源极和漏极、第二薄膜晶体管242的源极和漏极、第三薄膜晶体管243的源极和漏极；
像素电极层230，设置在第二金属层远离第一金属层的一侧，像素电极层包括主像素电极231和次像素电极232；
其中，主像素电极231与第一薄膜晶体管241的漏极连接，次像素电极232与第二薄膜晶体管242的漏极、第三薄膜晶体管243的源极连接，第三薄膜晶体管243的漏极通过过孔250与公共电极线212连接。
本实施例提供一种像素结构，该像素结构将连接于次像素电极的第三薄膜晶体管的漏极与栅极公共电极线连接，使得流经第三薄膜晶体管的电信号经由栅极公共电极线漏走，从而降低次像素区的电压；避免了现有像素结构中共享电极线影响开口率、产生白雾、易与数据线发生短接、不易检修等一系列问题；同时进一步缓解了现有像素结构将第三薄膜晶体管的漏极与彩膜基板上的公共电极线连接，影响显示面板开口率的问题。
在一种实施例中，如图3所示，第三薄膜晶体管的漏极与第一公共电极线连接。
具体的，第一金属层210图案化形成有扫描线211、第一栅极公共电极线2121、以及第二栅极公共电极线2122。扫描线211位于第一栅极公共电极线2121和第二栅极公共电极线2122之间，且与第一栅极公共电极线2121、第二栅极公共电极线2122彼此绝缘；扫描线211上包括第一薄膜晶体管241的栅极、第二薄膜晶体管242的栅极和第三薄膜晶体管243的栅极；第一栅极公共电极线2121上包括第一存储电容244的第一电极板，第二栅极公共电极线213上包括第二存储电容245的第一电极板；第一栅极公共电极线2121对应于主像素区域，第二栅极公共电极线2122对应于次像素区域。
第二金属层220图案化形成数据线221、第一薄膜晶体管241的源极和漏极、第二薄膜晶体管242的源极和漏极、第三薄膜晶体管243的源极和漏极、第一存储电容244的第二电极板、以及第二存储电容245的第二电极板。数据线221和第一薄膜晶体管241的源极、第二薄膜晶体管242的源极一体设置，第一薄膜晶体管241的漏极和第一存储电容244的第二电极板一体设置，第二薄膜晶体管242的漏极和第二存储电容245的第二电极板、第三薄膜晶体管243的源极一体设置，第三薄膜晶体管243的漏极通过过孔350与第一栅极公共电极线2121连接。
本实施通过将第三薄膜晶体管的漏极引线与第一栅极公共电极线连接，使得流经第三薄膜晶体管的电信号经由栅极公共电极线漏走，从而降低次像素区的电压；避免了现有像素结构中共享电极线影响开口率、产生白雾、易与数据线发生短接、不易检修等一系列问题；同时进一步缓解了现有像素结构将第三薄膜晶体管的漏极与彩膜基板上的公共电极线连接，影响显示面板开口率的问题。
在另一种实施例中，如图4所示，第三薄膜晶体管的漏极与第二栅极公共电极线连接。
具体的，第一金属层210图案化形成有扫描线211、第一栅极公共电极线2121、以及第二栅极公共电极线2122。扫描线211位于第一栅极公共电极线2121和第二栅极公共电极线2122之间，且与第一栅极公共电极线2121、第二栅极公共电极线2122彼此绝缘；扫描线211上包括第一薄膜晶体管241的栅极、第二薄膜晶体管242的栅极和第三薄膜晶体管243的栅极；第一栅极公共电极线2121上包括第一存储电容244的第一电极板，第二栅极公共电极线2122上包括第二存储电容245的第一电极板；第一栅极公共电极线21211对应于主像素区域，第二栅极公共电极线2122对应于次像素区域。
第二金属层220图案化形成数据线221、第一薄膜晶体管241的源极和漏极、第二薄膜晶体管242的源极和漏极、第三薄膜晶体管243的源极和漏极、第一存储电容244的第二电极板、以及第二存储电容245的第二电极板。数据线221和第一薄膜晶体管241的源极、第二薄膜晶体管242的源极一体设置，第一薄膜晶体管241的漏极和第一存储电容244的第二电极板一体设置，第二薄膜晶体管242的漏极和第二存储电容245的第二电极板、第三薄膜晶体管243的源极一体设置，第三薄膜晶体管243的漏极借由与之连接的连接导线、通过过孔450与第二栅极公共电极线2122连接。
本实施通过将第三薄膜晶体管的漏极引线与第二栅极公共电极线连接，使得流经第三薄膜晶体管的电信号经由栅极公共电极线漏走，从而降低次像素区的电压；避免了现有像素结构中共享电极线影响开口率、产生白雾、不易检修等一系列问题；同时进一步缓解了现有像素结构将第三薄膜晶体管的漏极与彩膜基板上的公共电极线连接，影响显示面板开口率的问题。
在一种实施例中，如图5所示，图5为本申请实施例提供的像素结构的第一种剖面结构示意图（部分膜层结构未画出）。像素结构包括衬底410、有源层420、第一绝缘层430、第一金属层210、第二绝缘层440、以及第二金属层220，有源层420设置在第一金属层210远离第二金属层220的一侧，第一绝缘层430设置在第一金属层210和有源层420之间，第二绝缘层440设置在第一金属层210和第二金属层220之间。
有源层420图案化形成有第三薄膜晶体管243的有源区，有源区包括沟道区和沟道区两侧的掺杂区，第一金属层210图案化形成有第三薄膜晶体管243的栅极2431和栅极公共电极线212，第二金属层220图案化形成有第三薄膜晶体管243的源极2432、漏极2433，第三薄膜晶体管243的源极2432、漏极2433分别通过贯穿第一绝缘层430、第二绝缘层440的过孔与沟道区两侧的掺杂区相连接，同时，第三薄膜晶体管243的漏极2433还通过贯穿第二绝缘层440的过孔与栅极公共电极线212连接。
在另一种实施例中，如图6所示，图6为本申请实施例提供的像素结构的第二种剖面结构示意图（部分膜层结构未画出）。像素结构包括衬底510、第一金属层210、绝缘层520、有源层530、以及第二金属层220，有源层530设置在第一金属层210和第二金属层220之间，第二金属层220部分覆盖有源层530，绝缘层520设置在第一金属层210和第二金属层220、有源层530之间。
第一金属层210图案化形成有第三薄膜晶体管243的栅极2431和栅极公共电极线212，有源层530图案化形成有第三薄膜晶体管243的有源区，有源区包括沟道区和沟道区两侧的掺杂区，第二金属层220图案化形成有第三薄膜晶体管243的源极2432、漏极2433，第三薄膜晶体管243的源极2432、漏极2433分别覆盖搭接沟道区两侧的掺杂区，同时，第三薄膜晶体管243的漏极2433还通过贯穿绝缘层530的过孔与栅极公共电极线212连接。
本申请还提供一种像素电路，如图7所示，该像素电路包括第一薄膜晶体管241、第二薄膜晶体管242、第三薄膜晶体管243、第一存储电容244、主液晶电容701、第二存储电容245、次液晶电容702，第一薄膜晶体管241的漏极与第一存储电容244的第二电极板、主液晶电容701的下极板连接，第二薄膜晶体管242的漏极与第二存储电容245的第二电极板、次液晶电容702下极板和第三薄膜晶体管243的源极连接；第一薄膜晶体管241的栅极、第二薄膜晶体管242的栅极、第三薄膜晶体管243的栅极与同一栅极线211连接，接入同一栅极信号；第一薄膜晶体管241的源极、第二薄膜晶体管242的源极与同一数据线221连接，接入同一数据信号，第三薄膜晶体管243的源极与栅极公共电极线连接，接入栅极公共电信号。
其中，第一薄膜晶体管241为控制主像素区的开关晶体管，用于控制主像素区的电路的导通，当第一薄膜晶体管241导通时，数据线221上的数据信号通过第一薄膜晶体管241输入到第一存储电容244和主液晶电容701，给第一存储电容244和主液晶电容701充电；第二薄膜晶体管242为控制次像素区的开关晶体管，第三薄膜晶体管243为共享薄膜晶体管，当第二薄膜晶体管242和第三薄膜晶体管243同时导通时，数据线221上的数据信号通过第二薄膜晶体管242后，一部分输入到第二存储电容245和次液晶电容702，给第二存储电容245和次液晶电容702充电，另一部分通过第三薄膜晶体管243流入栅极公共电极。
第三薄膜晶体管243拉低了次像素区域的电位，使得次像素区域的电压与低于主像素区域的电压不同，主像素区域与次像素区域中液晶分子的偏转角度也不同，进而使次像素区域的亮度低于主像素区域，以改善垂直配向型液晶显示面板的大视角色偏现象。
同时，本申请还提供一种显示面板，包括像素结构，该像素结构包括：
第一金属层，包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；
第二金属层，包括数据线、第一薄膜晶体管的源极和漏极、第二薄膜晶体管的源极和漏极、第三薄膜晶体管的源极和漏极；
像素电极层，设置在第二金属层远离第一金属层的一侧，像素电极层包括主像素电极和次像素电极；
其中，主像素电极与第一薄膜晶体管的漏极连接，次像素电极与第二薄膜晶体管的漏极、第三薄膜晶体管的源极连接，第三薄膜晶体管的漏极与公共电极线连接。
在一种实施例中，第三薄膜晶体管的漏极与第一栅极公共电极线连接。
在另一种实施例中，第三薄膜晶体管的漏极与第二栅极公共电极线连接。
在一种实施例中，扫描线与栅极公共电极线彼此绝缘；数据线与第一薄膜晶体管的源极、第二薄膜晶体管的源极连接。
在一种实施例中，第一金属层还包括第一存储电容的第一电极板、第二存储电容的第一电极板，第二金属层还包括第一存储电容的第二电极板、第二存储电容的第二电极板；第一薄膜晶体管的漏极与第一存储电容的第二电极板连接，第二薄膜晶体管的漏极与第二存储电容的第二电极板连接。
在一种实施例中，像素结构还包括有源层、绝缘层，有源层设置在第一金属层和第二金属层之间，绝缘层设置在第一金属层和有源层之间。
在一种实施例中，绝缘层上设置有过孔，第三薄膜晶体管的漏极通过过孔与公共电极线连接。
在另一种实施例中，像素结构还包括有源层、第一绝缘层、第二绝缘层，有源层设置在第一金属层远离第二金属层的一侧，第一绝缘层设置在第一金属层和有源层之间，第二绝缘层设置在第一金属层和第二金属层之间。
在一种实施例中，第二绝缘层上设置有过孔，第三薄膜晶体管的漏极通过过孔与公共电极线连接。
在一种实施例中，显示面板还包括像素电路，像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第一存储电容、第一液晶电容、第二存储电容、以及第二液晶电容；第一薄膜晶体管的漏极与第一存储电容、第一液晶电容连接，第二薄膜晶体管的漏极与第二存储电容、第二液晶电容和第三薄膜晶体管的源极连接；第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极连接同一扫描线，接入同一扫描电信号；第一薄膜晶体管的源极、第二薄膜晶体管的源极连接同一数据线，接入同一数据电信号；第三薄膜晶体管的源极接入栅极公共信号。
根据上述实施例可知：
本申请实施例提供了一种像素结构、像素电路及显示面板，该像素结构包括：第一金属层，第一金属层包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；第二金属层，第二金属层包括数据线、第一薄膜晶体管的源极和漏极、第二薄膜晶体管的源极和漏极、第三薄膜晶体管的源极和漏极；像素电极层，设置在第二金属层远离第一金属层的一侧，像素电极层包括主像素电极和次像素电极；其中，主像素电极与第一薄膜晶体管的漏极连接，次像素电极与第二薄膜晶体管的漏极、第三薄膜晶体管的源极连接，第三薄膜晶体管的漏极通过过孔与公共电极线连接。该像素结构避免了现有像素结构中共享电极线的存在，影响开口率、产生白雾、易与数据线发生短接、不易检修等一系列问题；同时进一步缓解了现有像素结构中，将第三薄膜晶体管的漏极与彩膜基板上的公共电极线连接，影响显示面板开口率的问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素结构，其包括：
    第一金属层，包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，所述栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；
    第二金属层，包括数据线、所述第一薄膜晶体管的源极和漏极、所述第二薄膜晶体管的源极和漏极、所述第三薄膜晶体管的源极和漏极；
    像素电极层，设置在所述第二金属层远离所述第一金属层的一侧，所述像素电极层包括主像素电极和次像素电极；
    其中，所述主像素电极与所述第一薄膜晶体管的漏极连接，所述次像素电极与所述第二薄膜晶体管的漏极、所述第三薄膜晶体管的源极连接，所述第三薄膜晶体管的漏极与所述公共电极线连接。
  2. 如权利要求1所述的像素结构，其中，所述第三薄膜晶体管的漏极与所述第一栅极公共电极线连接。
  3. 如权利要求1所述的像素结构，其中，所述第三薄膜晶体管的漏极与所述第二栅极公共电极线连接。
  4. 如权利要求1所述的像素结构，其中，所述扫描线与所述栅极公共电极线彼此绝缘；所述数据线与所述第一薄膜晶体管的源极、第二薄膜晶体管的源极连接。
  5. 如权利要求1所述的像素结构，其中，所述第一金属层还包括第一存储电容的第一电极板、第二存储电容的第一电极板，所述第二金属层还包括第一存储电容的第二电极板、第二存储电容的第二电极板；所述第一薄膜晶体管的漏极与所述第一存储电容的第二电极板连接，所述第二薄膜晶体管的漏极与所述第二存储电容的第二电极板连接。
  6. 如权利要求1所述的像素结构，其中，所述像素结构还包括有源层、绝缘层，所述有源层设置在所述第一金属层和所述第二金属层之间，所述绝缘层设置在所述第一金属层和所述有源层之间。
  7. 如权利要求6所述的像素结构，其中，所述绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
  8. 如权利要求1所述的像素结构，其中，所述像素结构还包括有源层、第一绝缘层、第二绝缘层，所述有源层设置在所述第一金属层远离所述第二金属层的一侧，所述第一绝缘层设置在所述第一金属层和所述有源层之间，所述第二绝缘层设置在所述第一金属层和所述第二金属层之间。
  9. 如权利要求7所述的像素结构，其中，所述第二绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
  10. 一种像素电路，其包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第一存储电容、第一液晶电容、第二存储电容、以及第二液晶电容；所述第一薄膜晶体管的漏极与所述第一存储电容、所述第一液晶电容连接，所述第二薄膜晶体管的漏极与所述第二存储电容、所述第二液晶电容和所述第三薄膜晶体管的源极连接；所述第一薄膜晶体管的栅极、所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极连接同一扫描线，接入同一扫描电信号；所述第一薄膜晶体管的源极、所述第二薄膜晶体管的源极连接同一数据线，接入同一数据电信号；所述第三薄膜晶体管的源极接入栅极公共信号。
  11. 一种显示面板，其包括像素结构，所述像素结构包括：
    第一金属层，包括扫描线、第一薄膜晶体管的栅极、第二薄膜晶体管的栅极、第三薄膜晶体管的栅极、以及栅极公共电极线，所述栅极公共电极线包括第一栅极公共电极线和第二栅极公共电极线；
    第二金属层，包括数据线、所述第一薄膜晶体管的源极和漏极、所述第二薄膜晶体管的源极和漏极、所述第三薄膜晶体管的源极和漏极；
    像素电极层，设置在所述第二金属层远离所述第一金属层的一侧，所述像素电极层包括主像素电极和次像素电极；
    其中，所述主像素电极与所述第一薄膜晶体管的漏极连接，所述次像素电极与所述第二薄膜晶体管的漏极、所述第三薄膜晶体管的源极连接，所述第三薄膜晶体管的漏极与所述公共电极线连接。
  12. 如权利要求11所述的显示面板，其中，所述第三薄膜晶体管的漏极与所述第一栅极公共电极线连接。
  13. 如权利要求11所述的显示面板，其中，所述第三薄膜晶体管的漏极与所述第二栅极公共电极线连接。
  14. 如权利要求11所述的显示面板，其中，所述扫描线与所述栅极公共电极线彼此绝缘；所述数据线与所述第一薄膜晶体管的源极、第二薄膜晶体管的源极连接。
  15. 如权利要求11所述的显示面板，其中，所述第一金属层还包括第一存储电容的第一电极板、第二存储电容的第一电极板，所述第二金属层还包括第一存储电容的第二电极板、第二存储电容的第二电极板；所述第一薄膜晶体管的漏极与所述第一存储电容的第二电极板连接，所述第二薄膜晶体管的漏极与所述第二存储电容的第二电极板连接。
  16. 如权利要求11所述的显示面板，其中，所述像素结构还包括有源层、绝缘层，所述有源层设置在所述第一金属层和所述第二金属层之间，所述绝缘层设置在所述第一金属层和所述有源层之间。
  17. 如权利要求16所述的显示面板，其中，所述绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
  18. 如权利要求11所述的显示面板，其中，所述像素结构还包括有源层、第一绝缘层、第二绝缘层，所述有源层设置在所述第一金属层远离所述第二金属层的一侧，所述第一绝缘层设置在所述第一金属层和所述有源层之间，所述第二绝缘层设置在所述第一金属层和所述第二金属层之间。
  19. 如权利要求17所述的显示面板，其中，所述第二绝缘层上设置有过孔，所述第三薄膜晶体管的漏极通过所述过孔与所述公共电极线连接。
  20. 如权利要求11所述的显示面板，其中，所述显示面板还包括像素电路，所述像素电路包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第一存储电容、第一液晶电容、第二存储电容、以及第二液晶电容；所述第一薄膜晶体管的漏极与所述第一存储电容、所述第一液晶电容连接，所述第二薄膜晶体管的漏极与所述第二存储电容、所述第二液晶电容和所述第三薄膜晶体管的源极连接；所述第一薄膜晶体管的栅极、所述第二薄膜晶体管的栅极、所述第三薄膜晶体管的栅极连接同一扫描线，接入同一扫描电信号；所述第一薄膜晶体管的源极、所述第二薄膜晶体管的源极连接同一数据线，接入同一数据电信号；所述第三薄膜晶体管的源极接入栅极公共信号。
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