WO2021142828A1 - 时间同步方法及装置、网络节点设备 - Google Patents

时间同步方法及装置、网络节点设备 Download PDF

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Publication number
WO2021142828A1
WO2021142828A1 PCT/CN2020/072979 CN2020072979W WO2021142828A1 WO 2021142828 A1 WO2021142828 A1 WO 2021142828A1 CN 2020072979 W CN2020072979 W CN 2020072979W WO 2021142828 A1 WO2021142828 A1 WO 2021142828A1
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Prior art keywords
time
physical
clock signal
clock
period
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PCT/CN2020/072979
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English (en)
French (fr)
Inventor
魏祥野
修黎明
白一鸣
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to US17/413,367 priority Critical patent/US11799578B2/en
Priority to CN202080000051.8A priority patent/CN113498623B/zh
Priority to JP2022504311A priority patent/JP7493581B2/ja
Priority to PCT/CN2020/072979 priority patent/WO2021142828A1/zh
Priority to EP20897615.9A priority patent/EP4093101A4/en
Publication of WO2021142828A1 publication Critical patent/WO2021142828A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658—Clock or time synchronisation among packet nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network

Definitions

  • the present disclosure relates to the technical field of communication networks, in particular to time synchronization methods and devices, and network node equipment.
  • clock synchronization is a vital component.
  • the embodiments of the present disclosure propose a time synchronization method and device, and network node equipment, so as to make the logical time of the network node equipment more accurate, so that the time of different network node equipment is more synchronized.
  • an embodiment of the present disclosure provides a time synchronization method, including: an adjustment phase, the adjustment phase includes N adjustment periods, and N is an integer greater than 1;
  • a physical clock signal is generated at least according to the frequency control word corresponding to the adjustment period obtained in advance, and a logical time is converted at least according to the physical clock signal and the physical time deviation;
  • the clock slope of the physical clock signal generated in each adjustment period reaches its corresponding target value, and the target value of the clock slope of the physical clock signal of the N adjustment periods gradually approaches 1;
  • the clock slope is the slope of the relationship curve between the physical time and the reference time generated based on the physical clock signal;
  • the physical time deviation is: the physical clock signal of the Nth adjustment period corresponds to the end time of the Nth adjustment period The time difference between the physical time and the reference time.
  • the time synchronization method further includes performing before the adjustment phase:
  • the adjustment period For each adjustment period, according to the target value of the clock slope of the physical clock signal in the adjustment period, the difference between the reference time corresponding to the initial time and the end time of the adjustment period, it is determined that the adjustment period corresponds to The frequency control word.
  • the target value S 1 of the clock slope of the physical clock signal of the first adjustment period is determined according to the following formula:
  • x is the clock frequency deviation coefficient of the physical clock signal in the initial stage acquired in advance
  • the target value S n of the clock slope of the physical clock signal of the nth adjustment period is determined according to the following formula:
  • S n-1 is the target value of the clock slope of the physical clock signal in the n-1 th adjustment period
  • n is an integer
  • 1 ⁇ n ⁇ N is the target value of the clock slope of the physical clock signal in the n-1 th adjustment period
  • the time synchronization method further includes: before the adjustment phase, determining the physical time deviation E according to the following formula:
  • ⁇ t is the standard clock period
  • M is the number of clock periods of the physical clock signal in a single adjustment period.
  • the time synchronization method further includes: before the adjustment phase, determining the physical time deviation E according to the following formula:
  • ⁇ t is the standard clock period
  • M is the number of clock periods of the physical clock signal in a single adjustment period.
  • converting the logical time at least according to the physical clock signal and the physical time deviation includes:
  • ⁇ t is the standard clock period, and E is the physical time deviation
  • the logical time is converted according to the physical clock signal and the first logical clock period.
  • the time synchronization method further includes performing in a continuous phase after the adjustment phase:
  • the logical time is converted according to the physical clock signal of the duration phase and the second logical clock period, wherein the second logical clock period is equal to the standard clock period.
  • the generating a physical clock signal at least according to a pre-acquired frequency control word corresponding to the adjustment period includes:
  • a physical clock signal is generated according to the reference clock signal and the frequency control word corresponding to the adjustment period.
  • an embodiment of the present disclosure also provides a time synchronization device, including:
  • the physical clock signal generation unit is configured to generate a physical clock signal according to at least a pre-acquired frequency control word corresponding to the adjustment period in each adjustment period of the adjustment period; the adjustment period includes N adjustment periods, N Is an integer greater than 1; wherein, the clock slope of the physical clock signal generated in each adjustment period reaches the respective target value, and the target value of the clock slope of the physical clock signal of the N adjustment periods gradually approaches 1; wherein the clock slope is the slope of the relationship curve between the physical time and the reference time generated based on the physical clock signal;
  • the logical time conversion unit is configured to convert the logical time at least according to the received physical clock signal and the physical time deviation in each adjustment period; the physical time deviation is: the physical clock signal of the Nth adjustment period is The time difference between the physical time corresponding to the end of the Nth adjustment cycle and the reference time.
  • the time synchronization device further includes:
  • the control word determining unit is configured to determine the target value of the clock slope of the physical clock signal in each adjustment period before the adjustment phase; and according to the target value of the clock slope of the physical clock signal in the adjustment period The value, the difference between the reference time corresponding to the initial time and the end time of the adjustment period, respectively, determines the frequency control word corresponding to the adjustment period.
  • the target value S 1 of the clock slope of the physical clock signal of the first adjustment period is determined according to the following formula:
  • x is the clock frequency deviation coefficient of the physical clock signal in the initial stage acquired in advance
  • the target value S n of the clock slope of the physical clock signal of the nth adjustment period is determined according to the following formula:
  • S n-1 is the target value of the clock slope of the physical clock signal in the n-1 th adjustment period
  • n is an integer
  • 1 ⁇ n ⁇ N is the target value of the clock slope of the physical clock signal in the n-1 th adjustment period
  • the time synchronization device further includes: a first time deviation determining unit configured to determine the physical time deviation E according to the following formula before the adjustment stage:
  • ⁇ t is the standard clock period
  • M is the number of standard clock periods in the adjustment period.
  • the time synchronization device further includes: a second time deviation determining unit configured to determine the physical time deviation E according to the following formula before the adjustment stage:
  • ⁇ t is the standard clock period
  • M is the number of standard clock periods in the adjustment period.
  • the logic time conversion unit is specifically configured to determine a first logic clock period T l_1 according to the following formula in each adjustment period, and according to the physical clock signal and the first logic The clock cycle is converted to logic time:
  • ⁇ t is the standard clock period
  • E is the physical time deviation
  • the physical clock signal generating unit is further configured to generate a physical clock signal according to the frequency control word corresponding to the Nth adjustment period in a continuous phase after the adjustment phase;
  • the logic time conversion unit is further configured to, in the duration phase, convert the logic time according to the physical clock signal of the duration phase and the second logic clock period, wherein the second logic clock period is the same as the standard clock period. equal.
  • the physical clock signal generating unit is specifically configured to generate a physical clock signal according to a reference clock signal and a frequency control word corresponding to the adjustment period.
  • the physical clock generation unit includes a time average frequency direct period synthesizer.
  • the embodiments of the present disclosure also provide a network node device, including the above-mentioned time synchronization device.
  • Figure 1 shows a schematic diagram of the plesiochronous architecture.
  • Figure 2 shows a schematic diagram of the master-slave architecture.
  • Fig. 3 shows a schematic diagram of a time synchronization method according to some embodiments of the present disclosure.
  • FIG. 4 shows a schematic diagram of the principle of time average frequency according to some embodiments of the present disclosure.
  • Fig. 5 shows another schematic diagram of a time synchronization method in some embodiments of the present disclosure.
  • FIG. 6 shows a schematic diagram of a method for converting logic time in each adjustment period according to some embodiments of the present disclosure.
  • Fig. 7 shows another schematic diagram of a time synchronization method in some embodiments of the present disclosure.
  • Fig. 8 shows a schematic block diagram of a time synchronization apparatus according to some embodiments of the present disclosure.
  • Fig. 9 shows another schematic block diagram of a time synchronization apparatus according to some embodiments of the present disclosure.
  • FIG. 10 shows a circuit diagram of a time average frequency direct period synthesizer according to some embodiments of the present disclosure.
  • Fig. 11 shows another schematic block diagram of a time synchronization apparatus according to some embodiments of the present disclosure.
  • Fig. 12 shows another schematic block diagram of a time synchronization apparatus according to some embodiments of the present disclosure.
  • Figure 13 shows the time offset curves of ten network node devices in the network when they are not time synchronized.
  • Figure 14 shows the synchronization error curve of the network time without time synchronization.
  • FIG. 15 shows the time offset curve of each network node device in the case of performing time synchronization according to the time synchronization method in the comparative example.
  • FIG. 16 shows the synchronization error curve of the network time in the case of performing time synchronization according to the time synchronization method in the comparative example.
  • FIG. 17 shows the time offset curve of each network node device in the case of performing time synchronization according to the time synchronization method in another comparative example.
  • FIG. 18 shows the synchronization error curve of the network time in the case of performing time synchronization according to the time synchronization method in another comparative example.
  • FIG. 19 shows a time offset curve of each network node device in the case of time synchronization according to the time synchronization method shown in FIG. 7.
  • FIG. 20 shows the synchronization error curve of the network time in the case of performing time synchronization according to the time synchronization method shown in FIG. 7.
  • the network architecture has evolved from a synchronous time division multiplexing (TDM) mode to an asynchronous packet switching mode.
  • TDM time division multiplexing
  • asynchronous packet switching system the physical link of the transmission frequency no longer exists, and all data and time information are exchanged through packets, thus increasing the difficulty of time synchronization.
  • the logical time (Logical Time) of the local device is generated based on a physical clock (Physicl Clock) signal.
  • the network node device has a physical clock signal generation unit, and the physical clock signal generation unit is a hardware device that can generate a physical clock signal.
  • the physical time can be described as: every time the clock period of the physical clock signal generated by the physical clock signal generating unit increases by 1, the physical time increases by T p .
  • the physical time is 0; when the clock period in the physical clock signal generated by the physical clock signal generating unit is 1, the physical time is T p ; when the physical clock signal reaches two clock periods, the physical time is 2 ⁇ T p ; and so on.
  • the physical time corresponding to each clock cycle can be converted into logical time.
  • T p is 0.01 second, when the clock cycle in the physical clock signal is 1 (or the first rising edge is generated) , The logical time is 00:00 minutes and 0.01 seconds; when the clock period of the physical clock signal is 2 (or the second rising edge is generated), the logical time is 00:00 minutes and 0.02 seconds, and so on, when the physical clock signal When the clock cycle of is 6000 (or the 6000th rising edge is generated), the logic time is 00:01:00.
  • the physical properties of the physical clock signal generation unit of each network node device may be different, which will cause the logic of different network node devices
  • the time is different, that is, the time is out of sync.
  • the architecture of network time synchronization is roughly divided into two categories, namely Plesiochronous and Master-Slave.
  • Figure 1 shows a schematic diagram of the quasi-synchronous architecture
  • Figure 2 shows a schematic diagram of the master-slave architecture. .
  • each network node device 1 in the quasi-synchronous architecture has an independent physical clock signal generating unit, and the clock frequency of the physical clock signal of each network node device 1 is set to the same value, but each network node device
  • the physical properties of the physical clock generating signal unit of 1 can not be completely consistent, and due to different aging coefficients, temperature drift coefficients, pressure drift coefficients, process errors, etc., the physical time or logical time will shift. Therefore, the accuracy of network time synchronization under this architecture will decrease as the working time increases.
  • the network node devices in the master-slave architecture are divided into a master node device 1a and a slave node device 1b, and each slave node device 1b receives time information sent by the master node device 1a.
  • the time of the master node device 1a is directly assigned to the slave node device 1b, so as to realize time synchronization between the slave node device 1b and the master node device 1a.
  • this synchronization method has certain risks.
  • the time information of a slave node device 1b is 00:53 (that is, 0 minutes and 53 seconds), and the time information sent by the master node device 1a is 00:52, then, When the slave node device 1b synchronizes the time to 00:52, it is equivalent to a time reverse for the slave node device 1b, which is very unfavorable to the system stability of the network node device.
  • FIG. 3 shows a schematic diagram of a time synchronization method according to some embodiments of the present disclosure.
  • the time synchronization method in an embodiment of the present disclosure includes: step S110.
  • the frequency control word corresponding to the adjustment period generates a physical clock signal, and at least converts the logical time according to the physical clock signal and the physical time deviation E.
  • the physical clock signal may be executed by a physical clock signal generating unit, and the physical clock signal generating unit may specifically generate the physical clock signal according to the frequency control word and the reference clock signal.
  • the clock frequency of the reference clock signal is fixed, for different frequency control words, the frequency (and period) of the physical clock signal generated by the physical clock signal generating unit is also different.
  • the physical clock signal generated in each adjustment period has a clock slope, and the clock slope of the physical clock signal generated in each adjustment period reaches the corresponding target value.
  • the target value of the clock slope of the physical clock signal gradually approaches 1.
  • the clock slope is the slope of the relationship curve between the physical time and the reference time.
  • the physical time is the time generated based on the physical clock signal.
  • the physical time deviation E is: the time difference between the physical time corresponding to the physical clock signal of the Nth adjustment period at the end of the Nth adjustment period and the reference time.
  • the reference time is the time provided by other network node devices, and the reference time can be generated according to the reference clock signal of other network node devices.
  • the reference clock signal is the physical clock signal of the master node device
  • the reference time is the logical time generated by the master node device based on the reference clock signal
  • the reference time may be an average value of the logical time of multiple other network node devices.
  • the reference time increases by 1/f after each clock cycle, and the reference time is between the number of clock cycles p of the reference clock signal
  • the clock frequency of the physical clock signal of the network node equipment is f, and due to process errors, temperature drift, etc., the actual clock frequency of the physical clock signal will reach f+ ⁇ f, and the physical clock signal will pass every clock cycle.
  • the normalized physical time in, x is: in the initial stage before the adjustment stage, the clock frequency deviation coefficient of the physical clock signal. It can be seen that the clock frequency deviation coefficient x is related to ⁇ f, and
  • the clock slope of the physical clock signal of N adjustment cycles gradually approaches 1, that is, the increase speed of the physical time gradually approaches the increase speed of the reference time, that is, the clock frequency of the physical clock signal gradually approaches The clock frequency of the reference clock signal.
  • N takes a larger value
  • the clock slope of the physical clock signal of the Nth adjustment cycle will be basically close to 1.
  • the “substantially close to 1" here can be set according to the application scenario and protocol, for example, between 1
  • the difference between is less than 10 -8 , or the difference with 1 is less than 10 -10 . Therefore, after N adjustment cycles, when the physical clock signal is continuously generated according to the frequency control word of the Nth adjustment cycle, the difference between the physical time and the reference time will no longer gradually increase.
  • the logical time of different network node devices can be made more accurate, and the time between different network node devices can be synchronized.
  • the physical time deviation E can be obtained in advance before the adjustment phase. In each adjustment cycle, the logical time is obtained based on the physical clock signal and the physical time deviation E, which can prevent the logical time from flowing backwards.
  • the physical clock signal may be generated based on Time Average Frequency (TAF).
  • TAF Time Average Frequency
  • FIG. 4 shows a schematic diagram of the principle of time average frequency according to some embodiments of the present disclosure.
  • two clock signals of different periods (the first period T A and the second period T B ) can be used to synthesize the required physical clock signal.
  • the reference clock signal includes K (K is an integer greater than 1) reference pulses with uniform phase intervals, and the time span (for example, phase difference) between any two adjacent reference pulses.
  • the first period and the second period T A T B can be represented by the following formula (1) and formula (2). Among them, I is the integer part of the frequency control word F, and r is the decimal part of the frequency control word F.
  • Using the first period and the second period T A T B, can be generated by a staggered manner comprises two different periods (of different frequencies) physical clock signal.
  • the average period of the generated physical clock signal is T TAF , and the average frequency f TAF is shown in the following formula (3).
  • f0 is the frequency of the reference pulse. Changing the frequency control word F, the generated clock frequency f TAF of the physical clock signal can complete the frequency switching after two cycles.
  • FIG. 5 shows another schematic diagram of the time synchronization method in some embodiments of the present disclosure. As shown in FIG. 5, in some embodiments, the time synchronization method further includes steps S101 to S103 performed before the adjustment phase. .
  • Step S101 Determine the target value of the clock slope of the physical clock signal in each adjustment period.
  • the target value of the clock slope of the physical clock signal in each adjustment period is determined according to the clock frequency deviation coefficient x of the physical clock signal in the initial stage.
  • the clock frequency deviation coefficient x can be obtained in advance through testing.
  • the target value of the target value S 1 of the clock slope of the physical clock signal of the first adjustment period is determined according to the following formula (4).
  • x is the clock frequency deviation coefficient of the physical clock signal in the initial stage acquired in advance
  • S n-1 is the target value of the clock slope of the physical clock signal in the n-1 th adjustment cycle
  • n is an integer
  • 1 ⁇ n ⁇ N is the target value of the clock slope of the physical clock signal in the n-1 th adjustment cycle
  • Step S102 For each adjustment period, determine the frequency control word corresponding to the adjustment period according to the target value of the clock slope of the physical clock signal in the adjustment period and the difference between the reference time corresponding to the initial time and the end time of the adjustment period.
  • the initial time and end time of the adjustment period are determined according to the target value of the clock slope of the physical clock signal in the adjustment period, and the difference between the reference time corresponding to the initial time and the end time of the adjustment period.
  • the difference in physical time corresponds to the difference in physical time; and according to the difference in physical time corresponding to the initial time and end time of the adjustment cycle, determine the target value of the frequency of the physical clock signal in the adjustment cycle, and then according to the target value of the frequency of the physical clock signal Determine the frequency control word.
  • the frequency control word can be determined according to the relationship between the frequency of the physical clock signal and the frequency control word (see the above formula (3)).
  • Step S103 Determine the physical time deviation.
  • the reference time T ref M ⁇ t ⁇ (N+1)
  • M is the number of clock cycles of the physical clock signal in the adjustment cycle, that is, the total number of clock cycles of the physical clock signal
  • M is the number of clock cycles of the physical clock signal in the adjustment cycle, that is, the total number of clock cycles of the physical clock signal
  • M is the number of clock cycles of the physical clock signal in the adjustment cycle, that is, the total number of clock cycles of the physical clock signal.
  • M 1000
  • ⁇ t is the standard clock period.
  • the standard clock cycle refers to the clock cycle when the physical clock signal has no frequency drift, that is, the clock cycle of the reference clock signal.
  • the physical time T phy generated from the physical clock signal is calculated according to the following formula (6).
  • the physical time deviation E is calculated according to the following formula (7).
  • the physical time deviation E is calculated according to the following formula (8).
  • formula (8) is obtained after simplifying the above formula (7). Although the calculation rules of the two formulas are different, the calculation results are basically the same. The simplified process of formula (7) is introduced below.
  • FIG. 6 shows a schematic diagram of a method for converting logic time in each adjustment period according to some embodiments of the present disclosure. As shown in FIG. 6, in each adjustment period, at least a physical clock signal and a physical time deviation E are converted into logic time. The time steps include step S111 and step S112.
  • Step S111 Determine a first logic clock period T l_1 , and the first logic clock period T l_1 is determined according to the following formula (9).
  • N is the total number of synchronization cycles
  • ⁇ t is the standard clock cycle
  • Step S112 Convert the logical time according to the physical clock signal and the first logical clock period.
  • T l_1 is increased on the basis of the current logical time.
  • FIG. 7 shows another schematic diagram of a time synchronization method according to some embodiments of the present disclosure.
  • the time synchronization method includes in addition to the above-mentioned step S110, further includes a step S120: after the adjustment phase During the duration of the period, the physical clock signal is generated according to the frequency control word corresponding to the Nth adjustment period; and the logical time is converted according to the physical clock signal of the duration and the second logical clock period, wherein the second logical clock period It is equal to the standard clock period ⁇ t.
  • the second logical clock period is added on the basis of the current logical time.
  • the embodiment of the present disclosure also provides a time synchronization device, which is used in a network node device and used to execute the time synchronization method provided in the above-mentioned embodiment of the present disclosure.
  • Fig. 8 shows a schematic block diagram of a time synchronization apparatus according to some embodiments of the present disclosure. As shown in FIG. 8, the time synchronization device includes: a physical clock signal generation unit 10 and a logical time conversion unit 20.
  • the physical clock signal generating unit 10 is configured to generate a physical clock signal according to at least a pre-acquired frequency control word corresponding to the adjustment period in each adjustment period of the adjustment phase.
  • the adjustment phase includes N adjustment cycles, and N is an integer greater than one.
  • the physical clock signal generated in each adjustment period has a clock slope, and the clock slope of the physical clock signal of N adjustment periods is gradually close to 1.
  • the clock slope is based on the physical time generated by the physical clock signal and the reference time. The slope of the relationship curve.
  • the physical clock signal generating unit 10 is configured to generate the physical clock signal according to the frequency control word F and the reference clock signal.
  • the reference clock signal may specifically include K reference pulses at equal intervals, and the time span (for example, phase difference) between two adjacent reference pulses is the reference time unit.
  • the pulse frequency of the reference clock signal is fixed, when the frequency control word changes, the frequency (and period) of the physical clock signal generated by the physical clock signal generating unit 10 also changes accordingly.
  • FIG. 9 shows another schematic block diagram of a time synchronization device according to some embodiments of the present disclosure.
  • the time synchronization device may further include a reference clock signal generating unit 30, which is It is configured to generate a reference clock signal, the reference clock signal including K (K is an integer greater than 1) pulses with evenly spaced phases.
  • the reference clock signal generating unit 30 may be a free-running oscillator.
  • the physical clock signal generation can be generated based on Time Average Frequency (TAF).
  • the physical clock signal generation unit 10 adopts direct periodic synthesis based on Time Average Frequency (TAF).
  • Period Synthesis (TAF-DPS) circuit architecture time average frequency direct period synthesizer.
  • FIG. 10 shows a circuit diagram of a time average frequency direct period synthesizer according to some embodiments of the present disclosure.
  • the time average frequency direct period synthesizer 100 may include a first input module, a second input module 1030, and Output module 1040.
  • the first input module includes a first logic control circuit 1010 and a second logic control circuit 1020.
  • the first logic control circuit 1010 includes a first adder 1011, a first register 1012, and a second register 1013.
  • the second logic control circuit 1020 may include a second adder 1021, a third register 1022, and a fourth register 1023.
  • the second input module 1030 includes a first K ⁇ 1 multiplexer 1031, a second K ⁇ 1 multiplexer 1032, and a 2 ⁇ 1 multiplexer 1033.
  • Each of the first K ⁇ 1 multiplexer 1031 and the second K ⁇ 1 multiplexer 1032 includes a plurality of input terminals, a control input terminal, and an output terminal.
  • the multiple input ends of the first K ⁇ 1 multiplexer 1031 and the second K ⁇ 1 multiplexer 1032 are respectively used to receive K pulses with uniform phase intervals output by the reference clock signal generating unit 30.
  • the 2 ⁇ 1 multiplexer 1033 includes a control input terminal, an output terminal, a first input terminal for receiving the output of the first K ⁇ 1 multiplexer 1031, and a second K ⁇ 1 multiplexer for receiving the output.
  • the second input terminal of the output of the user 1032 may be the reference time unit ⁇ .
  • the output module 1040 includes a trigger circuit.
  • the trigger circuit is used to generate pulse trains.
  • the trigger circuit includes a D flip-flop 1041, a first inverter 1042, and a second inverter 1043.
  • the D flip-flop 1041 includes a data input terminal, a clock input terminal for receiving the output from the output terminal of the 2 ⁇ 1 multiplexer 1033, and an output terminal for outputting the first clock signal CLK1.
  • the first inverter 1042 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting a signal to the data input terminal of the D flip-flop 1041.
  • the second inverter 1043 includes an input terminal for receiving the first clock signal CLK1 and an output terminal for outputting the second clock signal CLK2.
  • the first clock signal CLK1 is output to the control input terminal of the 2 ⁇ 1 multiplexer 1033, and the output terminal of the first inverter 1042 is connected to the data input terminal of the D flip-flop 1041.
  • the first adder 1011 may add the frequency control word F and the most significant bits stored in the first register 1012, and then save the result of the addition to the first at the rising edge of the second clock signal CLK2.
  • the first adder 1011 may add the frequency control word F and all the information stored in the first register 1012, and then save the result of the addition to the first register 1012 at the rising edge of the second clock signal CLK2 middle.
  • the most significant bit stored in the first register 1012 will be stored in the second register 1013 and used as the selection signal of the first K ⁇ 1 multiplexer 1031
  • One pulse is selected from the K pulses as the output signal of the first K ⁇ 1 multiplexer 1031.
  • the second adder 1021 may add the frequency control word F/2 and the most significant bit stored in the first register 1012, and then save the addition result in the third register 1022 at the rising edge of the second clock signal CLK2 .
  • the information stored in the third register 1022 will be stored in the fourth register 1023 and used as the selection signal of the second K ⁇ 1 multiplexer 1023 for slave K
  • One of the pulses is selected as the output signal of the second K ⁇ 1 multiplexer 1023.
  • the 2 ⁇ 1 multiplexer 1033 can select the output signal from the first K ⁇ 1 multiplexer 1031 and the second K ⁇ 1 multiplexer 1032 at the rising edge of the first clock signal CLK1 One of the output signals is used as the output signal of the 2 ⁇ 1 multiplexer 1033 and used as the input clock signal of the D flip-flop 1041.
  • one of the output terminal of the D flip-flop 1041 and the output terminal of the second inverter 1043 can be used as the output of the time average frequency direct periodic synthesizer 100.
  • the selection signal output by the second register 1013 can be used to select the falling edge of the synthesized clock signal generated by the time average frequency direct cycle synthesizer 100
  • the selection signal output by the fourth register 1023 can be used to select the time average frequency direct cycle
  • the signal fed back to the first adder 1011 by the first register 1012 can be used to control the period switching of the synthesized clock generated by the time average frequency direct cycle synthesizer 100.
  • the logical time conversion unit 20 is configured to convert the logical time at least according to the received physical clock signal and the physical time deviation E in each adjustment period; the physical time deviation E is: the Nth adjustment period The time difference between the physical time corresponding to the physical clock signal at the end of the Nth adjustment cycle and the reference time.
  • the logical time conversion unit 20 is specifically configured to determine the first logical clock period T l_1 in each adjustment period, and convert the logical time according to the physical clock signal and the first logical clock period, where the first The logic clock period T l_1 satisfies: Among them, ⁇ t is the standard clock cycle. For example, in the adjustment phase, every time the logical time conversion unit 20 receives a valid edge of the physical clock signal, the first logical clock period is added to the current logical time.
  • the physical clock signal generating unit 10 is further configured to generate the physical clock signal according to the frequency control word corresponding to the Nth adjustment period in the continuous phase after the adjustment phase.
  • the logic time conversion unit 20 is also configured to convert the logic time according to the physical clock signal and the second logic clock period in the sustain phase during the sustaining phase, wherein the second logic clock period is equal to the standard clock period. For example, in the continuation phase, every time the logical time conversion unit 20 receives a valid edge of the physical clock signal, the second logical clock period is added to the current logical time.
  • FIG. 11 shows another schematic block diagram of a time synchronization device according to some embodiments of the present disclosure.
  • the time synchronization device further includes: a control word determining unit 40.
  • the control word determining unit 40 is configured to determine the target value of the clock slope of the physical clock signal in each adjustment period before the adjustment phase; and according to the target value of the clock slope of the physical clock signal in the adjustment period, the initial value of the adjustment period The difference between the reference time corresponding to the time and the end time respectively determines the frequency control word corresponding to the adjustment period.
  • the time synchronization device further includes: a first time deviation determining unit 50, the first time deviation determining unit 50 is configured to determine the physical time deviation E according to the above formula (7) before the adjustment phase.
  • FIG. 12 shows another schematic block diagram of a time synchronization device according to some embodiments of the present disclosure.
  • the time synchronization device includes the aforementioned physical clock signal generation unit 10, a logical time conversion unit 20, and a control word determination unit.
  • the unit 40 further includes: a second time deviation determining unit 50, which is configured to determine the physical time deviation E according to the above formula (8) before the adjustment phase.
  • the embodiment of the present disclosure also provides a network node device, which includes the above-mentioned time synchronization device provided by the embodiment of the present disclosure.
  • the network node device of the embodiment of the present disclosure can generate accurate logical time through the above-mentioned time synchronization method, thereby improving the time synchronization of multiple network node devices.
  • simulations are also performed on the effect of network time synchronization in different situations.
  • the clock frequency deviation coefficient of each network node device indicates the degree of temperature drift and aging drift of the physical clock signal generating unit 10 of the network node.
  • Figure 13 shows the time offset curve of ten network node devices in the network when they are not time synchronized.
  • the horizontal axis represents the real time (the unit is the above-mentioned preset time unit), and the vertical axis represents the logical time and reference.
  • the time difference of time (the unit is the above-mentioned preset time unit), and the ten curves respectively represent the time offset curves of ten network nodes. It can be seen from Figure 13 that at the initial moment, the logical time of each network node device is the same.
  • Figure 14 shows the synchronization error curve of the network time without time synchronization, where the vertical axis represents the synchronization error of the network time, and the synchronization error of the network time is: the logical time of every two network node devices in the network The largest difference in the difference; the horizontal axis represents the real time. The larger the synchronization error, the worse the effect of network time synchronization. It can be seen from Figure 14 that as time accumulates, the synchronization error of the network time gradually increases.
  • each network node device uses the time synchronization method in the comparative example to synchronize time.
  • the time synchronization method in the comparative example is: time synchronization is performed on ten network node devices at regular intervals, and each time is synchronized.
  • Figure 15 shows the time offset curve of each network node device in the case of time synchronization according to the time synchronization method in the comparative example;
  • Figure 16 shows the network in the case of time synchronization according to the time synchronization method in the comparative example Time synchronization error curve.
  • the synchronization error of the network time can be controlled within a certain range.
  • the logical time of each network node device will be again There is a difference.
  • directly correcting the logical time of the network node device to the reference time may cause the logical time of the network node device to have a negative step.
  • the logical time of a network node device is 00:43 (that is, 0 minutes and 43 seconds).
  • the reference time is 00:42, if the logical time is corrected to 00:42, from the time flow point of view, the network node device has a time reverse, which is very unfavorable to the system stability of the network node device.
  • each network node device uses the time synchronization method in another comparative example for time synchronization.
  • the time synchronization method in the other comparative example is: adjust each network node device in each adjustment period of the adjustment phase The frequency of the physical clock signal, so that for any network node device, from the first adjustment cycle to the Nth adjustment cycle, the clock slope of the physical clock signal gradually approaches 1, and the logical time is converted according to the physical clock signal.
  • Figure 17 shows the time offset curve of each network node device in the case of time synchronization according to the time synchronization method in another comparative example
  • Figure 18 shows time synchronization according to the time synchronization method in another comparative example The synchronization error curve of the network time in the case of. It can be seen from Figure 17 and Figure 18 that after multiple adjustment cycles, the deviation between the logical time of each network node device and the reference time remains stable, and the synchronization error of the network time remains at a stable deviation value.
  • each network node device uses the time synchronization method shown in Figure 7 for time synchronization
  • Figure 19 shows the time of each network node device in the case of time synchronization according to the time synchronization method shown in Figure 7 Offset curve
  • Figure 20 shows the synchronization error curve of the network time in the case of time synchronization according to the time synchronization method shown in Figure 7, where the adjustment phase includes 10 adjustment cycles, and the time on the horizontal axis is 10 o'clock, enter In the first adjustment cycle, when the horizontal axis time is 110, the tenth adjustment cycle ends. It can be seen from FIG. 19 and FIG.
  • the logical time of each network node device can be basically consistent with the reference time after the 10th adjustment period.
  • the synchronization error of the entire network is basically zero, which is only affected by random noise.
  • the logical time converted by the network node device is more accurate, so that the time synchronization of each network node device in the network is higher, and the security and reliability of the network are fully guaranteed.

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Abstract

本公开实施例提供一种时间同步方法，包括：调节阶段，所述调节阶段包括N个调节周期，N为大于1的整数；在每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号，并至少根据所述物理时钟信号和物理时间偏差转换出逻辑时间；在每个调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值，N个调节周期的物理时钟信号的时钟斜率的目标值逐渐接近于1；所述时钟斜率为基于所述物理时钟信号生成的物理时间与参考时间的关系曲线的斜率；所述物理时间偏差为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。本公开实施例还提供一种时间同步装置和网络节点设备。

Description

时间同步方法及装置、网络节点设备 技术领域
本公开涉及通信网络技术领域，具体涉及时间同步方法及装置、网络节点设备。
背景技术
随着万物联网(Internet of everything)的发展，现代电子系统由传统的有线通信向无线通信演变。在电信网络、计算机网络或其他类型电子设备的网络的架构设计和实现中，时钟同步都是一个至关重要的组成。
发明内容
本公开实施例提出了一种时间同步方法及装置、网络节点设备，以使网络节点设备的逻辑时间更准确，从而使不同网络节点设备的时间更加同步。
第一方面，本公开实施例提供一种时间同步方法，包括：调节阶段，所述调节阶段包括N个调节周期，N为大于1的整数；
在每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号，并至少根据所述物理时钟信号和物理时间偏差转换出逻辑时间；
其中，在每个所述调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值，N个所述调节周期的物理时钟信号的时钟斜率的目标值逐渐接近于1；其中，所述时钟斜率为基于所述物理时钟信号生成的物理时间与参考时间的关系曲线的斜率；所述物理时间偏差为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。
在一些实施例中，所述时间同步方法还包括在所述调节阶段之前进行的：
确定每个所述调节周期中的物理时钟信号的时钟斜率的目标值；
对于每个所述调节周期，根据所述调节周期中的物理时钟信号的时钟斜率的目标值、所述调节周期的初始时刻和结束时刻分别对应的参考时间的差值，确定所述调节周期对应的频率控制字。
在一些实施例中，第一个所述调节周期的物理时钟信号的时钟斜率的目标值S 1根据以下公式确定：
S 1＝S 0(1-x)
其中，x为预先获取的、初始阶段的物理时钟信号的时钟频率偏差系数；S 0为在所述初始阶段，根据初始的频率控制字生成的物理时钟信号的时钟斜率的值，S 0＝1+x；
第n个所述调节周期的物理时钟信号的时钟斜率的目标值S n根据以下公式确定：
Figure PCTCN2020072979-appb-000001
其中，S n-1为在第n-1个所述调节周期的物理时钟信号的时钟斜率的目标值，n为整数，且1<n≤N。
在一些实施例中，所述时间同步方法还包括：在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
Figure PCTCN2020072979-appb-000002
其中，Δt为标准时钟周期，M为单个所述调节周期中的物理时钟信号的时钟周期的个数。
在一些实施例中，所述时间同步方法还包括：在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
Figure PCTCN2020072979-appb-000003
其中，Δt为标准时钟周期，M为单个所述调节周期中的物理时钟信号的时钟周期的个数。
在一些实施例中，所述至少根据所述物理时钟信号和物理时间偏差转换出逻辑时间，包括：
根据以下公式确定第一逻辑时钟周期T l_1：
Figure PCTCN2020072979-appb-000004
其中，Δt为标准时钟周期，E为所述物理时间偏差；
根据所述物理时钟信号和所述第一逻辑时钟周期转换出逻辑时间。
在一些实施例中，所述时间同步方法还包括在所述调节阶段之后的持续阶段进行的：
根据第N个调节周期对应的频率控制字生成物理时钟信号；
根据所述持续阶段的物理时钟信号和第二逻辑时钟周期转换出逻辑时间，其中，所述第二逻辑时钟周期与标准时钟周期相等。
在一些实施例中，所述至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号，包括：
根据基准时钟信号和与所述调节周期对应的频率控制字生成物理时钟信号。
第二方面，本公开实施例还提供一种时间同步装置，包括：
物理时钟信号生成单元，被配置为在调节阶段的每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号；所述调节阶段包括N个所述调节周期，N为大于1的整数；其中，在每个所述调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值，N个所述调节周期的物理时钟信号的时钟斜率的目标值逐渐接近于1；其中，所述时钟斜率为基于所述物理时钟信号生成的物理时间与参考时间的关系曲线的斜率；
逻辑时间转换单元，被配置为在每个所述调节周期，至少根据接收到的物理时钟信号和物理时间偏差转换出逻辑时间；所述物理时间偏差为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。
在一些实施例中，所述时间同步装置还包括：
控制字确定单元，被配置为在所述调节阶段之前，确定每个所述调节周期中的物理时钟信号的时钟斜率的目标值；并根据所述调节周期中的物理时钟信号的时钟斜率的目标值、所述调节周期的初始时刻和结束时刻分别对应的参考时间之差，确定所述调节周期对应的频率控制字。
在一些实施例中，第一个所述调节周期的物理时钟信号的时钟斜率的目标值S 1根据以下公式确定：
S 1＝S 0(1-x)
其中，x为预先获取的、初始阶段的物理时钟信号的时钟频率偏差系数；S 0为在所述初始阶段，根据初始的频率控制字生成的物理时钟信号的时钟斜率的值，S 0＝1+x；
第n个所述调节周期的物理时钟信号的时钟斜率的目标值S n根据以下公式确定：
Figure PCTCN2020072979-appb-000005
其中，S n-1为在第n-1个所述调节周期的物理时钟信号的时钟斜率的目标值，n为整数，且1<n≤N。
在一些实施例中，所述时间同步装置还包括：第一时间偏差确定单元，被配置为在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
Figure PCTCN2020072979-appb-000006
其中，Δt为标准时钟周期，M为所述调节周期中标准时钟周期的个数。
在一些实施例中，所述时间同步装置还包括：第二时间偏差确定单元，被配置为在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
Figure PCTCN2020072979-appb-000007
其中，Δt为标准时钟周期，M为所述调节周期中标准时钟周期的个数。
在一些实施例中，所述逻辑时间转换单元具体被配置为，在每个所述调节周期，根据以下公式确定第一逻辑时钟周期T l_1，并根据所述物理时钟信号和所述第一逻辑时钟周期转换出逻辑时间：
Figure PCTCN2020072979-appb-000008
其中，Δt为标准时钟周期，E为所述物理时间偏差。
在一些实施例中，所述物理时钟信号生成单元还被配置为，在所述调节阶段之后的持续阶段，根据第N个调节周期对应的频率控制字生成物理时钟信号；
所述逻辑时间转换单元还被配置为，在所述持续阶段，根据所述持续阶段的物理时钟信号和第二逻辑时钟周期转换出逻辑时间，其中，所述第二逻辑时钟周期与标准时钟周期相等。
在一些实施例中，所述物理时钟信号生成单元具体被配置为，根据基准时钟信号和与所述调节周期对应的频率控制字生成物理时钟信号。
在一些实施例中，所述物理时钟生成单元包括时间平均频率直接周期合成器。
第三方面，本公开实施例还提供一种网络节点设备，包括上述的时间同步装置。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1示出了准同步架构的示意图。
图2示出了主从架构的示意图。
图3示出了根据本公开的一些实施例的时间同步方法的示意图。
图4示出了根据本公开的一些实施例的时间平均频率的原理示意图。
图5示出了根据本公开的一些实施例中的时间同步方法的另一示意图。
图6示出了根据本公开一些实施例中在每个调节周期转换出逻辑时间的方法示意图。
图7示出了根据本公开的一些实施例中的时间同步方法的另一示意图。
图8示出了根据本公开的一些实施例的时间同步装置的示意性框图。
图9示出了根据本公开的一些实施例的时间同步装置的另一示意性框图。
图10示出了根据本公开的一些实施例的时间平均频率直接周期合成器的电路图。
图11示出了根据本公开的一些实施例的时间同步装置的另一示意性框图。
图12示出了根据本公开的一些实施例的时间同步装置的另一示意性框图。
图13示出了网络中的十个网络节点设备在未进行时间同步时的时间偏移曲线。
图14示出了在未进行时间同步的情况下网络时间的同步误差曲线。
图15示出了根据对比例中的时间同步方法进行时间同步的情况下每个网络节点设备的时间偏移曲线。
图16示出了根据对比例中的时间同步方法进行时间同步的情况下网络时间的同步误差曲线。
图17示出了根据另一对比例中的时间同步方法进行时间同步的情况下每个网络节点设备的时间偏移曲线。
图18示出了根据另一对比例中的时间同步方法进行时间同步的情况下网络时间的同步误差曲线。
图19示出了根据图7所示的时间同步方法进行时间同步的情况下每个网络节点设备的时间偏移曲线。
图20示出了根据图7所示的时间同步方法进行时间同步的情况下网络时间的同步误差曲线。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
这里用于描述本公开的实施例的术语并非旨在限制和/或限定本公开的范围。例如，除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。应该理解的是，本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。除非上下文另外清楚地指出，否则单数形式“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。
在过去的几十年中，网络架构从同步时分复用模式(time division multiplexing，TDM)演变为异步包交换模式。在TDM系统中，在各个网络节点设备之间存在一个物理链路实现频率传输。在异步包交换 系统中，传输频率的物理链路已经不复存在，所有的数据和时间信息都通过包来交换，从而增加了时间同步的难度。
网络中的网络节点设备在处理本地事务或与其他网络节点设备进行通信时，均是基于本地设备的逻辑时间来进行通信的。其中，本地设备的逻辑时间(Logical Time)基于物理时钟(Physicl Clock)信号生成。具体地，网络节点设备具有物理时钟信号生成单元，该物理时钟信号生成单元为一硬件设备，其能够生成物理时钟信号。根据该物理时钟信号可以生成物理时间(Physical Time)，例如，t p＝m·T p，其中，T p为物理时钟信号的时钟周期，m为物理时钟信号生成单元当前产生的时钟周期的个数或上升沿的个数。物理时间可以描述为：物理时钟信号生成单元生成的物理时钟信号的时钟周期每增加1，物理时间就增加T p，例如，当物理时钟信号生成单元还未开始生成物理时钟信号时，物理时间为0；当物理时钟信号生成单元生成的物理时钟信号中的时钟周期为1时，物理时间为T p；当物理时钟信号达到两个时钟周期时，物理时间为2·T p；以此类推。根据预设的转换规则可以将每个时钟周期对应的物理时间转换为逻辑时间，例如，T p为0.01秒，当物理时钟信号中的时钟周期为1(或者，产生第1个上升沿)时，逻辑时间为00点00分0.01秒；当物理时钟信号的时钟周期为2(或者，产生第2个上升沿)时，逻辑时间为00点00分0.02秒，以此类推，当物理时钟信号的时钟周期为6000(或者，产生第6000个上升沿)时，逻辑时间为00时01分00秒。
在通信网络中，每个网络节点设备的物理时钟信号生成单元的物理性质(例如，工艺参数、温度漂移参数、老化系数、压力漂移系数等)可能会出现差异，从而引起不同网络节点设备的逻辑时间出现差异，即，时间不同步。网络时间同步的架构大致分为两类，分别是准同步架构(Plesiochronous)和主从架构(Master-Slave)，图1示出了准同步架构的示意图，图2示出了主从架构的示意图。如图1所示，准同步架构中的每个网络节点设备1具有独立的物理时钟信号生成单元，每个网络节点设备1的物理时钟信号的时钟频率都设置为相同值， 但是各个网络节点设备1的物理时钟生成信号单元的物理性质不可能完全一致，而由于不同的老化系数、温度漂移系数、压力漂移系数、工艺误差等都会引起物理时间或者逻辑时间的偏移。因此，这种架构下网络时间同步的精度会随着工作时间的增长而降低。如图2所示，主从架构中的网络节点设备分为主节点设备1a和从节点设备1b，每个从节点设备1b都接收主节点设备1a发送的时间信息。在一具体示例中，每隔一段时间，将主节点设备1a的时间直接赋予给从节点设备1b，以实现从节点设备1b与主节点设备1a的时间同步。但是，该同步方法具有一定的风险，例如，一个从节点设备1b的时间信息是00:53(即，0分53秒)，而主节点设备1a发过来的时间信息是00:52，那么，从节点设备1b将时间同步为00:52时，对于从节点设备1b而言相当于出现时间倒流，这对网络节点设备的系统稳定性非常不利。
为了实现网络时间同步，本公开实施例提供一种时间同步方法，该时间同步方法可以由网络节点设备的时间同步装置来执行。本公开实施例中的时间同步方法包括：调节阶段，该调节阶段包括N个调节周期，N为大于1的整数，例如，N＝10，或者N＝20，或者N＝30等等。图3示出了根据本公开的一些实施例的时间同步方法的示意图，如图3所示，本公开实施例中的时间同步方法包括：步骤S110、在每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号，并至少根据物理时钟信号和物理时间偏差E转换出逻辑时间。
在一些实施例中，物理时钟信号可以由物理时钟信号生成单元来执行，该物理时钟信号生成单元具体可以根据频率控制字和基准时钟信号生成物理时钟信号。当基准时钟信号的时钟频率固定时，对于不同的频率控制字，物理时钟信号生成单元所生成的物理时钟信号的频率(和周期)也不同。
在本公开实施例中，在每个调节周期生成的物理时钟信号均具有时钟斜率，且每个所述调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值，N个调节周期的物理时钟信号的时钟斜率的目 标值逐渐接近于1。需要说明的是，时钟斜率为物理时间与参考时间的关系曲线的斜率。物理时间为基于物理时钟信号生成的时间。物理时间偏差E为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。参考时间为其他网络节点设备提供的时间，该参考时间可以根据其他网络节点设备的参考时钟信号生成。例如，当网络节点设备处于主从架构中时，参考时钟信号即为主节点设备的物理时钟信号，参考时间为主节点设备基于参考时钟信号生成的逻辑时间；当时间同步装置所在的网络节点设备处于准同步架构中时，参考时间可以为多个其他网络节点设备的逻辑时间的平均值。
假设参考时钟信号的时钟频率为f，参考时钟信号的时钟周期为1/f，则每经过一个时钟周期，参考时间增加1/f，参考时间与参考时钟信号的时钟周期的个数p之间的关系为：t＝p·1/f，即，参考时间t与时钟周期的个数p之间的关系曲线的斜率为1/f，对该斜率进行归一化处理后，得到参考时间t’＝p·1。在理想情况下，网络节点设备的物理时钟信号的时钟频率为f，而由于工艺误差、温度漂移等情况，会导致物理时钟信号实际的时钟频率达到f+Δf，物理时钟信号每经过一个时钟周期，则物理时间均增加1/(f+Δf)，因此，网络节点设备的物理时间为
Figure PCTCN2020072979-appb-000009
由于在计算参考时间时进行了归一化处理(即，参考时间除以1/f)，因此，对物理时间同样进行归一化处理后可得，归一化后的物理时间
Figure PCTCN2020072979-appb-000010
其中，
Figure PCTCN2020072979-appb-000011
x即为：在调节阶段之前的初始阶段，物理时钟信号的时钟频率偏差系数。可见，该时钟频率偏差系数x与Δf有关，且|x|<1。可以看出，在理想情况下，物理时钟信号的时钟频率与参考时钟信号的时钟频率相等，物理时钟信号的时钟斜率的值为1；而当物理时钟信号的时钟频率发生偏移时，在初始时刻，物理时钟信号的时钟斜率的值为1+x。在不进行任何修正的情况下，物理时间与参考时间之间的差异将会越来越大。
在本公开实施例中，N个调节周期的物理时钟信号的时钟斜率逐 渐接近于1，即，物理时间的增加速度逐渐接近于参考时间的增加速度，也即，物理时钟信号的时钟频率逐渐接近于参考时钟信号的时钟频率。当N取较大的值时，第N个调节周期的物理时钟信号的时钟斜率将基本接近于1，这里的“基本接近1”可以根据应用场景和协议来设定，例如，与1之间的差值小于10 -8，或者，与1之间的差值小于10 -10。因此，N个调节周期之后，继续根据第N个调节周期的频率控制字生成物理时钟信号时，物理时间与参考时间之间的差异将不再逐渐增大。但是，由于初始阶段的物理时钟信号的时钟斜率与1之间存在一定差距，因此，经过N个调节周期之后，虽然物理时钟信号的时钟斜率等于1，但是物理时钟信号对应的物理时间与参考时间仍有一定的时间差。而在本公开实施例中，在每个调节周期，逻辑时间是根据物理时钟信号和物理时间偏差E得到的，从而有利于在第N个调节阶段结束时，使得逻辑时间与参考时间之间不再存在偏差。在通信网络中，多个网络节点设备均采用本公开实施例的时间同步方法时，可以使不同网络节点设备的逻辑时间更准确，进而使得不同网络节点设备之间的时间同步。
需要说明的是，物理时间偏差E可以在调节阶段之前预先获得。在每个调节周期，逻辑时间是根据物理时钟信号和物理时间偏差E得到的，这样可以防止逻辑时间出现倒流。
在一些实施例中，可以基于时间平均频率(Time Average Frequency，TAF)来生成物理时钟信号，图4示出了根据本公开的一些实施例的时间平均频率的原理示意图。基于时间平均频率技术可以利用两种不同周期(分别为第一周期T A和第二周期T B)的时钟信号来合成所需要的物理时钟信号，如图4所示，对于基准时间单位Δ和频率控制字F＝I+r，可以获得两种时间周期：第一周期T A和第二周期T B。其中，基准时钟信号包括K(K为大于1的整数)个相位均匀间隔的基准脉冲，任意两个相邻的基准脉冲之间的时间跨度(例如，相位差)。第一周期T A和第二周期T B可以分别通过以下公式(1)和公式(2)表示。其中，I为频率控制字F的整数部分，r为频率控制字F的小数部 分。
T A＝I·Δ    (1)
T B＝(I+1)·Δ     (2)
利用第一周期T A和第二周期T B，通过交错的方式可以生成包括两种不同周期(不同的频率)的物理时钟信号。所生成的物理时钟信号的平均周期为T TAF，平均频率f TAF如下述公式(3)所示。
Figure PCTCN2020072979-appb-000012
其中，f0为基准脉冲的频率。改变频率控制字F，所生成的物理时钟信号的时钟频率f TAF即可在两个周期后完成频率切换。
图5示出了根据本公开的一些实施例中的时间同步方法的另一示意图，如图5所示，在一些实施例中，时间同步方法还包括在调节阶段之前进行的步骤S101至步骤S103。
步骤S101、确定每个所述调节周期中的物理时钟信号的时钟斜率的目标值。
在一些实施例中，根据初始阶段的物理时钟信号的时钟频率偏差系数x，确定每个调节周期中的物理时钟信号的时钟斜率的目标值。其中，时钟频率偏差系数x可以通过测试的方式预先获取。
例如，x为0.1，初始阶段的物理时钟信号的时钟斜率为1+0.1＝1.1；第一个调节周期的物理时钟信号的时钟斜率的目标值为1+0.09＝1.09；第二个调节周期的物理时钟信号的时钟斜率的目标值为1+0.08＝1.08，第三个调节周期的物理时钟信号的时钟斜率的目标值为1+0.07＝1.07，依次类推。
在一些实施例中，第一个所述调节周期的物理时钟信号的时钟斜率的目标值S 1的目标值根据以下公式(4)确定。
S 1＝S 0(1-x)    (4)
其中，x为预先获取的、初始阶段的物理时钟信号的时钟频率偏差系数；S 0为在所述初始阶段，根据初始的频率控制字生成的物理时钟 信号的时钟斜率的值，S 0＝1+x。
第二个调节周期的物理时钟信号的时钟斜率的目标值S 2＝S 1(1+x 2)＝1-x 4；第三个调节周期的物理时钟信号的时钟斜率的目标值S 3＝S 2(1+x 4)＝1-x 8；以此类推，第n个所述调节周期的物理时钟信号的时钟斜率的目标值S n根据以下公式(5)确定。
Figure PCTCN2020072979-appb-000013
其中，S n-1为在第n-1个调节周期的物理时钟信号的时钟斜率的目标值，n为整数，且1<n≤N。
由于x<1，
Figure PCTCN2020072979-appb-000014
接近0，因此，最后一个调节周期的物理时钟信号的时钟斜率的目标值S N接近1。并且，N取值越大，S N与1之间的差距越小。在一具体示例中，将N设置在10～15之间。例如，N＝10。
步骤S102、对于每个调节周期，根据调节周期中的物理时钟信号的时钟斜率的目标值、调节周期的初始时刻和结束时刻分别对应的参考时间的差值，确定调节周期对应的频率控制字。
例如，对于每个调节周期，根据调节周期中物理时钟信号的时钟斜率的目标值、调节周期的初始时刻的初始时刻和结束时刻分别对应的参考时间之差，确定调节周期的初始时刻和结束时刻分别对应的物理时间之差；并根据调节周期的初始时刻和结束时刻分别对应的物理时间之差，确定调节周期中的物理时钟信号的频率的目标值，进而根据物理时钟信号的频率的目标值确定频率控制字。可以理解的是，当物理时钟信号的频率的目标值确定之后，可以根据物理时钟信号的频率与频率控制字之间的关系(参见上述公式(3))确定频率控制字。
步骤S103、确定物理时间偏差。
在第N个调节周期的结束时刻，参考时间T ref＝M·Δt·(N+1)，M为调节周期中物理时钟信号的时钟周期的个数，即，物理时钟信号的时钟周期的总数每增加M个，则表示经过了一个调节周期。例如，M＝1000，Δt为标准时钟周期。标准时钟周期是指：物理时钟信号未发生频率漂移情况下的时钟周期，也即参考时钟信号的时钟周期。根据 物理时钟信号所生成的物理时间T phy根据以下公式(6)计算。
Figure PCTCN2020072979-appb-000015
在一些实施例中，物理时间偏差E根据以下公式(7)计算。
Figure PCTCN2020072979-appb-000016
在另一些实施例中，物理时间偏差E根据以下公式(8)进行计算。
Figure PCTCN2020072979-appb-000017
和公式(7)相比，公式(8)的计算过程更为简单，从而可以提高计算物理时间偏差E的效率。
需要说明的是，公式(8)是对上述公式(7)进行简化处理后得到的，虽然两个公式的计算规则不同，但是，计算结果是基本一致的。下面对公式(7)的简化处理过程进行介绍。
定义
Figure PCTCN2020072979-appb-000018
则E＝M·Δt·(x-S sq)。
已知
Figure PCTCN2020072979-appb-000019
令t＝2 n，并定义：
S i＝S t-x-S sq＝x 3+x 5+x 6+x 7+x 9+x 10+…+x t-1
＝x(x 2+x 4+x 8+…+x t)-x t+1+x 6+x 7+…+x t-1
≈x·S sq
则可以得到S t-x-S sq＝S i＝x·S sq，进而得到
Figure PCTCN2020072979-appb-000020
Figure PCTCN2020072979-appb-000021
因此，可以得到
Figure PCTCN2020072979-appb-000022
图6示出了根据本公开一些实施例中在每个调节周期转换出逻辑时间的方法示意图，如图6所示，在每个调节周期，至少根据物理时钟信号和物理时间偏差E转换出逻辑时间的步骤包括步骤S111和步骤S112。
步骤S111、确定第一逻辑时钟周期T l_1，该第一逻辑时钟周期T l_1根据以下公式(9)确定。
Figure PCTCN2020072979-appb-000023
其中，N为同步周期的总数，Δt为标准时钟周期。
步骤S112、根据物理时钟信号和第一逻辑时钟周期转换出逻辑时间。
例如，当前产生的物理时钟信号的时钟周期的总数每增加1个，则在当前的逻辑时间的基础上增加T l_1。
图7示出了根据本公开的一些实施例中的时间同步方法的另一示意图，如图7所示，该时间同步方法包括除了包括上述步骤S110之外，还包括步骤S120：在调节阶段之后的持续阶段，根据第N个调节周期对应的频率控制字生成物理时钟信号；并根据所述持续阶段的物理时钟信号和第二逻辑时钟周期转换出逻辑时间，其中，所述第二逻辑时钟周期与标准时钟周期Δt相等。
例如，物理时钟信号的有效沿(例如，上升沿)每增加一个，均在当前的逻辑时间的基础上增加第二逻辑时钟周期。
本公开实施例还提供一种时间同步装置，该时间同步装置用于网络节点设备中，并用于执行本公开的上述实施例提供的时间同步方法。图8示出了根据本公开的一些实施例的时间同步装置的示意性框图。如图8所示，时间同步装置包括：物理时钟信号生成单元10和逻辑时间转换单元20。
物理时钟信号生成单元10被配置为，在调节阶段的每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号。调节阶段包括N个调节周期，N为大于1的整数。其中，在每个调节周期生成的物理时钟信号均具有时钟斜率，N个调节周期的物理时钟信号的时钟斜率逐渐接近于1；其中，时钟斜率为基于物理时钟信号生成的物理时间与参考时间的关系曲线的斜率。
在一些实施例中，物理时钟信号生成单元10被配置为根据频率控制字F和基准时钟信号生成物理时钟信号。基准时钟信号具体可以包括K个等间隔的基准脉冲，相邻两个基准脉冲之间的时间跨度(例如，相位差)为基准时间单位。当基准时钟信号的脉冲频率固定的情况下， 当频率控制字发生改变时，物理时钟信号生成单元10所生成的物理时钟信号的频率(和周期)也相应发生改变。
图9示出了根据本公开的一些实施例的时间同步装置的另一示意性框图，如图9所示，在一些实施例中，时间同步装置还可以包括基准时钟信号生成单元30，其被配置为生成基准时钟信号，该基准时钟信号包括K(K为大于1的整数)个相位均匀间隔的脉冲。基准时钟信号生成单元30可以为自激振荡器。
如上文所述，物理时钟信号生成可以基于时间平均频率(Time Average Frequency，TAF)来生成，在一些实施例中，物理时钟信号生成单元10采用基于时间平均频率直接周期合成(Time Average Frequency-Direct Period Synthesis，TAF-DPS)电路架构的时间平均频率直接周期合成器。图10示出了根据本公开的一些实施例的时间平均频率直接周期合成器的电路图，如图10所示，时间平均频率直接周期合成器100可以包括第一输入模块、第二输入模块1030以及输出模块1040。
例如，如图10所示，第一输入模块包括第一逻辑控制电路1010和第二逻辑控制电路1020。第一逻辑控制电路1010包括第一加法器1011、第一寄存器1012和第二寄存器1013。第二逻辑控制电路1020可以包括第二加法器1021、第三寄存器1022和第四寄存器1023。
第二输入模块1030包括第一K→1多路复用器1031、第二K→1多路复用器1032和2→1多路复用器1033。第一K→1多路复用器1031和第二K→1多路复用器1032均包括多个输入端、控制输入端和输出端。第一K→1多路复用器1031和第二K→1多路复用器1032的多个输入端分别用于接收基准时钟信号生成单元30输出的K个相位均匀间隔的脉冲。2→1多路复用器1033包括控制输入端、输出端、用于接收第一K→1多路复用器1031的输出的第一输入端和用于接收第二K→1多路复用器1032的输出的第二输入端。例如，K个相位均匀间隔的脉冲中的任意两个相邻的脉冲之间的时间跨度(例如，相位差)可以为基准时间单位Δ。
例如，如图10所示，输出模块1040包括触发电路。触发电路用于生成脉冲串。触发电路包括D触发器1041、第一反相器1042和第二反相器1043。D触发器1041包括数据输入端、用于接收来自2→1多路复用器1033的输出端的输出的时钟输入端和用于输出第一时钟信号CLK1的输出端。第一反相器1042包括用于接收第一时钟信号CLK1的输入端和用于输出信号到D触发器1041的数据输入端的输出端。第二反相器1043包括用于接收第一时钟信号CLK1的输入端和用于输出第二时钟信号CLK2的输出端。
第一时钟信号CLK1被输出到2→1多路复用器1033的控制输入端，第一反相器1042的输出端连接到D触发器1041的数据输入端。
例如，第一加法器1011可以将频率控制字F和第一寄存器1012存储的最高有效位(most significant bits)相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器1012中；或者，第一加法器1011可以将频率控制字F和第一寄存器1012存储的所有信息相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第一寄存器1012中。在下一个第二时钟信号CLK2的上升沿时，第一寄存器1012存储的最高有效位将被存储到第二寄存器1013中，并作为第一K→1多路复用器1031的选择信号，用于从K个脉冲中选择一个脉冲作为第一K→1多路复用器1031的输出信号。
例如，第二加法器1021可以将频率控制字F/2和第一寄存器1012存储的最高有效位相加，然后在第二时钟信号CLK2的上升沿时将相加结果保存到第三寄存器1022中。在下一个第一时钟信号CLK1的上升沿时，第三寄存器1022存储的信息将被存储到第四寄存器1023中，并作为第二K→1多路复用器1023的选择信号，用于从K个脉冲中选择一个脉冲作为第二K→1多路复用器1023的输出信号。
2→1多路复用器1033可以在第一时钟信号CLK1的上升沿时，选择来自第一K→1多路复用器1031的输出信号和来自第二K→1多路复用器1032的输出信号中的一个作为2→1多路复用器1033的输出信号，以作为D触发器1041的输入时钟信号。
例如，D触发器1041的输出端和第二反相器1043的输出端之一可以作为时间平均频率直接周期合成器100的输出。
例如，第二寄存器1013输出的选择信号可以用于选择时间平均频率直接周期合成器100的生成的合成的时钟信号的下降沿，第四寄存器1023输出的选择信号可以用于选择时间平均频率直接周期合成器100的生成的合成的时钟信号的上升沿，第一寄存器1012反馈到第一加法器1011的信号可以用于控制时间平均频率直接周期合成器100的生成的合成的时钟的周期切换。
在一些实施例中，逻辑时间转换单元20被配置为，在每个调节周期，至少根据接收到的物理时钟信号和物理时间偏差E转换出逻辑时间；物理时间偏差E为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。
在一些实施例中，逻辑时间转换单元20具体被配置为，在每个调节周期确定第一逻辑时钟周期T l_1，并根据物理时钟信号和第一逻辑时钟周期转换出逻辑时间，其中，第一逻辑时钟周期T l_1满足：
Figure PCTCN2020072979-appb-000024
其中，Δt为标准时钟周期。例如，在调节阶段，逻辑时间转换单元20每接收到物理时钟信号的一个有效沿，则在当前逻辑时间的基础上增加第一逻辑时钟周期。
在一些实施例中，物理时钟信号生成单元10还被配置为，在调节阶段之后的持续阶段，根据第N个调节周期对应的频率控制字生成物理时钟信号。逻辑时间转换单元20还被配置为，在持续阶段，根据持续阶段的物理时钟信号和第二逻辑时钟周期转换出逻辑时间，其中，第二逻辑时钟周期与标准时钟周期相等。例如，在持续阶段，逻辑时间转换单元20每接收到物理时钟信号的一个有效沿，则在当前逻辑时间的基础上增加第二逻辑时钟周期。
图11示出了根据本公开的一些实施例的时间同步装置的另一示意性框图，如图11所示，在一些实施例中，时间同步装置还包括：控制字确定单元40。控制字确定单元40被配置为在调节阶段之前，确 定每个调节周期中的物理时钟信号的时钟斜率的目标值；并根据调节周期中的物理时钟信号的时钟斜率的目标值、调节周期的初始时刻和结束时刻分别对应的参考时间之差，确定调节周期对应的频率控制字。
在一些实施例中，第一个调节周期的物理时钟信号的时钟斜率的目标值S 1满足：S 1＝S 0(1-x)，其中，x为预先获取的、初始阶段的物理时钟信号的时钟频率偏差系数；S 0为在初始阶段，根据初始的频率控制字生成的物理时钟信号的时钟斜率的值，并且，S 0＝1+x。第二个调节周期的物理时钟信号的时钟斜率的目标值S 2＝S 1(1+x 2)＝1-x 4；第三个调节周期的物理时钟信号的时钟斜率的目标值S 3＝S 2(1+x 4)＝1-x 8；第n个调节周期的物理时钟信号的时钟斜率的目标值S n满足
Figure PCTCN2020072979-appb-000025
其中，S n-1为在第n-1个调节周期的物理时钟信号的时钟斜率的目标值，n为整数，且1<n≤N。
由于x<1，
Figure PCTCN2020072979-appb-000026
接近0，因此，最后一个调节周期的物理时钟信号的时钟斜率的目标值S N接近1。并且，N取值越大，S N与1之间的差距越小。在一具体示例中，将N设置在10～15之间。例如，N＝10。
如图11所示，时间同步装置还包括：第一时间偏差确定单元50，第一时间偏差确定单元50被配置为在调节阶段之前，根据上述公式(7)确定物理时间偏差E。
图12示出了根据本公开的一些实施例的时间同步装置的另一示意性框图，如图12所示，时间同步装置包括上述物理时钟信号生成单元10、逻辑时间转换单元20和控制字确定单元40，还包括：第二时间偏差确定单元50，第二时间偏差确定单元50被配置为在调节阶段之前，根据上述公式(8)确定物理时间偏差E。
本公开实施例还提供一种网络节点设备，其包括本公开实施例提供的上述时间同步装置。
本公开实施例的网络节点设备通过上述是时间同步方法能够产生准确的逻辑时间，进而使多个网络节点设备的时间同步性提高。
在本公开中，还对不同情况下的网络时间同步效果进行了模拟仿 真。其中，网络中设置有十个自由运转的网络节点设备，仿真模拟中的相关参数如下：标准时钟周期Δt＝0.01·t 0，t 0为预设时间单位，例如，该预设时间单位为1秒，或者为1毫秒。每个调节周期中的物理时钟信号的时钟周期的个数M＝1000，十个网络节点设备的时钟频率偏差系数分别为：±0.1，±0.08，±0.06，±0.04，±0.02。每个网络节点设备的时钟频率偏差系数指示网络节点的物理时钟信号生成单元10的温度漂移、老化漂移的程度。每个网络节点设备都对应有均值分布的随机噪声，用于模拟实际的环境变化、传输延迟等，随机噪声表示为：noise＝±0.02·Δt。
第一种情况，网络中的十个网络节点设备未进行时间同步。图13示出了网络中的十个网络节点设备在未进行时间同步时的时间偏移曲线，图13中横轴表示真实时间(单位为上述预设时间单位)，纵轴表示逻辑时间与参考时间的时间差(单位为上述预设时间单位)，十条曲线分别代表十个网络节点的时间偏移曲线。从图13可以看出，在初始时刻，每个网络节点设备的逻辑时间相同，随着时间的累积，不同网络节点设备的逻辑时间与参考时间之间会产生不同的时间差，从而造成不同网络节点设备的逻辑时间不同步。图14示出了在未进行时间同步的情况下网络时间的同步误差曲线，其中，纵轴表示网络时间的同步误差，网络时间的同步误差为：网络中每两个网络节点设备的逻辑时间的差值中的最大差值；横轴表示真实时间。同步误差越大，表示网络时间同步效果越差。从图14可以看出，随着时间的累积，网络时间的同步误差逐渐增加。
第二种情况，每个网络节点设备采用对比例中的时间同步方法进行时间同步，对比例中的时间同步方法为：每隔一段时间对十个网络节点设备进行一次时间同步，进行每次时间同步时，直接将每个网络节点设备当前的逻辑时间修正为当前的参考时间。图15示出了根据对比例中的时间同步方法进行时间同步的情况下每个网络节点设备的时间偏移曲线；图16示出了根据对比例中的时间同步方法进行时间同步的情况下网络时间的同步误差曲线。从图15和图16可以看出，通过 对比例中的时间同步方法，可以将网络时间的同步误差控制在一定范围内，但是，经过一次时间同步之后，各网络节点设备的逻辑时间将会再次出现差异。另外，将网络节点设备的逻辑时间直接修正为参考时间，则有可能导致网络节点设备的逻辑时间出现负步进，例如，某网络节点设备的逻辑时间是00:43(即，0分43秒)，参考时间为00:42，若将逻辑时间修正为00:42，则从时间流来看，该网络节点设备出现了时间倒流，这对网络节点设备的系统稳定性非常不利。
第三种情况，每个网络节点设备采用另一对比例中的时间同步方法进行时间同步，另一对比例中的时间同步方法为：在调节阶段的每个调节周期，调节每个网络节点设备的物理时钟信号的频率，以使对于任意一个网络节点设备而言，从第一个调节周期到第N个调节周期，物理时钟信号的时钟斜率逐渐接近于1，逻辑时间根据物理时钟信号转换得到。图17示出了根据另一对比例中的时间同步方法进行时间同步的情况下每个网络节点设备的时间偏移曲线；图18示出了根据另一对比例中的时间同步方法进行时间同步的情况下网络时间的同步误差曲线。从图17和图18可以看出，在经过多个调节周期后，各网络节点设备的逻辑时间与参考时间之间的偏差保持稳定，网络时间的同步误差保持在一稳定的偏差值。
第四种情况，每个网络节点设备采用图7所示的时间同步方法进行时间同步，图19示出了根据图7所示的时间同步方法进行时间同步的情况下每个网络节点设备的时间偏移曲线；图20示出了根据图7所示的时间同步方法进行时间同步的情况下网络时间的同步误差曲线，其中，调节阶段包括10个调节周期，横轴的时间为10时，进入第1个调节周期，横轴的时间为110时，第10个调节周期结束。从图19和图20可以看出，利用本公开实施例的时间同步方法，可以使得每个网络节点设备的逻辑时间在第10个调节周期之后与参考时间基本一致。整个网络的同步误差基本为0，仅受随机噪声的影响。
在本公开实施例中，在经过多个调节周期后，网络节点设备转换出的逻辑时间更准确，使得网络中各网络节点设备的时间同步性更高， 充分保证网络的安全性和可靠性。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种时间同步方法，包括：调节阶段，所述调节阶段包括N个调节周期，N为大于1的整数；
    在每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号，并至少根据所述物理时钟信号和物理时间偏差转换出逻辑时间；
    其中，在每个所述调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值，N个所述调节周期的物理时钟信号的时钟斜率的目标值逐渐接近于1；其中，所述时钟斜率为基于所述物理时钟信号生成的物理时间与参考时间的关系曲线的斜率；所述物理时间偏差为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。
  2. 根据权利要求1所述的时间同步方法，其中，所述时间同步方法还包括在所述调节阶段之前进行的：
    确定每个所述调节周期中的物理时钟信号的时钟斜率的目标值；
    对于每个所述调节周期，根据所述调节周期中的物理时钟信号的时钟斜率的目标值、所述调节周期的初始时刻和结束时刻分别对应的参考时间的差值，确定所述调节周期对应的频率控制字。
  3. 根据权利要求2所述的时间同步方法，其中，第一个所述调节周期的物理时钟信号的时钟斜率的目标值S 1根据以下公式确定：
    S 1＝S 0(1-x)
    其中，x为预先获取的、初始阶段的物理时钟信号的时钟频率偏差系数；S 0为在所述初始阶段，根据初始的频率控制字生成的物理时钟信号的时钟斜率的值，S 0＝1+x；
    第n个所述调节周期的物理时钟信号的时钟斜率的目标值S n根据以下公式确定：
    Figure PCTCN2020072979-appb-100001
    其中，S n-1为在第n-1个所述调节周期的物理时钟信号的时钟斜率的目标值，n为整数，且1<n≤N。
  4. 根据权利要求2所述的时间同步方法，其中，所述时间同步方法还包括：在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
    Figure PCTCN2020072979-appb-100002
    其中，Δt为标准时钟周期，M为单个所述调节周期中的物理时钟信号的时钟周期的个数。
  5. 根据权利要求2的时间同步方法，其中，所述时间同步方法还包括：在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
    Figure PCTCN2020072979-appb-100003
    其中，Δt为标准时钟周期，M为单个所述调节周期中的物理时钟信号的时钟周期的个数。
  6. 根据权利要求1至5中任意一项所述的时间同步方法，其中，所述至少根据所述物理时钟信号和物理时间偏差转换出逻辑时间，包括：
    根据以下公式确定第一逻辑时钟周期T l_1：
    Figure PCTCN2020072979-appb-100004
    其中，Δt为标准时钟周期，E为所述物理时间偏差；
    根据所述物理时钟信号和所述第一逻辑时钟周期转换出逻辑时间。
  7. 根据权利要求1至5中任意一项所述的时间同步方法，其中，所述时间同步方法还包括在所述调节阶段之后的持续阶段进行的：
    根据第N个调节周期对应的频率控制字生成物理时钟信号；
    根据所述持续阶段的物理时钟信号和第二逻辑时钟周期转换出逻辑时间，其中，所述第二逻辑时钟周期与标准时钟周期相等。
  8. 根据权利要求1至5中任意一项所述的方法，其中，所述至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号，包括：
    根据基准时钟信号和与所述调节周期对应的频率控制字生成物理时钟信号。
  9. 一种时间同步装置，包括：
    物理时钟信号生成单元，被配置为在调节阶段的每个调节周期，至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号；所述调节阶段包括N个所述调节周期，N为大于1的整数；其中，在每个所述调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值，N个所述调节周期的物理时钟信号的时钟斜率的目标值逐渐接近于1；其中，所述时钟斜率为基于所述物理时钟信号生成的物理时间与参考时间的关系曲线的斜率；
    逻辑时间转换单元，被配置为在每个所述调节周期，至少根据接收到的物理时钟信号和物理时间偏差转换出逻辑时间；所述物理时间偏差为：第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。
  10. 根据权利要求9所述的时间同步装置，其中，所述时间同步装置还包括：
    控制字确定单元，被配置为在所述调节阶段之前，确定每个所述调节周期中的物理时钟信号的时钟斜率的目标值；并根据所述调节周期中的物理时钟信号的时钟斜率的目标值、所述调节周期的初始时刻和结束时刻分别对应的参考时间之差，确定所述调节周期对应的频率控制字。
  11. 根据权利要求10所述的时间同步装置，其中，第一个所述调节周期的物理时钟信号的时钟斜率的目标值S 1根据以下公式确定：
    S 1＝S 0(1-x)
    其中，x为预先获取的、初始阶段的物理时钟信号的时钟频率偏差系数；S 0为在所述初始阶段，根据初始的频率控制字生成的物理时钟信号的时钟斜率的值，S 0＝1+x；
    第n个所述调节周期的物理时钟信号的时钟斜率的目标值S n根据以下公式确定：
    Figure PCTCN2020072979-appb-100005
    其中，S n-1为在第n-1个所述调节周期的物理时钟信号的时钟斜率的目标值，n为整数，且1<n≤N。
  12. 根据权利要求10所述的时间同步装置，其中，所述时间同步装置还包括：第一时间偏差确定单元，被配置为在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
    Figure PCTCN2020072979-appb-100006
    其中，Δt为标准时钟周期，M为单个所述调节周期中的物理时钟信号的时钟周期的个数。
  13. 根据权利要求10所述的时间同步装置，其中，所述时间同步装置还包括：第二时间偏差确定单元，被配置为在所述调节阶段之前，根据以下公式确定所述物理时间偏差E：
    Figure PCTCN2020072979-appb-100007
    其中，Δt为标准时钟周期，M为单个所述调节周期中的物理时钟信号的标准时钟周期的个数。
  14. 根据权利要求9至13中任意一项所述的时间同步装置，其中，所述逻辑时间转换单元具体被配置为，在每个所述调节周期，根据以下公式确定第一逻辑时钟周期T l_1，并根据所述物理时钟信号和所述第一逻辑时钟周期转换出逻辑时间：
    Figure PCTCN2020072979-appb-100008
    其中，Δt为标准时钟周期，E为所述物理时间偏差。
  15. 根据权利要求9至13中任意一项所述的时间同步装置，其中，所述物理时钟信号生成单元还被配置为，在所述调节阶段之后的持续阶段，根据第N个调节周期对应的频率控制字生成物理时钟信号；
    所述逻辑时间转换单元还被配置为，在所述持续阶段，根据所述持续阶段的物理时钟信号和第二逻辑时钟周期转换出逻辑时间，其中，所述第二逻辑时钟周期与标准时钟周期相等。
  16. 根据权利要求9至13中任意一项所述的时间同步装置，其中，所述物理时钟信号生成单元具体被配置为，根据基准时钟信号和与所述调节周期对应的频率控制字生成物理时钟信号。
  17. 根据权利要求16所述的时间同步装置，其中，所述物理时钟生成单元包括时间平均频率直接周期合成器。
  18. 一种网络节点设备，包括权利要求9至17中任意一项所述的 时间同步装置。
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