CN113498623A - 时间同步方法及装置、网络节点设备 - Google Patents
时间同步方法及装置、网络节点设备 Download PDFInfo
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- CN113498623A CN113498623A CN202080000051.8A CN202080000051A CN113498623A CN 113498623 A CN113498623 A CN 113498623A CN 202080000051 A CN202080000051 A CN 202080000051A CN 113498623 A CN113498623 A CN 113498623A
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 230000033228 biological regulation Effects 0.000 claims abstract description 46
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 230000000737 periodic effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 24
- 230000000052 comparative effect Effects 0.000 description 13
- 230000000630 rising effect Effects 0.000 description 12
- 230000001360 synchronised effect Effects 0.000 description 6
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 5
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- 230000003750 conditioning effect Effects 0.000 description 4
- 230000032683 aging Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010606 normalization Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 1
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Electric Clocks (AREA)
Abstract
本公开实施例提供一种时间同步方法,包括:调节阶段,所述调节阶段包括N个调节周期,N为大于1的整数;在每个调节周期,至少根据预先获取的与该调节周期对应的频率控制字生成物理时钟信号,并至少根据所述物理时钟信号和物理时间偏差转换出逻辑时间;在每个调节周期生成的物理时钟信号的时钟斜率均达到各自对应的目标值,N个调节周期的物理时钟信号的时钟斜率的目标值逐渐接近于1;所述时钟斜率为基于所述物理时钟信号生成的物理时间与参考时间的关系曲线的斜率;所述物理时间偏差为:第N个调节周期的物理时钟信号在第N个调节周期的结束时刻所对应的物理时间与参考时间之间的时间差。本公开实施例还提供一种时间同步装置和网络节点设备。
Description
PCT国内申请,说明书已公开。
Claims (18)
- PCT国内申请,权利要求书已公开。
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PCT/CN2020/072979 WO2021142828A1 (zh) | 2020-01-19 | 2020-01-19 | 时间同步方法及装置、网络节点设备 |
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CN113498623B CN113498623B (zh) | 2023-06-20 |
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US (1) | US11799578B2 (zh) |
EP (1) | EP4093101A4 (zh) |
JP (1) | JP7493581B2 (zh) |
CN (1) | CN113498623B (zh) |
WO (1) | WO2021142828A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114095166A (zh) * | 2021-11-23 | 2022-02-25 | 北京京东方技术开发有限公司 | 生成节点临时身份标识的方法、节点及系统 |
CN115276617A (zh) * | 2022-06-21 | 2022-11-01 | 上海芯问科技有限公司 | 时钟偏差调制电路、接口系统及电子设备 |
Families Citing this family (1)
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CN111446962B (zh) * | 2020-04-03 | 2023-12-12 | 京东方科技集团股份有限公司 | 时钟信号产生电路、时钟信号产生方法及电子设备 |
Citations (5)
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CN102752843A (zh) * | 2012-06-20 | 2012-10-24 | 中国科学院信息工程研究所 | 一种时间同步方法 |
CN105553598A (zh) * | 2016-01-10 | 2016-05-04 | 北京航空航天大学 | 一种基于m估计稳健回归的时间触发以太网时钟补偿方法 |
CN107300688A (zh) * | 2017-06-01 | 2017-10-27 | 中国电子科技集团公司第二十八研究所 | 一种多点定位系统中的时钟频率标校方法 |
CN107425851A (zh) * | 2017-08-09 | 2017-12-01 | 京东方科技集团股份有限公司 | 频率补偿器、电子设备和频率补偿方法 |
CN110581743A (zh) * | 2018-06-11 | 2019-12-17 | 京东方科技集团股份有限公司 | 电子设备、时间同步系统及时间同步方法 |
Family Cites Families (8)
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JP5556412B2 (ja) | 2010-06-17 | 2014-07-23 | 富士通株式会社 | タイミング同期装置、タイミング同期方法 |
CN101883420B (zh) | 2010-06-25 | 2012-12-12 | 中国科学院软件研究所 | 一种无线传感器网络时间同步方法 |
WO2013078105A1 (en) | 2011-11-22 | 2013-05-30 | Aclara Power-Line Systems Inc. | Metrology timekeeping systems and methods |
US10292103B2 (en) * | 2013-03-27 | 2019-05-14 | Qualcomm Incorporated | Systems and methods for synchronization within a neighborhood aware network |
US9178637B2 (en) * | 2013-12-09 | 2015-11-03 | Khalifa University of Science, Technology, and Research | Method and devices for synchronization using linear programming |
US9740235B1 (en) * | 2015-03-05 | 2017-08-22 | Liming Xiu | Circuits and methods of TAF-DPS based interface adapter for heterogeneously clocked Network-on-Chip system |
US10025344B2 (en) * | 2015-04-21 | 2018-07-17 | The United States Of America As Represented By The Administrator Of Nasa | Self-stabilizing distributed symmetric-fault tolerant synchronization protocol |
US10503534B1 (en) | 2016-09-09 | 2019-12-10 | Hewlett-Packard Development Company, L.P. | Adaptive clock scaling to optimize time-based operations within virtualized guest operating systems |
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2020
- 2020-01-19 CN CN202080000051.8A patent/CN113498623B/zh active Active
- 2020-01-19 WO PCT/CN2020/072979 patent/WO2021142828A1/zh active Application Filing
- 2020-01-19 EP EP20897615.9A patent/EP4093101A4/en active Pending
- 2020-01-19 JP JP2022504311A patent/JP7493581B2/ja active Active
- 2020-01-19 US US17/413,367 patent/US11799578B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102752843A (zh) * | 2012-06-20 | 2012-10-24 | 中国科学院信息工程研究所 | 一种时间同步方法 |
CN105553598A (zh) * | 2016-01-10 | 2016-05-04 | 北京航空航天大学 | 一种基于m估计稳健回归的时间触发以太网时钟补偿方法 |
CN107300688A (zh) * | 2017-06-01 | 2017-10-27 | 中国电子科技集团公司第二十八研究所 | 一种多点定位系统中的时钟频率标校方法 |
CN107425851A (zh) * | 2017-08-09 | 2017-12-01 | 京东方科技集团股份有限公司 | 频率补偿器、电子设备和频率补偿方法 |
CN110581743A (zh) * | 2018-06-11 | 2019-12-17 | 京东方科技集团股份有限公司 | 电子设备、时间同步系统及时间同步方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114095166A (zh) * | 2021-11-23 | 2022-02-25 | 北京京东方技术开发有限公司 | 生成节点临时身份标识的方法、节点及系统 |
CN115276617A (zh) * | 2022-06-21 | 2022-11-01 | 上海芯问科技有限公司 | 时钟偏差调制电路、接口系统及电子设备 |
Also Published As
Publication number | Publication date |
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WO2021142828A1 (zh) | 2021-07-22 |
US20220311529A1 (en) | 2022-09-29 |
CN113498623B (zh) | 2023-06-20 |
JP7493581B2 (ja) | 2024-05-31 |
EP4093101A1 (en) | 2022-11-23 |
EP4093101A4 (en) | 2023-01-18 |
JP2023519041A (ja) | 2023-05-10 |
US11799578B2 (en) | 2023-10-24 |
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