WO2021139039A1 - 氧化镓肖特基二极管及其制作方法 - Google Patents

氧化镓肖特基二极管及其制作方法 Download PDF

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WO2021139039A1
WO2021139039A1 PCT/CN2020/086191 CN2020086191W WO2021139039A1 WO 2021139039 A1 WO2021139039 A1 WO 2021139039A1 CN 2020086191 W CN2020086191 W CN 2020086191W WO 2021139039 A1 WO2021139039 A1 WO 2021139039A1
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layer
gallium oxide
metal
schottky diode
anode
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PCT/CN2020/086191
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English (en)
French (fr)
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吕元杰
王元刚
周幸叶
刘宏宇
宋旭波
梁士雄
马春雷
徐森锋
冯志红
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中国电子科技集团公司第十三研究所
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Publication of WO2021139039A1 publication Critical patent/WO2021139039A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes

Definitions

  • This application belongs to the field of semiconductor technology, and in particular relates to a gallium oxide Schottky diode and a manufacturing method thereof.
  • the gallium nitride material which is the representative of the third-generation semiconductor, has the advantages of high breakdown voltage, high working temperature and strong radiation resistance due to its wide band gap and high thermal conductivity.
  • the band gap of gallium oxide is very large, ranging from 4.8 to 4.9 eV, and the insulation breakdown electric field is also large, ranging from 7 to 8 MV/cm. Therefore, a Schottky barrier diode (SBD) of gallium oxide is used as a switching element for power devices. Very promising. However, the research on gallium oxide SBD power devices in the prior art is still lacking, resulting in that the gallium oxide SBD power devices have not exerted their theoretical advantages.
  • the applicant of this application found that in the gallium oxide SBD power device, there are more interface states between the dielectric layer and the low-doped gallium oxide epitaxial layer, so that the anode metal and the dielectric layer and the low-doped gallium oxide epitaxial layer are three A high concentration of electrons will be induced at the intersection of the participants. If the anode metal is in direct contact with the dielectric layer and the low-doped gallium oxide epitaxial layer at the same time, it will cause the device to have a large leakage, prone to breakdown, which is detrimental to the breakdown characteristics of the device.
  • the present application provides a gallium oxide Schottky diode and a manufacturing method thereof to reduce the influence of the interface state on the leakage of the device and improve the breakdown characteristics of the gallium oxide Schottky diode device.
  • the first aspect of the embodiments of the present application provides a gallium oxide Schottky diode.
  • the gallium oxide Schottky diode includes a cathode metal layer, a highly doped gallium oxide substrate, and a low doped gallium oxide epitaxial layer from bottom to top.
  • Anode metal and anode field plate, the upper part of the low-doped gallium oxide epitaxial layer further includes a multi-layer dielectric layer distributed around the anode metal;
  • the corrosion rate of each dielectric layer in the multi-layer dielectric layer decreases with the increase in the number of layers, the top layer of the multi-layer dielectric layer is in contact with the anode metal, and the bottom layer of the multi-layer dielectric layer Separated from the anode metal.
  • the second aspect of the embodiments of the present application provides a manufacturing method of a gallium oxide Schottky diode, including:
  • a photoresist is suspended on the top surface of the multilayer dielectric layer, and the anode metal opening pattern is formed by exposure and development;
  • Dry etching combined with wet etching or only wet etching is used to remove the dielectric corresponding to the opening of the anode metal opening pattern to form a multi-layer dielectric layer whose bottom layer is more corroded than the top layer;
  • the metal is evaporated on the low-doped gallium oxide epitaxial layer based on the metal opening pattern of the field plate to form an anode metal with an anode field plate above it.
  • the thickness of the anode metal is 50 nanometers to 1000 nanometers
  • the thickness of the anode field plate is 50 nanometers to 1000 nanometers.
  • the opening of the field plate metal opening pattern is larger than the opening of the anode metal opening pattern.
  • the opening edge of the field plate metal opening pattern and the opening edge of the anode metal opening pattern are separated by 100 nanometers to 15 micrometers.
  • the multi-layer dielectric layer includes two dielectric layers, a bottom layer and a top layer.
  • the inner edges of the bottom layer and the top layer are 1 nanometer to 1000 nanometers apart.
  • the dielectric of the bottom layer is silicon dioxide
  • the dielectric of the top layer is silicon nitride
  • the thickness of the bottom layer ranges from 5 nanometers to 500 nanometers
  • the thickness of the top layer ranges from 50 nanometers to 1000 nanometers.
  • this application has a multilayer dielectric layer, the top layer of the multilayer dielectric layer is in contact with the anode metal, and the bottom layer of the multilayer dielectric layer is separated from the anode metal. Since the bottom layer of the multilayer dielectric layer is separated from the anode metal, it can effectively isolate the contact between the anode metal and the interface state between the multilayer dielectric layer and the low-doped gallium oxide epitaxial layer, thereby effectively preventing the generation of high-concentration electrons around the bottom of the anode metal , Improve the influence of the interface state on the leakage of the device, and improve the breakdown characteristics of the device.
  • gallium oxide Schottky diode manufactured through the process steps provided in this application has a better corrosion rate because the corrosion rate of each dielectric layer increases with the increase in the number of layers, and the corrosion rate of the same layer of the dielectric is the same. Structural symmetry.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a gallium oxide Schottky diode provided by an embodiment of the present application;
  • FIG. 2 is an implementation flowchart of a method for manufacturing a gallium oxide Schottky diode provided by an embodiment of the present application
  • FIG. 3 is a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 203 in the manufacturing method of a gallium oxide Schottky diode according to an embodiment of the present application;
  • step 204 is a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 204 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application;
  • FIG. 5 is a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 205 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application;
  • FIG. 6 is a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 206 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a cross-sectional structure of a gallium oxide Schottky diode provided by an embodiment of the present application, and the details are as follows:
  • a gallium oxide Schottky diode includes a cathode metal layer 11, a highly doped gallium oxide substrate 12, a low doped gallium oxide epitaxial layer 13, an anode metal 151 and an anode field plate from bottom to top. 152.
  • the upper portion of the low-doped gallium oxide epitaxial layer 13 further includes a multilayer dielectric layer (141, 142) distributed around the anode metal 151.
  • FIG. 1 shows a schematic diagram of the multilayer dielectric layer including two dielectric layers.
  • the corrosion rate of each dielectric layer in the multi-layer dielectric layer decreases with the increase in the number of layers.
  • the corrosion rate of the bottom layer 141 in contact with the low-doped gallium oxide epitaxial layer 13 is greater than The corrosion rate of the top layer 142 thereon. Therefore, when the dielectric corrosion is performed, the corrosion degree of the bottom layer 141 will be greater than that of the top layer 142. Since the media of each layer are uniform, when the media is corroded, the corrosion degree of the media of the same layer is symmetrical.
  • the top layer 142 of the multilayer dielectric layer (141, 142) is in contact with the anode metal 151, and the bottom layer 141 of the multilayer dielectric layer (141, 142) is separated from the anode metal 151. As shown in FIG. 1, there is a gap between the bottom layer 141 of the multilayer dielectric layer (141, 142) and the anode metal 151.
  • this application has a multilayer dielectric layer, and the top layer of the multilayer dielectric layer is in contact with the anode metal, and the bottom layer of the multilayer dielectric layer is separated from the anode metal.
  • the bottom layer of the dielectric layer is separated from the anode metal, which can effectively isolate the contact between the anode metal and the interface state between the multilayer dielectric layer and the low-doped gallium oxide epitaxial layer, thereby effectively preventing the generation of high-concentration electrons around the bottom of the anode metal and improving the interface The impact of the state on the leakage of the device, and improve the breakdown characteristics of the device.
  • FIG. 2 shows an implementation flow chart of the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application, which is described in detail as follows:
  • step 201 a low-doped gallium oxide epitaxial layer is epitaxially grown on a highly-doped gallium oxide substrate;
  • an n-type low-doped gallium oxide epitaxial layer can be epitaxially grown on a highly doped gallium oxide substrate, and the n-type low-doped gallium oxide epitaxial layer can be realized by doping silicon or germanium.
  • the doping concentration may be in the range of 1.0 ⁇ 1015 cm-3 to 1.0 ⁇ 1020 cm-3. In some application scenarios, the doping concentration of the low-doped gallium oxide epitaxial layer may also be gradiently changed.
  • step 202 the cathode metal layer is evaporated on the back of the highly doped gallium oxide substrate
  • the cathode metal layer can be made by evaporation on the back of the highly doped gallium oxide substrate.
  • the material of the cathode metal can be Ti and Au, or Ti, Al, Ni and Au can be selected.
  • the superalloy forms ohmic contacts.
  • step 203 two or more dielectric layers are deposited on the low-doped gallium oxide epitaxial layer to form a multilayer dielectric layer, wherein the corrosion rate of each dielectric layer in the multilayer dielectric layer increases with the number of layers. And reduce.
  • two or more dielectric layers may be deposited on the low-doped gallium oxide epitaxial layer.
  • the corrosion rates of the deposited dielectric layers are different, and the corrosion rate of each dielectric layer decreases with the increase in the number of layers.
  • two dielectric layers can be deposited, one layer is a silicon dioxide (SiO2) dielectric, one The layer is silicon nitride (SiN) dielectric; since the corrosion rate of silicon dioxide (SiO2) dielectric is greater than that of silicon nitride (SiN) dielectric, the bottom layer can be deposited as silicon dioxide (SiO2) dielectric, and the top layer is deposited as nitride Silicon (SiN) dielectric.
  • the multilayer dielectric layer may adopt PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) or ALD (Atomic layer deposition, atomic layer deposition) and other deposition methods.
  • PECVD Plasma enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition
  • ALD Atomic layer deposition, atomic layer deposition
  • the thickness of the bottom layer of the multilayer dielectric layer may range from 5 nanometers to 500 nanometers, and the thickness of the top layer may range from 50 nanometers to 1000 nanometers.
  • FIG. 3 it shows a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 203 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application.
  • the cathode metal layer is sequentially included from bottom to top. 11.
  • step 204 a photoresist is suspended on the top surface of the multilayer dielectric layer, and an anode metal opening pattern is formed by exposure and development;
  • an etching resistant photoresist (such as AZ1500, etc.) is suspended on the top surface of the multilayer dielectric layer, and the anode metal opening pattern is realized through exposure and development.
  • the opening of the anode metal opening pattern can be flexible according to the actual situation. The selection, for example, can be square.
  • FIG. 4 shows a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 204 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application.
  • the cathode metal layer is sequentially included from bottom to top. 11.
  • Highly-doped gallium oxide substrate 12, low-doped gallium oxide epitaxial layer 13, multilayer dielectric layer (bottom layer 141, top layer 142) and photoresist 16 the middle part of the photoresist 16 in the figure is the anode Metal opening pattern.
  • step 205 dry etching combined with wet etching or only wet etching is used to remove the dielectric corresponding to the opening of the anode metal opening pattern to form a multilayer dielectric layer whose bottom layer is more corroded than the top layer.
  • dry etching combined with wet etching may be used, or wet etching may be directly used to remove the medium corresponding to the opening of the anode metal opening pattern. Due to the fast corrosion rate of the bottom layer medium and the slow rate of the top layer medium, a structure with a smaller edge of the bottom layer medium than the edge of the top layer can be formed. In one embodiment, the difference between the edges of the bottom layer and the top layer can range from 1 nanometer to 1000 Nano.
  • FIG. 5 it shows a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 205 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application.
  • the cathode metal layer is sequentially included from bottom to top. 11.
  • Highly-doped gallium oxide substrate 12, low-doped gallium oxide epitaxial layer 13, multilayer dielectric layer (bottom layer 141, top layer 142) and photoresist 16 the middle part of the photoresist 16 in the figure is the anode Metal opening.
  • both the bottom layer 141 and the top layer 142 are etched into two left and right parts, and the distance between the left and right parts of the bottom layer 141 is greater than the distance between the left and right parts of the top layer 142.
  • step 206 the photoresist is suspended again on the top surface of the multilayer dielectric layer, and the metal opening pattern of the field plate is formed by exposure and development;
  • the photoresist 16 that is suspended for the first time can be removed first, and then the photoresist can be suspended again on the top surface of the multilayer dielectric layer, and the field plate metal opening pattern can be realized by exposure and development.
  • the opening of the plate metal opening pattern can be flexibly selected according to the actual situation, for example, it can be square.
  • the opening of the metal opening pattern of the field plate needs to be larger than the opening of the anode metal opening pattern realized by the first suspension coating and development.
  • the opening size of the anode metal opening pattern realized by the first suspension coating development corresponds to the range of the anode metal
  • the opening size of the field plate metal opening pattern realized by the second suspension coating development corresponds to the size range of the field plate metal.
  • the length of the field plate metal beyond the range of the anode metal can be 100 nanometers to 15 microns.
  • FIG. 6 it shows a schematic cross-sectional structure diagram corresponding to the manufacturing result of step 206 in the manufacturing method of a gallium oxide Schottky diode provided by an embodiment of the present application.
  • the cathode metal layer is sequentially included from bottom to top. 11.
  • Highly doped gallium oxide substrate 12, low-doped gallium oxide epitaxial layer 13, multi-layer dielectric layer (bottom layer 141, top layer 142) and photoresist 17 (field plate metal opening pattern realized by the second suspension coating and development) the middle part on both sides of the photoresist 17 in the figure is the field plate metal opening.
  • the distance between the two sides of the top layer 141 corresponds to the size of the anode metal
  • the distance between the two sides of the photoresist 17 corresponds to the size of the field plate metal.
  • step 207 metal is evaporated on the low-doped gallium oxide epitaxial layer based on the field plate metal opening pattern to form an anode metal with an anode field plate above it.
  • the metal is evaporated through the metal opening pattern of the field plate, and the anode metal 151 can be obtained on the low-doped gallium oxide epitaxial layer (see FIG. 1), and the part after the evaporated metal exceeds the top layer 142 is the anode field plate 152, thereby forming the anode metal 151 with the anode field plate 152 above it.
  • the anode metal and anode field plate can be made of Ni and Au, or Pt and Au.
  • the anode field plate can be evaporated by a platinum metal layer first, and then evaporated on the platinum metal layer. A layer of gold metal.
  • the thickness of the anode metal 151 may be 50 nm to 1000 nm, and the thickness of the anode field plate 152 may also be 50 nm to 1000 nm.
  • this application has a multilayer dielectric layer, and the top layer of the multilayer dielectric layer is in contact with the anode metal, and the bottom layer of the multilayer dielectric layer is separated from the anode metal.
  • the bottom layer of the dielectric layer is separated from the anode metal, which can effectively isolate the contact between the anode metal and the interface state between the multilayer dielectric layer and the low-doped gallium oxide epitaxial layer, thereby effectively preventing the generation of high-concentration electrons around the bottom of the anode metal and improving the interface

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Abstract

一种氧化镓肖特基二极管及其制作方法，该氧化镓肖特基二极管由下至上依次包括阴极金属层（11），高掺杂氧化镓衬底（12），低掺杂氧化镓外延层（13）、阳极金属（151）和阳极场板（152）。其中，低掺杂氧化镓外延层（13）上部还包括环绕阳极金属（151）分布的多层介质层（141、142），所述多层介质层（141、142）中的各介质层（141、142）的腐蚀速率随其所在层数的增加而减小，所述多层介质层（141、142）的顶层（142）与所述阳极金属（151）接触，且，所述多层介质层（141、142）的底层（141）与所述阳极金属（151）分离。可以改善界面态对器件漏电的影响，提升器件的击穿特性，并且具有较好的结构对称性。

Description

氧化镓肖特基二极管及其制作方法 技术领域
本申请属于半导体技术领域，尤其涉及一种氧化镓肖特基二极管及其制作方法。
 背景技术
目前，作为第三代半导体代表的氮化镓材料，因其具有较宽的禁带宽度，较高的热导率，因此具有击穿电压高、工作承受的温度高以及抗辐射能力强等优点，是比较理想的大功率半导体材料，然而其制备工艺复杂，制备成本较高，难以实现量产。
而氧化镓带隙非常大，为4.8～4.9eV，绝缘击穿电场也大，为7～8MV/cm，因此，使用氧化镓的肖特基势垒二极管（SBD）作为功率器件用的开关元件非常有希望。然而，现有技术中对氧化镓SBD功率器件的研究尚有欠缺，导致氧化镓SBD功率器件并未发挥出其理论优势。
 技术问题
本申请的申请人发现，在氧化镓SBD功率器件中，介质层和低掺杂氧化镓外延层之间存在较多的界面态，从而在阳极金属与介质层和低掺杂氧化镓外延层三者交汇处会感生出高浓度的电子。如果阳极金属直接与介质层和低掺杂氧化镓外延层同时接触，会导致器件漏电大，容易发生击穿，对器件击穿特性不利。
 技术解决方案
有鉴于此，本申请提供了一种氧化镓肖特基二极管及其制作方法，以降低界面态对器件漏电的影响力度，提升氧化镓肖特基二极管器件的击穿特性。
本申请实施例的第一方面提供了一种氧化镓肖特基二极管，该氧化镓肖特基二极管由下至上依次包括阴极金属层，高掺杂氧化镓衬底，低掺杂氧化镓外延层，阳极金属和阳极场板，所述低掺杂氧化镓外延层上部还包括环绕所述阳极金属分布的多层介质层；
所述多层介质层中的各介质层的腐蚀速率随其所在层数的增加而减小，所述多层介质层的顶层与所述阳极金属接触，且，所述多层介质层的底层与所述阳极金属分离。
本申请实施例的第二方面提供了一种氧化镓肖特基二极管的制作方法，包括：
在高掺杂氧化镓衬底上外延生长低掺杂氧化镓外延层；
在高掺杂氧化镓衬底背面蒸发阴极金属层；
在低掺杂氧化镓外延层上淀积两层以上的介质，形成多层介质层，其中，所述多层介质层中各介质层的腐蚀速率随其所在层数的增加而减小；
在多层介质层的顶层表面悬涂光刻胶，通过曝光显影形成阳极金属开口图形；
采用干法刻蚀结合湿法腐蚀或者仅采用湿法腐蚀去除所述阳极金属开口图形的开口处对应的介质，形成底层比顶层被腐蚀程度大的多层介质层；
在多层介质层的顶层表面再次悬涂光刻胶，通过曝光显影形成场板金属开口图形；
基于场板金属开口图形在低掺杂氧化镓外延层上蒸发金属，形成上方具有阳极场板的阳极金属。
可选的，所述阳极金属的厚度为50纳米至1000纳米，所述阳极场板的厚度为50纳米至1000纳米。
可选的，所述场板金属开口图形的开口大于所述阳极金属开口图形的开口。
可选的，所述场板金属开口图形的开口边缘和所述阳极金属开口图形的开口边缘相距100纳米至15微米。
可选的，所述多层介质层包括底层和顶层两个介质层。
可选的，所述底层和所述顶层的内侧边缘相距1纳米至1000纳米。
可选的，所述底层的介质为二氧化硅，所述顶层的介质为氮化硅。
可选的，所述底层的厚度范围为5纳米至500纳米，所述顶层的厚度范围为50纳米至1000纳米。
 有益效果
本申请相比常规氧化镓肖特基二极管，其具有多层介质层，多层介质层的顶层与所述阳极金属接触，且，所述多层介质层的底层与所述阳极金属分离。由于多层介质层的底层与阳极金属分离，可以有效隔绝阳极金属与多层介质层和低掺杂氧化镓外延层之间界面态的接触，从而能够有效阻止阳极金属底部周围高浓度电子的生成，改善界面态对器件漏电的影响，提升器件的击穿特性。并且，通过本申请提供的工艺步骤制作的氧化镓肖特基二极管，由于各介质层的腐蚀速率随其所在层数的增加而减小，同层介质的腐蚀速率相同，因此还具有较好的结构对称性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的氧化镓肖特基二极管的截面结构示意图；
图2是本申请实施例提供的氧化镓肖特基二极管的制作方法的实现流程图；
图3是本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤203的制作结果的截面结构示意图；
图4是本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤204的制作结果的截面结构示意图；
图5是本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤205的制作结果的截面结构示意图；
图6是本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤206的制作结果的截面结构示意图。
本申请的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图通过具体实施例来进行说明。
参见图1，其示出了本申请实施例提供的氧化镓肖特基二极管的截面结构示意图，详述如下：
如图1所示，一种氧化镓肖特基二极管，由下至上依次包括阴极金属层11，高掺杂氧化镓衬底12，低掺杂氧化镓外延层13，阳极金属151和阳极场板152，低掺杂氧化镓外延层13上部还包括环绕阳极金属151分布的多层介质层（141，142），图1中示出的是多层介质层包括两层介质的示意图。
其中，多层介质层（141，142）中的各介质层的腐蚀速率随其所在层数的增加而减小，例如，与低掺杂氧化镓外延层13相接触的底层141的腐蚀速率大于其上的顶层142的腐蚀速率。由此，在进行介质腐蚀时，底层141的被腐蚀程度会大于顶层142。而由于各层介质是均匀的，故在进行介质腐蚀时，对于同层介质，其被腐蚀程度是对称的。
其中，多层介质层（141，142）的顶层142与阳极金属151接触，且，多层介质层（141，142）的底层141与阳极金属151分离。如图1所示，多层介质层（141，142）的底层141与阳极金属151之间存在着间隙。
本申请相比常规氧化镓肖特基二极管，其具有多层介质层，且，多层介质层的顶层与阳极金属接触，且，多层介质层的底层与所述阳极金属分离，由于多层介质层的底层与阳极金属分离，可以有效隔绝阳极金属与多层介质层和低掺杂氧化镓外延层之间界面态的接触，从而能够有效阻止阳极金属底部周围高浓度电子的生成，改善界面态对器件漏电的影响，提升器件的击穿特性。
参见图2，其示出了本申请实施例提供的氧化镓肖特基二极管的制作方法的实现流程图，详述如下：
在步骤201中、在高掺杂氧化镓衬底上外延生长低掺杂氧化镓外延层；
在本申请实施例中，可以在高掺杂氧化镓衬底上外延生长n型的低掺杂氧化镓外延层，n型的低掺杂氧化镓外延层可以通过掺杂硅或锗等元素实现，掺杂浓度可以为1.0×1015 cm-3至1.0×1020 cm-3范围之间，在一些应用场景中，低掺杂氧化镓外延层的掺杂浓度也可以是梯度变化的。
在步骤202中、在高掺杂氧化镓衬底背面蒸发阴极金属层；
在本申请实施例中，可以在高掺杂氧化镓衬底背面的背面通过蒸发制作阴极金属层，阴极金属的制成材料可以选用Ti和Au，或者，可以选用Ti、Al、Ni和Au，高温合金形成欧姆接触。
在步骤203中、在低掺杂氧化镓外延层上淀积两层以上的介质，形成多层介质层，其中，所述多层介质层中各介质层的腐蚀速率随其所在层数的增加而减小。
在本申请实施例中，可以在低掺杂氧化镓外延层上淀积两层以上的介质（包括两层）。所淀积的各层介质的腐蚀速率不同，各介质层的腐蚀速率随其所在层数的增加而减小，例如，可以淀积两层介质，一层为二氧化硅（SiO2）介质，一层为氮化硅（SiN）介质；由于二氧化硅（SiO2）介质的腐蚀速率大于氮化硅（SiN）介质，故可以底层淀积为二氧化硅（SiO2）介质，顶层淀积为氮化硅（SiN）介质。
在本申请实施例中，多层介质层可以采用PECVD（Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法）、LPCVD（Low Pressure Chemical Vapor Deposition，低压力化学气相沉积法）或ALD（Atomic layer deposition，原子层沉积）等淀积方式实现。
在一个实施例中，多层介质层的底层厚度范围可以为5纳米至500纳米，顶层厚度范围可以为50纳米至1000纳米。
参考图3，其示出了本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤203的制作结果的截面结构示意图，如图3所示，由下至上依次包括阴极金属层11，高掺杂氧化镓衬底12，低掺杂氧化镓外延层13和多层介质层（底层141，顶层142）。
在步骤204中、在多层介质层的顶层表面悬涂光刻胶，通过曝光显影形成阳极金属开口图形；
在本申请实施例中，在多层介质层的顶层表面悬涂耐刻蚀光刻胶（如AZ1500等），并通过曝光显影实现阳极金属开口图形，阳极金属开口图形的开口可以根据实际情况灵活选择，例如可以为方形。
参考图4，其示出了本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤204的制作结果的截面结构示意图，如图4所示，由下至上依次包括阴极金属层11，高掺杂氧化镓衬底12，低掺杂氧化镓外延层13，多层介质层（底层141，顶层142）和光刻胶16，图中光刻胶16两侧中间的部分为阳极金属开口图形。
在步骤205中、采用干法刻蚀结合湿法腐蚀或者仅采用湿法腐蚀去除所述阳极金属开口图形的开口处对应的介质，形成底层比顶层被腐蚀程度大的多层介质层。
在本申请实施例中，可以采用干法刻蚀结合湿法腐蚀，或者，直接采用湿法腐蚀去除阳极金属开口图形的开口处对应的介质。由于底层介质腐蚀速率快，顶层介质腐蚀速率慢，最后可以形成底层介质边缘比顶层介质边缘小的结构，在一个实施例中，底层和顶层两层介质边缘的差值范围可以为1纳米至1000纳米。
参考图5，其示出了本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤205的制作结果的截面结构示意图，如图5所示，由下至上依次包括阴极金属层11，高掺杂氧化镓衬底12，低掺杂氧化镓外延层13，多层介质层（底层141，顶层142）和光刻胶16，图中光刻胶16两侧中间的部分为阳极金属开口。在截面结构图中可以看出，底层141和顶层142均被腐蚀为左右两部分，且，底层141的左右两部分的距离大于顶层142的左右两部分的距离。
在步骤206中、在多层介质层的顶层表面再次悬涂光刻胶，通过曝光显影形成场板金属开口图形；
在本申请实施例中，可以首先将第一次悬涂的光刻胶16去除，再在多层介质层的顶层表面再次悬涂光刻胶，并通过曝光显影实现场板金属开口图形，场板金属开口图形的开口可以根据实际情况灵活选择，例如可以为方形。
在本申请实施例中，场板金属开口图形的开口需要大于第一次悬涂显影实现的阳极金属开口图形的开口。
实际上，第一次悬涂显影实现的阳极金属开口图形的开口的大小对应于阳极金属的范围，第二次悬涂显影实现的场板金属开口图形的开口对应于场板金属的大小范围，在实际应用中，场板金属超出阳极金属的范围之外的长度可以是100纳米至15微米。
参考图6，其示出了本申请实施例提供的对应于氧化镓肖特基二极管的制作方法中步骤206的制作结果的截面结构示意图，如图6所示，由下至上依次包括阴极金属层11，高掺杂氧化镓衬底12，低掺杂氧化镓外延层13，多层介质层（底层141，顶层142）和光刻胶17（第二次悬涂显影实现的场板金属开口图形），图中光刻胶17两侧中间的部分为场板金属开口。在截面结构图中可以看出，顶层141的两侧之间的距离对应于阳极金属的大小，光刻胶17的两侧之间的距离对应于场板金属的大小。
在步骤207中、基于场板金属开口图形在低掺杂氧化镓外延层上蒸发金属，形成上方具有阳极场板的阳极金属。
在本申请实施例中，通过场板金属开口图形进行蒸发金属，在低掺杂氧化镓外延层上可以得到阳极金属151（参见图1），蒸发的金属超过顶层142之后的部分为阳极场板152，从而形成了上方具有阳极场板152的阳极金属151。
在本申请实施例中，阳极金属、阳极场板的材料可以为Ni和Au，也可以为Pt和Au，例如，阳极场板可以是先蒸发一层铂金属层，再在铂金属层上蒸发一层金金属层。其中，阳极金属151的厚度可以为50纳米至1000纳米，阳极场板152的厚度也可以为50纳米至1000纳米。
本申请相比常规氧化镓肖特基二极管，其具有多层介质层，且，多层介质层的顶层与阳极金属接触，且，多层介质层的底层与所述阳极金属分离，由于多层介质层的底层与阳极金属分离，可以有效隔绝阳极金属与多层介质层和低掺杂氧化镓外延层之间界面态的接触，从而能够有效阻止阳极金属底部周围高浓度电子的生成，改善界面态对器件漏电的影响，提升器件的击穿特性
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (9)

  1. 一种氧化镓肖特基二极管，由下至上依次包括阴极金属层，高掺杂氧化镓衬底，低掺杂氧化镓外延层，阳极金属和阳极场板，其特征在于，所述低掺杂氧化镓外延层上部还包括环绕所述阳极金属分布的多层介质层；
    所述多层介质层中的各介质层的腐蚀速率随其所在层数的增加而减小，所述多层介质层的顶层与所述阳极金属接触，且，所述多层介质层的底层与所述阳极金属分离。
  2. 一种氧化镓肖特基二极管的制作方法，其特征在于，所述制作方法包括：
    在高掺杂氧化镓衬底上外延生长低掺杂氧化镓外延层；
    在高掺杂氧化镓衬底背面蒸发阴极金属层；
    在低掺杂氧化镓外延层上淀积两层以上的介质，形成多层介质层，其中，所述多层介质层中各介质层的腐蚀速率随其所在层数的增加而减小；
    在多层介质层的顶层表面悬涂光刻胶，通过曝光显影形成阳极金属开口图形；
    采用干法刻蚀结合湿法腐蚀或者仅采用湿法腐蚀去除所述阳极金属开口图形的开口处对应的介质，形成底层比顶层被腐蚀程度大的多层介质层；
    在多层介质层的顶层表面再次悬涂光刻胶，通过曝光显影形成场板金属开口图形；
    基于场板金属开口图形在低掺杂氧化镓外延层上蒸发金属，形成上方具有阳极场板的阳极金属。
  3. 根据权利要求2所述的氧化镓肖特基二极管的制作方法，其特征在于，所述阳极金属的厚度为50纳米至1000纳米，所述阳极场板的厚度为50纳米至1000纳米。
  4. 根据权利要求2所述的氧化镓肖特基二极管的制作方法，其特征在于，所述场板金属开口图形的开口大于所述阳极金属开口图形的开口。
  5. 根据权利要求4所述的氧化镓肖特基二极管的制作方法，其特征在于，所述场板金属开口图形的开口边缘和所述阳极金属开口图形的开口边缘相距100纳米至15微米。
  6. 根据权利要求2所述的氧化镓肖特基二极管的制作方法，其特征在于，所述多层介质层包括底层和顶层两个介质层。
  7. 根据权利要求6所述的氧化镓肖特基二极管的制作方法，其特征在于，所述底层和所述顶层的内侧边缘相距1纳米至1000纳米。
  8. 根据权利要求6所述的氧化镓肖特基二极管的制作方法，其特征在于，所述底层的介质为二氧化硅，所述顶层的介质为氮化硅。
  9. 根据权利要求8所述的氧化镓肖特基二极管的制作方法，其特征在于，所述底层的厚度范围为5纳米至500纳米，所述顶层的厚度范围为50纳米至1000纳米。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116454638A (zh) * 2023-06-07 2023-07-18 中国人民解放军国防科技大学 一种L-Ku频段的超宽带微纳能量选择表面

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653707B1 (en) * 2000-09-08 2003-11-25 Northrop Grumman Corporation Low leakage Schottky diode
CN103107151A (zh) * 2011-11-11 2013-05-15 万国半导体股份有限公司 用于氮化镓肖特基二极管的端接结构
US20160042949A1 (en) * 2014-08-06 2016-02-11 Tamura Corporation METHOD OF FORMING HIGH-RESISTIVITY REGION IN Ga2O3-BASED SINGLE CRYSTAL, AND CRYSTAL LAMINATE STRUCTURE AND SEMICONDUCTOR ELEMENT
CN106876484A (zh) * 2017-01-23 2017-06-20 西安电子科技大学 高击穿电压氧化镓肖特基二极管及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6653707B1 (en) * 2000-09-08 2003-11-25 Northrop Grumman Corporation Low leakage Schottky diode
CN103107151A (zh) * 2011-11-11 2013-05-15 万国半导体股份有限公司 用于氮化镓肖特基二极管的端接结构
US20160042949A1 (en) * 2014-08-06 2016-02-11 Tamura Corporation METHOD OF FORMING HIGH-RESISTIVITY REGION IN Ga2O3-BASED SINGLE CRYSTAL, AND CRYSTAL LAMINATE STRUCTURE AND SEMICONDUCTOR ELEMENT
CN106876484A (zh) * 2017-01-23 2017-06-20 西安电子科技大学 高击穿电压氧化镓肖特基二极管及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116454638A (zh) * 2023-06-07 2023-07-18 中国人民解放军国防科技大学 一种L-Ku频段的超宽带微纳能量选择表面
CN116454638B (zh) * 2023-06-07 2023-09-01 中国人民解放军国防科技大学 一种L-Ku频段的超宽带微纳能量选择表面

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