WO2017190511A1 - 场发射器件及其制作方法 - Google Patents

场发射器件及其制作方法 Download PDF

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Publication number
WO2017190511A1
WO2017190511A1 PCT/CN2016/112479 CN2016112479W WO2017190511A1 WO 2017190511 A1 WO2017190511 A1 WO 2017190511A1 CN 2016112479 W CN2016112479 W CN 2016112479W WO 2017190511 A1 WO2017190511 A1 WO 2017190511A1
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Prior art keywords
layer
emitter
field emission
emission device
semiconductor
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PCT/CN2016/112479
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English (en)
French (fr)
Inventor
赵德胜
黄宏娟
曾中明
张宝顺
Original Assignee
中国科学院苏州纳米技术与纳米仿生研究所
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Priority claimed from CN201610288516.XA external-priority patent/CN107346720B/zh
Priority claimed from CN201611218533.2A external-priority patent/CN108242466B/zh
Application filed by 中国科学院苏州纳米技术与纳米仿生研究所 filed Critical 中国科学院苏州纳米技术与纳米仿生研究所
Publication of WO2017190511A1 publication Critical patent/WO2017190511A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems

Definitions

  • the present invention belongs to the field of semiconductor technology, and in particular to a field emission device and a method of fabricating the same.
  • Field emission devices have a wide range of applications in vacuum microelectronics, including ultra-high-speed high-frequency devices, field emission displays, and microwave amplifiers.
  • Field-emitting cathodes have received much attention as the core of vacuum microelectronic devices.
  • To achieve excellent field emission characteristics it is mainly achieved by reducing the electron affinity of the field emission cathode and increasing the field enhancement factor by using nanostructures.
  • semiconductor materials have become a hotspot in field emission cathode materials research due to their mature micro-nano processing technology.
  • some semiconductor materials have low electron affinity or negative electron affinity.
  • the electron affinity of GaN is about 2.7 eV to 3.3 eV, which is likely to cause a lower emission potential in a heterostructure.
  • the base material, and the N-type doping of the semiconductor material is easy to achieve a high electron concentration, and is an ideal field emission cathode material.
  • the lateral structure field emission device can realize the control of the distance between the emitter cathode and the collector by micro-nano processing, and the lateral structure field emission device is easier to integrate than the vertical structure field emission device.
  • the lateral structure field emission device needs to be implemented by a subsequent complicated process, how to realize the lateral structure field emission device is crucial for the preparation and application of future devices.
  • the fabrication process of the lateral field emission device how to realize the nanometer cathode-anode spacing and the switching control of the field emission device through the gate is a key process for device fabrication.
  • the present invention provides a field emission device and a fabrication method thereof, the field emission device being a field emission device having a lateral structure, A higher enhancement factor.
  • a field emission device comprising a substrate and a buffer layer disposed on the substrate; the buffer layer is provided with an emitter layer, and the emitter layer comprises a first semiconductor layer and a second layer which are sequentially stacked a semiconductor layer; an ion implantation layer further disposed on the buffer layer, the emitter layer being embedded in the ion implantation layer, and the ion implantation layer having a gap so that an emission end surface of the emitter layer is Exposed at the notch, the emission end surface includes an end surface of at least a portion of the first semiconductor layer adjacent to each other and an end surface of at least a portion of the second semiconductor layer; a collector layer is disposed at a notch of the ion implantation layer, and the collector An end surface of the layer is opposite to the emission end surface and has a channel therebetween; and the emitter layer is further laminated with a gate dielectric layer and a gate electrode.
  • a two-dimensional electron gas structure is formed at a connection interface of the first semiconductor layer and the second semiconductor layer.
  • the material of the first semiconductor layer is GaN, the material of the second semiconductor layer is AlGaN; or the material of the first semiconductor layer is GaAs, and the material of the second semiconductor layer is AlGaAs;
  • the material of the first semiconductor layer is InAs, and the material of the second semiconductor layer is GaSb.
  • the material of the collector layer is a metal electrode material.
  • the angle of the emitting end surface is 0° to 180°.
  • a top surface of the collector layer is higher than a top surface of the emitter layer.
  • the width of the channel does not exceed 100 nm.
  • Another object of the present invention is to provide a method of fabricating a field emission device according to any of the above, comprising: sequentially forming a buffer material layer, an emitter material layer and a gate dielectric material layer on a substrate; wherein the emission The pole material layer comprises a first semiconductor material layer and a second semiconductor material layer which are sequentially stacked; the buffer material layer, the emitter material layer and the gate dielectric material layer are ion-implanted to form a buffer layer, and the buffer layer is located An ion implantation layer thereon, and an emitter layer and a gate dielectric layer disposed on the buffer layer in sequence; the ion implantation layer surrounds the emitter layer and the gate dielectric layer; Preparing a gate on the layer; removing a portion of the ion implantation layer to form a gap such that an emission end surface of the emitter layer is exposed from the gap, the emission end surface including a continuous first region and a second region The first region is located at an end surface of the first semiconductor layer, and the second
  • the thickness of the dielectric film layer does not exceed 100 nm.
  • a portion of the ion implantation layer is removed, a portion of the gate dielectric layer and a portion of the emitter layer are collectively removed, and the collector layer is in contact with the first semiconductor layer.
  • a third object of the present invention is to provide a field emission device including a substrate, a buffer layer disposed on the substrate, an emitter layer and a metal collector layer respectively disposed at both ends of the buffer layer, respectively disposed at An electrode layer on the emitter layer and the metal collector layer, wherein a channel is formed between the emitter layer and the metal collector layer.
  • the metal collector layer is a Cr/Au composite film electrode or a Mo film electrode.
  • the emitter layer has at least one pointed protrusion toward a side of the metal collector layer
  • the metal collector layer has at least one pointed recess corresponding to a side of the emitter layer, the pointed convex The portion is disposed in cooperation with the pointed portion such that the channel is non-linear.
  • the apex angle of each of the pointed protrusions is a, 0° ⁇ a ⁇ 90°.
  • the emitter layer adopts a GaN-based superlattice structure or a GaN multilayer heterostructure or a GaN highly doped structure.
  • the electrode layer is a Ti/Al/Ni/Au composite film electrode.
  • the substrate is made of sapphire or GaN or SiC.
  • a fourth object of the present invention is to provide a method of fabricating a field emission device as described above, comprising the steps of: forming a buffer layer on a substrate; and forming a buffer layer Forming an emitter material layer; etching the emitter material layer such that at least one pointed protrusion is formed on one side of the emitter material layer, obtaining the emitter layer formed on one side of the buffer layer; deposition medium a film layer to completely cover the emitter layer; corresponding to the emitter layer, forming a metal collector layer on the other side of the buffer layer such that the metal collector layer faces the emitter layer One side has a pointed concave portion corresponding to the pointed convex portion; wet etching removes the dielectric film layer to form a channel between the emitter layer and the metal collector layer; at the emitter layer And forming the electrode layer on the metal collector layer.
  • the metal collector layer is a Ti/Au composite film electrode or a Mo film electrode.
  • the apex angle of each of the pointed protrusions is a, 0° ⁇ a ⁇ 90°.
  • the emitter material layer adopts a GaN-based superlattice structure or a GaN multilayer heterostructure or a GaN highly doped structure.
  • the electrode layer material is a Ti/Al/Ni/Au gold composite film electrode.
  • the substrate is made of sapphire or GaN or SiC.
  • the present invention provides a field emission device having a lateral field emission and a pitch nano-level air channel, the emission end face of the field emission device being capable of any angle between 0° and 180°.
  • the two-dimensional electron gas formed at the interface between the first semiconductor layer and the second semiconductor layer can enhance the enhancement factor of the field emission device, and on the other hand, the gate can utilize the two-dimensional electron gas Control the switching of the device; at the same time, the isolation of the ion implantation layer achieves effective isolation of the active region and reduces leakage current generation.
  • the invention also provides another field emission device, wherein the collector layer is made of a metal material, and the angle of the convex portion of the emitter can be designed to an arbitrary angle according to the performance of the field emission device, and since the collector layer is used
  • the metal material does not require the addition of a mask when forming a nano-pitch in the wet etching dielectric film layer, which simplifies the process, reduces the cost, and improves the performance.
  • FIG. 1 is a cross-sectional structural view of a field emission device according to Embodiment 1 of the present invention.
  • FIG. 2 is a partial structural schematic view of the field emission device of FIG. 1 after removing a collector layer;
  • Figure 3 is a partial enlarged view of the X area of Figure 1;
  • Embodiment 5 is an I-V curve of a field emission device according to Embodiment 1 of the present invention when a gate voltage is 0V;
  • Figure 6 is a transfer characteristic curve of a field emission device according to Embodiment 1 of the present invention.
  • Figure 7 is an output characteristic curve of a field emission device according to Embodiment 1 of the present invention.
  • FIG. 8 to FIG. 14 are process flow charts of a method of fabricating a field emission device according to Embodiment 2 of the present invention.
  • Figure 15 is a schematic structural view of a field emission device according to Embodiment 3 of the present invention.
  • 16 to 23 are process flow charts of a method of fabricating a field emission device according to Embodiment 3 of the present invention.
  • Figure 24 is a schematic structural view of a field emission device according to Embodiment 4 of the present invention.
  • FIG. 1 is a schematic structural view of a field emission device according to the present embodiment
  • FIG. 2 is a partial structural view of the field emission device of FIG. 1 after removing a collector layer
  • FIG. 3 is a partial enlarged view of the X region of FIG.
  • the field emission device includes: a substrate 1, a buffer layer 2, an emitter layer 3, and a gate dielectric layer 4 which are sequentially stacked on a substrate 1, and are disposed on the buffer layer 2.
  • the ion implantation layer 5 has a notch 51 when it surrounds the emitter layer 3, and the emission end face B of the emitter layer 3 is exposed from the notch 51.
  • the emitter layer 3 includes a first semiconductor layer 31 and a second semiconductor layer 32 which are sequentially stacked, and the emission end surface B includes end faces of at least a portion of the first semiconductor layer 31 adjacent to each other and at least a portion of the second semiconductor The end face of layer 32. That is, the emission end face B exposed by the notch 51 is to include a first region (not shown) and a second region (not shown) adjacent to each other, wherein the first region is located at the first semiconductor layer. 31 faces the end face at the notch 51, and the second region is located on the end face of the second semiconductor layer 32 facing the notch 51.
  • the collector layer 8 has an end face opposite to the emission end face B, and has a channel A between the two end faces; that is, a channel A is formed between the emitter layer 3 and the collector layer 8. .
  • the channel A is an air channel and the pitch thereof does not exceed 100 nm.
  • the spacing of the channel A is less than the mean free path of electrons in the air, so that the transmission of electrons when the field emission device operates under atmospheric pressure is not affected, ensuring good performance of the device.
  • a two-dimensional electron gas is formed at a connection interface of the first semiconductor layer 31 and the second semiconductor layer 32, and the structure of the two-dimensional electron gas can be used as an emission tip of the emitter layer 3, so that the angle of the emission end face B can be It is set to any angle from 0° to 180° without setting it to a sharp shape with a small angle such as 30° or 60°.
  • the two-dimensional electron gas also ensures that the gate 7 can be used to control the switching of the field emission device.
  • the angle of the emission end face B is 180°, that is, the emission end face B has a planar shape.
  • the material of the first semiconductor layer 31 is GaN, the material of the second semiconductor layer 32 is AlGaN; or the material of the first semiconductor layer 31 is GaAs, and the material of the second semiconductor layer 32 is AlGaAs; Or the material of the first semiconductor 31 layer is InAs, and the material of the second semiconductor layer 32 is GaSb.
  • the material of the first semiconductor layer 31 is GaN
  • the material of the second semiconductor layer 32 is AlGaN; thus, the first semiconductor layer 31 and the second semiconductor layer 32 form a GaN/AlGaN superlattice structure.
  • GaN materials have very good electron field emission properties, mainly characterized by large band gap, low electron affinity, high chemical and mechanical stability, and poor sputter corrosion. Therefore, they can be used as emitters of field emission devices.
  • the material of layer 3 is such that the emitter layer 3 of the field emission device has a long emission lifetime; and the GaN-based superlattice structure has extremely strong spontaneous polarization and piezoelectric polarization; in addition, GaN/AlGaN supercrystal
  • the lattice structure contains alloys with different valence bands, which improves the band characteristics, and the periodic oscillation of the valence band edge also increases the number of carriers.
  • the material of the collector layer 8 is a metal electrode material, such as Cr/Mo or Mo, which may be laminated.
  • the height of the collector layer 8 is higher than the height of the emitter layer 3; that is, the top surface of the collector layer 8. It is higher than the top surface of the emitter layer 3.
  • the material of the buffer layer 2 is high-resistance GaN; the material of the gate dielectric layer 4 is a silicon-nitrogen compound; the material of the ohmic contact 6 is Ti/Al/Ni/Au which are sequentially stacked; The material of the pole 7 is a laminated Cr/Au.
  • both the ohmic contact 6 and the gate 7 extend and cover a portion of the ion implantation layer 5.
  • the field emission device of the present embodiment can be widely applied to the field of vacuum microelectronics, and the field emission device can operate at atmospheric pressure without vacuum packaging.
  • the field emission device of the present embodiment was subjected to transmission electron microscopy (SEM), which The test results are shown in Figure 4.
  • SEM transmission electron microscopy
  • the left side is the emitter layer 3 of the field emission device
  • the right side is the collector layer 8 of the field emission device
  • the width between the emitter layer 3 and the collector layer 8 is about 45 nm; that is, in the field emission device, the channel A has a pitch of 45 nm, which can ensure the normal use of the field emission device.
  • V g is the IV curve when 0V.
  • the two ordinates are used; the left ordinate is the collector current I c and the right ordinate is the collector current I c .
  • Logarithm base 10
  • the turn-on voltage of the field emission device is about 2.6V.
  • FIG. 6 is a transfer characteristic curve of the field emission device of the present embodiment. As can be seen from FIG. 6, when the gate voltage V g is greater than a threshold voltage of ⁇ 13.15 V, the collector current I c is significantly increased, and the gate leakage I g is approximately It is 5pA.
  • FIG. 7 is an output characteristic curve of the field emission device of the present embodiment. As can be seen from FIG. 7, when the gate voltage V g is -13 V and the collector voltage V c is 4 V, the transmissive g m of the field emission device is shown. It can be calculated to be about 400 ⁇ S according to the formula (1).
  • the field emission device of the present embodiment has a low gate leakage, and the gate 7 has a good current control effect on the collector layer 8 as a collector, and the device performance is good.
  • This embodiment discloses a method of fabricating the field emission device described in Embodiment 1.
  • the method of fabricating the field emission device according to the present embodiment includes the following steps:
  • the material of the substrate 1 may be selected from materials such as sapphire, GaN, SiC, etc.; the material of the buffer material layer 2a is preferably high resistance GaN.
  • the first semiconductor material layer 31a and the second semiconductor layer 32a constitute the emitter material layer 3a; the interface between the first semiconductor layer 31a and the second semiconductor layer 32a can form a two-dimensional electron gas Structure 311, the two-dimensional electron gas structure 311 can be used as the emission tip of the subsequently obtained emitter layer, thereby avoiding the requirement of the emission end face angle of the emitter layer.
  • the materials of the first semiconductor material layer 31a and the second semiconductor material layer 32a are not limited to those described in the embodiment, and the material of the first semiconductor material layer 31a may be GaAs, corresponding to the second semiconductor material layer 32a.
  • the material is AlGaAs; or the material of the first semiconductor material layer 31a is InAs, and the material corresponding to the second semiconductor material layer 32a is GaSb.
  • the deposition method, thickness and type of the gate dielectric material layer 4a can be adjusted according to the specific requirements of the process, and those skilled in the art can refer to the prior art.
  • the material of the gate dielectric material layer 4a is a silicon nitride compound.
  • patterning is performed by a photolithography process, and ion implantation is performed on the buffer material layer 2a, the emitter material layer 3a, and the gate dielectric material layer 4a in an ion implantation process to form an active region; then, the wet method The photoresist remaining at the time of ion implantation is removed, and the ion implantation layer 5 as shown in FIG. 9 is formed.
  • the arrangement of the ion implantation layer 5 can ensure effective isolation of the active region located inside thereof and the peripheral material, so that the subsequently prepared gate can well control the working state during operation and reduce the leakage phenomenon.
  • an ohmic contact 5 is prepared on the second semiconductor layer 32, and a gate electrode 6 is formed on the gate dielectric layer 4; as shown in FIGS. 10 and 11.
  • the ohmic contact 5 preferably extends and covers a portion of the ion implantation layer 5.
  • a portion of the gate dielectric layer 4 is removed by a dry etching process to partially expose the second semiconductor layer 32; then, a Ti/Al/Ni/Au deposition and lift-off process is sequentially performed, in the second semiconductor layer 32.
  • An ohmic contact 5 as in FIG. 10 is formed on the ion implantation layer 5.
  • the material of the ohmic contact 5 may be based on the specific material of the second semiconductor layer 32. It is determined that, at the same time, the specific preparation process of the ohmic contact 5 can be determined according to whether it needs to be annealed, and details are not described herein, and those skilled in the art can refer to the prior art.
  • the gate electrode 6 also preferably extends and covers a portion of the ion implantation layer 5.
  • gate metal Cr/Au photolithography, deposition, and lift-off of the gate metal Cr/Au are performed on the gate dielectric layer 4 and the ion implantation layer 5 to form the gate electrode 6 as shown in FIG.
  • the portion of the ion implantation layer 5 is removed to form a notch 51 such that the end faces of the first semiconductor layer 31, the second semiconductor layer 32, and the gate dielectric layer 4 are exposed by the notches 51;
  • the exposed end faces of the first semiconductor layer 31 and the second semiconductor layer 32 form the emission end face B; and the top surface of the gate dielectric layer 4, the side end face of the gate dielectric layer 4, the emission end face B, and the gap of the ion implantation layer 5 At 51, a "stepped" structure is formed.
  • the emission end face B includes at least a portion of the first semiconductor layer 31 adjacent to each other facing the end surface of the notch 51 and an end surface of at least a portion of the second semiconductor layer 32 facing the notch.
  • a part of the active region and a portion of the ion implantation layer 5 connected to the portion of the active region can be generally formed by photolithography and etching processes. The removal is performed together so that the end faces of the first semiconductor layer 31, the second semiconductor layer 32, and the gate dielectric layer 4 are exposed together.
  • the emission end face B may not have a requirement for its angle.
  • the angle of the emission end face B in this embodiment is 180°, that is, a horizontal shape. .
  • the thickness of the dielectric film layer 9 is controlled to not exceed 100 nm.
  • the dielectric film layer 9 is deposited at the notch 51 of the ion implantation layer 5 and the surface of the gate dielectric layer 4 by an atomic layer deposition process (abbreviated as ALD process), so that the dielectric film layer 9 covers the steps formed above. .
  • ALD process atomic layer deposition process
  • a collector layer 8 is prepared at the notch 51 of the ion implantation layer 5; as shown in FIG.
  • the collector layer 8 is opposed to the emission end surface B.
  • the collector layer 8 is in contact with the upper surface portion of the first semiconductor layer 31, but its contact has little effect on the performance of the finally obtained field emission device.
  • the collector layer 8 is prepared in a region where the ion implantation layer 5 is removed by a photolithography, plating, and lift-off process; the material of the collector layer 8 is a metal electrode material, such as a laminated metal electrode material such as Cr/Au. It may also be a single-layer metal electrode material such as Mo.
  • the top surface height of the collector layer 8 is ensured to be higher than that of the emitter. The top surface of layer 3.
  • the dielectric film layer 9 is removed, and a channel A is formed between the emitter layer 3 and the collector layer 8.
  • the dielectric film layer 9 between the emitter layer 3 and the collector layer 8 is removed by a wet etching process, so that a channel A is formed between the emitter layer 3 and the collector layer 8 as an air channel. That is, the field emission device shown in Fig. 1 was obtained.
  • the pitch of the formed channel A is the thickness of the dielectric film layer 9 described above, which is smaller than the mean free path of electrons in the air, so that the electron emission of the finally obtained field emission device is not affected when operating under atmospheric pressure, which ensures Device performance.
  • Figure 15 is a schematic view showing the structure of a field emission device according to this embodiment.
  • a field emission device includes a substrate 10, a buffer layer 20 disposed over the substrate 10, and an emitter layer 30 and a metal collector layer 40 respectively disposed over both ends of the buffer layer 20. a first electrode layer 101 disposed over the emitter layer 30 and a second electrode layer 102 disposed over the metal collector layer 40, wherein the channel 100 is disposed between the emitter layer 30 and the metal collector layer 40
  • the metal collector layer 40 employs a Cr/Au composite film electrode or a Mo film electrode.
  • the substrate 10 may be made of, for example, sapphire, GaN or SiC material or the like; the buffer layer 20 may be made of a high-resistance GaN material. In this embodiment, preferably, the substrate 10 is made of GaN. As the material, the buffer layer 20 may be a Fe-doped high-resistance GaN material.
  • the emitter layer 30 adopts a GaN-based superlattice structure or a GaN multilayer heterostructure or a GaN highly doped structure.
  • the emitter layer 30 may also adopt other semiconductor materials. This is not intended to limit the invention.
  • the emitter layer 30 has a pointed convex portion 30a toward one side of the metal collector layer.
  • the metal collector layer 40 has a pointed concave portion 40a corresponding to one side of the emitter layer 30, wherein the pointed convex portion 30a is disposed in cooperation with the pointed concave portion 40a, and is formed between the pointed convex portion 30a and the pointed concave portion 40a.
  • the collector layer of the field emission device of the present embodiment is made of a metal material, when the pointed convex portion 30a adopts an arbitrary angle, the pointed concave portion 40a can correspond thereto, so that the shape and the emitter layer of the metal collector layer 40 are made.
  • the shape of 30 is well matched.
  • the angle of the apex angle of the pointed convex portion 30a is a, 0° ⁇ a ⁇ 90°, preferably 0° ⁇ a ⁇ 60°.
  • the first metal electrode layer 101 and the second metal electrode layer 102 each use a metal material that forms good ohmic contact with the emitter layer 30 and the metal collector layer 40, such as a Ti/Al/Ni/Au material system, etc., in other embodiments.
  • the first metal electrode layer 101 and the second metal electrode layer 102 may also be AuGe/Ni/Au or Ni/Au depending on the material of the emitter and the collector.
  • 16 to 23 are process flow charts of a method of fabricating a field emission device according to the present embodiment.
  • a buffer layer 20 is formed on a substrate 10.
  • the substrate 10 may be, for example, a sapphire, GaN or SiC material or the like.
  • the buffer layer 20 may be a high resistance GaN material.
  • the buffer layer 20 may be a Fe-doped high resistance GaN material.
  • an emitter material layer 50 is formed on the buffer layer 20. Due to the very good electron field emission properties of GaN materials, the main performance is the forbidden band width and electron affinity. It has the advantages of low potential, high chemical and mechanical stability, and low sputter corrosion, so it can be used as the emitter of a field emission device, so that the emitter of the field emission device has a long emission lifetime. Therefore, in the embodiment, the emitter material layer 50 adopts a GaN-based superlattice structure or a GaN multilayer heterostructure or a GaN highly doped structure. Of course, in other embodiments, the emitter material layer 50 may also adopt other Semiconductor materials are not used herein to limit the invention.
  • the emitter material layer 50 is etched so that at least one pointed convex portion 30a is formed on one side of the emitter material layer 50, and the emitter layer 30 formed on one side of the buffer layer 20 is obtained.
  • the photoresist which can be deposited on the emitter 50 electrode material layer of SiO 2 dielectric layer 105, the photoresist as a mask dry etching SiO 2 dielectric film 105, SiO 2 dielectric film layer so that the remaining portion of the pattern 105 is formed Then, the photoresist is removed by wet method, and the emitter material layer 50 is dry-etched by using the remaining portion of the SiO 2 dielectric film layer 105 as a mask to form at least one sharp protrusion on the side of the emitter material layer 50.
  • the portion 30a obtains the emitter layer 30 formed on the side of the buffer layer 20.
  • a dielectric film layer 103 is deposited to completely cover the emitter layer 30, the remaining portion of the SiO 2 dielectric film layer 105, and the buffer layer 20 exposed in Fig. 2c.
  • the dielectric film layer 103 may be made of a SiO 2 material.
  • the "emitter layers 30, the remaining portion of the silicon dioxide dielectric layer 105 completely covers” means that the surface of the remaining portion of the SiO 2 dielectric layer 105 and the respective side surfaces of the emitter layer 30 and the Each side surface is covered by the dielectric film layer 103.
  • the dielectric film layer 103 on the exposed buffer layer 20 is etched away.
  • a metal collector layer 40 is formed on the exposed buffer layer 20 such that the metal collector layer 40 corresponds to the emitter layer 30, and the metal collector layer 40 faces the side of the emitter layer 30. There is a pointed recess 40a corresponding to the pointed convex portion 30a. Further, the metal collector layer 40 is a Cr/Au composite film electrode or a Mo film electrode.
  • the remaining portion of the SiO 2 dielectric film layer 105 and the dielectric film layer 103 completely covering the emitter layer 30 are removed by a wet etching process.
  • the dielectric film layer 103 on both side faces where the pointed convex portion 30a is formed is removed, a non-linear channel is formed between the two side faces forming the pointed convex portion 30a and the two side faces forming the pointed concave portion 40a. 100.
  • a first metal electrode 101 and a second metal electrode 102 are formed on the emitter layer 30 and the metal collector layer 40, respectively.
  • the first metal electrode layer 101 and the second metal electrode layer 102 each employ a metal material that forms good ohmic contact with the emitter layer 30 and the metal collector layer 40, such as a Ti/Al/Ni/Au material system, etc., in other
  • the first metal electrode layer 101 and the second metal electrode layer 102 may also be AuGe/Ni/Au or Ni/Au depending on the material of the emitter and the collector.
  • the present embodiment is different from Embodiment 3 in that the side end of the emitter layer 30 has a plurality of pointed portions 30a, and correspondingly, the metal collector layer 40 has a plurality of tips on one side of the emitter layer 30.
  • the concave portion 40a, the plurality of pointed convex portions 30a and the plurality of pointed concave portions 40a are formed in a zigzag shape, and the manufacturing method of the field emission device of the present embodiment is the same as that of the third embodiment, and details are not described herein again.
  • the collectors of the field emission devices of Embodiment 3 and Embodiment 4 of the present invention are made of a metal material, and the angle of the convex portion of the emitter can be designed to an arbitrary angle according to the performance of the field emission device, and since the collector is used
  • the metal material does not require the addition of a mask when forming a nano-pitch in the wet etching dielectric film layer, which simplifies the process, reduces the cost, and improves the performance.

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Abstract

一种场发射器件，包括叠层设置的衬底（1）和缓冲层（2）；缓冲层（2）上设置有发射极层（3），发射极层（3）包括依次叠层设置的第一半导体层（31）和第二半导体层（32）；缓冲层（2）上还设置有使发射极层（3）嵌入其中的离子注入层（5），离子注入层（5）具有一缺口（51），以使发射极层（3）的发射端面（B）从缺口（51）处暴露出，发射端面（B）包括相互邻接的至少部分第一半导体层的端面以及至少部分第二半导体层的端面；离子注入层（5）的缺口（51）处设置有集电极层（8），集电极层（8）的端面与发射端面（B）相对并且两者之间具有沟道（A）；发射极层（3）上还依次叠层设置有栅介质层（4）和栅极（7）。该场发射器件具有横向结构且具有纳米空气沟道（A）。

Description

场发射器件及其制作方法 技术领域
本发明属于半导体技术领域，具体地讲，涉及一种场发射器件及其制作方法。
背景技术
场发射器件在真空微电子(包括超高速高频器件、场发射显示器和微波放大器等)方面有着广泛的应用，场发射阴极作为真空微电子器件的核心而倍受关注。要实现优异的场发射特性，主要通过降低场发射阴极的电子亲和势以及采用纳米结构提高场增强因子来实现。其中，半导体材料因其成熟的微纳加工制造技术，近年来成为场发射阴极材料研究的一个热点领域。
在半导体材料中，某些半导体材料具有低的电子亲和势或者负电子亲和势，如GaN的电子亲和势约2.7eV～3.3eV，极可能致使在异质结构中形成较低发射势垒，且半导体材料N型掺杂容易实现高的电子浓度，是理想的场发射阴极材料。
在场发射器件中，横向结构场发射器件可以通过微纳加工实现发射阴极-集电极之间距离的控制，且横向结构场发射器件比垂直结构场发射器件更容易集成。但是，由于横向结构场发射器件需要经过后续复杂工艺来实现，因此，如何实现横向结构场发射器件对未来器件的制备和应用都至关重要。在横向场发射器件的制作过程中，如何实现纳米级阴极与阳极间距以及通过栅极实现场发射器件的开关控制为成为器件制备的关键工艺。
发明内容
为解决上述现有技术存在的问题，本发明提供了一种场发射器件及其制作方法，该场发射器件为一具有横向结构的场发射器件，具有 更高的增强因子。
为了达到上述发明目的，本发明采用了如下的技术方案：
一种场发射器件，包括衬底和设置在所述衬底上的缓冲层；所述缓冲层上设置有发射极层，所述发射极层包括依次叠层设置的第一半导体层和第二半导体层；所述缓冲层上还设置有离子注入层，所述发射极层嵌入所述离子注入层中，且所述离子注入层具有一缺口，以使所述发射极层的发射端面从所述缺口处暴露出，所述发射端面包括相互邻接的至少部分第一半导体层的端面以及至少部分第二半导体层的端面；所述离子注入层的缺口处设置有集电极层，所述集电极层的端面与所述发射端面相对并且两者之间具有沟道；所述发射极层上还依次叠层设置有栅介质层和栅极。
进一步地，所述第一半导体层和所述第二半导体层的连接界面处形成二维电子气结构。
进一步地，所述第一半导体层的材料为GaN，所述第二半导体层的材料为AlGaN；或所述第一半导体层的材料为GaAs，所述第二半导体层的材料为AlGaAs；或所述第一半导体层的材料为InAs，所述第二半导体层的材料为GaSb。
进一步地，所述集电极层的材料为金属电极材料。
进一步地，所述发射端面的角度为0°～180°。
进一步地，所述集电极层的顶面高于所述发射极层的顶面。
进一步地，所述沟道的宽度不超过100nm。
本发明的另一目的在于提供一种如上任一所述的场发射器件的制作方法，包括：在衬底上依次形成缓冲材料层、发射极材料层和栅介质材料层；其中，所述发射极材料层包括依次叠层设置的第一半导体材料层和第二半导体材料层；对所述缓冲材料层、发射极材料层、栅介质材料层进行离子注入，形成缓冲层、位于所述缓冲层上的离子注入层、以及依次叠层设置在所述缓冲层上的发射极层和栅介质层；所述离子注入层环绕在所述发射极层和栅介质层的四周；在所述栅介 质层上制备栅极；去除部分所述离子注入层形成一缺口，以使所述发射极层的发射端面从所述缺口处暴露出，所述发射端面包括连续的第一区域和第二区域，所述第一区域位于所述第一半导体层的端面，所述第二区域位于所述第二半导体层的端面；制备介质膜层，使得所述介质膜层完全覆盖所述发射端面；在所述离子注入层的缺口处制备集电极层，所述集电极层的端面与所述发射端面相对；去除所述介质膜层，在所述发射极层与所述集电极层之间形成所述沟道。
进一步地，所述介质膜层的厚度不超过100nm。
进一步地，在去除部分所述离子注入层时，部分所述栅介质层和部分所述发射极层被一并去除，所述集电极层与所述第一半导体层相接触。
本发明的第三目的在于提供一种场发射器件，包括衬底、设置在所述衬底上的缓冲层、分别设置在所述缓冲层两端的发射极层和金属集电极层、分别设置在所述发射极层和所述金属集电极层上的电极层，其中，所述发射极层与所述金属集电极层之间具有沟道。
进一步地，所述金属集电极层采用Cr/Au复合薄膜电极或Mo薄膜电极。
进一步地，所述发射极层朝向所述金属集电极层一侧具有至少一个尖凸部，所述金属集电极层朝向所述发射极层的一侧对应具有至少一个尖凹部，所述尖凸部与所述尖凹部配合设置使得所述沟道呈非直线状。
进一步地，每个所述尖凸部的顶角角度为a，0°＜a≤90°。
进一步地，所述发射极层采用GaN基超晶格结构或GaN多层异质结构或GaN高掺杂结构。
进一步地，所述电极层采用Ti/Al/Ni/Au复合薄膜电极。
进一步地，所述衬底采用的材料为蓝宝石或GaN或SiC。
本发明的第四目的在于提供一种如上所述的场发射器件的制作方法，其特征在于，包括步骤：在衬底上形成缓冲层；在缓冲层上形 成发射极材料层；刻蚀所述发射极材料层，以使所述发射极材料层一侧形成至少一尖凸部，获得形成在所述缓冲层一侧的所述发射极层；沉积介质膜层，以将所述发射极层完全覆盖；对应于所述发射极层、在所述缓冲层另一侧形成金属集电极层，以使得所述金属集电极层朝向所述发射极层的一侧具有与所述尖凸部对应的尖凹部；湿法腐蚀去除所述介质膜层，以使所述发射极层与所述金属集电极层之间形成沟道；在所述发射极层和所述金属集电极层上分别形成所述电极层。
进一步地，所述金属集电极层采用Ti/Au复合薄膜电极或Mo薄膜电极。
进一步地，每个所述尖凸部的顶角角度为a，0°＜a≤90°。
进一步地，所述发射极材料层采用GaN基超晶格结构或GaN多层异质结构或GaN高掺杂结构。
进一步地，所述电极层材质采用Ti/Al/Ni/Au金复合薄膜电极。
进一步地，所述衬底采用的材料为蓝宝石或GaN或SiC。
本发明提供了一种具有横向场发射、且间距纳米级空气沟道的场发射器件，该场发射器件中的发射端面能够呈0°～180°之间的任意角度。在该场发射器件中，一方面第一半导体层和第二半导体层的界面处所形成的二维电子气能够提高该场发射器件的增强因子，另一方面栅极可利用该二维电子气来控制器件的开关；同时，通过离子注入层的隔离作用实现了有源区的有效隔离，减少漏电流的产生。
本发明还提供了另一种场发射器件，其中的集电极层采用金属材质，可以根据场发射器件的性能将发射极的尖凸部角度设计为任意角度，而且，由于所述集电极层采用的是金属材质，在湿法腐蚀介质膜层形成纳米间距时不需要添加掩膜，简化了工艺、降低了成本、提高了性能。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例1的场发射器件的剖面结构示意图；
图2是图1中的场发射器件在去除集电极层后的局部结构示意图；
图3是图1中X区域的局部放大图；
图4是根据本发明的实施例1的场发射器件的SEM图片；
图5是根据本发明的实施例1的场发射器件在栅电压为0V时的I-V曲线；
图6是根据本发明的实施例1的场发射器件的转移特征曲线；
图7是根据本发明的实施例1的场发射器件的输出特性曲线；
图8-图14是根据本发明的实施例2的场发射器件的制作方法的工艺流程图；
图15是根据本发明的实施例3的场发射器件的结构示意图；
图16-图23是根据本发明的实施例3的场发射器件的制作方法的工艺流程图；
图24是根据本发明的实施例4的场发射器件的结构示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。在附图中，为了清楚起见，可以夸大元件的形状和尺寸，并且相同的标号将始终被用于表示相同或相似的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
实施例1
图1是根据本实施例的场发射器件的结构示意图，图2是图1中的场发射器件在去除集电极层后的局部结构示意图，图3是图1中X区域的局部放大图。
参照图1-图3，根据本实施例的场发射器件包括：衬底1、依次叠层设置在衬底1上的缓冲层2、发射极层3、栅介质层4，设置在缓冲层2上并环绕在发射极层3、栅介质层4四周的离子注入层5；设置在发射极层3上的欧姆接触6；设置在栅介质层4上的栅极7；以及设置在离子注入层5上的集电极层8。
其中，离子注入层5在环绕发射极层3时具有一缺口51，该发射极层3的发射端面B从该缺口51处暴露出。
具体来讲，发射极层3包括依次叠层设置的第一半导体层31和第二半导体层32，而该发射端面B包括相互邻接的至少部分第一半导体层31的端面以及至少部分第二半导体层32的端面。也就是说，由缺口51处暴露出的发射端面B要包括相互邻接的第一区域(图中未示出)和第二区域(图中未示出)，其中第一区域位于第一半导体层31朝向缺口51处的端面上，而第二区域位于第二半导体层32朝向缺口51处的端面上。
相应地，集电极层8具有与发射端面B相对的端面，且在两个端面之间具有一沟道A；也就是说，在发射极层3与集电极层8之间即形成沟道A。
在本实施例中，该沟道A是一种空气沟道，且其间距不超过100nm。如此，该沟道A的间距即小于电子在空气中的平均自由程，从而使得该场发射器件在大气压下工作时电子的传输不受影响，保证器件的良好性能。
第一半导体层31和第二半导体层32的连接界面处形成二维电子气，该二维电子气的结构即可用作发射极层3的发射尖端，如此，即可将发射端面B的角度设置成0°～180°的任意角度，而无需设置为30°、60°等具有较小角度的尖锐的形状。同时，该二维电子气还保证了栅极7可利用其来控制该场发射器件的开关。
在本实施例中，为了简化制作工艺，该发射端面B的角度为180°，也就是说，该发射端面B呈一平面状。
与上述二维电子气相对应地，第一半导体层31的材料为GaN，第二半导体层32的材料为AlGaN；或第一半导体层31的材料为GaAs，第二半导体层32的材料为AlGaAs；或第一半导体31层的材料为InAs，第二半导体层32的材料为GaSb。
在本实施例中，第一半导体层31的材料为GaN，第二半导体层32的材料为AlGaN；如此，第一半导体层31和第二半导体层32即形成了GaN/AlGaN超晶格结构。GaN材料具有非常好的电子场发射性能，主要表现为禁带宽度大、电子亲和势低、化学和力学稳定性高以及不易产生溅射腐蚀等优点，因此其可以作为场发射器件的发射极层3的材料，以使场发射器件的发射极层3具有较长的发射寿命；并且GaN基超晶格结构具有极强的自发极化和压电极化现象；此外，GaN/AlGaN超晶格结构包含着具有不同价带的合金，从而改善了能带特性，价带边缘的周期性振荡也增加了载流子的数目。
具体地，集电极层8的材料为金属电极材料，如可以是叠层设置的Cr/Mo或Mo等。
为了保证场发射过程中集电极层8能够有效地收集由发射极层3发出的电子，集电极层8的高度要高于发射极层3的高度；也就是说，集电极层8的顶面要高于发射极层3的顶面。
具体地，在本实施例中，缓冲层2的材料为高阻GaN；栅介质层4的材料为硅氮化合物；欧姆接触6的材料为依次叠层设置的Ti/Al/Ni/Au；栅极7的材料为叠层设置的Cr/Au。
优选地，欧姆接触6和栅极7均延伸并覆盖部分离子注入层5。
本实施例的场发射器件可以广泛地应用于真空微电子领域，同时该场发射器件无需真空封装即可在大气压下工作。
对本实施例的场发射器件的性能进行了表征与测试。
对本实施例的场发射器件进行了透射电镜测试(简称SEM)，其 测试结果如图4所示。从图4中可以看出，左侧为该场发射器件的发射极层3，而右侧为该场发射器件的集电极层8，发射极层3与集电极层8之间的宽度约为45nm；也就是说，在该场发射器件中，沟道A的间距为45nm，能够保证该场发射器件的正常使用。
图5为本实施例的场发射器件在栅电压Vg为0V时的I-V曲线。为了更清晰地表明集电极电流Ic的大小，在图5中，采用双纵坐标的方式来表示；左侧纵坐标为集电极电流Ic，右侧纵坐标为该集电极电流Ic的对数(以10为底)。从图5中可以看出，该场发射器件的开启电压约为2.6V。
图6为本实施例的场发射器件的转移特征曲线，从图6中可以看出，当栅电压Vg大于-13.15V的阈值电压时，集电极电流Ic明显增加，栅漏电Ig约为5pA。
图7为本实施例的场发射器件的输出特性曲线，从图7中可以看出，当栅电压Vg为-13V、集电极电压Vc为4V时，该场发射器件的跨导gm可根据式(1)算得约为400μS。
gm＝dIc/VVg       (1)
由此可以看出，本实施例的场发射器件栅漏电较低，栅极7对作为收集极的集电极层8的电流控制作用良好，器件性能良好。
实施例2
本实施例公开了实施例1所述的场发射器件的制作方法。
具体参照图8-图14，根据本实施例的场发射器件的制作方法包括如下步骤：
S1、在衬底1上依次制备缓冲材料层2a、第一半导体材料层31a、第二半导体材料层32a和栅介质材料层4a；如图8。
在本实施例中，衬底1的材料可选自蓝宝石、GaN、SiC等材料；缓冲材料层2a的材料优选为高阻GaN。
第一半导体材料层31a和第二半导体层32a组成发射极材料层3a；第一半导体层31a和第二半导体层32a的界面处能够形成二维电子气 结构311，该二维电子气结构311即可作为后续获得的发射极层的发射尖端，从而免于对发射极层的发射端面角度的要求。当然，第一半导体材料层31a和第二半导体材料层32a的材料并不限于本实施例中所述，如还可以是第一半导体材料层31a的材料为GaAs，对应第二半导体材料层32a的材料为AlGaAs；或第一层半导体材料层31a的材料为InAs，对应第二半导体材料层32a的材料为GaSb。
具体来讲，栅介质材料层4a的沉积方法、厚度和种类可根据工艺具体要求进行调整，本领域技术人员参照现有技术即可。在本实施例中，栅介质材料层4a的材料为硅氮化合物。
S2、对缓冲材料层2a、发射极材料层3a、栅介质材料层4a进行离子注入，形成缓冲层2、位于缓冲层2上的离子注入层5、以及依次叠层设置在缓冲层2上的发射极层3和栅介质层4，离子注入层5环绕在发射极层3和栅介质层4的四周；发射极层3包括依次叠层设置在缓冲层2上的第一半导体层31和第二半导体层32；如图9。
具体地，首先，采用光刻工艺图形化，并结合离子注入工艺对缓冲材料层2a、发射极材料层3a、栅介质材料层4a的四周进行离子注入，隔离形成有源区；然后，湿法去除离子注入时残留的光刻胶，形成了如图9所示的离子注入层5。
离子注入层5的设置可以保证位于其内部的有源区与外围材料的有效隔离，从而使后续制备的栅极能够良好地控制工作时的工作状态，减少漏电的不良现象。
S3、在第二半导体层32上制备欧姆接触5，在栅介质层4上制备栅极6；如图10和图11。
在本实施例中，欧姆接触5优选延伸并覆盖部分离子注入层5。
具体地，首先，采用干法刻蚀工艺去除部分栅介质层4，使得第二半导体层32部分外露；然后，依次进行Ti/Al/Ni/Au的沉积和剥离工艺，在第二半导体层32和离子注入层5上形成如图10中的欧姆接触5。
当然，欧姆接触5的材料可根据第二半导体层32的具体材料来 确定，同时，欧姆接触5的具体制备工艺可根据其是否需进行退火而确定，此处不再赘述，本领域技术人员参照现有技术即可。
在本实施例中，栅极6也优选延伸并覆盖部分离子注入层5。
更为具体地，在栅介质层4及离子注入层5上进行栅金属Cr/Au的光刻、沉积和剥离，形成如图11中的栅极6。
S4、去除部分离子注入层5形成一缺口51，使得第一半导体层31、第二半导体层32和栅介质层4的端面由缺口51处外露；如图12。
如此，外露的第一半导体层31和第二半导体层32的端面即形成发射端面B；而栅介质层4的顶面、栅介质层4的侧端面、发射端面B以及离子注入层5的缺口51处即形成一“台阶状”的结构。
也就是说，发射端面B包括相互邻接的至少部分第一半导体层31朝向缺口51的端面以及至少部分第二半导体层32朝向缺口的端面。
考虑到工艺需求，一般难以恰好将上述区域处的离子注入层5完全去除，因此一般可通过光刻和刻蚀工艺将部分有源区及与该部分有源区相连接的部分离子注入层5一并去除，以使第一半导体层31、第二半导体层32和栅介质层4的端面一并露出。
鉴于上述二维电子气结构311的作用，此时发射端面B即对其角度可没有要求，为简化工艺，本实施例中该发射端面B的角度为180°，也就是说，呈一水平状。
S5、制备介质膜层9，使得介质膜层9完全覆盖发射端面B；如图13。
一般地，控制介质膜层9的厚度不超过100nm。
在本实施例中，采用原子层沉积工艺(简称ALD工艺)在离子注入层5的缺口51处以及栅介质层4的表面延伸沉积介质膜层9，使得该介质膜层9覆盖上述形成的台阶。
S6、在离子注入层5的缺口51处制备集电极层8；如图14。
如此，集电极层8的一个端面与发射端面B相对。在本实施例中，集电极层8与第一半导体层31的上表面部分接触，但其是否接触对最终获得的场发射器件的性能影响不大。
具体地，采用光刻、镀膜、剥离的工艺在去除了离子注入层5的区域制备集电极层8；集电极层8的材料为金属电极材料，如可以是Cr/Au等叠层金属电极材料，也可以是Mo等单层金属电极材料。
为了在场发射过程中集电极层8能够更为有效地收集由发射极层3的发射端面B发出的电子，在制备集电极层8时，保证集电极层8的顶面高度要高于发射极层3的顶面。
S7、去除介质膜层9，在发射极层3与集电极层8之间形成沟道A。
通过湿法腐蚀工艺去除位于发射极层3及集电极层8之间的介质膜层9，如此，即在发射极层3与集电极层8之间形成了沟道A，以作为空气沟道；即制作获得了如图1所示的场发射器件。
该形成的沟道A的间距即为上述介质膜层9的厚度，其小于电子在空气中的平均自由程，使得最终获得的场发射器件在大气压下工作时电子的传输不受影响，保证了器件性能。
实施例3
图15根据本实施例的场发射器件的结构示意图。
参照图15，根据本实施例的场发射器件包括衬底10、设置在衬底10之上的缓冲层20、分别设置在缓冲层20两端之上的发射极层30和金属集电极层40、设置在发射极层30之上的第一电极层101和设置在金属集电极层40之上的第二电极层102，其中，发射极层30与金属集电极层40之间具有沟道100，以实现大气压下的电子的弹道运输，优选地，所述金属集电极层40采用Cr/Au复合薄膜电极或Mo薄膜电极。
其中，衬底10可例如采用蓝宝石、GaN或SiC材料等；缓冲层20可采用高阻GaN材料。本实施例中，优选地，衬底10采用GaN 材料，缓冲层20可采用掺Fe的高阻GaN材料。
GaN材料具有非常好的电子场发射性能，主要表现为禁带宽度大、电子亲和势低、化学和力学稳定性高以及不易产生溅射腐蚀等优点，因此其可以作为场发射器件的发射极，以使场发射器件的发射极具有较长的发射寿命。所以，在本实施例中，发射极层30采用GaN基超晶格结构或GaN多层异质结构或GaN高掺杂结构，当然在其他实施例中，发射极层30也可以采用其他半导体材料，这里不用于对本发明进行限定。
此外，由于发射极层30与金属集电极层40的形状影响阈值电压的大小，所以在本实施例中，优选地，发射极层30朝向所述金属集电极层的一侧具有尖凸部30a，所述金属集电极层40朝向所述发射极层30的一侧对应具有尖凹部40a，其中，尖凸部30a与尖凹部40a配合设置，并且在尖凸部30a与尖凹部40a之间形成非直线型沟道100。由于本实施例中场发射器件的集电极层采用的是金属材质，在尖凸部30a采用任意角度时，尖凹部40a都可以与之对应，从而使得金属集电极层40的形状与发射极层30的形状很好的配合，为了提升场发射器件的性能，优选地，尖凸部30a的顶角的角度为a，0°＜a≤90°，优选地，0°＜a≤60°。
第一金属电极层101和第二金属电极层102均采用与发射极层30和金属集电极层40形成良好欧姆接触的金属材料，例如Ti/Al/Ni/Au材料系等，在其他实施例中，根据发射极以及集电极的材料，第一金属电极层101和第二金属电极层102也可以采用AuGe/Ni/Au或Ni/Au。
图16至图23是根据本实施例的场发射器件的制作方法的工艺流程图。
在图16中，在衬底10上形成缓冲层20。这里，衬底10可例如采用蓝宝石、GaN或SiC材料等。缓冲层20可采用高阻GaN材料，优选地，缓冲层20可采用掺Fe的高阻GaN材料。
在图17中，在缓冲层20上形成发射极材料层50。由于GaN材料具有非常好的电子场发射性能，主要表现为禁带宽度大、电子亲和 势低、化学和力学稳定性高以及不易产生溅射腐蚀等优点，因此其可以作为场发射器件的发射极，以使场发射器件的发射极具有较长的发射寿命。所以，在本实施例中，发射极材料层50采用GaN基超晶格结构或GaN多层异质结构或GaN高掺杂结构，当然在其他实施例中，发射极材料层50也可以采用其他半导体材料，这里不用于对本发明进行限定。
在图18中，刻蚀发射极材料层50，以使所述发射极材料层50一侧形成至少一尖凸部30a，获得形成在所述缓冲层20一侧的所述发射极层30。
其中，可以在发射极材料层50上沉积一层SiO2介质膜层105，以光刻胶为掩膜干法刻蚀SiO2介质膜层105，使得剩余部分的SiO2介质膜层105形成图案，然后湿法去除光刻胶，再以剩余部分的SiO2介质膜层105作为掩膜，干法刻蚀发射极材料层50，以使所述发射极材料层50一侧形成至少一尖凸部30a，获得形成在所述缓冲层20一侧的所述发射极层30。
在图19中，沉积介质膜层103，以将发射极层30、剩余部分SiO2介质膜层105和图2c中暴露的缓冲层20完全覆盖。这里，介质膜层103可采用SiO2材料。此外，所述“将发射极层30、剩余部分二氧化硅介质膜层105完全覆盖”是指所述剩余部分SiO2介质膜层105的上表面和各个侧表面以及所述发射极层30的各个侧表面均被介质膜层103所覆盖。
在图20中，将暴露的缓冲层20上的介质膜层103刻蚀去除掉。
在图21中，在暴露的缓冲层20上形成金属集电极层40，以使得所述金属集电极层40与所述发射极层30对应，金属集电极层40朝向发射极层30的一侧具有与所述尖凸部30a对应的尖凹部40a。此外，金属集电极层40采用Cr/Au复合薄膜电极或Mo薄膜电极。
在图22中，采用湿法腐蚀工艺将完全覆盖发射极层30的剩余部分SiO2介质膜层105以及介质膜层103去除。这里，由于将形成尖凸部30a的两个侧面上的介质膜层103去除掉，因此，形成尖凸部30a的两个侧面与形成尖凹部40a的两个侧面之间形成非直线型沟道 100。
在图23中，在发射极层30和金属集电极层40上分别形成第一金属电极101和第二金属电极102。这里，第一金属电极层101和第二金属电极层102均采用与发射极层30和金属集电极层40形成良好欧姆接触的金属材料，例如Ti/Al/Ni/Au材料系等，在其他实施例中，根据发射极以及集电极的材料，第一金属电极层101和第二金属电极层102也可以采用AuGe/Ni/Au或Ni/Au。
实施例4
参照图24，本实施例与实施例3不同之处在于发射极层30的侧端具有多个尖凸部30a，对应地，金属集电极层40朝向发射极层30的一侧具有多个尖凹部40a，多个尖凸部30a与多个尖凹部40a形成相互插合的锯齿状，本实施例场发射器件的制作方法与实施例3的制作方法一样，这里不再赘述。
本发明的实施例3和实施例4的场发射器件中的集电极采用金属材质，可以根据场发射器件的性能将发射极的尖凸部角度设计为任意角度，而且，由于所述集电极采用的是金属材质，在湿法腐蚀介质膜层形成纳米间距时不需要添加掩膜，简化了工艺、降低了成本、提高了性能。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (23)

  1. 一种场发射器件，包括衬底和设置在所述衬底上的缓冲层；其特征在于，所述缓冲层上设置有发射极层，所述发射极层包括依次叠层设置的第一半导体层和第二半导体层；所述缓冲层上还设置有离子注入层，所述发射极层嵌入所述离子注入层中，且所述离子注入层具有一缺口，以使所述发射极层的发射端面从所述缺口处暴露出，所述发射端面包括相互邻接的至少部分第一半导体层的端面和至少部分第二半导体层的端面；所述离子注入层的缺口处设置有集电极层，所述集电极层的端面与所述发射端面相对并且两者之间具有沟道；所述发射极层上还依次叠层设置有栅介质层和栅极。
  2. 根据权利要求1所述的场发射器件，其特征在于，所述第一半导体层和所述第二半导体层的连接界面处形成二维电子气结构。
  3. 根据权利要求2所述的场发射器件，其特征在于，所述第一半导体层的材料为GaN，所述第二半导体层的材料为AlGaN；
    或所述第一半导体层的材料为GaAs，所述第二半导体层的材料为AlGaAs；
    或所述第一半导体层的材料为InAs，所述第二半导体层的材料为GaSb。
  4. 根据权利要求1所述的场发射器件，其特征在于，所述集电极层的材料为金属电极材料。
  5. 根据权利要求1-4任一所述的场发射器件，其特征在于，所述发射端面的角度为0°～180°。
  6. 根据权利要求1-4任一所述的场发射器件，其特征在于，所述集电极层的顶面高于所述发射极层的顶面。
  7. 根据权利要求1-4任一所述的场发射器件，其特征在于，所述沟道的宽度不超过100nm。
  8. 一种如权利要求1-7任一所述的场发射器件的制作方法，其特征在于，包括：
    在衬底上依次形成缓冲材料层、发射极材料层和栅介质材料层；其中，所述发射极材料层包括依次叠层设置的第一半导体材料层和第二半导体材料层；
    对所述缓冲材料层、发射极材料层、栅介质材料层进行离子注入，形成缓冲层、位于所述缓冲层上的离子注入层、以及依次叠层设置在所述缓冲层上的发射极层和栅介质层；所述离子注入层环绕在所述发射极层和栅介质层的四周；
    在所述栅介质层上制备栅极；
    去除部分所述离子注入层形成一缺口，以使所述发射极层的发射端面从所述缺口处暴露出，所述发射端面包括相互邻接的至少部分第一半导体层的端面以及至少部分第二半导体层的端面；
    制备介质膜层，使得所述介质膜层完全覆盖所述发射端面；
    在所述离子注入层的缺口处制备集电极层，所述集电极层的端面与所述发射端面相对；
    去除所述介质膜层，在所述发射极层与所述集电极层之间形成所述沟道。
  9. 根据权利要求8所述的制作方法，其特征在于，所述介质膜层的厚度不超过100nm。
  10. 根据权利要求8所述的制作方法，其特征在于，在去除部分所述离子注入层时，部分所述栅介质层和部分所述发射极层被一并去除，所述集电极层与所述第一半导体层相接触。
  11. 一种场发射器件，其特征在于，包括衬底、设置在所述衬底上的缓冲层、分别设置在所述缓冲层两端的发射极层和金属集电极层、分别设置在所述发射极层和所述金属集电极层上的电极层，其中，所述发射极层与所述金属集电极层之间具有沟道。
  12. 根据权利要求11所述的场发射器件，其特征在于，所述金属集电极层采用Cr/Au复合薄膜电极或Mo薄膜电极。
  13. 根据权利要求12所述的场发射器件，其特征在于，所述发 射极层朝向所述金属集电极层一侧具有至少一个尖凸部，所述金属集电极层朝向所述发射极层的一侧对应具有至少一个尖凹部，所述尖凸部与所述尖凹部配合设置使得所述沟道呈非直线状。
  14. 根据权利要求13所述的场发射器件，其特征在于，每个所述尖凸部的顶角角度为a，0°＜a≤90°。
  15. 根据权利要求11所述的场发射器件，其特征在于，所述发射极层采用GaN基超晶格结构或GaN多层异质结构或GaN高掺杂结构。
  16. 根据权利要求11所述的场发射器件，其特征在于，所述电极层采用Ti/Al/Ni/Au复合薄膜电极。
  17. 根据权利要求11～16任一所述的场发射器件，其特征在于，所述衬底采用的材料为蓝宝石或GaN或SiC。
  18. 一种权利要求11所述的场发射器件的制作方法，其特征在于，包括步骤：
    在衬底上形成缓冲层；
    在缓冲层上形成发射极材料层；
    刻蚀所述发射极材料层，以使所述发射极材料层一侧形成至少一尖凸部，获得形成在所述缓冲层一侧的所述发射极层；
    沉积介质膜层，以将所述发射极层完全覆盖；
    对应于所述发射极层、在所述缓冲层另一侧形成金属集电极层，以使得所述金属集电极层朝向所述发射极层的一侧具有与所述尖凸部对应的尖凹部；
    湿法腐蚀去除所述介质膜层，以使所述发射极层与所述金属集电极层之间形成沟道；
    在所述发射极层和所述金属集电极层上分别形成所述电极层。
  19. 根据权利要求18所述的制作方法，其特征在于，所述金属集电极层采用Cr/Au复合薄膜电极或Mo薄膜电极。
  20. 根据权利要求18所述的制作方法，其特征在于，每个所述尖凸部的顶角角度为a，0°＜a≤90°。
  21. 根据权利要求8所述的制作方法，其特征在于，所述发射极材料层采用GaN基超晶格结构或GaN多层异质结构或GaN高掺杂结构。
  22. 根据权利要求18所述的制作方法，其特征在于，所述电极层材质采用Ti/Al/Ni/Au复合薄膜电极。
  23. 根据权利要求18～22任一所述的制作方法，其特征在于，所述衬底采用的材料为蓝宝石或GaN或SiC。
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CN113643949A (zh) * 2021-08-11 2021-11-12 东南大学 一种基于二维绝缘材料的多层真空纳米沟道晶体管

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CN109887818B (zh) * 2019-03-13 2024-03-12 西安众力为半导体科技有限公司 一种电子束器件及其制作方法
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