WO2021129050A1 - Circuit de commutation d'horloge sans transitoires - Google Patents

Circuit de commutation d'horloge sans transitoires Download PDF

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Publication number
WO2021129050A1
WO2021129050A1 PCT/CN2020/120445 CN2020120445W WO2021129050A1 WO 2021129050 A1 WO2021129050 A1 WO 2021129050A1 CN 2020120445 W CN2020120445 W CN 2020120445W WO 2021129050 A1 WO2021129050 A1 WO 2021129050A1
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Prior art keywords
clock
signal
flip
flop
signals
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PCT/CN2020/120445
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English (en)
Chinese (zh)
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张涤非
梁远军
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深圳市紫光同创电子有限公司
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Priority to KR1020227013018A priority Critical patent/KR102654395B1/ko
Publication of WO2021129050A1 publication Critical patent/WO2021129050A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the technical field of clock circuits, and in particular to a glitch-free clock switching circuit.
  • MUX multiplexer
  • the waveform diagram can refer to Figure 1, where clk[0] ⁇ clk[3] are four-way input clocks, sel[0] ⁇ sel[3] are the four-way clock selection corresponding to clk[0] ⁇ clk[3] Signal, at a certain moment, only one of sel[0] ⁇ sel[3] is high level, and clk_out is the output clock.
  • the multiplexer When sel[0] is high, the multiplexer outputs clk[0], when sel[1] is high, the multiplexer outputs clk[1], when sel[2] is high, multiplexes are selected When the output of clk[2] and sel[3] are high, the multiplexer outputs clk[3]. In this clock switching mode, if the timing is not properly controlled, the clock switching will cause glitches in the output clock. These burrs may trigger certain functions by mistake, so it is necessary to find a way to remove these burrs.
  • the present application provides a glitch-free clock switching circuit, which can realize that when multiple clock signals are switched, the output clock does not produce glitches.
  • the present application provides a glitch-free clock switching circuit, including: a clock selection signal generation circuit, a synchronization circuit, and a multiplexer.
  • the clock selection signal generation circuit is used to generate multiple clock selection signals.
  • the number of clock selection signals is the same as the number of multiple clock signals for switching, and the multiple clock signals for switching are a set of clock signals that are sequentially delayed in time sequence, and the clock selection signal is the same as the number of clock signals for switching.
  • the multiple clock signals that are switched have a one-to-one correspondence, and at any time, only one clock selection signal is valid.
  • the synchronization circuit is configured to perform synchronization processing on the multiple clock selection signals generated by the clock selection signal generating circuit according to multiple clock signals for switching, and each clock selection signal after synchronization processing satisfies the following characteristics: any adjacent Of the two clock selection signals, the falling edge of the previous clock selection signal is aligned with the rising edge of the next clock selection signal, and the rising edge of each clock selection signal is aligned with the rising edge of the corresponding clock signal. Each clock selection The falling edge of the signal is aligned with the rising edge of the next clock signal of the corresponding clock signal.
  • the input terminal of the multiplexer inputs multiple clock signals for switching, and the control terminal of the multiplexer inputs a control signal, and the control signal is multiple clock selection signals processed by the synchronization circuit synchronously
  • the output terminal of the multiplexer outputs a clock output signal, and the clock output signal is a clock signal corresponding to a valid clock selection signal after synchronization processing.
  • the synchronization circuit includes: a type I synchronization processing unit and a plurality of type II synchronization processing units, the sum of the number of the type I synchronization processing unit and the type II synchronization processing unit and the clock selection
  • the number of clock selection signals generated by the signal generating circuit is the same, wherein the type I synchronization processing unit is used for synchronizing the clock selection signal corresponding to the first clock signal in time sequence; each type II synchronization processing unit is used for The clock selection signals corresponding to all the clock signals after the first clock signal in the sequence are synchronized in a one-to-one correspondence.
  • the I-type synchronization processing unit includes: a first D flip-flop, a second D flip-flop, and a third D flip-flop connected in series, and a two-input AND gate, wherein the first D flip-flop
  • the input signal of the input terminal is the clock selection signal corresponding to the first clock signal in the timing sequence
  • the clock terminal of the first D flip-flop inputs a first clock signal
  • the first clock signal is the plurality of clocks for switching
  • the output terminal of the first D flip-flop is connected to the input terminal of the second D flip-flop
  • the clock terminal of the second D flip-flop inputs a second clock signal
  • the second clock signal Is the next adjacent clock signal after the clock signal with the highest timing sequence
  • the output terminal of the second D flip-flop is connected to the input terminal of the third D flip-flop, while the output terminal of the second D flip-flop is connected To the first input terminal of the two-input AND gate
  • the clock terminal of the third D flip-flop inputs a third clock signal
  • the type II synchronization processing unit includes: a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop connected in series, and a two-input OR gate, wherein the fourth D flip-flop
  • the input signal of the input terminal is any one of the clock selection signals corresponding to all the clock signals after the most advanced clock signal in the timing sequence.
  • the clock terminal of the fourth D flip-flop inputs a fourth clock signal, the fourth clock signal To be the same clock signal as the first clock signal, the output terminal of the fourth D flip-flop is connected to the input terminal of the fifth D flip-flop; the clock terminal of the fifth D flip-flop inputs a fifth clock Signal, the fifth clock signal is the clock signal corresponding to the clock selection signal input by the fourth D flip-flop, the output terminal of the fifth D flip-flop is connected to the input terminal of the sixth D flip-flop, and at the same time
  • the output terminal of the fifth D flip-flop is connected to the first input terminal of the two-input OR gate; the clock terminal of the sixth D flip-flop inputs a sixth clock signal, and the sixth clock signal is the first An adjacent clock signal after five clock signals, the output terminal of the sixth D flip-flop is connected to the second input terminal of the two-input OR gate, and the output terminal of the two-input OR gate outputs the synchronized clock Select the signal.
  • a synchronous clock is input to the clock terminal of the first D flip-flop, and the synchronous clock is any one of a plurality of clock signals for switching.
  • the synchronous clock is the clock signal with the most advanced timing sequence.
  • n clock selection signals there are n clock selection signals, n-1 type II synchronization processing units, and n is an integer.
  • each type II synchronization processing unit has the same structure.
  • the clock selection signal input by each type II synchronization processing unit is different.
  • the input clock of the first D flip-flop of each type II synchronization processing unit is the most advanced clock signal in time sequence.
  • the input clock of the D flip-flop in the middle of each type II synchronization processing unit is the clock signal corresponding to the clock selection signal input by the first D flip-flop.
  • the clock signal input by the last D flip-flop of each type II synchronization processing unit is an adjacent clock signal after the clock signal input by the D flip-flop in the middle position.
  • a clock signal generating circuit configured to generate the multiple clock signals for switching.
  • the clock signal generating circuit includes a plurality of D flip-flops, and the plurality of D flip-flops are used to delay generating a plurality of clock signals for switching.
  • the clock signal generating circuit is connected to the synchronization circuit and the multiplexer respectively.
  • the clock selection signal generating circuit includes an internal counter, which utilizes the internal counter to cyclically generate a binary control code, and then converts the binary control code into a code of 1 out of N, where N is the number of clock selection signals.
  • the clock selection signal generating circuit is connected to the synchronization circuit.
  • the synchronization circuit is connected to the multiplexer.
  • the present application also provides a glitch-free clock switching method, which is applied to the glitch-free clock switching circuit of the first aspect.
  • the method includes: a clock selection signal generating circuit generates a plurality of clock selection signals, and selects the plurality of clocks The signal is sent to the synchronization circuit; the synchronization circuit performs synchronization processing on the multiple clock selection signals generated by the clock selection signal generation circuit according to the multiple clock signals for switching to obtain the processed multiple clock selection signals; the multiplexer receives for switching And output a clock output signal, and the clock output signal is a clock signal corresponding to the effective clock selection signal after synchronization processing.
  • the synchronization circuit performs synchronization processing on multiple clock selection signals generated by the clock selection signal generation circuit according to multiple clock signals for switching, including: using an I-type synchronization processing unit to select the clock corresponding to the most advanced clock signal in time sequence The signal is synchronized; a plurality of type II synchronization processing units are used to synchronize the clock selection signals corresponding to all the clock signals after the first clock signal in the sequence.
  • the glitch-free clock switching circuit provided in this application adds a synchronization circuit, which uses multiple clocks to synchronize the control signals of the multiplexer, and adjusts the pulse width of the control signals, which can avoid outputting clocks during the switching of multiple clocks.
  • the signal generates burrs, and the realization method is simple, and it is not limited by the process.
  • FIG. 1 is a timing diagram of the existing clock switching
  • FIG. 2 is a schematic structural diagram of a glitch-free clock switching circuit according to an embodiment of the application.
  • Fig. 3 is a schematic diagram of an implementation circuit of the synchronization circuit in Fig. 2;
  • FIG. 4 is a schematic structural diagram of a glitch-free clock switching circuit according to another embodiment of the application.
  • FIG. 5 is a timing diagram of the glitch-free clock switching circuit when switching clocks according to an embodiment of the application
  • FIG. 6 is a method flowchart of a glitch-free clock switching method according to an embodiment of the application.
  • the embodiment of the present application provides a glitch-free clock switching circuit, as shown in FIG. 2, comprising: a clock selection signal generation circuit 21, a synchronization circuit 22, and a multiplexer 23.
  • the clock selection signal generation circuit 21 is used to generate A plurality of clock selection signals, the number of the clock selection signals is the same as the number of the plurality of clock signals for switching, and the plurality of clock signals for switching are a set of clock signals that are sequentially delayed in time sequence, and
  • the clock selection signal has a one-to-one correspondence with multiple clock signals for switching. At any time, only one clock selection signal is valid.
  • n there are n multiple clock signals for switching, which are respectively denoted as clk[0] ⁇ clk[n-1], n is an integer greater than or equal to 2, and the multiple clock signals for switching clk[0] ⁇ clk[n-1] are a set of clock signals delayed in sequence.
  • Multiple clock selection signals are denoted as sel_0[0] ⁇ sel_0[n-1], which can be abbreviated as sel_0[n- 1:0], sel_0[0] corresponds to clk[0], sel_0[1] corresponds to clk[1], and so on, sel_0[n-1] corresponds to clk[n-1].
  • the synchronization circuit 22 is used for synchronizing the multiple clock selection signals sel_0[n-1:0] generated by the clock selection signal generating circuit according to multiple clock signals clk[0] to clk[n-1] for switching Processing, among the multiple clock selection signals sel[n-1:0] after synchronization processing, each clock selection signal after synchronization processing satisfies the following characteristics: In any two adjacent clock selection signals, the previous clock selection signal The falling edge of the clock selection signal is aligned with the rising edge of the next clock selection signal, the rising edge of each clock selection signal is aligned with the rising edge of the corresponding clock signal, and the falling edge of each clock selection signal is aligned with the next item of the clock signal The rising edge of the clock signal is aligned.
  • the input terminal of the multiplexer 23 inputs multiple clock signals clk[0] ⁇ clk[n-1] for switching, the control terminal of the multiplexer 23 inputs a control signal, and the control signal is synchronized by the synchronization circuit 22
  • the output terminal of the multiplexer 23 outputs a clock output signal clk_out under the control of the control signal, and the clock output signal clk_out is a slave
  • the clock selection signal generation circuit 21 uses an internal counter to cyclically generate a binary control code, and then converts the binary control code into a code of 1 out of N, where N is the number of clock selection signals, which are output to the synchronization circuit 22 for processing Synchronous processing.
  • the synchronization circuit 22 includes a type I synchronization processing unit and a plurality of type II synchronization processing units.
  • the sum of the number of the type I synchronization processing unit and the type II synchronization processing unit is equal to the sum of the number of the type I synchronization processing unit and the type II synchronization processing unit.
  • the number of clock selection signals generated by the clock selection signal generating circuit is the same. In this embodiment, there are n clock selection signals.
  • n-1 type II synchronization processing units there are n-1 type II synchronization processing units, and the type I synchronization processing unit It is used for synchronizing the clock selection signal sel_0[0] corresponding to the clock signal clk[0] at the top of the time sequence; each of the type II synchronization processing units is used for one-to-one correspondence to the clock signals after the clock signal at the top of the time sequence.
  • the clock selection signal sel_0[n-1:1] corresponding to all the clock signals clk[n-1:1] is synchronized.
  • the I-type synchronization processing unit includes three D flip-flops connected in series and a two-input AND gate AND04.
  • the three D flip-flops are a first D flip-flop DFF01 and a second D flip-flop.
  • the clock terminal of the first D flip-flop DFF01 inputs a synchronization clock
  • the synchronization clock is any one of the multiple clock signals for switching, in this embodiment, the synchronization clock selects clk[0], the first D flip-flop DFF01
  • the output terminal of is connected to the input terminal of the second D flip-flop DFF02.
  • the clock signal input from the clock terminal of the second D flip-flop DFF02 is an adjacent clock signal clk[1] after the first clock signal clk[0] in the timing sequence, and the output of the second D flip-flop DFF02
  • the terminal is connected to the input terminal of the third D flip-flop DFF03, and the output terminal of the second D flip-flop DFF02 is connected to the first input terminal of the two-input AND gate AND04.
  • the clock signal input from the clock terminal of the third D flip-flop DFF03 is the clock signal clk[0] with the highest timing sequence.
  • the output terminal of the third D flip-flop DFF03 is connected to the second input terminal of the two-input AND gate AND04, and the two inputs are connected to the second input terminal of the two-input AND gate AND04.
  • the output terminal of the gate AND04 outputs the clock selection signal sel[0] after synchronization processing.
  • each type II synchronization processing unit has the same structure.
  • a type II synchronization processing unit for processing the clock selection signal sel_0[1] is taken as an example.
  • the type II synchronization processing unit includes : Three D flip-flops connected in series and a two-input OR gate OR14.
  • the three D flip-flops are the fourth D flip-flop DFF11, the fifth D flip-flop DFF12 and the sixth D flip-flop DFF13, respectively.
  • the input signal of the input terminal of the four D flip-flop DFF11 is the unsynchronized clock selection signal sel_0[1] corresponding to the next clock signal clk[0] after the first clock signal clk[0] in the timing sequence, and the fourth D trigger
  • the clock signal input by the clock terminal of the DFF11 is the same as the synchronous clock input by the DFF01, which is also clk[0], and the output terminal of the fourth D flip-flop DFF11 is connected to the input terminal of the fifth D flip-flop DFF12.
  • the clock signal input from the clock terminal of the fifth D flip-flop DFF12 is an adjacent clock signal clk[1] after the first clock signal clk[0] in the timing sequence, and the output terminal of the fifth D flip-flop DFF12 is connected To the input terminal of the sixth D flip-flop DFF13, while the output terminal of the fifth D flip-flop DFF12 is connected to the first input terminal of the two-input OR gate OR14.
  • the clock signal input from the clock terminal of the sixth D flip-flop DFF13 is an adjacent clock signal clk[2] after the input clock signal of the fifth D flip-flop DFF12, and the output terminal of the sixth D flip-flop DFF13 is connected to the second input
  • the second input terminal of the OR gate OR14 and the output terminal of the two-input OR gate OR14 output the synchronized clock selection signal sel[1].
  • the input clock of the first D flip-flop is clk[0], and the D in the middle position
  • the input clock of the flip-flop is the clock signal corresponding to the clock selection signal input by the first D flip-flop
  • the clock signal input by the last D flip-flop is an adjacent clock signal after the clock signal input by the D flip-flop in the middle position.
  • the clock selection signals sel_0[0] ⁇ sel_0[n-1] generated by the clock selection signal generation circuit 21 are first synchronized by the same clock clk[0], so that all clock selection signals are synchronized and the clock is eliminated
  • the delay between the selection signals is synchronized for the first time with multiple clocks respectively, and the rising and falling edges of different clock selection signals are aligned with the rising edges of the corresponding clock signals, and then multiple clocks are used for the second time Synchronization, so that the rising and falling edges of different clock selection signals are aligned with the rising edge of the next clock of the corresponding clock signal, and the results of the last two multiple clock synchronizations are logically operated, on the one hand, the synchronized processing In any two adjacent clock selection signals, the falling edge of the previous clock selection signal is aligned with the rising edge of the next clock selection signal to achieve seamless switching of the clock selection signal; The rising edge of each clock selection signal is aligned with the rising edge of the corresponding clock signal
  • the state of the previous clock selected for output is the same as the state of the next clock selected for output to avoid glitches.
  • the rising edge of the previous clock selection signal is aligned with the falling edge of the next clock selection signal, and the state of the previous clock at the time of clock transition The state is the same as the latter clock, so the output clock will not produce glitches.
  • the glitch-free clock switching circuit provided by another embodiment of the present application further includes: a clock signal generating circuit 24.
  • the clock signal generating circuit 24 includes a plurality of D flip-flops, using a plurality of D flip-flops. Delay generation of multiple clock signals clk[0] ⁇ clk[n-1] for switching. These multiple clock signals are used as multiple clock inputs of the multiplexer on the one hand, and output to the synchronization circuit on the other hand for synchronizing the clock selection signal.
  • Figure 5 shows the timing diagram of the glitch-free clock switching circuit provided by the embodiment of the present application when switching clocks, where clk[0] ⁇ clk[n-1] are multiple clock signals for switching, sel_1[0] ⁇ sel_1 [n-1] is the clock selection signal after using the same clock synchronization, sel_2[0] ⁇ sel_2[n-1] is the clock selection signal after using multiple clocks for the first synchronization, sel_3[0] ⁇ sel_3[ n-1] is the clock selection signal after the second synchronization using multiple clocks, sel[0] ⁇ sel[n-1] is the clock selection signal output after synchronization, clk_out is the clock output signal output by the multiplexer .
  • the rising edge of [0] is aligned, the rising edge of sel_2[n-2] is aligned with the rising edge of clk[n-2], the falling edge of sel_2[n-2] is aligned with the rising edge of clk[n-2], sel_3[ The rising edge of n-2] is aligned with the rising edge of clk[n-1], the falling edge of sel_3[n-2] is aligned with the rising edge of clk[n-1], and the rising edge of sel[n-2] is aligned with clk[ The rising edge of n-2] is aligned, the falling edge of sel[n-2] is aligned with the rising edge of clk[n-1], and the rest of the signals are deduced by analogy. Finally, clk_out will not generate glitches during clock switching.
  • an embodiment of the present application provides a glitch-free clock switching method, which is applied to the glitch-free clock switching circuit described above.
  • the method may include steps S301 to S303.
  • Step S301 The clock selection signal generating circuit generates a plurality of clock selection signals, and sends the plurality of clock selection signals to the synchronization circuit.
  • Step S302 the synchronization circuit performs synchronization processing on the multiple clock selection signals generated by the clock selection signal generating circuit according to the multiple clock signals for switching, to obtain processed multiple clock selection signals.
  • the present application can use the type I synchronization processing unit to synchronize the clock selection signal corresponding to the most advanced clock signal in the timing sequence, and use multiple type II synchronization processing units to perform the synchronization processing on all clocks after the most advanced clock signal in timing sequence.
  • the clock selection signal corresponding to the signal is synchronized.
  • the sum of the number of type I synchronization processing units and type II synchronization processing units is the same as the number of clock selection signals generated by the clock selection signal generating circuit.
  • Step S303 The multiplexer receives multiple clock signals for switching and processed multiple clock selection signals, and outputs a clock output signal, the clock output signal is a clock signal corresponding to the effective clock selection signal after synchronization processing .

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Abstract

La présente invention concerne un circuit de commutation d'horloge sans transitoires, comprenant : un circuit de génération de signal de sélection d'horloge, un circuit de synchronisation et un sélecteur à trajets multiples. Le circuit de génération de signal de sélection d'horloge est utilisé pour générer de multiples signaux de sélection d'horloge. Le circuit de synchronisation est utilisé pour synchroniser les multiples signaux de sélection d'horloge sur la base de multiples signaux d'horloge pour la commutation. Les signaux de sélection d'horloge synchronisés satisfont les caractéristiques suivantes : dans deux quelconques signaux de sélection d'horloge adjacents, le front descendant du signal de sélection d'horloge précédent est aligné avec le front montant du signal de sélection d'horloge suivant, le front montant de chaque signal de sélection d'horloge est aligné avec le front montant du signal d'horloge correspondant à celui-ci, et le front descendant de chaque signal de sélection d'horloge est aligné avec le front montant du signal d'horloge après le signal d'horloge correspondant au signal de sélection d'horloge. Le sélecteur à trajets multiples sélectionne l'un parmi de multiples signaux d'horloge entrés en vue d'une sortie sur la base des multiples signaux de sélection d'horloge synchronisés. La présente invention empêche la génération de transitoires par le signal d'horloge émis pendant un processus de commutation à trajets multiples.
PCT/CN2020/120445 2019-12-26 2020-10-12 Circuit de commutation d'horloge sans transitoires WO2021129050A1 (fr)

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