WO2021120836A1 - 一种频率合成器、频率合成方法、电子设备及存储介质 - Google Patents

一种频率合成器、频率合成方法、电子设备及存储介质 Download PDF

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WO2021120836A1
WO2021120836A1 PCT/CN2020/122943 CN2020122943W WO2021120836A1 WO 2021120836 A1 WO2021120836 A1 WO 2021120836A1 CN 2020122943 W CN2020122943 W CN 2020122943W WO 2021120836 A1 WO2021120836 A1 WO 2021120836A1
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Prior art keywords
frequency
signal
frequency synthesizer
synthesizer circuit
output
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PCT/CN2020/122943
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English (en)
French (fr)
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陈松
李雪林
肖伟
陈豪
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中兴通讯股份有限公司
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Publication of WO2021120836A1 publication Critical patent/WO2021120836A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the embodiments of the present application relate to the field of communications, and in particular, to a frequency synthesizer, a frequency synthesis method, electronic equipment, and a storage medium.
  • the signal is synthesized and output by the phase-locked loop frequency synthesizer, and the bandwidth of the output signal becomes larger and larger, due to the frequency resolution of the fractional frequency synthesizer
  • the characteristics of high rate and wide output frequency range make it widely used in electronic communication test systems.
  • the fractional frequency synthesizer needs to output a wide frequency band full coverage RF signal, it is inevitable that the fractional spurs will fall within the loop bandwidth of the phase-locked loop under the traditional scheme.
  • fractional spurious suppression methods are mainly realized by using two or more fractional frequency synthesizer circuits, that is, one or more fractional frequency synthesizers are connected after the reference clock signal to realize the input to the final fractional frequency synthesizer.
  • the phase discrimination frequency is adjusted to suppress the fractional spurs of the final fractional frequency synthesizer.
  • phase detection frequency When signal synthesis is performed, adjusting the phase detection frequency requires a more complicated circuit structure, and the control is complicated when the phase detection frequency is switched, which may introduce new fractional spurs.
  • the embodiments of the present application provide a frequency synthesizer, a frequency synthesis method, an electronic device, and a storage medium.
  • the embodiment of the present application provides a frequency synthesizer, including: a reference crystal oscillator, an integer frequency synthesizer circuit, and a fractional frequency synthesizer circuit; wherein the reference crystal oscillator is connected to the reference clock input terminal of the integer frequency synthesizer circuit for The integer frequency synthesizer circuit provides a reference clock signal; the output end of the integer frequency synthesizer circuit is connected to the reference clock input end of the fractional frequency synthesizer circuit, which is used to provide a reference clock signal for the fractional frequency synthesizer circuit for the decimal frequency synthesizer circuit according to The reference clock signal obtains the phase discrimination frequency; the fractional frequency synthesizer circuit is used to generate a frequency signal with a fractional spurious value greater than a preset threshold according to the phase discrimination frequency.
  • the embodiment of the present application also provides a frequency synthesis method, including: applied to a frequency synthesizer, the frequency synthesizer includes: a reference crystal oscillator, an integer frequency synthesizer circuit and a fractional frequency synthesizer circuit, a reference crystal oscillator and an integer frequency synthesizer circuit
  • the reference clock input terminal of the integer frequency synthesizer circuit is connected, and the output terminal of the integer frequency synthesizer circuit is connected to the reference clock input terminal of the decimal frequency synthesizer circuit
  • the frequency synthesis method includes: obtaining the output signal of the integer frequency synthesizer circuit, and using the output signal as a fractional frequency synthesizer
  • the reference clock signal of the circuit is input to the fractional frequency synthesizer circuit; it is detected whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold; if it is not greater than the preset threshold, adjust the integer frequency synthesizer circuit Output signal, and re-detec
  • the embodiments of the present application also provide an electronic device, including: at least one processor; and a memory communicatively connected with the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are at least One processor executes, so that at least one processor can execute the aforementioned frequency synthesis method.
  • the embodiment of the present application also provides a computer-readable storage medium that stores a computer program, and the computer program is executed by a processor to implement the above-mentioned frequency synthesis method.
  • Fig. 1 is a schematic structural diagram of a frequency synthesizer according to the prior art
  • Fig. 2 is a schematic structural diagram of another frequency synthesizer according to the prior art
  • Fig. 3 is a schematic structural diagram of a frequency synthesizer in the first embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a frequency synthesizer in the second embodiment of the present application.
  • FIG. 5 is a flowchart of a frequency synthesis method according to the third embodiment of the present application.
  • Fig. 6 is a schematic diagram of the structure of an electronic device in a fourth embodiment according to the present application.
  • the difference ⁇ f between the harmonics of the phase detection frequency closest to the output signal frequency and the output signal frequency is usually used as the quantization target of the fractional spurs.
  • the fractional spurs are in the fractional frequency synthesizer loop. At positions 20 to 30 times the filter bandwidth BW, most fractional spurs can be suppressed.
  • the structure diagram of the signal synthesis with fractional spur avoidance function in the prior art is shown in Figure 1 and Figure 2.
  • the first fractional frequency synthesizer and the second fractional frequency synthesizer are provided
  • An identical reference crystal oscillator obtains two outputs ref1 and ref2 through two fractional frequency synthesizers, and then connects the output of the two fractional frequency synthesizers to a radio frequency switch, and inputs to the third fractional frequency synthesizer according to the radio frequency switch selection
  • the reference clock signal of the third decimal frequency synthesizer is further adjusted to adjust the phase detection frequency determined according to the reference clock, so that the phase detection frequency of the third decimal frequency synthesizer is adjustable.
  • reference crystal oscillator 1 and reference crystal oscillator 2 generate different reference crystal oscillators through different power supplies with the help of a frequency generator, and then input the reference crystal oscillator to the RF switch, and through the crystal oscillator switching circuit,
  • the reference crystal of the frequency detector is selected, and after the phase-locked loop circuit determines the phase-discrimination frequency according to the reference crystal, the synthesized signals of different frequencies are output according to the phase-discrimination frequency, and one of the multiple reference crystals is selected as the phase-locked loop
  • the reference crystal oscillator of the circuit realizes the switching of the phase discrimination frequency of the phase-locked loop circuit.
  • the embodiments of the present application provide a frequency synthesizer, a frequency synthesis method, an electronic device, and a storage medium, so that the phase discrimination frequency can be flexibly switched according to the frequency of the output signal, so as to achieve good avoidance of fractional spurs, and reduce circuit complexity and Control the difficulty and improve the spectral quality of the output signal.
  • the first embodiment of the application relates to a frequency synthesizer.
  • the structure diagram of the frequency synthesizer in this embodiment is shown in FIG. 3, and the output of the integer frequency synthesizer circuit is used as the input of the reference clock of the fractional frequency synthesizer circuit. According to the frequency of the output signal of the fractional frequency synthesizer circuit, the output of the integer frequency synthesizer circuit is adjusted, so as to flexibly adjust the phase discrimination frequency of the fractional frequency synthesizer circuit.
  • the reference crystal oscillator is connected to the reference clock input terminal of the integer frequency synthesizer circuit, and the reference crystal oscillator is used as the input of the integer frequency synthesizer circuit to provide the reference clock signal for the integer frequency synthesizer circuit so that the integer
  • the frequency synthesizer can generate an output signal according to the reference crystal oscillator; the output of the integer frequency synthesizer circuit is connected to the reference clock input of the decimal frequency synthesizer circuit, and the output of the integer frequency synthesizer circuit is used as the reference clock signal of the fractional frequency synthesizer circuit , So that the reference clock input of the fractional frequency synthesizer circuit can be flexibly changed according to the output of the integer frequency synthesizer circuit.
  • the fractional frequency synthesizer circuit determines its own phase discrimination frequency according to the reference clock signal provided by the integer frequency synthesizer circuit, and then According to the phase discrimination frequency, a frequency signal with a fractional spurious value greater than a preset threshold is generated.
  • the reference clock of the fractional frequency synthesizer circuit can be changed according to the output of the integer frequency synthesizer circuit, thereby flexibly switching the decimal frequency synthesizer circuit
  • the phase-discrimination frequency makes it possible for the fractional frequency synthesizer circuit to perform good fractional spur avoidance when outputting signals of different frequencies.
  • the output of the integer frequency synthesizer circuit As the reference clock of the fractional frequency synthesizer circuit, adjust the reference clock signal of the fractional frequency synthesizer circuit by adjusting the output of the integer frequency synthesizer circuit, thereby ensuring the performance of the fractional frequency synthesizer circuit.
  • the phase discrimination frequency can be flexibly adjusted according to the frequency of the output signal, so as to achieve good fractional spur avoidance when outputting signals of various frequencies; the output of the integer frequency synthesizer circuit is used as the reference clock of the fractional frequency synthesizer circuit It avoids the complicated circuit structure and control method caused by multiple fractional frequency synthesizer circuits, avoids the introduction of new fractional spurs, and improves the spectral quality of the output signal.
  • the integer frequency synthesizer circuit includes: a first phase detector, a first loop filter, a first voltage-controlled oscillator, a first frequency divider, and a second frequency divider;
  • the first input terminal of the phase detector is connected to the reference crystal oscillator, the second input terminal of the first phase detector is connected to the output terminal of the first frequency divider, and the output terminal of the first phase detector is connected to the input terminal of the first loop filter.
  • first loop filter Used to perform phase discrimination on the first phase discrimination frequency determined according to the reference crystal oscillator and the divided feedback signal of the first voltage-controlled oscillator, and transmit the phase discrimination result to the first loop filter;
  • first loop filter The output terminal of the converter is connected to the input terminal of the first voltage-controlled oscillator, and is used to generate a first control signal according to the phase discrimination result, and transmit the first control signal to the first voltage-controlled oscillator;
  • the feedback of the first voltage-controlled oscillator The output terminal is connected to the input terminal of the first frequency divider, and the signal output terminal of the first voltage-controlled oscillator is connected to the input terminal of the second frequency divider for adjusting the frequency of the output signal and transmitting the feedback signal to the first frequency divider ;
  • the first frequency divider is used to divide the feedback signal of the first voltage-controlled oscillator;
  • the output end of the second frequency divider is connected to the reference clock input end of the fractional frequency synthesizer circuit for the first voltage-controlled oscillator
  • the output signal can be adjusted according to the reference clock signal required by the fractional frequency synthesizer, thereby ensuring that the fractional frequency synthesizer circuit can detect the phase according to the reference clock signal. Frequency is a good way to avoid the fractional spurs of the output signal.
  • the integer frequency synthesizer circuit further includes: a third frequency divider; the input end of the third frequency divider is connected to the reference crystal oscillator, and the output end of the third frequency divider is connected to the second input of the first phase detector The terminal is used to divide the frequency of the reference crystal obtained by the integer frequency synthesizer circuit.
  • the output signal of the integer frequency synthesizer circuit can be more in line with the reference clock signal required by the fractional frequency synthesizer circuit, so that the fractional frequency synthesizer can obtain a reference clock that meets the requirements. Ensure the spectral quality of the final output signal.
  • the frequency of the output signal of the integer frequency synthesizer circuit is more in line with the frequency of the reference clock signal of the fractional frequency synthesizer circuit, so that the fractional frequency synthesizer can obtain a reference clock that meets the requirements, thereby ensuring the final The quality of the output signal.
  • the fractional frequency synthesizer circuit includes: a second phase detector, a second loop filter, a second voltage-controlled oscillator, and a fourth frequency divider; the first input terminal of the second phase detector is connected The circuit output terminal of the integer frequency synthesizer circuit, the second input terminal of the second phase detector is connected to the output terminal of the fourth frequency divider, and the output terminal of the second phase detector is connected to the input terminal of the second loop filter.
  • the output terminal of the second loop filter is connected to the input terminal of the second voltage-controlled oscillator, and is used to generate a second control signal according to the phase discrimination result and transmit the second control signal to the second voltage-controlled oscillator;
  • the feedback output terminal of the controlled oscillator is connected to the input terminal of the fourth frequency divider, and is used to adjust the frequency of the signal to be output, output the frequency signal and transmit the feedback signal to the fourth frequency divider;
  • the fourth frequency divider is used to The feedback signal of the controlled oscillator is frequency-divided, and the output signal of the fourth frequency divider enters the second phase detector for phase discrimination and comparison with the reference signal; the second loop filter is based on the feedback signal and discriminator determined by the second phase detector.
  • the phase frequency discrimination result produces a control signal to adjust the frequency of the output signal of the second voltage-controlled oscillator, so that when the signal output of each frequency is carried out, it can effectively avoid the fractional spur of the output signal; fractional frequency synthesizer circuit It is realized based on ⁇ - ⁇ modulation technology. By performing feedback control adjustment according to the phase detection result of the phase detector, it is ensured that the fractional spurs of the output signal can be effectively avoided.
  • the fractional frequency synthesizer circuit further includes: a fifth frequency divider; the input end of the fifth frequency divider is connected to the circuit output end of the integer frequency synthesizer circuit, and the output end of the fifth frequency divider is connected to the second frequency divider.
  • the first input terminal of the phase detector is used to divide the frequency of the reference clock signal provided by the integer frequency synthesizer circuit; the first input terminal of the second phase detector is connected to the circuit of the integer frequency synthesizer circuit through the fifth frequency divider At the output end, the obtained reference clock signal is divided by the fifth frequency divider to ensure that the determined phase discrimination frequency meets the requirements of the fractional frequency synthesizer circuit, and achieves good avoidance of fractional spurs.
  • the configuration data of the first voltage-controlled oscillator of the integer frequency synthesizer circuit and the frequency division coefficient of the second frequency divider are first adjusted by software to obtain the integer frequency synthesis
  • the Fout1 of different frequencies that can be output by the frequency synthesizer circuit is formed according to these possible outputs of the integer frequency synthesizer circuit to form a reference clock signal candidate library for the fractional frequency synthesizer circuit, and then the fractional spurs are determined according to the loop bandwidth of the fractional frequency synthesizer circuit.
  • the fractional frequency synthesizer circuit is configured to calculate the phase discrimination frequency that can meet the requirements of fractional spurious avoidance when the fractional frequency synthesizer circuit outputs each frequency signal, and then the fractional frequency synthesis is determined according to the determined phase discrimination frequency
  • the reference clock signal required by the frequency converter circuit adjusts the configuration data of the integer frequency synthesizer circuit according to the determined reference clock signal, so that the integer frequency synthesizer circuit outputs a frequency signal that meets the requirements.
  • the evasion principle can be set to ⁇ f ⁇ n ⁇ BW for evasion, so that the fractional spurs fall outside the loop bandwidth of n times and are filtered out by the loop filter. , Considering issues such as design and circuit cost, the value range of n can be set from 30 to 120.
  • the frequency range of the output signal of the fractional frequency synthesizer circuit is between 3-9GHz
  • the loop bandwidth of the output signal is 50kHz
  • the basic phase detection frequency is 50MHz.
  • n is selected as 100, that is The fractional spurs fall at 100 times the loop bandwidth.
  • avoidance measures need to be taken, that is, when the fractional spurs ⁇ f ⁇ 5MHz, you need to reselect the discrimination.
  • the phase frequency is calculated by software to obtain all possible outputs of the integer frequency synthesizer circuit, and the reference clock signal candidate library is obtained.
  • the 50MHz output signal is selected as the basic output signal.
  • the fractional frequency synthesizer circuit performs signal synthesis and output, first set the configuration data of the second frequency divider and the first voltage-controlled oscillator of the integer frequency synthesizer according to the basic output signal, and output a 50MHz output signal.
  • the fractional frequency synthesizer circuit outputs a 4500.03MHz signal.
  • the phase discrimination frequency obtained from the reference clock signal is the basic phase discrimination frequency of 50MHz. Through software calculation, the 90th harmonic of the phase discrimination frequency is closest to the output frequency.
  • the signal with a frequency of 51.28205MHz is used as the signal to be output, and the configuration data of the second frequency divider and the first voltage-controlled oscillator are adjusted according to the frequency of the signal to be output, so that the output signal of the integer frequency synthesizer circuit is 51.28205MHz, At this time, the phase detection frequency of the fractional frequency synthesizer circuit is changed to 51.28205MHz. At this time, the 88th harmonic of the phase detection frequency is closest to the frequency of the output signal.
  • this embodiment provides a frequency synthesizer, which provides an appropriate reference clock signal for the fractional frequency synthesizer circuit by means of the integer frequency synthesizer circuit, so that the fractional frequency synthesizer circuit can be changed according to the output of the integer frequency synthesizer circuit.
  • Obtaining the corresponding phase discrimination frequency ensures that when the fractional frequency synthesizer outputs signals of different frequencies, it can achieve good fractional spur avoidance; the integer frequency synthesizer circuit provides the reference clock of the fractional frequency synthesizer circuit, avoiding the need Setting multiple reference clock signal generating circuits simplifies the circuit structure, reduces circuit complexity and control difficulty, saves circuit area and cost, and avoids the possibility of introducing new decimals when multiple fractional frequency synthesizer circuits are combined.
  • the problem of spurs ensures the effect of decimal spur avoidance and improves the quality of the output signal.
  • the second embodiment of the present application relates to a frequency synthesizer.
  • the second embodiment is roughly the same as the first embodiment.
  • the feedback signal of the fractional frequency synthesizer is added
  • the sixth frequency divider that pre-divides the feedback signal reduces the frequency division requirements and difficulty of the fourth frequency divider by pre-dividing the feedback signal, and prevents the signal quality from being affected by a high frequency division ratio.
  • the phase discrimination result further guarantees the quality of the output signal.
  • FIG. 4 The schematic diagram of the structure of this embodiment is shown in Fig. 4.
  • the remaining modules are similar to the modules in the first embodiment. To avoid repetition, they will not be repeated here. Only the sixth divider will be described.
  • the fractional frequency synthesizer circuit further includes: a sixth frequency divider; the input end of the sixth frequency divider is connected to the feedback output end of the second voltage-controlled oscillator, and the output end of the sixth frequency divider is connected to the fourth frequency divider.
  • the input end of the frequency divider is used to pre-divide the feedback signal of the second voltage-controlled oscillator. By pre-dividing the feedback signal, the frequency division ratio in the fourth frequency divider is reduced and the frequency division is avoided. Too high frequency ratio leads to the problem of reduced signal quality, which ensures the signal quality of the output signal.
  • a sixth frequency divider is added to the fractional frequency synthesizer circuit, because the phase detector compares the frequency between a certain harmonic of the phase detection frequency and the frequency of the signal received by the fourth frequency divider. Therefore, the fractional spur at this time is ⁇ f/p, where p is the frequency division coefficient of the sixth frequency divider.
  • the fractional frequency synthesizer needs to output a signal of 3 to 9 GHz.
  • the basic discrimination of the fractional frequency synthesizer is The phase frequency is 50MHz, the loop bandwidth is 50kHz, and the frequency division coefficient of the sixth phase detector is 2.
  • the frequency of the output signal is 4500.03MHz, and the 90th harmonic of the phase detector frequency is fed back to the fourth
  • the signal frequency of the frequency divider is the closest.
  • the feedback signal that needs to be output to the phase detector should be the signal after the output frequency is divided by the sixth frequency divider and the fourth frequency divider.
  • the coefficient is 2, and the feedback signal has been divided. Therefore, at this time, it is only necessary to set the frequency division coefficient of the fourth frequency divider to 45.0003.
  • the parameters of the circuit are adjusted so that the integer frequency synthesizer circuit outputs a suitable frequency, and the phase discrimination frequency of the fractional frequency synthesizer circuit is modified until the fractional spur avoidance effect meets the requirements.
  • this embodiment provides a frequency synthesizer, by adding a sixth frequency divider before the fourth frequency divider in the feedback signal transmission channel of the fractional frequency synthesizer circuit, the frequency division process of the feedback signal It becomes the second frequency division, which reduces the frequency division ratio of the fourth frequency divider, avoids the signal quality degradation caused by the excessive frequency division ratio, and ensures the quality of the signal received by the phase detector, thereby ensuring the phase detection
  • the accuracy of the result prevents the inaccurate phase discrimination result from affecting the evasion effect of decimal spurs and guarantees the quality of the output signal.
  • the frequency division ratio and difficulty of the fourth frequency divider are reduced, the problem of signal quality degradation due to excessive frequency division ratio is avoided, and the signal quality of the output signal is guaranteed.
  • the third embodiment of the present application relates to a frequency synthesis method.
  • the specific process is shown in FIG. 5, and is applied to the frequency synthesizer of any of the above embodiments.
  • the frequency synthesis method includes:
  • Step 101 Obtain the output signal of the integer frequency synthesizer circuit.
  • the decimal Frequency synthesizer circuit before synthesizing and outputting the frequency signal, obtain the output signal of the integer frequency synthesizer circuit, and use the obtained output signal of the integer frequency synthesizer circuit as the reference clock signal of the fractional frequency synthesizer circuit and input it to the decimal Frequency synthesizer circuit.
  • Step 102 Detect whether the fractional spur value is greater than a preset threshold, if it is greater than the preset threshold, go to step 104, and if it is not greater than the preset threshold, go to step 103.
  • the phase detection frequency of the fractional frequency synthesizer circuit is determined according to the reference clock signal of the fractional frequency synthesizer circuit, According to the determined phase discrimination frequency and the frequency of the frequency signal to be output, calculate the difference between the harmonics of the phase discrimination frequency, the harmonic closest to the output frequency and the output frequency, and determine the decimal of the frequency signal generated by the fractional frequency synthesizer circuit
  • the spurious value is to detect whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold, if it is greater than the preset threshold, go to step 104, and if it is not greater than the preset threshold, go to step 103.
  • the preset threshold of the fractional spur value can be set according to the actual situation of the requirement of fractional spur avoidance, and the specific value of the preset threshold is not limited in this embodiment.
  • Step 103 Adjust the output of the integer frequency synthesizer circuit.
  • the reference clock signal candidate library 1 is generated according to all the candidate frequencies of the obtained integer frequency synthesizer circuit output signal, and then the reference clock signal candidate library 1 is generated according to the basic discrimination of the fractional frequency synthesizer circuit.
  • Phase frequency in the reference clock signal library 1, select the basic output signal of the integer frequency synthesizer circuit, and then according to the frequency range of the output signal of the fractional frequency synthesizer circuit, through software calculation, the output of the traversal fractional frequency synthesizer circuit is different
  • the phase discrimination frequency required for the frequency signal is based on the current phase discrimination frequency to detect the applicable output signal frequency range of the current phase discrimination frequency.
  • the reference clock Select the target frequency that is closest to the current output signal frequency in library 1, adjust the configuration data of the integer frequency synthesizer circuit according to the target frequency, for the integer frequency synthesizer circuit to output the output signal of the target frequency, and then detect the corresponding corresponding to the new reference clock signal The range of the output signal that can be used by the phase-detection frequency until all the output signals of the fractional frequency synthesizer circuit are traversed.
  • the integer frequency synthesizer circuit configuration data is adjusted for the integer frequency synthesizer circuit to output the output signal of the target frequency.
  • the target frequency may be the frequency value that is closest to the current signal frequency among the frequencies greater than the current signal frequency or less than the current signal frequency. This embodiment does not limit the specific selection rules.
  • a fractional frequency synthesizer needs to output a signal of 3-9GHz.
  • the basic phase detection frequency of the fractional frequency synthesizer is 50MHz, and the loop bandwidth is 50kHz.
  • the frequency of the output signal of the integer frequency synthesizer circuit includes the frequency of the output signal of the integer frequency synthesizer circuit.
  • the phase detection frequency required for 3-9GHz signal output includes: 50MHz, 51.28205 MHz, 51.35135MHz, 52.63157MHz and 52.77777MHz, according to the reference clock signals corresponding to these 5 phase discrimination frequencies, the reference clock alternative library 2 is generated.
  • the fractional frequency synthesizer circuit outputs a 4500.03MHz signal.
  • the phase detection frequency is 50MHz.
  • the 90th harmonic of the phase detection frequency is closest to the frequency of the output signal.
  • the difference ⁇ f between the two is 30kHz, that is, the fractional spurious value at this time is 30kHz, which does not satisfy the fractional spurious.
  • the configuration data of the frequency converter circuit makes it output a signal with a frequency of 51.28205MHz, and then returns to step 102 to re-detect whether the fractional spurious value of the frequency signal generated by the fractional frequency synthesizer circuit is greater than the preset threshold.
  • Step 104 Output a frequency signal.
  • the phase discrimination frequency corresponding to the current reference clock can be used in the synthesis and output process of the signal of the current frequency.
  • the frequency signal is output directly according to the current reference clock signal.
  • this embodiment provides a frequency synthesis method, by using the output of the integer frequency synthesizer circuit as the input of the reference clock signal of the fractional frequency synthesizer circuit, so that the reference clock of the fractional frequency synthesizer can be flexibly based on the integer frequency.
  • the output of the synthesizer is changed to realize the flexible change of the phase detection frequency; the selection of the reference clock signal and the adjustment of the integer frequency synthesizer circuit are carried out through the pre-established reference clock alternative library, which improves the efficiency of the phase detection frequency adjustment;
  • the relationship between the calculation result of the fractional spur value and the preset threshold value is used to adjust the output signal of the integer frequency synthesizer circuit, so that the phase discrimination frequency of the fractional frequency synthesizer circuit can be changed according to the output signal of different frequencies.
  • the fourth embodiment of the present application relates to an electronic device, as shown in FIG. 6, including at least one processor; and a memory communicatively connected with the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor , The instructions are executed by at least one processor, so that the at least one processor can execute the aforementioned frequency synthesis method.
  • the memory and the processor are connected in a bus mode
  • the bus may include any number of interconnected buses and bridges, and the bus connects one or more processors and various circuits of the memory together.
  • the bus can also connect various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are all well-known in the art, and therefore, no further description will be given herein.
  • the bus interface provides an interface between the bus and the transceiver.
  • the transceiver may be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on the transmission medium.
  • the data processed by the processor is transmitted on the wireless medium through the antenna, and further, the antenna also receives the data and transmits the data to the processor.
  • the processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions.
  • the memory can be used to store data used by the processor when performing operations.
  • the fifth embodiment of the present application relates to a computer-readable storage medium that stores a computer program.
  • the computer program is executed by the processor, the above method embodiment is realized.
  • the program is stored in a storage medium and includes several instructions to enable a device ( It may be a single-chip microcomputer, a chip, etc.) or a processor (processor) that executes all or part of the steps of the methods described in the embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

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Abstract

一种频率合成器、频率合成方法、电子设备及存储介质。频率合成器包括：参考晶振、整数频率合成器电路和小数频率合成器电路；参考晶振用于为整数频率合成器电路提供参考时钟信号；整数频率合成器电路用于为小数频率合成器电路提供参考时钟信号，供小数频率合成器电路根据参考时钟信号得到鉴相频率；小数频率合成器电路用于根据鉴相频率生成小数杂散值大于预设阈值的频率信号。

Description

一种频率合成器、频率合成方法、电子设备及存储介质
相关申请的交叉引用
本申请基于申请号为201911326845.9、申请日为2019年12月20日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请实施例涉及通信领域，特别涉及一种频率合成器、频率合成方法、电子设备及存储介质。
背景技术
随着通信技术的发展，在进行电子通信的过程中，通过锁相环频率合成器对信号进行合成和输出，并且输出的信号的频带宽度变得越来越大，由于小数频率合成器频率分辨率高，输出频率范围宽等特性，使其被广泛应用在电子通讯测试系统中。当小数频率合成器需要输出一个宽频段全覆盖的射频信号时，在传统方案下不可避免的会出现小数杂散落在锁相环环路带宽以内的情况，如何抑制小数杂散问题一直是一个技术难题，现有的小数杂散抑制方法主要通过使用两个或多个小数频率合成器电路实现，即在参考时钟信号后连接一个或多个小数频率合成器来实现输入到最终的小数频率合成器的鉴相频率调节，从而来抑制最终的小数频率合成器的小数杂散。或者采取多个参考晶振给小数频率合成器做参考，通过开关切换不同的参考源，实现输入到最终的小数频率合成器的参考频率切换，从而实现最终的小数频率合成器的鉴相频率调节来实现小数杂散抑制。
在进行信号合成的时候，调节鉴相频率需要较为复杂的电路结构，切换鉴相频率时控制复杂，可能引入新的小数杂散。
发明内容
本申请实施方式提供了一种频率合成器、频率合成方法、电子设备及存储介质。
本申请的实施方式提供了一种频率合成器，包括：参考晶振、整数频率合成器电路和小数频率合成器电路；其中，参考晶振与整数频率合成器电路的参考时钟输入端相连，用于为 整数频率合成器电路提供参考时钟信号；整数频率合成器电路的输出端连接小数频率合成器电路的参考时钟输入端，用于为小数频率合成器电路提供参考时钟信号，供小数频率合成器电路根据参考时钟信号得到鉴相频率；小数频率合成器电路用于根据鉴相频率生成小数杂散值大于预设阈值的频率信号。
本申请的实施方式还提供了一种频率合成方法，包括：应用于频率合成器，频率合成器包括：参考晶振、整数频率合成器电路和小数频率合成器电路，参考晶振与整数频率合成器电路的参考时钟输入端相连，整数频率合成器电路的输出端连接小数频率合成器电路的参考时钟输入端；频率合成方法包括：获取整数频率合成器电路的输出信号，将输出信号作为小数频率合成器电路的参考时钟信号，输入到小数频率合成器电路；检测小数频率合成器电路生成的频率信号的小数杂散值是否大于预设阈值；若不大于预设阈值，则调整整数频率合成器电路的输出信号，并重新检测小数频率合成器电路生成的频率信号的小数杂散值是否大于预设阈值，直至小数频率合成器电路生成的频率信号的小数杂散值大于预设阈值。
本申请的实施方式还提供了一种电子设备，包括：至少一个处理器；以及，与至少一个处理器通信连接的存储器；其中，存储器存储有可被至少一个处理器执行的指令，指令被至少一个处理器执行，以使至少一个处理器能够执行上述的频率合成方法。
本申请的实施方式还提供了一种计算机可读存储介质，存储有计算机程序，计算机程序被处理器执行时实现上述的频率合成方法。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定。
图1是根据现有技术中的一种频率合成器的结构示意图；
图2是根据现有技术中的另一种频率合成器的结构示意图；
图3是根据本申请第一实施方式中的频率合成器的结构示意图；
图4是根据本申请第二实施方式中的频率合成器的结构示意图；
图5是根据本申请第三实施方式中的频率合成方法流程图；
图6是根据本申请第四实施方式中的电子设备结构示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施方式中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施方式的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
在进行小数杂散规避的时候，通常是将最接近输出信号频率的鉴相频率的谐波和输出信号频率的差值Δf作为小数杂散的量化目标，一般小数杂散在小数频率合成器环路滤波器带宽BW的20至30倍位置处，即可将小数杂散绝大部分抑制。现有技术中具备小数杂散规避功能的信号合成的结构示意图如图1和图2所示，在图1所示的结构中，通过为第一小数频率合成器和第二小数频率合成器提供一个相同的参考晶振，通过两个小数频率合成器得到两个输出ref1和ref2，然后将两个小数频率合成器的输出连接到一个射频开关上，根据射频开关选择向第三小数频率合成器输入的参考时钟信号，进而对第三小数频率合成器的参考时钟进行调整，从而调整根据参考时钟确定的鉴相频率，使得第三小数频率合成器的鉴相频率可调。
在图2所示的结构中，参考晶振1和参考晶振2通过不同的供电电源，借助频率发生器产生不同的参考晶振，然后将参考晶振输入到射频开关，通过晶振切换电路，对要输入到频率检测器的参考晶振进行选取，再通过锁相环电路根据参考晶振确定鉴相频率后，根据鉴相频率输出合成后的不同频率的信号，通过在多个参考晶振中选取一个作为锁相环电路的参考晶振，从而实现锁相环电路鉴相频率的切换。
通过多个小数频率合成器结合射频开关进行第三小数频率合成器的鉴相频率的调整时，存在需要较多的小数频率合成器，电路结构和控制都比较复杂，并且可能引入新的小数杂散的问题；通过射频开关在多个参考晶振中选择一个为锁相环电路提供参考时钟信号，通过选取的参考时钟信号来调整鉴相频率时，存在需要多个参考晶振，占用较大的电路面积的问题。
本申请实施方式的提供了一种频率合成器、频率合成方法、电子设备及存储介质，使得能够根据输出信号的频率灵活切换鉴相频率，实现对小数杂散的良好规避，降低电路复杂程度和控制难度，提高输出信号的频谱质量。
本申请的第一实施方式涉及一种频率合成器，本实施方式中的频率合成器的结构示意图如图3所示，通过整数频率合成器电路的输出作为小数频率合成器电路参考时钟的输入，根 据小数频率合成器电路输出信号的频率，调节整数频率合成器电路的输出，从而灵活调整小数频率合成器电路的鉴相频率。
下面对本实施方式中的频率合成器的实现细节进行具体的说明，以下内容仅为方便理解提供的实现细节，并非实施本方案的必须。
在本实施方式的频率合成器中，参考晶振和整数频率合成器电路的参考时钟输入端相连，将参考晶振作为整数频率合成器电路的输入，为整数频率合成器电路提供参考时钟信号，使得整数频率合成器可以根据参考晶振生成输出信号；整数频率合成器电路的输出端和小数频率合成器电路的参考时钟输入端相连，将整数频率合成器电路的输出作为小数频率合成器电路的参考时钟信号，使得小数频率合成器电路的参考时钟输入可以根据整数频率合成器电路的输出进行灵活的变更，小数频率合成器电路根据整数频率合成器电路提供的参考时钟信号，确定自身的鉴相频率，然后根据鉴相频率生成小数杂散值大于预设阈值的频率信号。通过将整数频率合成器电路的输出作为小数频率合成器电路的参考时钟输入，使得小数频率合成器电路的参考时钟可以根据整数频率合成器电路的输出进行变更，进而灵活的切换小数频率合成器电路的鉴相频率，使得小数频率合成器电路输出不同频率的信号时，都能够进行良好的小数杂散规避。通过将整数频率合成器电路的输出作为小数频率合成器电路的参考时钟，借助调整整数频率合成器电路的输出的方法调整小数频率合成器电路的参考时钟信号，进而保证了小数频率合成器电路的鉴相频率能够根据输出信号的频率进行灵活的调整，从而实现输出各频率的信号的时候都能进行良好的小数杂散规避；通过整数频率合成器电路的输出作为小数频率合成器电路的参考时钟，避免了需要多个小数频率合成器电路导致的电路结构和控制方式复杂的问题，并避免了引入新的小数杂散，提高了输出信号的频谱质量。
在一个实施例中，整数频率合成器电路包括：第一鉴相器、第一环路滤波器、第一压控振荡器、第一分频器和第二分频器；其中，第一鉴相器的第一输入端连接参考晶振，第一鉴相器的第二输入端连接第一分频器的输出端，第一鉴相器的输出端连接第一环路滤波器的输入端，用于对根据参考晶振确定的第一鉴相频率与分频后的第一压控振荡器的反馈信号进行鉴相，并将鉴相结果传输到第一环路滤波器；第一环路滤波器的输出端连接第一压控振荡器的输入端，用于根据鉴相结果生成第一控制信号，并将第一控制信号传输到第一压控振荡器；第一压控振荡器的反馈输出端连接第一分频器的输入端，第一压控振荡器的信号输出端连接第二分频器的输入端，用于调整输出信号的频率，并向第一分频器传输反馈信号；第一分频器用于对第一压控振荡器的反馈信号进行分频；第二分频器的输出端连接小数频率合成器电路的参考时钟输入端，用于对第一压控振荡器的输出信号进行分频。通过对整数频率合成器 电路输出信号的分频和调整，使得输出信号能够根据小数频率合成器需要的参考时钟信号进行频率的调整，进而保证小数频率合成器电路能够根据参考时钟信号对应的鉴相频率对输出信号的小数杂散进行良好的规避。通过调整可编程调整的第二分频器的分频系数对整数频率合成器电路输出的信号进行分频得到Fout1，将分频后的输出信号Fout1传输到小数频率合成器电路的参考时钟信号输入端，使得小数频率合成器电路根据获取到的参考时钟信号对应的鉴相频率进行信号的合成和输出时，能够对各种频率的输出信号都具有良好的小数杂散规避效果。
在一个实施例中，整数频率合成器电路还包括：第三分频器；第三分频器的输入端连接参考晶振，第三分频器的输出端连接第一鉴相器的第二输入端，用于对整数频率合成器电路获取到的参考晶振进行分频。通过对参考晶振提供的参考时钟信号的分频，使整数频率合成器电路的输出信号能够更加符合小数频率合成器电路需要的参考时钟信号，供小数频率合成器获取到符合要求的参考时钟，从而保证最终输出的信号的频谱质量。通过对参考晶振的分频，使得整数频率合成器电路的输出信号的频率更加吻合小数频率合成器电路对参考时钟信号频率的需求，供小数频率合成器获取到符合要求的参考时钟，从而保证最终输出的信号的质量。
在一个实施例中，小数频率合成器电路包括：第二鉴相器、第二环路滤波器、第二压控振荡器和第四分频器；第二鉴相器的第一输入端连接整数频率合成器电路的电路输出端，第二鉴相器的第二输入端连接第四分频器的输出端，第二鉴相器的输出端连接第二环路滤波器的输入端，用于对根据整数频率合成器电路提供的参考时钟信号确定的鉴相频率和分频后的第二压控振荡器的反馈信号进行鉴相，并将鉴相结果传输到第二环路滤波器；第二环路滤波器的输出端连接第二压控振荡器的输入端，用于根据鉴相结果生成第二控制信号，并将第二控制信号传输到第二压控振荡器；第二压控振荡器的反馈输出端连接第四分频器的输入端，用于调整待输出信号的频率，输出频率信号并向第四分频器传输反馈信号；第四分频器用于对第二压控振荡器的反馈信号进行分频，第四分频器的输出信号进入第二鉴相器与参考信号进行鉴相比较；第二环路滤波器根据第二鉴相器确定的反馈信号和鉴相频率的鉴相结果产生控制信号调整第二压控振荡器输出信号的频率，实现了进行各频率的信号输出时，都能够有效的对输出信号的小数杂散进行规避；小数频率合成器电路是基于Σ-Δ调制技术实现。通过根据鉴相器的鉴相结果进行反馈控制调节，保证了能够有效的对输出信号的小数杂散进行规避。
在一个实施例中，小数频率合成器电路还包括：第五分频器；第五分频器的输入端连接 整数频率合成器电路的电路输出端，第五分频器的输出端连接第二鉴相器的第一输入端，用于对整数频率合成器电路提供的参考时钟信号进行分频；第二鉴相器的第一输入端通过第五分频器连接整数频率合成器电路的电路输出端，通过第五分频器对获取到的参考时钟信号进行分频，保证确定的鉴相频率符合小数频率合成器电路的需求，实现对小数杂散的良好规避。
在一个例子中，频率合成器进行信号的合成与输出时，先通过软件调节整数频率合成器电路的第一压控振荡器的配置数据以及第二分频器的分频系数，得到整数频率合成器电路能够输出的不同频率的Fout1，根据整数频率合成器电路这些可能的输出组成小数频率合成器电路的参考时钟信号备选库，然后根据小数频率合成器电路的环路带宽确定小数杂散的规避要求，在进行信号的合成与输出时，通过配置算法计算小数频率合成器电路输出各频率信号时，能够满足小数杂散规避要求的鉴相频率，然后根据确定的鉴相频率确定小数频率合成器电路所需的参考时钟信号，根据确定的参考时钟信号调节整数频率合成器电路的配置数据，使整数频率合成器电路输出满足要求的频率信号。在这里，为了实现更好的小数杂散消除效果，可以将规避原则设置为Δf<n·BW时进行规避，使得小数杂散落在n倍的环路带宽以外，从而被环路滤波器滤除，考虑到设计和电路成本等问题，n的取值范围可以设置为30至120。
例如，小数频率合成器电路输出信号的频率范围在3-9GHz之间，输出信号的环路带宽为50kHz，基础鉴相频率为50MHz，根据小数杂散的规避原则，选定n等于100，即小数杂散落在100倍的环路带宽处，此时即为设定了鉴相频率谐波和输出频率差值Δf<5MHz就需要采取规避措施，即小数杂散Δf<5MHz时需要重新选取鉴相频率，通过软件计算得到整数频率合成器电路所有可能的输出，得到了参考时钟信号备选库，根据小数频率合成器电路的基础鉴相频率，选取50MHz输出信号作为基础输出信号。在小数频率合成器电路进行信号合成和输出的时候，先根据基础输出信号设置整数频率合成器的第二分频器和第一压控振荡器的配置数据，输出50MHz的输出信号。某一时刻，小数频率合成器电路进行4500.03MHz信号的输出，根据参考时钟信号获取到的鉴相频率是基础鉴相频率50MHz，通过软件计算，鉴相频率的第90次谐波最接近输出频率，并且此时的Δf＝30kHz，小于50kHz，也就是说，此时的小数杂散将会出现在50kHz的环路带宽以内，判定不能够满足小数杂散的规避要求，此时，通过查询参考时钟信号备选库中的数据，将频率大于当前信号频率，并且最接近当前信号频率的备选信号作为待输出信号，通过查询参考时钟备选库中的数据，得到最接近50MHz的是51.28205MHz，则将频率为51.28205MHz的信号作为待输出信号，根据待输出信号的频率调整第二分频器和第一压控振荡器的配置数据，使得整数频率合成器电路的输出信号为51.28205MHz，此时，小数频率合成器电路的鉴相频率变更为51.28205MHz，此时， 鉴相频率的第88次谐波最接近输出信号的频率，计算得到Δf＝12.7904MHz，远大于50kHz，能够实现良好的小数杂散规避，因此，维持当前第二分频器和第一压控振荡器的配置数据不变，供小数频率合成器电路进行频率信号的合成和输出。
由此，本实施方式提供了一种频率合成器，通过借助整数频率合成器电路为小数频率合成器电路提供适当的参考时钟信号，使得小数频率合成器电路能够根据整数频率合成器电路的输出变更获得对应的鉴相频率，保证了小数频率合成器输出不同频率的信号时，都能够实现良好的小数杂散的规避；通过整数频率合成器电路提供小数频率合成器电路的参考时钟，避免了需要设置多个参考时钟信号发生电路，简化了电路的结构，降低了电路复杂程度和控制难度，节约了电路面积和成本，并且避免了多个小数频率合成器电路进行组合时，可能引入新的小数杂散的问题，保证了小数杂散规避的效果，提高了输出信号的质量。
本申请的第二实施方式涉及一种频率合成器，第二实施方式与第一实施方式大致相同，在本实施方式中，在小数频率合成器电路中，为小数频率合成器的反馈信号增加了对反馈信号进行预分频的第六分频器，通过对反馈信号的预分频，降低了对第四分频器的分频要求和难度，避免分频比过高导致信号质量下降而影响鉴相结果，进一步保证输出信号的质量。
本实施方式的结构示意图如图4所示，本实施方式中除第六分频器外，其余模块和第一实施方式中的各模块相似，为了避免重复，在此就不再一一赘述，仅对第六分频器进行说明。
本实施方式中，小数频率合成器电路还包括：第六分频器；第六分频器的输入端连接第二压控振荡器的反馈输出端，第六分频器的输出端连接第四分频器的输入端，用于对第二压控振荡器的反馈信号进行预分频，通过对反馈信号进行预分频，降低了在第四分频器的分频比，避免了由于分频比过高导致信号质量降低的问题，保证了输出信号的信号质量。
在一个例子中，在小数频率合成器电路中增设了第六分频器，由于鉴相器进比较的是鉴相频率某次谐波和第四分频器接收到的信号的频率之间的差值，因此，此时的小数杂散为Δf/p，其中，p为第六分频器的分频系数，例如，小数频率合成器需要输出3～9GHz信号，小数频率合成器的基础鉴相频率为50MHz，环路带宽为50kHz，第六鉴相器的分频系数为2，某一时刻，输出信号的频率为4500.03MHz，鉴相频率的第90次谐波和反馈到第四分频器的信号频率最为接近，此时，需要输出到鉴相器的反馈信号应该是输出频率经过第六分频器和第四分频器分频后的信号，由于第六分频器分频系数为2，已经对反馈信号进行了分频，因此，此时只需第四分频器的分频系数设置为45.0003即可，此时，鉴相频率第90次谐波和第六分频器输出频率的差值Δf＝30kHz，对应的小数杂散为Δf/p，也就是15kHz，然后根据小数杂散规避要求对当前小数杂散规避效果进行检测，并根据检测结果对整数频率合成器电路 的参数进行调整，使得整数频率合成器电路输出合适的频率，实现小数频率合成器电路鉴相频率的修改，直到小数杂散规避效果满足要求。
由此，本实施方式提供了一种频率合成器，通过在小数频率合成器电路的反馈信号传输通道中，在第四分频器前增设一个第六分频器，将反馈信号的分频过程变为二次分频，降低了第四分频器的分频比，避免了由于分频比过大导致的信号质量下降，保证了鉴相器收到的信号的质量，进而保证了鉴相结果的准确性，从而避免由于鉴相结果不准确影响小数杂散的规避效果，保证输出信号的质量。通过对反馈信号进行预分频，降低了第四分频器的分频比和难度，避免了由于分频比过高导致信号质量降低的问题，保证输出信号的信号质量。
本申请的第三实施方式涉及一种频率合成方法，具体地流程如图5所示，应用于上述任一实施方式的频率合成器，频率合成方法包括：
步骤101，获取整数频率合成器电路的输出信号。
具体地说，在进行频率信号的合成及输出之前，获取整数频率合成器电路的输出信号，将获取到的整数频率合成器电路的输出信号作为小数频率合成器电路的参考时钟信号，输入到小数频率合成器电路。
步骤102，检测小数杂散值是否大于预设阈值，若大于预设阈值，则进入步骤104，若不大于预设阈值，则进入步骤103。
具体地说，在将获取到的整数频率合成器电路的输出信号作为小数频率合成器电路的参考时钟信号后，根据小数频率合成器电路的参考时钟信号确定小数频率合成器电路的鉴相频率，根据确定的鉴相频率和待输出频率信号的频率，计算鉴相频率谐波中，最接近输出频率的谐波和输出频率之间的差值，确定小数频率合成器电路生成的频率信号的小数杂散值，检测小数频率合成器电路生成的频率信号的小数杂散值是否大于预设阈值，若大于预设阈值，则进入步骤104，若不大于预设阈值，则进入步骤103。
在实际应用中，小数杂散值的预设阈值可以根据小数杂散规避需求的实际情况进行设置，关于预设阈值的具体取值，本实施方式不做限制。
步骤103，调整整数频率合成器电路的输出。
具体地说，在检测到按照当前参考时钟信号对应的鉴相频率进行信号的合成与输出，小数杂散值不大于预设阈值时，判定当前参考时钟信号对应的鉴相频率不能在进行当前频率的信号合成及输出的过程中，实现良好的小数杂散的规避，需要调整参考时钟信号，即，调整整数频率合成器电路的输出信号，然后重新回到步骤102，重新检测小数频率合成器电路生成的频率信号的小数杂散值是否大于预设阈值，直至小数频率合成器电路生成的频率信号的 小数杂散值大于预设阈值。
在一个例子中，进行频率信号的合成与输出时，根据获取到的整数频率合成器电路输出信号的所有备选频率，生成参考时钟信号备选库1，然后根据小数频率合成器电路的基础鉴相频率，在参考时钟信号备选库1中，选取出整数频率合成器电路的基础输出信号，然后根据小数频率合成器电路输出信号的频率范围，通过软件计算，遍历小数频率合成器电路输出不同频率信号时所需的鉴相频率，以当前鉴相频率为基础检测当前鉴相频率能够适用的输出信号频率范围，检测到当前鉴相频率不满足小数杂散规避的要求时，在参考时钟备选库1中选取最接近当前输出信号频率的目标频率，根据目标频率调整整数频率合成器电路的配置数据，供整数频率合成器电路输出目标频率的输出信号，然后检测根据新的参考时钟信号对应的鉴相频率能够使用的输出信号范围，直到对小数频率合成器电路所有输出信号完成遍历。根据遍历计算过程中选取出的参考时钟信号生成参考时钟信号备选库2，在进行整数频率合成器电路输出调整时，直接在参考时钟信号备选库2中，选取频率最接近当前鉴相频率的目标频率，并根据选取的目标频率调整整数频率合成器电路配置数据，供整数频率合成器电路输出目标频率的输出信号。
在实际应用中，目标频率可以是大于当前信号频率的频率或者小于当前信号频率的频率中，最接近当前信号频率的频率值，本实施方式对于具体的选取规则不做限制。
例如，小数频率合成器需要输出3～9GHz信号，小数频率合成器的基础鉴相频率为50MHz，环路带宽为50kHz，整数频率合成器电路输出信号的频率包括整数频率合成器电路输出信号的频率包括：50MHz、55.55555MHz、54.05405MHz、52.63157MHz、51.28205MHz、48.78048MHz、47.61904MHz、46.51162MHz、45.45454MHz、55.88235MHz、54.28571MHz、52.77777MHz、51.35135MHz、48.71794MHz、47.5MHz、46.34146MHz、45.23809MHz等，根据整数频率合成器电路这多个可能的输出信号生成参考时钟备选库1，然后通过软件遍历计算，确定出进行3～9GHz信号输出时，需要的鉴相频率包括：50MHz、51.28205MHz、51.35135MHz、52.63157MHz和52.77777MHz，根据这5个鉴相频率对应的参考时钟信号，生成参考时钟备选库2，某一时刻，小数频率合成器电路输出4500.03MHz信号，此时采用的鉴相频率是50MHz，鉴相频率的第90次谐波最接近输出信号的频率，两者之间的差值Δf为30kHz，即，此时的小数杂散值为30kHz，不满足小数杂散规避要求，此时，从参考时钟备选库2中选取频率大于当前鉴相频率的信号中，最接近当前鉴相频率的51.28205MHz参考时钟作为待输出信号，并根据选取的信号调整整数频率合成器电路的配置数据，使其输出频率为51.28205MHz的信号，然后回到步骤102，重新检测小数频率合成器电路生成的频率信号的小数杂散值是否大于预 设阈值。
步骤104，输出频率信号。
具体地说，在检测到小数频率合成器电路输出频率信号的小数杂散值大于预设阈值的时候，可以直接判定当前参考时钟对应的鉴相频率能够在进行当前频率的信号的合成与输出过程中，实现良好的小数杂散的规避，因此，直接按照当前参考时钟信号进行频率信号的输出。
由此，本实施方式提供了一种频率合成方法，通过将整数频率合成器电路的输出作为小数频率合成器电路的参考时钟信号的输入，使得小数频率合成器的参考时钟可以灵活地根据整数频率合成器的输出进行变更，进而实现鉴相频率的灵活变更；通过预先建立的参考时钟备选库进行参考时钟信号的选取和整数频率合成器电路的调整，提高了鉴相频率调整的效率；通过小数杂散值的计算结果和预设阈值的关系进行整数频率合成器电路输出信号的调整，使得小数频率合成器电路的鉴相频率能够根据不同频率输出信号进行变更，实现输出不同频率信号时，都能进行良好的小数杂散规避，保证了输出信号的质量。
上面各种方法的步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对算法中或者流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其算法和流程的核心设计都在该专利的保护范围内。
本申请第四实施方式涉及一种电子设备，如图6所示，包括至少一个处理器；以及，与至少一个处理器通信连接的存储器；其中，存储器存储有可被至少一个处理器执行的指令，指令被至少一个处理器执行，以使至少一个处理器能够执行上述的频率合成方法。
其中，存储器和处理器采用总线方式连接，总线可以包括任意数量的互联的总线和桥，总线将一个或多个处理器和存储器的各种电路连接在一起。总线还可以将诸如外围设备、稳压器和功率管理电路等之类的各种其他电路连接在一起，这些都是本领域所公知的，因此，本文不再对其进行进一步描述。总线接口在总线和收发机之间提供接口。收发机可以是一个元件，也可以是多个元件，比如多个接收器和发送器，提供用于在传输介质上与各种其他装置通信的单元。经处理器处理的数据通过天线在无线介质上进行传输，进一步，天线还接收数据并将数据传送给处理器。
处理器负责管理总线和通常的处理，还可以提供各种功能，包括定时，外围接口，电压调节、电源管理以及其他控制功能。而存储器可以被用于存储处理器在执行操作时所使用的数据。
本申请第五实施方式涉及一种计算机可读存储介质，存储有计算机程序。计算机程序被 处理器执行时实现上述方法实施例。
即，本领域技术人员可以理解，实现上述实施例方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种频率合成器，包括：参考晶振、整数频率合成器电路和小数频率合成器电路；
    其中，所述参考晶振与所述整数频率合成器电路的参考时钟输入端相连，用于为所述整数频率合成器电路提供参考时钟信号；
    所述整数频率合成器电路的输出端连接所述小数频率合成器电路的参考时钟输入端，用于为所述小数频率合成器电路提供参考时钟信号，供所述小数频率合成器电路根据所述参考时钟信号得到鉴相频率；
    所述小数频率合成器电路用于根据所述鉴相频率生成小数杂散值大于预设阈值的频率信号。
  2. 根据权利要求1所述的频率合成器，其中，所述整数频率合成器电路包括：第一鉴相器、第一环路滤波器、第一压控振荡器、第一分频器和第二分频器；
    其中，所述第一鉴相器的第一输入端接入所述参考晶振，所述第一鉴相器的第二输入端连接所述第一分频器的输出端，所述第一鉴相器的输出端连接所述第一环路滤波器的输入端，用于对根据所述参考晶振提供的参考时钟信号确定的第一鉴相频率与分频后的所述第一压控振荡器的反馈信号进行鉴相，并将鉴相结果传输到所述第一环路滤波器；
    所述第一环路滤波器的输出端连接所述第一压控振荡器的输入端，用于根据所述鉴相结果生成第一控制信号，并将所述第一控制信号传输到所述第一压控振荡器；
    所述第一压控振荡器的反馈输出端连接所述第一分频器的输入端，所述第一压控振荡器的信号输出端连接所述第二分频器的输入端，用于调整待输出信号的频率，输出频率信号并向所述第一分频器传输反馈信号；
    所述第一分频器用于对所述第一压控振荡器的反馈信号进行分频；
    所述第二分频器的输出端连接所述小数频率合成器电路的所述参考时钟输入端，用于对所述第一压控振荡器的输出信号进行分频。
  3. 根据权利要求1所述的频率合成器，其中，所述整数频率合成器电路包括：第一鉴相器、第一环路滤波器、第一压控振荡器、第一分频器、第二分频器和第三分频器；
    其中，所述第三分频器的输入端连接所述参考晶振，所述第三分频器的输出端连接所述第一鉴相器的第一输入端，用于对所述参考晶振提供的参考时钟信号进行分频；
    所述第一鉴相器的第二输入端连接所述第一分频器的输出端，所述第一鉴相器的输出端连接所述第一环路滤波器的输入端，用于对根据分频后的参考时钟信号确定的第一鉴相频率 与分频后的所述第一压控振荡器的反馈信号进行鉴相，并将鉴相结果传输到所述第一环路滤波器；
    所述第一环路滤波器的输出端连接所述第一压控振荡器的输入端，用于根据所述鉴相结果生成第一控制信号，并将所述第一控制信号传输到所述第一压控振荡器；
    所述第一压控振荡器的反馈输出端连接所述第一分频器的输入端，所述第一压控振荡器的信号输出端连接所述第二分频器的输入端，用于调整待输出信号的频率，输出频率信号并向所述第一分频器传输反馈信号；
    所述第一分频器用于对所述第一压控振荡器的反馈信号进行分频；
    所述第二分频器的输出端连接所述小数频率合成器电路的所述参考时钟输入端，用于对所述第一压控振荡器的输出信号进行分频。
  4. 根据权利要求1所述的频率合成器，其中，所述小数频率合成器电路包括：第二鉴相器、第二环路滤波器、第二压控振荡器和第四分频器；
    其中，所述第二鉴相器的第一输入端连接所述整数频率合成器电路的电路输出端，所述第二鉴相器的第二输入端连接所述第四分频器的输出端，所述第二鉴相器的输出端连接所述第二环路滤波器的输入端，用于对根据所述整数频率合成器电路提供的参考时钟信号确定的鉴相频率和分频后的所述第二压控振荡器的反馈信号进行鉴相，并将鉴相结果传输到所述第二环路滤波器；
    所述第二环路滤波器的输出端连接所述第二压控振荡器的输入端，用于根据所述鉴相结果生成第二控制信号，并将所述第二控制信号传输到所述第二压控振荡器；
    所述第二压控振荡器的反馈输出端连接所述第四分频器的输入端，用于调整待输出信号的频率，输出频率信号并向所述第四分频器传输反馈信号；
    所述第四分频器用于对所述第二压控振荡器的反馈信号进行分频。
  5. 根据权利要求1所述的频率合成器，其中，所述小数频率合成器电路包括：第二鉴相器、第二环路滤波器、第二压控振荡器、第四分频器和第五分频器；
    其中，所述第五分频器的输入端连接所述整数频率合成器电路的电路输出端，所述第五分频器的输出端连接所述第二鉴相器的第一输入端，用于对所述整数频率合成器电路提供的参考时钟信号进行分频；
    所述第二鉴相器的第二输入端连接所述第四分频器的输出端，所述第二鉴相器的输出端连接所述第二环路滤波器的输入端，用于对根据分频后的所述整数频率合成器电路提供的参考时钟信号确定的鉴相频率和分频后的所述第二压控振荡器的反馈信号进行鉴相，并将鉴相 结果传输到所述第二环路滤波器；
    所述第二环路滤波器的输出端连接所述第二压控振荡器的输入端，用于根据所述鉴相结果生成第二控制信号，并将所述第二控制信号传输到所述第二压控振荡器；
    所述第二压控振荡器的反馈输出端连接所述第四分频器的输入端，用于调整待输出信号的频率，输出频率信号并向所述第四分频器传输反馈信号；
    所述第四分频器用于对所述第二压控振荡器的反馈信号进行分频。
  6. 根据权利要求1所述的频率合成器，其中，所述小数频率合成器电路包括：第二鉴相器、第二环路滤波器、第二压控振荡器、第四分频器、第五分频器和第六分频器；
    其中，所述第五分频器的输入端连接所述整数频率合成器电路的电路输出端，所述第五分频器的输出端连接所述第二鉴相器的第一输入端，用于对所述整数频率合成器电路提供的参考时钟信号进行分频；
    所述第二鉴相器的第一输入端连接所述第五分频器的输出端，所述第二鉴相器的第二输入端连接所述第四分频器的输出端，所述第二鉴相器的输出端连接所述第二环路滤波器的输入端，用于对根据分频后的所述整数频率合成器电路提供的参考时钟信号确定的鉴相频率和分频后的所述第二压控振荡器的反馈信号进行鉴相，并将鉴相结果传输到所述第二环路滤波器；
    所述第二环路滤波器的输出端连接所述第二压控振荡器的输入端，用于根据所述鉴相结果生成第二控制信号，并将所述第二控制信号传输到所述第二压控振荡器；
    所述第二压控振荡器的反馈输出端连接所述第六分频器的输入端，用于调整待输出信号的频率，输出频率信号并向所述第六分频器传输反馈信号；
    所述第六分频器的输出端连接所述第四分频器的输入端，用于对所述第二压控振荡器的反馈信号进行预分频，并将预分频后的所述第二压控振荡器的反馈信号输出到所述第四分频器，供所述第四分频器对预分频后的所述第二压控振荡器的反馈信号进行再分频。
  7. 一种频率合成方法，应用于频率合成器，其中，所述频率合成器包括：参考晶振、整数频率合成器电路和小数频率合成器电路，所述参考晶振与所述整数频率合成器电路的参考时钟输入端相连，所述整数频率合成器电路的输出端连接所述小数频率合成器电路的参考时钟输入端；所述频率合成方法包括：
    获取所述整数频率合成器电路的输出信号，将所述输出信号作为所述小数频率合成器电路的参考时钟信号，输入到所述小数频率合成器电路；
    检测所述小数频率合成器电路生成的频率信号的小数杂散值是否大于预设阈值；
    若不大于所述预设阈值，则调整所述整数频率合成器电路的输出信号，并重新检测所述小数频率合成器电路生成的频率信号的小数杂散值是否大于所述预设阈值，直至所述小数频率合成器电路生成的频率信号的小数杂散值大于所述预设阈值。
  8. 根据权利要求7所述的频率合成方法，其中，所述调整所述整数频率合成器电路的输出信号，包括：
    获取所述整数频率合成电路输出信号的所有备选频率；
    根据所述备选频率，确定最接近当前输出信号频率的目标频率；
    根据所述目标频率调整所述整数频率合成器电路的配置数据，供所述整数频率合成器电路输出所述目标频率的输出信号。
  9. 一种电子设备，包括：
    至少一个处理器；以及，
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如权利要求7或8所述的频率合成方法。
  10. 一种计算机可读存储介质，存储有计算机程序，其中，所述计算机程序被处理器执行时实现权利要求7或8所述的频率合成方法。
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