WO2018126800A1 - 一种低相位噪声频率合成器 - Google Patents

一种低相位噪声频率合成器 Download PDF

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WO2018126800A1
WO2018126800A1 PCT/CN2017/111496 CN2017111496W WO2018126800A1 WO 2018126800 A1 WO2018126800 A1 WO 2018126800A1 CN 2017111496 W CN2017111496 W CN 2017111496W WO 2018126800 A1 WO2018126800 A1 WO 2018126800A1
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phase
locked loop
locked
frequency
signal
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PCT/CN2017/111496
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French (fr)
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吴成林
王崔州
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成都西蒙电子技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • the present invention relates to the field of frequency synthesis, and in particular to a low phase noise frequency synthesizer.
  • FIG. 1 A block diagram of a frequency synthesizer using a phase-locked loop (PLL) is shown in Figure 1: including a phase detector (PD), a loop filter (LF), a voltage controlled oscillator (VCO), and a phase detector that references the input signal.
  • the phase of (XTAL) is compared with the phase of the VCO signal, and the phase error of the two input signals is converted by the PD into an error voltage, which is filtered by the loop filter as a control voltage of the VCO, and the control voltage changes the output of the VCO.
  • the output frequency of the VCO reaches the required frequency, and the output frequency is locked with the reference frequency.
  • the output frequency is higher than the reference frequency, it is generally necessary to increase the frequency divider (N) in the feedback branch so that the two signals input to the PD are substantially equal in frequency.
  • a reference divider (R) can be used for the reference signal to obtain a smaller phase-detection frequency.
  • the carrier near-end phase noise of the output frequency is generally considered.
  • the near-end phase noise formula of the whole system can be obtained as:
  • PN total PN REF + PN 1Hz +10*log(fcomp)+20*log(N)
  • PNref is the phase noise of the reference frequency
  • PN1Hz is the equivalent noise floor of the phase detector.
  • Fcomp is the phase discrimination frequency
  • fcomp fout/N
  • N is the feedback division ratio. Since the phase-locked loop is essentially equivalent to the frequency multiplier, the phase noise of the output frequency relative to the phase-detection frequency or the reference frequency is 20*log(N).
  • the architecture changes, usually using the method of intra-band mixing, first mix the output frequency with a frequency f1, get a lower feedback frequency to phase with the reference frequency.
  • the disclosure of U.S. Patent Application Serial No. US20563208 is hereby incorporated by reference.
  • phase noise cancellation technology such as feedforward technology, etc.
  • see the application date is US$2007.5.15, and the application number is US80360207.
  • phase noise improvement 10*log(N) is obtained.
  • IMS International Microwave Symposium
  • the correlation phase noise deterioration factor of 20*log(N) is not changed, and the phase noise of the output frequency is a coefficient of 20*log(N).
  • Deterioration When the output frequency is high or N is large, the phase noise of the output frequency deteriorates more.
  • Method 5 has great difficulty in implementing technology, especially when the frequency is high, and when the output frequency is not a point frequency but needs a certain bandwidth, it is very difficult to achieve, and the phase noise is improved by cancellation. It is also very limited.
  • Method 6 based on the uncorrelated phase noise superposition theory is really able to greatly improve the output phase noise index. However, it uses a phase noise filter method to obtain uncorrelated multipath signals.
  • phase noise filter itself has a certain bandwidth, it can only improve the phase noise of the far end (such as 1M), and the near phase noise is due to There is still correlation between the multiplexed signals, so the near-end phase noise cannot be improved.
  • the filter is a fixed frequency device, the method can only be applied to the point frequency signal, and the frequency synthesizer signal requiring a frequency variation bandwidth for the output signal is also not applicable.
  • the existing scheme has limited improvement in phase noise of the output signal of the frequency synthesizer, and the circuit structure is complicated.
  • the present invention overcomes the above-mentioned deficiencies of the prior art and provides a low phase noise frequency synthesizer capable of effectively improving phase noise and having a simple circuit structure.
  • a low phase noise frequency synthesizer comprising a reference crystal for generating a reference signal, the reference crystal connected to a power divider, the power divider being coupled to a signal input of at least one phase locked synthesis unit for reference
  • the signal is distributed and sent to each of the phase-locked synthesis units, wherein the phase-locked synthesis unit includes a first phase-locked loop for phase-locking the first crystal, and a second phase-locked loop for The crystal oscillator is phase-locked, the first crystal oscillator outputs a first signal to a fourth phase-locked loop, the second crystal oscillator outputs a second signal to a third phase-locked loop, and the third phase-locked loop is used for the The two signals are phase-locked; the third phase-locked loop and the fourth phase-locked loop combine the output signals and output the signals.
  • the phase locked loop includes a phase detector, a loop filter, a voltage controlled oscillator, and a frequency divider that are sequentially connected.
  • phase detector is a digital phase detector or an analog phase detector.
  • first phase locked loop and the second phase locked loop are both narrow band phase locked loops.
  • the narrowband phase-locked loop loop bandwidth is less than 10 Hz.
  • the low phase noise frequency synthesizer of the present invention utilizes a non-correlated phase noise superposition principle, uses a narrow band phase lock technique to obtain multiple uncorrelated frequency signals, and combines these signals by frequency and structure by means of an in-loop mixing architecture. Get the desired output frequency. Due to the use of uncorrelated phase noise superposition, the deterioration of the output phase noise is degraded by a multiple of 10*log(N) with respect to the reference signal, instead of the 20*log(N) multiple of the prior art, which is relative to the existing The technology can obtain a phase noise improvement of 10*log(N), and obtain extremely low phase noise. At the same time, the circuit structure of the invention is simple and easy to implement.
  • FIG. 1 is a block diagram of a low phase noise frequency synthesizer module of the present invention.
  • Figure 2 shows two low phase noise frequency synthesizer circuits in one embodiment.
  • Figure 3 shows a two-way low phase noise frequency synthesizer circuit in another embodiment.
  • Figure 4 shows a four-way low phase noise frequency synthesizer circuit.
  • Figure 5 shows a multi-channel low phase noise frequency synthesizer circuit.
  • 1 is a block diagram of a low phase noise frequency synthesizer module of the present invention, including a reference crystal for generating a reference signal, the reference crystal connected to a power splitter, the power splitter connecting a signal of at least one phase locked synthesizing unit
  • the input end is configured to distribute the reference signal to each of the lock phase synthesis units, wherein the lock phase synthesis unit includes a first phase locked loop for phase locking the first crystal oscillator, and the second lock a phase loop for phase locking the second crystal oscillator, the first crystal oscillator outputs a first signal to a fourth phase locked loop, and the second crystal oscillator outputs a second signal to a third phase locked loop, the third lock
  • the phase loop is configured to phase lock the second signal; the third phase locked loop and the fourth phase locked loop mix and output the output signal.
  • the phase locked loop includes a phase detector, a loop filter, a voltage controlled oscillator, and a frequency divider that are sequentially connected.
  • the phase detector is a digital phase detector or an analog phase detector.
  • the first phase locked loop and the second phase locked loop are both narrow band phase locked loops.
  • the narrowband phase-locked loop has a bandwidth of less than 10 Hz.
  • the invention utilizes the principle that the phase noise of the combination of multiple uncorrelated signals is linearly superimposed.
  • narrow-band phase-locking to obtain multiple uncorrelated signals first, and combining these signals by intra-ring mixing, the phase noise improvement of 10*logN compared with conventional phase-locked technology can be obtained, where N is an uncorrelated frequency. Number of roads.
  • Figure 2 shows a frequency synthesizer circuit diagram including only one set of phase-locked synthesis units, where X0 is the reference crystal and X1 and X2 are also crystals. V1 and V2 are voltage controlled oscillators (VCOs).
  • the PD is a phase detector, which can be a digital phase detector or an analog phase detector.
  • N is a frequency divider.
  • PS is a power divider.
  • the LPF is a loop filter for each loop.
  • X1 and X2 are locked respectively.
  • PLL1 and PLL2 are the locked loops of X1 and X2.
  • These two loops use a narrow-band phase-locking technique, that is, the loop bandwidth of PLL1 and PLL2 is adjusted to be very narrow, about 10 Hz, which is calculated at 10 Hz in this embodiment.
  • the phase noise of the output frequencies f1 and f2 of the two loops is only relevant if the frequency deviates from the output frequency by 10 Hz and is related to the reference crystal X0.
  • the phase noise of the output frequency f4 is equal to the sum of the N*f1 frequency phase noise and the N*f2 frequency phase noise. Since in the narrowband phase-locked loops PLL1 and PLL2, f1 and f2 have been deviated from the center frequency by 10 Hz. The phase noise is irrelevant. Therefore, according to the principle of linear superposition of uncorrelated signal noise, the phase noise outside the center frequency of 10 Hz at the output frequency f4 is:
  • FIG. 3 is another embodiment of the present invention, which employs the principle of frequency addition.
  • the present invention also provides phase noise comparison at the output frequency of 13 GHz in the prior art and the solution in the first embodiment.
  • the phase noise of the prior art scheme is -112.5 dBc/Hz at 1K, 10K and 100K, respectively. -117dBc/Hz, -118.86dBc/Hz.
  • the present invention is -115.1 dBc/Hz, -119.4 dBc/Hz, -120 dBc/Hz.
  • the phase noise of the inventive scheme at 1K, 10K, and 100K has an increase of 2.6 dB, 2.4 dB, and 1.14 dB, respectively.
  • phase noise improvement when there are a plurality of phase-locked synthesis units, as shown in FIG. 4 and FIG. 5, as the number of ways increases, the phase noise is also improved. For example, when the number of combined paths is 4 or 8, Theoretically, phase noise improvement of 6dB and 9dB can be obtained.

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Abstract

本发明公开了一种低相位噪声频率合成器，包括参考晶振，用于产生参考信号，所述参考晶振连接功率分配器，所述功率分配器连接至少一个锁相合成单元的信号输入端，用于将所参考信号分配后发送到每个所述锁相合成单元，其中，所述锁相合成单元包括第一锁相环，用于对第一晶振进行锁相，第二锁相环，用于对第二晶振进行锁相，所述第一晶振输出第一信号到第四锁相环，所述第二晶振输出第二信号到第三锁相环，所述第三锁相环用于对所述第二信号进行锁相；所述第三锁相环、第四锁相环将输出的信号进行混频组合后输出。本发明的方案利用非相关相噪叠加原理，能够改善相位噪声、电路结构简单。

Description

一种低相位噪声频率合成器 技术领域
本发明涉及频率合成领域，特别涉及一种低相位噪声频率合成器。
背景技术
随着电子设备的发展，电子系统对频率源提出了愈来愈高的要求，特别是在相位噪声、跳频速度、杂散等关键指标上更是如此。
现代频率合成器主要采用直接数字合成和锁相环技术。其中，绝大部分频率合成器采用的是锁相环技术。采用锁相环(PLL)的频率合成器组成框图如图1所示：包括鉴相器(PD)、环路滤波器(LF)、压控振荡器(VCO)，鉴相器把参考输入信号(XTAL)的相位与VCO信号的相位进行比较，由PD将这两个输入信号的相位误差转换为误差电压，该电压由环路滤波器滤波后作为VCO的控制电压，控制电压改变VCO的输出频率，当闭环系统稳定后，VCO的输出频率即达到所需要的频率，完成输出频率与参考频率的锁定。当输出频率高于参考频率时，一般还需要在反馈支路增加分频器(N)，使得输入到PD的两路信号频率大致相等。同样，参考信号也可以使用一个分频器(R)，来获得较小的鉴相频率。
在实际应用中，一般重点考虑输出频率的载波近端相位噪声，通过对PLL架构的数学推导，可以得到整个系统的输出近端相位噪声公式为：
PNtotal＝PNREF+PN1Hz+10*log(fcomp)+20*log(N)
其中，PNref为参考频率的相位噪声，PN1Hz为鉴相器的等效噪声基底， 当采用数字鉴相器时，该值是评估鉴相器相噪特性好坏的重要参数。fcomp为鉴相频率，fcomp＝fout/N。N为反馈分频比。由于锁相环本质上是等同于倍频器，因此输出频率相对于鉴相频率或者参考频率的相噪恶化为20*log(N)。
从上式中可以看出，为了获得具有更低相位噪声的输出频率，目前现有以下几种方法：
1、采用更低相噪指标的参考频率，即降低PNREF。但该指标受系统底噪的影响而不能无限降低。
2、降低鉴相器的等效噪声基底，即降低PN1HZ。普遍的方法是采用取样鉴相器代替数字鉴相器。如申请日为2003.11.14，申请号为US71371703的美国发明与申请日为1993.5.12，申请号为US6075593的美国发明公开的内容即采用这种方式。
3、降低鉴相频率或降低分频比，即降低fcomp和N。但减小fcomp必然会增加N，反而会带来相噪的恶化。因此常用的办法是增大fcomp而使得N减小。但这样的坏处是无法获得比较小的频率步进。
4、架构上改变，通常是采用环内混频的方法，先将输出频率与一个频率f1相混频，得到一个比较低的反馈频率去同参考频率鉴相。这样，输出频率fout＝f1+N2*fcomp＝N1*fref+N2*fcomp。由于f1可以采用一个点源或者大步进的频综，因此f1的输出相噪式中可以采用前面3种方法相对容易的获得较好的相位噪声指标。从而改善第3点中无法获得小的频率步进的问题，即兼顾了相噪和小的频率步进。如申请日为2008.9.5，申请号为US20563208的美国发明专利公开的方案。
5、采用相噪对消技术，比如前馈技术等，参看申请日为2007.5.15，申请号为US80360207的美国发明专利公开的方案。
6、利用不相关的相位噪声叠加仅仅是线性功率叠加的原理，获得10*log(N)的相噪改善。具体参看《Phase Noise Improvement for Array Systems》，Shilei Hao，Tongning Hu，Qun Jane Gu，P1～4，2016IEEE MTT-S International Microwave Symposium(IMS)与《A High Frequency Low Phase-Noise Signal Source Generated Using a Self-Oscillating Mixer》，IET Microw.Antennas Propag.，2013，Vol.7，Iss.2，pp.123-130，公开的方案。
根据对现有上述方案的分析可知，在前述的方法2-4中，并没有改变20*log(N)的相关相位噪声恶化因子，输出频率的相位噪声是按照20*log(N)的系数恶化的。当输出频率很高或者N很大时，输出频率的相位噪声恶化比较多。方法5在实现技术上有较大的困难，特别是在频率较高时，而且在输出频率不是点频而是需要有一定带宽时，更是非常难以实现，而且对消带来的相噪提升也非常有限。方法6基于非相关相噪叠加理论是真正能够较大的改善输出相噪指标。但是其使用的是相噪滤波器的方法获得非相关的多路信号，由于相噪滤波器本身具有一定的带宽，所以只能改善远端(如1M)的相噪，而近端相噪由于多路信号之间仍然具有相关性，所以不能对近端相噪进行改善。同时，由于滤波器是频率固定的器件，该方法也仅能适用于点频信号，对于输出信号需要一段频率变化带宽的频率合成器信号也不适用。
综上所述，现有方案对频率合成器输出信号的相位噪声改善有限、且电路结构复杂。
发明内容
本发明在于克服现有技术的上述不足，提供一种能够有效改善相位噪声、电路结构简单的低相位噪声频率合成器。
为了实现上述发明目的，本发明采用的技术方案是：
一种低相位噪声频率合成器，包括参考晶振，用于产生参考信号，所述参考晶振连接功率分配器，所述功率分配器连接至少一个锁相合成单元的信号输入端，用于将所参考信号分配后发送到每个所述锁相合成单元，其中，所述锁相合成单元包括第一锁相环，用于对第一晶振进行锁相，第二锁相环，用于对第二晶振进行锁相，所述第一晶振输出第一信号到第四锁相环，所述第二晶振输出第二信号到第三锁相环，所述第三锁相环用于对所述第二信号进行锁相；所述第三锁相环、第四锁相环将输出的信号进行混频组合后输出。
进一步地，所述锁相环包括依次连接的鉴相器、环路滤波器、压控振荡器、分频器。
进一步地，所述鉴相器为数字鉴相器或模拟鉴相器。
进一步地，所述第一锁相环、第二锁相环均为窄带锁相环。
进一步地，所述窄带锁相环环路带宽小于10Hz。
与现有技术相比，本发明的有益效果
本发明的低相位噪声频率合成器利用非相关相噪叠加原理，采用窄带锁相技术来获得多路的非相关频率信号，并通过环内混频的架构和方法将这些信号进行频率组合，以获得需要的输出频率。由于采用了非相关相噪叠加，输出相噪的恶化相对于参考信号是按照10*log(N)的倍数恶化，而不是现有技术的20*log(N)倍数恶化，这样相对于现有技术可以得到10*log(N)的相噪提升，获得极低的相位噪声，同时，本发明电路结构简单、容易实现。
附图说明
图1所示为本发明的低相位噪声频率合成器模块框图。
图2所示为一个实施例中的两路低相位噪声频率合成器电路。
图3所示为另一个实施例中的两路低相位噪声频率合成器电路。
图4所示为四路低相位噪声频率合成器电路。
图5所示为多路低相位噪声频率合成器电路。
具体实施方式
下面结合具体实施方式对本发明作进一步的详细描述。但不应将此理解为本发明上述主题的范围仅限于以下的实施例，凡基于本发明内容所实现的技术均属于本发明的范围。
图1所示为本发明的低相位噪声频率合成器模块框图，包括参考晶振，用于产生参考信号，所述参考晶振连接功率分配器，所述功率分配器连接至少一个锁相合成单元的信号输入端，用于将所参考信号分配后发送到每个所述锁相合成单元，其中，所述锁相合成单元包括第一锁相环，用于对第一晶振进行锁相，第二锁相环，用于对第二晶振进行锁相，所述第一晶振输出第一信号到第四锁相环，所述第二晶振输出第二信号到第三锁相环，所述第三锁相环用于对所述第二信号进行锁相；所述第三锁相环、第四锁相环将输出的信号进行混频后输出。
所述锁相环包括依次连接的鉴相器、环路滤波器、压控振荡器、分频器。
所述鉴相器为数字鉴相器或模拟鉴相器。
所述第一锁相环、第二锁相环均为窄带锁相环。
所述窄带锁相环带宽小于10Hz。
本发明利用多路非相关信号组合的相位噪声呈线性叠加的原理。通过窄带锁相先获得多路非相关的信号，并将这些信号通过环内混频的方式进行频率组合，能获得较常规锁相技术10*logN的相噪提升，其中N为不相关的频率路数。
实施例1：
图2所示为仅包括一组锁相合成单元的频率合成器电路图，其中，X0为参考晶振，X1和X2也是晶振。V1和V2为压控振荡器(VCO)。PD为鉴相器，可以是数字鉴相器也可以是模拟鉴相器。N为分频器。PS为功分器。LPF为各环路的环路滤波器。
参考晶振通过功分器分成两路后，分别对X1和X2进行锁定。其中PLL1和PLL2就是X1和X2的锁定环路。这两个环路采用窄带锁相技术，也就是将PLL1和PLL2的环路带宽调到很窄，大约在10Hz以内，本实施例以10Hz计算。这样这两个环路的输出频率f1和f2的相位噪声仅在频率偏离输出频率10Hz以内是相关的，并相关于参考晶振X0。在偏离10Hz以外的相位噪声是X1和X2的本身相位噪声，他们之间是不相关的。因此，输出频率f1和f2还是具有本身晶振的相噪特性，同时他们的输出频率由于窄带锁相的结果是严格相同的，即f1＝f2。
f2通过PLL3环路得到输出频率f3，f3＝N3*f2
PLL4是主环路，输出频率f4与f3混频后经过分频器与参考频率f2鉴相，因此有f4＝f3+N4*f1＝N3*f2+N4*f1，N3＝N4＝N时，f1＝f2，f4＝N*f1+N*f2＝2*N*f1。在相噪上，输出频率f4的相噪等于N*f1频率相噪和N*f2频率相噪的和。由于在窄带锁相环PLL1和PLL2中，已经将f1和f2在偏离中心频率10Hz以外 的相位噪声是不相关的。因此，按照不相关信号噪声的线性叠加原理，在输出频率f4偏离中心频率10Hz以外的相位噪声为：
PN(f4)＝PN(N*f1)+PN(N*f2)＝PN(N*f1)+10*log2。
具体的，当有多个锁相环单元时，最终输出频率是由后续的多路锁相环频率逐步叠加上来的，由最后一个锁相环的频率得到倒数第二个锁相环频率，即，fn-1＝2*fn。。。。。，以此类推，得到的第一路的频率f0＝2*f1＝2*....*2*fn。
实施例2：
图3为本发明另一实施方式，采用的是频率相加的原理。这种框图中仍然先采用窄带锁相的方法得到两路不相关的参考频率f1和f2，通过锁相或者倍频的方法得到不相关的两路频率f3和f4。因此有：f5＝f3+f4＝N3*f2+N4*f1，其原理与实施例1原理一样，因此得到的相位噪声改善也是一样的。
而采用现有锁相或者倍频技术得到的PN(f4)＝PN(N*f1)+20*log2，因此本实施例中两路信号组合的相位噪声改善为20*log2-10*log2＝10*log2＝3dB。
本发明还给出了现有技术与实施例1中方案的在输出频率为13GHz时的相位噪声对比，现有技术方案的相位噪声在1K、10K和100K处分别为：-112.5dBc/Hz，-117dBc/Hz，-118.86dBc/Hz。
而本发明为-115.1dBc/Hz，-119.4dBc/Hz，-120dBc/Hz。相比而言，本发明的方案在1K、10K和100K处的相位噪声分别有2.6dB、2.4dB和1.14dB的提升。
此外，当锁相合成单元为多个时，如图4、图5所示，随着路数的增加，相位噪声的改善也随之增加，如，在合路路数为4或者8时，理论上可以得到6dB和9dB的相噪改善。
上面结合附图对本发明的具体实施方式进行了详细说明，但本发明并不限 制于上述实施方式，在不脱离本申请的权利要求的精神和范围情况下，本领域的技术人员可以作出各种修改或改型。

Claims (5)

  1. 一种低相位噪声频率合成器，其特征在于，包括参考晶振，用于产生参考信号，所述参考晶振连接功率分配器，所述功率分配器连接至少一个锁相合成单元的信号输入端，用于将所参考信号分配后发送到每个所述锁相合成单元，其中，所述锁相合成单元包括第一锁相环，用于对第一晶振进行锁相，第二锁相环，用于对第二晶振进行锁相，所述第一晶振输出第一信号到第四锁相环，所述第二晶振输出第二信号到第三锁相环，所述第三锁相环用于对所述第二信号进行锁相；所述第三锁相环、第四锁相环将输出的信号进行混频组合后输出。
  2. 根据权利要求1所述的低相位噪声频率合成器，其特征在于，所述锁相环包括依次连接的鉴相器、环路滤波器、压控振荡器、分频器。
  3. 根据权利要求2所述的低相位噪声频率合成器，其特征在于，所述鉴相器为数字鉴相器或模拟鉴相器。
  4. 根据权利要求1所述的低相位噪声频率合成器，其特征在于，所述第一锁相环、第二锁相环均为窄带锁相环。
  5. 根据权利要求4所述的低相位噪声频率合成器，其特征在于，所述窄带锁相环带宽小于10Hz。
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