GB2567463A - Phase locked loop circuit - Google Patents

Phase locked loop circuit Download PDF

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Publication number
GB2567463A
GB2567463A GB1716751.1A GB201716751A GB2567463A GB 2567463 A GB2567463 A GB 2567463A GB 201716751 A GB201716751 A GB 201716751A GB 2567463 A GB2567463 A GB 2567463A
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phase detector
phase
input
output
frequency
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GB201716751D0 (en
GB2567463B (en
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Pritchard John
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COMMUNICATIONS AUDIT UK Ltd
Communications Audit Uk Ltd
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COMMUNICATIONS AUDIT UK Ltd
Communications Audit Uk Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1077—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the phase or frequency detection means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A phase locked loop 300 comprises a voltage controlled oscillator (VCO) 304 and a first phase detector (PD) 302. The first PD 302 receives a reference signal and the output signal of the VCO 304. The PLL circuit further comprises a second phase detector 310 and a switching device 314. The second PD 310 receives the reference signal and the output of the VCO 304. The second PD 310 may be external. The operating frequency of the first PD 302 may be lower than that of the second PD 310. The first and second phase detectors 302, 310 may be coupled selectively to the VCO 304 via the switching device 314. The VCO 304 and the first PD may be integrated on a single PLL chip. In operation, the switch 314 may initially be set to the integrated phase detector 302. Once lock is achieved, the switch 314 may be changed to select the external detector 310. The external detector 310 may be a high quality, high frequency, phase detector. The external loop may employ a mixer and no divider (fig.6). As a result, the output phase noise is very low, without the need for a conventional pre-tuning system.

Description

Phase Locked Loop Circuit
Field of the Invention
This invention relates generally to phase locked loops (PLLs) and more particularly to a phase locked loop (PLL) circuit for generating a Local Oscillator (LO) signal, for example.
Background of the Invention
Radio receivers and related technologies, such as television receivers, mobile phones, etc. require a Local Oscillator (LO) signal to ‘tune’ the receiver to the correct channel or frequency. LO signals are required, for most applications, to be of variable frequency and, in general, a synthesizer is used to synthesize the various frequencies. The most common form of synthesizer used in modern systems is based on a Phase Locked Loop (PLL) circuit that is used to generate the LO signal.
A PLL is, essentially, a feedback control system. It compares the phases of two input signals and produces an error signal that is proportional to the difference between their phases. The error signal is then low pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the phase error signal will increase, driving the frequency in the opposite direction so as to reduce the error. The PLL thus ‘locks’ the LO to a stable frequency reference, usually derived from a crystal oscillator, so as to ‘tune’ the receiver to the desired frequency.
A PLL circuit therefore comprises a number of elements, including a VoltageControlled Oscillator (VCO), a Phase Detector (PD), a loop filter (i.e. a low pass filter or LPF) and a frequency divider. In recent years, there is an increasing drive to utilize integrated circuits in electronic equipment of the type described above, in view of their mass production capability, reliability and building block approach to circuit design. In that regard, then, it is typical to utilize a PLL integrated circuit in such equipment.
A typical integrated PLL synthesizer is illustrated in Figure 1 of the drawings. In the PLL synthesizer of Figure 1, the VCO and PD are integrated in a silicon chip 100. The illustrated synthesizer comprises a reference frequency divider 102, an integrated Phase Detector 104, an integrated VCO 106 and a Feedback Frequency Divider 108. In use, an output of the Phase Detector 104 is fed to a loop filter (or LPF) 110, and a reference frequency source (typically derived from a crystal oscillator, not shown) is connected at an input of the reference frequency divider 102. The (divided) reference frequency signal and the (divided) signal from the VCO106 are connected into the Phase Detector 104. The output from the phase detector 104 is passed through the loop filter 110 and then applied to the VCO 106.
The VCO 106 produces a (divided) signal which enters the Phase Detector 104. The phase of the signals from the (divided) VCO 106 and the incoming reference signal are compared and a resulting difference or error voltage is produced, that corresponds to the phase difference between the two signals. The error signal from the phase detector 104 passes through the loop filter 110, which removes any high frequency elements on the signal. After filtering, the error signal is applied to the control terminal of the VCO 106 as its tuning voltage. The sense of any change in this voltage is such that it tries to reduce the phase difference and hence the frequency between the two signals, and the error voltage will pull the frequency of the VCO 106 towards that of the reference until it cannot reduce the error any further and the loop is locked. The time that this process takes is known as the ‘lock time’ and is a key performance parameter in respect of PLLs generally.
Another key performance parameter or quality metric in respect of a PLL-based LO circuit is known as ‘phase noise’, which can be thought of as a characterisation of the short term frequency stability of the signal. For a carrier frequency at a given power level, the phase noise of a synthesizer is the ratio of the carrier power to the power found in a 1-Hz bandwidth at a defined frequency offset and is normally characterised as a relative power spectral density. This spectral density varies with offset frequency from the required signal and is expressed in dBc/Hz. Each of the blocks of a PLL contributes to the phase noise of the signal, but ‘in-band’ phase noise is usually dominated by the phase detector and frequency divider elements of the circuit where the VCO noise contribution is well below the loop filter bandwidth and is, therefore, largely filtered out.
It will be known to a person skilled in the art that in-band phase noise, for a given output frequency of the PLL, is inversely proportional to the frequency of operation of the phase detector in the locked state. In other words, the in-band phase noise is proportional to the frequency multiplication within the loop. Therefore, the higher the frequency of operation of the phase detector, for a given output frequency, the higher the quality of the signal (in terms of phase noise).
It will also be known to a person skilled in the art that the phase noise power spectral density, for frequencies far above the loop filter bandwidth, is dominated by the phase noise contribution from the VCO. Thus, the higher the quality of the VCO, the higher will be the quality of the LO.
The highest quality commercially available integrated PLLs have very high quality VCOs that are comparable to the highest quality stand-alone VCOs available. However, the corresponding phase detector in such integrated circuits is of limited quality and/or frequency of operation when compared with the best quality standalone phase detectors available. As a result, when using an integrated PLL of the type described above, the quality of the signal achievable is significantly lower than that which could be achieved by using individual, stand-alone devices.
In order to achieve a broad range of frequency of operation of the VCO of an integrated PLL, as well as low phase noise, it is known for manufacturers to calibrate the VCO at each output frequency. Typically, every time the frequency of the synthesizer is changed, an auto-calibration routine is triggered which automatically controls and configures the VCO to operate at the new frequency. This calibration takes time, which may be undesirable in some applications.
Another known option is to utilize an offset or frequency translation loop, wherein (and referring to Figure 2 of the drawings) the feedback frequency divider of the circuit of Figure 1 is removed and replaced by a frequency mixer 112 and LO source. An offset loop of this type offers the possibility of very high quality, low phase noise synthesis because there is no frequency division within the loop; the LO source adds to the loop phase noise, rather than multiplying it. A further refinement involves including a frequency multiplier in the loop, which has the effect of reducing the phase noise by the multiplication factor. However, the frequency mixer 112 and the optional multiplier in the loop produce a large number of unwanted products, which the filter 114 on the output of the mixer 112 reduce but cannot eliminate completely. Thus, the PLL can lock to the wrong frequency. Typically, this is overcome by pretuning the VCO to approximately the wanted frequency before the loop is closed.
However, the pre-tuning functionality can add significant complexity to the system to achieve sufficient accuracy and prevent false locking over time and temperature.
Aspects of the present invention seek to address at least some of these issues.
Summary of the Invention
According to an aspect of the present invention, there is provided a phase locked loop circuit comprising a first phase detector and a voltage controlled oscillator, wherein said first phase detector comprises a first input for receiving a reference signal, and an output of said voltage controlled oscillator is coupled to a second input of said first phase detector, the circuit further comprising a second phase detector and a switching device, wherein said second phase detector comprises a first input for receiving said reference signal, an output of said voltage controlled oscillator is coupled to a second input of said second phase detector, and said first and second phase detectors are selectively couplable to an input of said voltage controlled oscillator via said switching device.
In an exemplary embodiment, the first phase detector and said voltage controlled oscillator may be integrated in a single PLL chip.
Optionally, the frequency of operation of said first phase detector may be lower than that of said second phase detector.
In an exemplary embodiment, the switching device may be configured, in use, to couple the output of said first phase detector to an input of said voltage controlled oscillator until the frequency of the output thereof is locked to the frequency of said reference signal, and then switch to couple the output of the second phase detector to said input of said voltage controlled oscillator.
A first loop filter may be provided between an output of said first phase detector and said input of said voltage controlled oscillator. In an exemplary embodiment, the circuit may comprise first and second loop filters between respective outputs of said first and second phase detectors and said input of said voltage controlled oscillator.
An output of said voltage controlled oscillator may be coupled to said second input of said first phase detector via a feedback frequency divider.
In an exemplary embodiment, the circuit may further comprise a reference frequency divider having an input for receiving a reference frequency source and an output coupled to said first input of said first phase detector.
The circuit may further comprise a second feedback frequency divider having an input coupled to an output of said voltage controlled oscillator and an output coupled to said second input of said second phase detector. In this case, the second phase detector and said feedback frequency divider may be integrated in a single chip.
In an exemplary embodiment, the first phase detector may be a variable gain phase detector. In this case, a single common loop filter may be provided at the output of the voltage controlled oscillator.
In yet another exemplary embodiment, the or each loop filter may comprise a partial loop filter. Thus, the circuit may comprise a first partial loop filter at an output of said first phase detector, a second partial loop filter at an output of said second phase detector, and a third partial loop filter at an input of said voltage controlled oscillator, wherein said switching device is located between said third partial loop filter and said first and second partial loop filters.
In yet another exemplary embodiment, the circuit may comprise a frequency mixer having a first input coupled to an output of said voltage controlled oscillator and an output coupled to said second input of said second phase detector. In this case, the circuit may comprise a filter between said output of said frequency mixer and said second input of said second phase detector, and, optionally, a local oscillator source may be coupled to a second input of said frequency mixer.
The circuit may further comprise a frequency multiplier, such as a frequency comb generator, between said output of said voltage controlled oscillator and said second input of said second phase detector.
These and other aspects of the invention will be apparent from the following detailed description.
Brief Description of the Drawings
Embodiments of the present invention will now be described by way of examples only and with reference to accompanying drawings, in which:
Figure 1 is a schematic block diagram of a phase locked loop circuit according to a first example of the prior art;
Figure 2 is a schematic block diagram of a phase locked loop circuit according to a second example of the prior art;
Figure 3 is a schematic block diagram of a phase locked loop circuit according to a first exemplary embodiment of the present invention;
Figure 4 is a schematic block diagram of a phase locked loop circuit according to a second exemplary embodiment of the present invention;
Figure 5 is a schematic block diagram of a phase locked loop circuit according to a third exemplary embodiment of the present invention; and
Figure 6 is a schematic block diagram of a phase locked loop circuit according to a fourth exemplary embodiment of the present invention.
Detailed Description
Referring to Figure 3 of the drawings, a phase locked loop circuit according to a first exemplary embodiment of the present invention comprises an integrated PLL circuit 300 comprises an integrated phase detector 302 and an integrated VoltageControlled Oscillator (VCO) 304. A reference frequency source (typically derived from a crystal oscillator, not shown) is applied to an input of the integrated phase detector 302 via a reference frequency divider 306, which is also integrated on the chip 300. An integrated frequency feedback divider 308 is coupled between the output of the VCO 304 and a second input of the integrated phase detector 302. The circuit further comprises a second, external phase detector 310, and an external feedback frequency divider 312 is coupled between the output of the VCO 304 and an input of the external phase detector 310. The reference frequency source is applied to a second input of the external phase detector 310.
One or both of the frequency dividers may advantageously comprise a fractional-N frequency divider. An important class of fractional-N divider is a ‘delta-sigma frequency divider’, as will be known to a person skilled in the art. These types of dividers are typically used as the feedback frequency dividers in PLL synthesizers for good phase noise performance. However,the present invention is not necessarily intended to be limited in this regard.
A switching device 314 is configured to selectively couple the outputs of the integrated and external phase detectors 302, 310 (via a respective loop filter 316a, 316b) to the input of the VCO 304. Thus, in effect, the phase locked loop circuit of the first exemplary embodiment of the present invention comprises an integrated PLL (with integrated, high quality VCO) coupled to an external, high quality, high frequency phase detector to enable production of a high quality signal with low phase noise in a compact form. This embodiment can be made especially compact since the high quality external phase detector 310 and frequency feedback divider 312 can also be obtained on a single silicon chip, although the present invention is not necessarily intended to be limited in this regard.
Initially, the switching device is set to select the integrated PLL path (i.e. the output of the integrated phase detector 302 is coupled, via the second loop filter 316b, to the input of the VCO 304). In this configuration, the circuit operates in a similar manner to that described with reference to the prior art illustrated above in relation to Figure 1 of the drawings. Thus, once the switching device 314 is set to select the integrated PLL path and both loops (the integrated PLL loop and the external phase detector loop) have been configured and calibrated, an output of the integrated Phase Detector 302 is fed through the second loop filter 316b and then applied to the VCO 304. The VCO 304 produces a signal which enters the integrated Phase Detector 302. The phase of the signals from the VCO 304 and the incoming reference signal are compared and a resulting difference or error voltage is produced, that corresponds to the phase difference between the two signals. The error signal from the integrated phase detector 302 passes through the second loop filter 316b, which removes any high frequency elements on the signal. After filtering, the error signal is applied to the control terminal of the VCO 304 as its tuning voltage. The sense of any change in this voltage is such that it tries to reduce the phase difference and hence the frequency between the two signals, and the error voltage will pull the frequency of the VCO 304 towards that of the reference until it cannot reduce the error any further and the loop is locked.
Once the integrated PLL is locked, the switching device 314 is changed to select the external phase detector path (i.e. the output from the external phase detector 310 is fed (via the first loop filter 316a) to the input of the VCO 304). Since this path utilises a high quality, high frequency phase detector, the output phase noise is very low.
The circuit of Figure 3 utilises two loop filters 316a, 316b. This is because, in general, the loop dynamics will change between the two switching states and the respective loop filter will need to be different for optimum performance. However, integrated phase detectors often have variable gain, and it is envisaged that this may be used to advantage in a second exemplary embodiment of the present invention.
Thus, referring to Figure 4 of the drawings, in a phase locked loop circuit according to a second exemplary embodiment of the present invention, an integrated circuit 400 including an integrated phase detector 402 and an integrated VCO 404 is once again provided. A reference frequency source is fed to an input of the integrated phase detector 402, via a reference frequency divider 406. The output of the VCO 404 is coupled, via a feedback frequency divider 408, to a second input of the integrated phase detector 402. Once again, an external phase detector 410 is also provided, wherein the reference frequency source is coupled to a first input thereof and the output of the VCO 404 is coupled, via an external feedback frequency divider 412, to a second input thereof. In this case, a single loop filter 416 is provided, and coupled to an input of the VCO 404, and the switching device 414 is located upstream of the loop filter 416, such that the output of both the integrated phase detector 402 and the output of the external phase detector 410 passes through the same loop filter 416 when its respective path is selected.
Once again, one or both of the frequency dividers may advantageously comprise a fractional-N frequency divider, such as a delta-sigma frequency divider, although the present invention is not necessarily intended to be limited in this regard.
The integrated phase detector 402 is a variable gain phase detector and the loop filter 416 may be designed to control the dynamics for the external phase detector loop, whereas the variable gain phase detector 402 may be set to control the dynamics for the integrated phase detector loop.
Otherwise, operation of the circuit illustrated in Figure 4 of the drawings is substantially the same as that described above in relation to the circuit illustrated in Figure 3 of the drawings.
The operation of the switching device can introduce unwanted glitches into the system. Referring to Figure 5 of the drawings, in a third exemplary embodiment of the present invention, a reduced susceptibility to such switch glitches is introduced. In the phase locked loop circuit illustrated in Figure 5 of the drawings, an integrated circuit 500 including an integrated phase detector 502 and an integrated VCO 504 is once again provided. A reference frequency source is fed to an input of the integrated phase detector 502, via a reference frequency divider 506. The output of the VCO 504 is coupled, via a feedback frequency divider 508, to a second input of the integrated phase detector 502. Once again, an external phase detector 510 is also provided, wherein the reference frequency source is coupled to a first input thereof and the output of the VCO 504 is coupled, via an external feedback frequency divider 512, to a second input thereof. In this case, the loop filter for each phase detector loop is effectively split into two. Thus, in respect of the external phase detector loop, a first partial loop filter 516a is provided before the switching device 514, and, in respect of the integrated phase detector loop, a second partial loop filter 516b is provided before the switching device 514. A common partial loop filter 516c is provided after the switching device 514. Operation of the phase locked loop circuit of the third exemplary embodiment illustrated in Figure 5 of the drawings is substantially the same as that described above in relation to the first (and second) embodiments; and the common filter 516c, after the switching device 514, reduces loop disturbance caused by switch glitches.
As before, one or both of the frequency dividers may advantageously comprise a fractional-N frequency divider, such as a delta-sigma frequency divider, although the present invention is not necessarily intended to be limited in this regard.
In order to reduce the time taken to change frequency, the optimum configuration and calibration states for the integrated VCO for each possible output frequency can be determined in advance. The data can be stored in the system controller and retrieved and applied as required for each output frequency, thereby eliminating the time otherwise required for an auto-calibration routine.
Referring now to Figure 6 of the drawings, in yet another exemplary embodiment of the present invention, it is possible to utilise an offset or frequency translation loop, as described above, to further improve quality and reduce phase noise. The phase locked loop circuit of Figure 6 is similar in many respects to that of Figure 3. Thus, the circuit comprises an integrated PLL circuit 600 comprising an integrated phase detector 602 and an integrated Voltage-Controlled Oscillator (VCO) 604. A reference frequency source (typically derived from a crystal oscillator, not shown) is applied to an input of the integrated phase detector 602 via a reference frequency divider 606, which is also integrated on the chip 600. An integrated frequency feedback divider 608 is coupled between the output of the VCO 604 and a second input of the integrated phase detector 602. The circuit further comprises a second, external phase detector 610, and a frequency mixer 618 and LO source is coupled between the output of the VCO 604 and an input of the external phase detector 610. The reference frequency source is applied to a second input of the external phase detector 610, and a filter 620 is provided on the output of the mixer 618 to reduce unwanted mixing products.
A switching device 614 is configured to selectively couple the outputs of the integrated and external phase detectors 602, 610 (via a respective loop filter 616a, 616b) to the input of the VCO 604. Thus, in effect, the phase locked loop circuit of the fourth exemplary embodiment of the present invention once again comprises an integrated PLL (with integrated, high quality VCO) coupled to an external, high quality, high frequency phase detector to enable production of a high quality signal with low phase noise in a compact form.
Initially, the switching device is set to select the integrated PLL path (i.e. the output of the integrated phase detector 602 is coupled, via the second loop filter 616b, to the input of the VCO 604). In this configuration, the circuit operates in a similar manner to that described with reference to the prior art illustrated above in relation to Figure 1 of the drawings. Thus, once the switching device 614 is set to select the integrated PLL path and both loops (the integrated PLL loop and the external phase detector loop) have been configured and calibrated, an output of the integrated Phase Detector 602 is fed through the second loop filter 616b and then applied to the VCO 604. The VCO 604 produces a signal which enters the integrated Phase Detector 602. The phase of the signals from the VCO 604 and the incoming reference signal are compared and a resulting difference or error voltage is produced, that corresponds to the phase difference between the two signals. The error signal from the integrated phase detector 602 passes through the second loop filter 616b, which removes any high frequency elements on the signal. After filtering, the error signal is applied to the control terminal of the VCO 604 as its tuning voltage. The sense of any change in this voltage is such that it tries to reduce the phase difference and hence the frequency between the two signals, and the error voltage will pull the frequency of the VCO 604 towards that of the reference until it cannot reduce the error any further and the loop is locked.
Once the integrated PLL is locked, the switching device 614 is changed to select the external phase detector path (i.e. the output from the external phase detector 610 is fed (via the first loop filter 616a) to the input of the VCO 604).
It will be understood, therefore, that both loops are configured to operate at the desired frequency and the switching device 614 is initially set for the integrated loop. Once the integrated loop is locked, the VCO 604 is operating at the exact desired frequency and the switching device 614 is changed to select the external loop. Since there is no frequency divider in the external loop and the external phase detector 610 can operate at high frequency and be of high quality, this loop can be of very low phase noise. The system can be very compact since the integrated loop can be realised on a single silicon chip. Additionally, the system can be made simple to operate, since the VCO 604 is automatically pre-tuned to the exact required frequency, eliminating the need for a conventional pre-tuning system.
The exemplary embodiment described in relation to Figure 6 can be further refined to reduce switch glitch susceptibility (using first, second and third partial loop filters, as described in relation to Figure 5 of the drawings), or by utilizing a variable gain integrated phase detector and a single loop filter, as described above in relation to Figure 4 of the drawings.
An important possible refinement to the embodiment described with reference to Figure 6 of the drawings might be the inclusion of a frequency multiplier within the external loop to reduce phase noise even further, and as described above. The frequency multiplier can take the form of a frequency comb generator to add additional flexibility to the system and allow the system to lock up to any number of comb related frequencies, rather than a fixed multiplication value. The LO source for the exemplary embodiment of Figure 6 (or as refined) is required to be a low phase noise signal, and this may be generated by another phase locked loop circuit according to an exemplary embodiment of the present invention.
Embodiments of the present invention can be used in any application that requires a low phase noise synthesiser, especially in systems where the output of the synthesizer is required to be multiplied up to a final higher frequency, and thus wherein the low phase noise characteristics are important.
It will be apparent to a person skilled in the art, from the foregoing description, that modifications and variations can be made to the described embodiments, without departing from the scope of the invention as defined by the appended claims.

Claims (18)

1. A phase locked loop circuit comprising a first phase detector and a voltage controlled oscillator, wherein said first phase detector comprises a first input for receiving a reference signal, and an output of said voltage controlled oscillator is coupled to a second input of said first phase detector, the circuit further comprising a second phase detector and a switching device, wherein said second phase detector comprises a first input for receiving said reference signal, an output of said voltage controlled oscillator is coupled to a second input of said second phase detector, and said first and second phase detectors are selectively couplable to an input of said voltage controlled oscillator via said switching device.
2. A phase locked loop circuit according to claim 1, wherein said first phase detector and said voltage controlled oscillator are integrated in a single PLL chip.
3. A phase locked loop circuit according to claim 1 or claim 2, wherein the frequency of operation of said first phase detector is lower than that of said second phase detector.
4. A phase locked loop circuit according to any of the preceding claims, wherein said switching device is configured, in use, to couple the output of said first phase detector to an input of said voltage controlled oscillator until the frequency of the output thereof is locked to the frequency of said reference signal, and then switch to couple the output of the second phase detector to said input of said voltage controlled oscillator.
5. A phase locked loop circuit according to any of the preceding claims, further comprising a first loop filter between an output of said first phase detector and said input of said voltage controlled oscillator.
6. A phase locked loop circuit according to claim 5, comprising first and second loop filters between respective outputs of said first and second phase detectors and said input of said voltage controlled oscillator.
7. A phase locked loop circuit according to any of the preceding claims, wherein an output of said voltage controlled oscillator is coupled to said second input of said first phase detector via a feedback frequency divider.
8. A phase locked loop circuit according to any of the preceding claims, further comprising a reference frequency divider having an input for receiving a reference frequency source and an output coupled to said first input of said first phase detector.
9. A phase locked loop circuit according to any of the preceding claims, further comprising a feedback frequency divider having an input coupled to an output of said voltage controlled oscillator and an output coupled to said second input of said second phase detector.
10. A phase locked loop according to claim 9, wherein said second phase detector and said feedback frequency divider are integrated in a single chip.
11. A phase locked loop circuit according to any of the preceding claims, wherein said first phase detector is a variable gain phase detector.
12. A phase locked loop circuit according to claim 5 or claim 6, wherein each loop filter is a partial loop filter.
13. A phase locked loop circuit according to claim 12, comprising a first partial loop filter at an output of said first phase detector, a second partial loop filter at an output of said second phase detector, and a third partial loop filter at an input of said voltage controlled oscillator, wherein said switching device is located between said third partial loop filter and said first and second partial loop filters.
5
14. A phase locked loop circuit according to any of claims 1 to 8, further comprising a frequency mixer having a first input coupled to an output of said voltage controlled oscillator and an output coupled to said second input of said second phase detector.
15. A phase locked loop circuit according to claim 14, comprising a filter between io said output of said frequency mixer and said second input of said second phase detector.
16. A phase locked loop circuit according to claim 14 or claim 15, wherein a local oscillator source is coupled to a second input of said frequency mixer.
17. A phase locked loop circuit according to any of claims 14 to 16, further
15 comprising a frequency multiplier between said output of said voltage controlled oscillator and said second input of said second phase detector.
18. A phase locked loop circuit according to claim 17, wherein said frequency multiplier comprises a frequency comb generator.
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US5982239A (en) * 1995-08-14 1999-11-09 Hitachi, Ltd. Phase locked loop circuit and a picture reproducing device
US20070001713A1 (en) * 2005-07-01 2007-01-04 Via Technologies, Inc. Phase detecting circuit having adjustable gain curve and method thereof
US20100207693A1 (en) * 2009-02-13 2010-08-19 Qualcomm Incorporated Frequency synthesizer with multiple tuning loops
US20110204937A1 (en) * 2010-02-23 2011-08-25 Agilent Technologies, Inc. Phase- locked loop with switched phase detectors
GB2498241A (en) * 2011-10-20 2013-07-10 Renesas Mobile Corp Frequency synthesiser with short locking time

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US4975650A (en) * 1989-07-24 1990-12-04 Motorola, Inc. Phase detector
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US20220239301A1 (en) * 2021-01-28 2022-07-28 Anritsu Company Frequency synthesizers having low phase noise
US11817871B2 (en) * 2021-01-28 2023-11-14 Anritsu Company Frequency synthesizers having low phase noise

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