WO2021117334A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021117334A1
WO2021117334A1 PCT/JP2020/038747 JP2020038747W WO2021117334A1 WO 2021117334 A1 WO2021117334 A1 WO 2021117334A1 JP 2020038747 W JP2020038747 W JP 2020038747W WO 2021117334 A1 WO2021117334 A1 WO 2021117334A1
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WIPO (PCT)
Prior art keywords
region
solder
terminal
heat sink
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2020/038747
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English (en)
French (fr)
Japanese (ja)
Inventor
俊介 荒井
雅由 西畑
真二 平光
規行 柿本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to CN202080085890.4A priority Critical patent/CN114846601B/zh
Publication of WO2021117334A1 publication Critical patent/WO2021117334A1/ja
Priority to US17/747,629 priority patent/US12476172B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/186—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/493—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2089—Modifications to facilitate cooling, ventilating, or heating for power electronics, e.g. for inverters for controlling motor
    • H05K7/209—Heat transfer by conduction from internal heat source to heat radiating structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2089—Modifications to facilitate cooling, ventilating, or heating for power electronics, e.g. for inverters for controlling motor
    • H05K7/20936—Liquid coolant with phase change

Definitions

  • the disclosure in this specification relates to semiconductor devices.
  • Patent Document 1 has a double-sided heat-dissipating structure including a semiconductor element having main electrodes on both sides, and a wiring member including a heat-dissipating portion arranged so as to sandwich the semiconductor element and a terminal portion connected to the heat-dissipating portion as a conductor portion. Disclose semiconductor devices. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification.
  • the height variation caused by the dimensional tolerance, assembly tolerance, etc. of the elements constituting the semiconductor device depends on the joint material. Absorb. When the height varies toward the narrower distance between the two conductors, the excess bonding material overflows from the two opposing regions to absorb the height variation. If a groove as described in Patent Document 1 is provided on one of the conductor portions, excess bonding material can be accommodated. The groove is formed by press working. Further improvements are required of semiconductor devices in the above-mentioned viewpoints or in other viewpoints not mentioned.
  • One purpose to be disclosed is to provide a semiconductor device capable of accommodating a surplus bonding material with a simple configuration.
  • the semiconductor device disclosed herein is At least one semiconductor element having a main electrode on one surface and the back surface opposite to the one surface in the plate thickness direction. At least one set of heat radiating parts, which are arranged on one side and the back side so as to sandwich the semiconductor element in the plate thickness direction and are electrically connected to the corresponding main electrodes, and a plurality of terminal parts connected to the heat radiating part.
  • the wiring member includes a plurality of conductor portions including, and at least one joint portion formed by arranging a bonding material between the two conductor portions in the plate thickness direction.
  • the first conductor portion which is one of the conductor portions, has a highly wet region and a plan view in the plate thickness direction on the surface facing the second conductor portion, which is the other conductor portion. It has a low wet region which is provided adjacent to the high wet region so as to define the outer periphery of the high wet region and has a lower wettability to the joint material than the high wet region.
  • the highly wet region is a region that overlaps with the formation region of the joint portion in the second conductor portion in a plan view, and is connected to the overlap region in which the bonding material is arranged at least partially and the overlap region, and the joint portion of the second conductor portion is joined. It has a non-overlapping region, which is a region that does not overlap with the portion forming region.
  • the non-overlapping region includes at least a storage region for accommodating the excess joint material with respect to the joint portion.
  • the accommodating region which is a highly wet region, is connected to the overlapping region, and the surplus bonding material easily wets and spreads from the overlapping region to the accommodating region.
  • Excess joint material is restricted from spreading by the low wetting area. Therefore, the low wet area adjacent to the high wet area promotes the wet spread to the accommodation area and / or suppresses the wet spread to the outside of the accommodation area. Therefore, the surplus bonding material can be accommodated in the accommodating area without providing the groove.
  • FIG. 6 is a plan view of FIG. 6 viewed from the X1 direction. It is a top view which shows the state which omitted the heat sink on the emitter side. It is a top view which shows the semiconductor module which concerns on 1st Embodiment. 9 is a plan view of FIG.
  • FIG. 16 is a plan view of FIG. 16 as viewed from the X3 direction. This is a model of the upper and lower arms used to verify the position of the load line. It is a figure which shows the current which flows to each output terminal at the time of driving a switching element. It is an equivalent circuit diagram of the semiconductor module considering the wiring resistance.
  • FIG. 5 is a cross-sectional view taken along the line LVII-LVII shown in FIG. 55. It is a top view which shows the modification. It is a top view seen from the X4 direction of FIG. 58. It is an enlarged plan view around the joint part. It is a top view which shows the semiconductor device which concerns on 6th Embodiment. It is an equivalent circuit diagram of the semiconductor device which constitutes a lower arm.
  • the semiconductor device and the semiconductor module according to the present embodiment are applied to a power conversion device.
  • Power converters are applied, for example, to vehicle drive systems.
  • the power converter can be applied to vehicles such as electric vehicles (EVs) and hybrid vehicles (HVs).
  • EVs electric vehicles
  • HVs hybrid vehicles
  • an example applied to a hybrid vehicle will be described.
  • the vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.
  • the DC power supply 2 is a rechargeable secondary battery such as a lithium ion battery or a nickel hydrogen battery.
  • the motor generator 3 is a three-phase AC rotary electric machine.
  • the motor generator 3 functions as a traveling drive source of the vehicle, that is, an electric motor. It also functions as a generator during regeneration.
  • the vehicle includes an engine (not shown) and a motor generator 3 as a traveling drive source.
  • the power conversion device 4 performs power conversion between the DC power supply 2 and the motor generator 3.
  • the power conversion device 4 includes an inverter 5, a control circuit unit 6, and a smoothing capacitor Cs.
  • the inverter 5 is a power conversion unit.
  • the inverter 5 is a DC-AC converter.
  • the power conversion unit includes upper and lower arms 7.
  • the upper and lower arms 7 is a circuit in which the upper arm 7U and the lower arm 7L are connected in series.
  • Each of the upper arm 7U and the lower arm 7L has a plurality of switching elements provided with gate electrodes.
  • a plurality of switching elements are connected in parallel to each other.
  • an n-channel type IGBT is adopted as the switching element.
  • the upper arm 7U has two switching elements Q1.
  • a freewheeling diode D1 is individually connected to the two switching elements Q1.
  • the diode D1 is connected in antiparallel to the corresponding switching element Q1.
  • the two switching elements Q1 connected in parallel are controlled by a gate drive signal in which the high level and the low level are switched at the same timing.
  • the gate electrodes of the two switching elements Q1 are electrically connected to, for example, the same drive circuit unit (gate driver).
  • the upper arm 7U is composed of two semiconductor elements 31 which will be described later.
  • the lower arm 7L has two switching elements Q2.
  • a freewheeling diode D2 is individually connected to the two switching elements Q2.
  • the diode D2 is connected in antiparallel to the corresponding switching element Q2.
  • the two switching elements Q2 connected in parallel are controlled by a gate drive signal in which the high level and the low level are switched at the same timing.
  • the gate electrodes of the two switching elements Q2 are electrically connected to, for example, the same drive circuit unit.
  • the lower arm 7L is composed of two semiconductor elements 32, which will be described later.
  • the switching elements Q1 and Q2 are not limited to IGBTs.
  • MOSFETs can also be adopted.
  • Parasitic diodes can also be used as the diodes D1 and D2.
  • the upper arm 7U and the lower arm 7L are connected in series between the power lines 8P and 8N with the upper arm 7U on the power line 8P side.
  • the power line 8P is a power line on the high potential side.
  • the power line 8P is connected to the positive electrode of the DC power supply 2.
  • the power line 8P is connected to a terminal on the positive electrode side of the smoothing capacitor Cs.
  • the power line 8N is a power line on the low potential side.
  • the power line 8N is connected to the negative electrode of the DC power supply 2.
  • the power line 8N is connected to a terminal on the negative electrode side of the smoothing capacitor Cs.
  • the power line 8N is also referred to as a ground line.
  • the inverter 5 is connected to the DC power supply 2 via the smoothing capacitor Cs.
  • the inverter 5 has three sets of the above-mentioned upper and lower arms 7.
  • the inverter 5 has three-phase upper and lower arms 7.
  • the collector electrode of the switching element Q1 is connected to the power line 8P.
  • the emitter electrode of the switching element Q2 is connected to the power line 8N.
  • the emitter electrode of the switching element Q1 and the collector electrode of the switching element Q2 are connected to each other to form a connection point of the upper and lower arms 7.
  • connection point of the U-phase upper and lower arms 7 is connected to the U-phase winding provided in the stator of the motor generator 3.
  • connection point of the V-phase upper and lower arms 7 is connected to the V-phase winding of the motor generator 3.
  • connection point of the W-phase upper and lower arms 7 is connected to the W-phase winding of the motor generator 3.
  • the connection points of the upper and lower arms 7 of each phase are connected to the windings of the corresponding phases via load lines 9 provided for each phase.
  • the load line 9 is also referred to as an output line.
  • the inverter 5 converts the DC voltage into a three-phase AC voltage and outputs it to the motor generator 3 according to the switching control by the control circuit unit 6. As a result, the motor generator 3 is driven so as to generate a predetermined torque. During regenerative braking of the vehicle, the motor generator 3 generates a three-phase AC voltage by receiving the rotational force from the wheels.
  • the inverter 5 can also convert the three-phase AC voltage generated by the motor generator 3 into a DC voltage according to switching control by the control circuit unit 6 and output it to the power line 8P. In this way, the inverter 5 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.
  • the control circuit unit 6 is configured to include, for example, a microcomputer (microcomputer).
  • the control circuit unit 6 generates a drive command for operating the switching elements Q1 and Q2 of the inverter 5 and outputs the drive command to a drive circuit unit (not shown).
  • the control circuit unit 6 outputs a PWM signal as a drive command.
  • the drive command is, for example, the output duty ratio.
  • the control circuit unit 6 generates a drive command based on a torque request input from a higher-level ECU (not shown) and signals detected by various sensors.
  • the various sensors include a current sensor that detects the phase current flowing in the winding of each phase of the motor generator 3, a rotation angle sensor that detects the rotation angle of the rotor of the motor generator 3, and a voltage across the smoothing capacitor Cs, that is, a power line. There is a voltage sensor that detects a voltage of 8P.
  • the power converter 4 has these sensors (not shown).
  • the power conversion device 4 has a drive circuit unit (not shown).
  • the drive circuit unit generates a drive signal based on a drive command from the control circuit unit 6 and outputs the drive signal to the gate electrodes of the switching elements Q1 and Q2 of the corresponding upper and lower arms 7. As a result, the switching elements Q1 and Q2 are driven, that is, on-drive and off-drive.
  • the drive circuit unit is provided for each arm, for example.
  • the smoothing capacitors Cs are connected between the power lines 8P and 8N.
  • the smoothing capacitor Cs is provided between the DC power supply 2 and the inverter 5, and is connected in parallel with the inverter 5.
  • the smoothing capacitor Cs smoothes the DC voltage supplied from the DC power supply 2, for example, and stores the electric charge of the DC voltage.
  • the voltage between both ends of the smoothing capacitor Cs becomes a high DC voltage for driving the motor generator 3.
  • the power conversion device 4 may further include a converter, a filter capacitor, and the like, which are power conversion units.
  • the converter is a DC-DC converter that converts a DC voltage into a DC voltage of a different value.
  • the converter is provided between the DC power supply 2 and the smoothing capacitor Cs.
  • the converter boosts the DC voltage supplied from, for example, the DC power supply 2.
  • the converter can also have a step-down function.
  • the converter is configured to have, for example, upper and lower arms and a reactor.
  • the upper and lower arms of the converter may have the same configuration as the upper and lower arms 7.
  • the lower arm side of the converter may have the same configuration as the lower arm 7L of the inverter 5, and the upper arm side may be configured with a diode.
  • the filter capacitor is connected in parallel to the DC power supply 2.
  • the filter capacitor removes power supply noise from, for example, the DC power supply 2.
  • the semiconductor module 10 includes two types (two product numbers) of semiconductor devices 11 and 12 shown in FIGS. 2 to 8.
  • the semiconductor device 11 constitutes the upper arm 7U
  • the semiconductor device 12 constitutes the lower arm 7L.
  • the thickness directions of the respective semiconductor elements are orthogonal to the Z direction and the Z direction, and the directions in which at least two semiconductor elements are arranged side by side are the directions orthogonal to the X direction, the Z direction, and the X direction. Is the Y direction.
  • the shape along the XY plane defined by the X direction and the Y direction is a planar shape.
  • the two semiconductor devices 11 and 12 are shown side by side.
  • the sealing resin body is omitted.
  • the heat sink on the emitter side is omitted.
  • the state of the lead frame before removing unnecessary portions such as tie bars is shown.
  • the semiconductor device 11 on the upper arm 7U side will be described.
  • the end of the code number is "1".
  • the semiconductor device 11 includes a sealing resin body 21, a semiconductor element 31, heat sinks 41 and 51, a terminal 61, a main terminal 71, and a signal terminal 81.
  • the sealing resin body 21 seals the corresponding semiconductor element 31 and the like.
  • the sealing resin body 21 is made of, for example, an epoxy resin.
  • the sealing resin body 21 is molded by, for example, a transfer molding method. As shown in FIGS. 2 to 5, the sealing resin body 21 has a substantially rectangular parallelepiped shape.
  • the sealing resin body 21 has a substantially rectangular shape in a plane.
  • the semiconductor element 31 is formed by forming a switching element Q1 and a diode D1 on a semiconductor substrate.
  • An RC (Reverse Conducting) -IGBT is formed on the semiconductor element 31.
  • the semiconductor element 31 is also referred to as a semiconductor chip.
  • the semiconductor element 31 has a vertical structure in which a current flows in the Z direction.
  • the collector electrode 31c is formed on one surface (first main surface) of the semiconductor element 31, and the emitter electrode 31e is formed on the back surface (second main surface).
  • the collector electrode 31c also serves as the cathode electrode of the diode D1, and the emitter electrode 31e also serves as the anode electrode of the diode D1.
  • the collector electrode 31c is the electrode on the high potential side (main electrode), and the emitter electrode 31e is the electrode on the low potential side (main electrode).
  • a pad (not shown), which is an electrode for signals, is also formed on the emitter electrode forming surface. The pad is formed at an end portion of the emitter electrode 31e opposite to the forming region in the Y direction.
  • the semiconductor element 31 has five pads arranged along the X direction.
  • the pads are arranged in the order of the cathode potential of the temperature sensor (temperature sensitive diode) that detects the temperature of the semiconductor element 30, the anode potential, the gate electrode, the current sense, and the Kelvin emitter that detects the potential of the emitter electrode 31e. I'm out.
  • the temperature sensor temperature sensitive diode
  • the semiconductor device 11 has a plurality of semiconductor elements 31.
  • a plurality of semiconductor elements 31 are connected in parallel to form an upper arm 7U.
  • it has two semiconductor elements 31.
  • the two semiconductor elements 31 have structures that substantially coincide with each other, that is, have the same shape and the same size as each other.
  • the semiconductor element 31 has a substantially rectangular shape in a plane.
  • the two semiconductor elements 31 are arranged so that the collector electrodes 31c are on the same side in the Z direction.
  • the two semiconductor elements 31 are located at substantially the same height in the Z direction and are arranged side by side in the X direction.
  • the two semiconductor elements 31 are arranged line-symmetrically with the axis AX1 orthogonal to the X-direction and the Z-direction as the axis of symmetry.
  • the sealing resin body 21 has a substantially rectangular shape in a plane, and the two semiconductor elements 31 are arranged so that the axis AX1 substantially coincides with the center of the outer shape of the sealing resin body 21 in the X direction. ing.
  • the arrangement order of the pads is the same.
  • the heat sinks 41 and 51 have a function of dissipating the heat of the semiconductor element 31 to the outside of the semiconductor device 11.
  • the heat sinks 41 and 51 are also referred to as heat dissipation members.
  • the heat sinks 41 and 51 are electrically connected to the semiconductor element 31 and function as wiring.
  • the heat sinks 41 and 51 are also referred to as wiring members.
  • the heat sinks 41 and 51 are formed of a metal material such as copper.
  • the heat sinks 41 and 51 are also referred to as metal members.
  • the heat sinks 41 and 51 are arranged so as to sandwich the plurality of semiconductor elements 31.
  • the semiconductor element 31 is included in the heat sinks 41 and 51 in the projection view from the Z direction.
  • the plate thickness directions of the heat sinks 41 and 51 are substantially parallel to the Z direction.
  • the X direction is the longitudinal direction and the Y direction is the lateral direction.
  • the heat sinks 41 and 51 are electrically connected to the semiconductor element 31 via a joining member such as solder. As shown in FIG. 4, the heat sink 41 is connected to the collector electrode 31c via the solder 91a. The heat sink 51 is connected to the emitter electrode 31e via the solders 91b and 91c and the terminal 61.
  • the terminal 61 is a metal member that electrically relays the semiconductor element 31 and the heat sink 51.
  • the terminal 61 has a shape that substantially matches the emitter electrode 31e in the projection view from the Z direction.
  • the terminal 61 has a substantially rectangular shape in a plane.
  • the heat sink 51 is connected to the terminal 61 via the solder 91c.
  • the surface of the terminal 61 opposite to the heat sink 51 is connected to the emitter electrode 31e via the solder 91b.
  • the heat sink 51 has a main body portion 51a and a joint portion 51b.
  • a semiconductor element 31 is connected to one surface of the main body 51a via a terminal 61.
  • the joint portion 51b is connected to the main body portion 51a.
  • the joint portion 51b is integrally provided with the main body portion 51a as one member.
  • the joint portion 51b extends from one end of the main body portion 51a in the Y direction.
  • the joint portion 51b is thinner than the main body portion 51a.
  • the heat sinks 41 and 51 are covered with the sealing resin body 21. Of the surfaces of the heat sinks 41 and 51, the surface opposite to the semiconductor element 31 is exposed from the sealing resin body 21. In the Z direction, the heat sink 41 is exposed from one surface 21a of the sealing resin body 21, and the heat sink 51 is exposed from the back surface 21b opposite to the one surface 21a. The exposed surface of the heat sink 41 is substantially flush with the back surface 21a, and the exposed surface of the heat sink 51 is substantially flush with the back surface 21b.
  • the main terminal 71 is a terminal through which the main current flows among the external connection terminals.
  • the semiconductor device 11 includes three or more main terminals 71.
  • the main terminal 71 has a collector terminal C1 and an emitter terminal E1.
  • the collector terminal C1 is connected to the heat sink 41.
  • the collector terminal C1 is electrically connected to the collector electrode 41c via the heat sink 41.
  • the emitter terminal E1 is connected to the heat sink 51.
  • the emitter terminal E1 is electrically connected to the emitter electrode 31e via the heat sink 51 and the terminal 61.
  • the semiconductor device 11 has three main terminals 71. As shown in FIGS. 2, 3, 6, and 8, the main terminal 71 has one collector terminal C1 and two emitter terminals E1. As shown in FIG. 8, the lead frame 101 includes a heat sink 41, a collector terminal C1 and an emitter terminal E1 which are main terminals 71, and a signal terminal 81.
  • the heat sink 41 is thicker than the other parts of the lead frame 101, that is, the main terminal 71 and the signal terminal 81.
  • the main terminal 71 and the signal terminal 81 are substantially flush with each other on the element mounting surface of the heat sink 41.
  • the ends of the plurality of main terminals 71 on the same side are connected to the outer frame 101a.
  • the heat sink 41 is fixed to the outer frame 101a via the collector terminal C1 and the suspension lead 101b.
  • the signal terminal 81 is fixed to the suspension lead 101b via the tie bar 101c.
  • the lead frame 101 is provided with a plurality of reference holes 101d for positioning.
  • the collector terminal C1 is integrally provided with the heat sink 41 as one member.
  • the collector terminal C1 has a bent portion in the sealing resin body 21, and projects outward from the vicinity of the center in the Z direction on one side surface 21c of the sealing resin body 21.
  • the emitter terminal E1 has a portion E1a facing the joint portion 51b of the heat sink 51, respectively. As shown in FIG. 5, the facing portion E1a is connected to the joint portion 51b via the solder 91d.
  • the emitter terminal E1 has a bent portion in the sealing resin body 21, and projects outward from the vicinity of the center in the Z direction on the same side surface 21c as the collector terminal C1. All main terminals 71 project from the side surface 21c.
  • the heat sink 51 may be formed with, for example, an annular groove (not shown) so as to surround the connection portions with the solders 91c and 91d, respectively.
  • the overflowing solder is contained in the groove.
  • a roughened portion by roughening plating or laser light irradiation may be provided instead of the groove.
  • the protruding portions of the collector terminal C1 and the emitter terminal E1 extend in the Y direction.
  • the collector terminal C1 and the emitter terminal E1 are arranged side by side in the X direction, and their respective plate thickness directions substantially coincide with the Z direction.
  • the collector terminal C1 is arranged between the emitter terminals E1 in the X direction.
  • the arrangement order of the main terminals 71 is symmetrical with respect to the center of the arrangement.
  • the main terminals 71 are arranged side by side in the order of the emitter terminal E1, the collector terminal C1, and the emitter terminal E1.
  • each of the collector terminal C1 and the emitter terminal E1 are arranged line-symmetrically with the axis AX1 as the axis of symmetry.
  • the collector terminal C1 is arranged on the shaft AX1, and the center of the width of the collector terminal C1 substantially coincides with the shaft AX1.
  • the two emitter terminals E1 are arranged line-symmetrically with the axis AX1 as the axis of symmetry.
  • one of the semiconductor elements 31 may be referred to as a semiconductor element 31a, and the other one of the semiconductor elements 31 may be referred to as a semiconductor element 31b.
  • One of the emitter terminals E1 is biased toward the semiconductor element 31a with respect to the shaft AX1, and the other one of the emitter terminals E1 is biased toward the semiconductor element 31b with respect to the shaft AX1.
  • the signal terminal 81 is connected to the pad of the corresponding semiconductor element 31.
  • the signal terminal 81 is connected to the pad inside the sealing resin body 21 via a bonding wire 111.
  • the signal terminal 81 projects outward from the side surface of the sealing resin body 21, specifically, the side surface 21d opposite to the side surface 21c.
  • the signal terminal 81 projects in the Y direction and in the direction opposite to that of the main terminal 71.
  • the sealing resin body 21 integrally seals a part of each of the semiconductor element 31, the heat sink 41, and 51, and a part of each of the terminal 61, the main terminal 71, and the signal terminal 81. There is.
  • the semiconductor device 12 includes a sealing resin body 22, a semiconductor element 32, heat sinks 42 and 52, a terminal 62, a main terminal 72, and a signal terminal 82. Since the semiconductor device 12 has the same components as the semiconductor device 11 and has substantially the same structure, mainly different parts will be described.
  • the sealing resin body 22 seals the semiconductor element 32 and the like.
  • the collector electrode 32c is formed on one surface of the semiconductor element 32
  • the emitter electrode 32e is formed on the back surface.
  • the semiconductor device 12 also has a plurality of semiconductor elements 32.
  • a plurality of semiconductor elements 32 are connected in parallel to form a lower arm 7L. In this embodiment, it has two semiconductor elements 32.
  • the two semiconductor elements 32 have the same structure.
  • the two semiconductor elements 32 are located at substantially the same height in the Z direction and are arranged side by side in the X direction.
  • the two semiconductor elements 32 are arranged line-symmetrically with the axis AX2 orthogonal to the X-direction and the Z-direction as the axis of symmetry.
  • the sealing resin body 22 has a substantially rectangular shape in a plane, and the two semiconductor elements 32 are arranged so that the axis AX2 substantially coincides with the center of the outer shape of the sealing resin body 22 in the X direction. ing.
  • the heat sinks 42 and 52 are arranged so as to sandwich the plurality of semiconductor elements 32.
  • the plate thickness directions of the heat sinks 42 and 52 are substantially parallel to the Z direction.
  • the X direction is the longitudinal direction and the Y direction is the lateral direction.
  • the heat sink 42 is connected to the collector electrode 32c via the solder 92a.
  • the heat sink 52 is connected to the emitter electrode 32e via the solders 92b and 92c and the terminal 62.
  • the heat sink 52 has a main body portion 52a to which the semiconductor element 32 is connected via the terminal 62, and a joint portion 52b connected to the main body portion 52a.
  • the joint portion 52b extends from one end of the main body portion 52a in the Y direction.
  • the joint portion 52b is thinner than the main body portion 52a.
  • the heat sink 42 is exposed from one surface 22a of the sealing resin body 22, and the heat sink 52 is exposed from the back surface 22b opposite to the one surface 22a.
  • the exposed surface of the heat sink 42 is substantially flush with the back surface 22a, and the exposed surface of the heat sink 52 is substantially flush with the back surface 22b.
  • the semiconductor device 12 includes three or more main terminals 72.
  • the main terminal 72 has a collector terminal C2 and an emitter terminal E2.
  • the collector terminal C2 is electrically connected to the collector electrode 42c via the heat sink 42.
  • the emitter terminal E2 is electrically connected to the emitter electrode 32e via the heat sink 52 and the terminal 62.
  • the semiconductor device 12 has the same number of main terminals 72 as the semiconductor device 11.
  • the main terminal 72 has two collector terminals C2 and one emitter terminal E2.
  • the lead frame 102 includes a heat sink 42, a collector terminal C2 and an emitter terminal E2 which are main terminals 72, and a signal terminal 82.
  • Reference numeral 102a shown in FIG. 8 is an outer frame
  • reference numeral 102b is a hanging lead
  • reference numeral 102c is a tie bar
  • reference numeral 102d is a reference hole.
  • the collector terminal C2 is integrally provided with the heat sink 42 as one member.
  • the collector terminal C2 has a bent portion in the sealing resin body 21, and projects outward from the vicinity of the center in the Z direction on one side surface 22c of the sealing resin body 22.
  • the emitter terminal E2 has a portion E2a facing the joint portion 52b of the heat sink 52.
  • the facing portion E2a is connected to the joint portion 52b via the solder 92d.
  • the emitter terminal E2 has a bent portion in the sealing resin body 22, and projects outward from the vicinity of the center in the Z direction on the same side surface 22c as the collector terminal C2.
  • the heat sink 52 may be formed with, for example, an annular groove so as to surround the connection portions with the solders 92c and 92d, respectively.
  • the protruding portions of the collector terminal C2 and the emitter terminal E2 extend in the Y direction.
  • the collector terminal C2 and the emitter terminal E2 are arranged side by side in the X direction, and their respective plate thickness directions substantially coincide with the Z direction.
  • the emitter terminal E2 is arranged between the collector terminals C2 in the X direction.
  • the arrangement order of the main terminals 72 is symmetrical with respect to the center of the arrangement.
  • the main terminals 72 are arranged side by side in the order of the collector terminal C2, the emitter terminal E2, and the collector terminal C2.
  • the order of the main terminals 72 and the main terminals 71 is reversed from each other.
  • each of the collector terminal C2 and the emitter terminal E2 are arranged line-symmetrically with the axis AX2 as the axis of symmetry.
  • the emitter terminal E2 is arranged on the shaft AX2, and the center of the width of the emitter terminal E2 substantially coincides with the shaft AX2.
  • the two collector terminals C2 are arranged line-symmetrically with the axis AX2 as the axis of symmetry.
  • one of the semiconductor elements 32 may be referred to as a semiconductor element 32a, and the other one of the semiconductor elements 32 may be referred to as a semiconductor element 32b.
  • One of the collector terminals C2 is biased toward the semiconductor element 32a with respect to the shaft AX2, and the other one of the collector terminals C2 is biased toward the semiconductor element 32b with respect to the shaft AX2.
  • the signal terminal 81 is connected to the pad of the semiconductor element 32 via the bonding wire 112 inside the sealing resin body 22.
  • the signal terminal 82 projects outward from the side surface 22d opposite to the side surface 22c in the sealing resin body 21.
  • each element constituting the semiconductor device 11 is prepared.
  • the lead frame 101 shown in FIG. 8 is prepared. Further, the semiconductor element 31, the terminal 61, and the heat sink 51 are prepared.
  • the semiconductor element 31 is arranged on the mounting surface of the heat sink 41 of the lead frame 101 via the solder 91a.
  • the semiconductor element 31 is arranged on the solder 91a so that the collector electrode 31c is on the mounting surface side.
  • the terminal 61 is arranged on the emitter electrode 31e via the solder 91b.
  • the solder 91c is arranged on the surface of the terminal 61 opposite to the semiconductor element 31.
  • the solder 91c is arranged in an amount capable of absorbing the height variation in the semiconductor device 11.
  • the solders 91b and 91c may be provided in advance at the terminal 61 as solder.
  • the solder 91d is arranged on the facing portion E1a of the emitter terminal E1.
  • the solder 91d is also arranged in an amount capable of absorbing the height variation in the semiconductor device 11.
  • the collector electrode 31c of the semiconductor element 31 and the heat sink 41 are connected via the solder 91a.
  • the emitter electrode 31e of the semiconductor element 31 and the corresponding terminal 61 are connected via the solder 91b. That is, it is possible to obtain a connector in which the lead frame 101, the semiconductor element 31, and the terminal 61 are integrated.
  • the solders 91c and 91d serve as the receiving solder used in the subsequent process in the connecting body.
  • the pad of the semiconductor element 31 and the signal terminal 81 are electrically connected.
  • the pad of the semiconductor element 31 and the signal terminal 81 are connected by the bonding wire 111.
  • the heat sink 41 is placed on a pedestal (not shown) so that the terminal 61 side faces up. Then, the heat sink 51 is arranged on the heat sink 41 so that the mounting surface on the terminal 61 side is on the bottom. In this arrangement state, 2nd reflow is performed. By the 2nd reflow, the heat sink 51 is integrated with the connection body including the lead frame 101.
  • the sealing resin body 21 is formed.
  • the transfer mold method is adopted.
  • a connecting body including the lead frame 101 is placed in the mold to form the sealing resin body 21.
  • the sealing resin body 21 is molded so that the heat sinks 41 and 51 are completely covered.
  • the inverter 5 is composed of three semiconductor modules. As shown in FIGS. 9 and 10, the semiconductor module 10 includes the above-mentioned semiconductor devices 11 and 12, a connecting member 13, and a cooler 14. In FIG. 9, the cooler 14 is omitted for convenience.
  • the cooler 14 is formed by using a metal material having excellent thermal conductivity, for example, an aluminum-based material.
  • the cooler 14 has a flat tubular body as a whole.
  • the semiconductor devices 11 and 12 and the cooler 14 are alternately laminated.
  • the semiconductor devices 11 and 12 and the cooler 14 are arranged side by side in the Z direction.
  • Each of the semiconductor devices 11 and 12 is sandwiched by the cooler 14.
  • the semiconductor devices 11 and 12 are cooled from both sides by the cooler 14.
  • An introduction pipe and a discharge pipe are connected to the cooler 14.
  • the refrigerant is supplied to the introduction pipe by a pump (not shown)
  • the refrigerant flows through the flow path in the stacked coolers 14.
  • each of the semiconductor devices 11 and 12 is cooled by the refrigerant.
  • the refrigerant flowing through each of the coolers 14 is discharged through the discharge pipe.
  • the collector terminal C1 on the high potential side is electrically connected to the power line 8P.
  • the emitter terminal E1 on the low potential side is an output terminal.
  • the collector terminal C1 is also referred to as a P terminal or a positive electrode terminal, and the output terminal is also referred to as an O terminal.
  • the collector terminal C2 on the high potential side is an output terminal.
  • the emitter terminal E2 on the low potential side is electrically connected to the power line 8N.
  • the collector terminal C2 is also referred to as an O terminal, and the emitter terminal E2 is also referred to as an N terminal or a negative electrode terminal.
  • a set of semiconductor devices 11 and 12 constituting the upper and lower arms 7 are arranged so as to be adjacent to each other via the cooler 14.
  • the semiconductor devices 11 and 12 are arranged so that the collector terminal C1 and the emitter terminal E2 face each other, and the emitter terminal E1 and the collector terminal C2 face each other.
  • Opposing is a state in which the plate surfaces face each other at least a part of the protruding portions from the corresponding sealing resin bodies 21 and 22.
  • the protruding portions from the corresponding sealing resin bodies 21 and 22 face each other in almost the entire area.
  • the connecting member 13 is a member that connects the semiconductor devices 11 and 12.
  • the connecting member 13 is a wiring that electrically connects the upper arm 7U and the lower arm 7L.
  • the connecting member 13 electrically connects the emitter terminal E1 and the collector terminal C2, which are output terminals.
  • One semiconductor module 10 includes two connecting members 13 for connecting two sets of output terminals.
  • the connecting member 13 is formed by processing, for example, a metal plate.
  • the connecting member 13 is also referred to as a cross-linking member or a connecting bus bar.
  • the connecting member 13 is connected to the emitter terminal E1 and the collector terminal C2 by welding, for example.
  • the connecting member 13 of the present embodiment has a substantially U-shape (substantially U-shape).
  • the emitter terminal E1 is connected to one end of the connecting member 13, and the collector terminal C2 is connected to the other end.
  • the connecting member 13 is arranged so that the corresponding output terminals and the plate surfaces face each other, and are connected in this arranged state.
  • the two connecting members 13 have the same structure.
  • FIG. 11 is an equivalent circuit diagram in consideration of the wiring inductance (parasitic inductance) of the semiconductor module 10, that is, the upper and lower arms 7.
  • the switching elements Q1 the switching element formed on the semiconductor element 31a
  • the switching element formed on the semiconductor element 31b is shown as Q1b
  • the switching element formed on the semiconductor element 31b is shown as Q1b
  • the switching element formed on the semiconductor element 32a is referred to as Q2a
  • the switching element formed on the semiconductor element 32b is referred to as Q2b.
  • Lc11, Lc12, Le11, and Le12 indicate the wiring inductance of the parallel circuit of the switching element Q1.
  • Lc21, Lc22, Le21, and Le22 indicate the wiring inductance of the parallel circuit of the switching element Q2.
  • the semiconductor devices 11 and 12 are provided with three or more main terminals 71 and 72, respectively. That is, the semiconductor device 11 includes a plurality of at least one of the collector terminal C1 and the emitter terminal E1. Further, the semiconductor device 12 includes a plurality of at least one of the collector terminal C2 and the emitter terminal E2. Multiple main terminals of the same type are used in parallel. For example, the emitter terminal E1 is parallelized and the collector terminal C2 is parallelized. As a result, the inductance of the main terminal can be reduced.
  • the main circuit is a circuit including a smoothing capacitor Cs and an upper and lower arm 7.
  • the order of the collector terminal C1 and the emitter terminal E1 is symmetrical with respect to the center of the arrangement.
  • the wiring inductances Lc11 and Lc12 can be brought closer to each other, and the wiring inductances Le11 and Le12 can be brought closer to each other.
  • the arrangement order of the collector terminal C2 and the emitter terminal E2 is symmetrical with respect to the center of the arrangement.
  • the wiring inductances Lc21 and Lc22 can be brought closer to each other, and the wiring inductances Le21 and Lc22 can be brought closer to each other.
  • the inductance can be reduced by the effect of canceling the magnetic flux. Similarly, in the semiconductor device 12, the inductance can be reduced.
  • a plurality of semiconductor elements 31 are arranged line-symmetrically with respect to the axis AX1 orthogonal to the X direction, which is the arrangement direction.
  • the collector terminal C1 and the emitter terminal E1 are arranged line-symmetrically with the axis AX1 as the axis of symmetry.
  • the current path of the collector terminal C1 ⁇ the switching element Q1a ⁇ the emitter terminal E2 and the current path of the collector terminal C1 ⁇ the switching element Q1b ⁇ the emitter terminal E2 become substantially line symmetric with the axis AX1 as the axis of symmetry. That is, the wiring inductances Lc11 and Lc12 are substantially equal to each other.
  • the wiring inductances Le11 and Le12 are substantially equal to each other. Therefore, in the semiconductor device 11, the imbalance of AC current can be effectively suppressed.
  • the plurality of semiconductor elements 32 are arranged line-symmetrically with respect to the axis AX2 orthogonal to the X direction, which is the arrangement direction.
  • the collector terminal C2 and the emitter terminal E2 are arranged line-symmetrically with the axis AX2 as the axis of symmetry.
  • the current path of the collector terminal C2 ⁇ the switching element Q2a ⁇ the emitter terminal E2 and the current path of the collector terminal C2 ⁇ the switching element Q2b ⁇ the emitter terminal E2 become substantially line symmetric with the axis AX2 as the axis of symmetry. That is, the wiring inductances Lc21 and Lc22 are substantially equal to each other.
  • the wiring inductances Le21 and Le22 are substantially equal to each other. Therefore, in the semiconductor device 12, the imbalance of the AC current can be effectively suppressed.
  • the centers of the semiconductor elements 31 arranged side by side are completely aligned in the Y direction. Further, the centers of the semiconductor elements 32 arranged side by side are completely aligned in the Y direction. According to this, the imbalance of the AC current can be suppressed more effectively. However, it is not limited to the exact coincidence of the center. If there is a slight deviation in the Y direction, an effect similar to the above effect can be obtained.
  • a bus bar or the like is connected to the main terminals 71 and 72 for electrical connection with the smoothing capacitor Cs and the motor generator 3. Busbars are welded, for example. Therefore, the above effect can be obtained if at least the portion forming the current path, that is, the portion up to the connection position with the bus bar is line-symmetrical with respect to each of the main terminals 71 and 72.
  • the shaft AX1 substantially coincides with the center of the outer shape of the sealing resin body 21 in the X direction. As a result, the above effect can be achieved while reducing the size of the semiconductor device 11.
  • the shaft AX2 substantially coincides with the center of the outer shape of the sealing resin body 22 in the X direction. As a result, the above effect can be achieved while reducing the size of the semiconductor device 12.
  • the semiconductor devices 11 and 12 are connected by a plurality of connecting members 13. By increasing the connection paths between the upper arm 7U and the lower arm 7L, the inductance of the main circuit wiring can be reduced.
  • All the main terminals 71 project from the side surface 21c of the sealing resin body 21 and are arranged along the X direction. All the main terminals 72 project from the side surface 22c of the sealing resin body 22 and are arranged along the X direction.
  • the protruding portions of the collector terminal C1 and the emitter terminal E2 face each other in almost the entire area, and the protruding portions of the emitter terminal E1 and the collector terminal C2 face each other in almost the entire area. Therefore, the inductance of the main circuit wiring can be effectively reduced.
  • the heat sinks 41 and 51 are shared by a plurality of semiconductor elements 31. Therefore, the voltage fluctuation between the switching elements Q1 can be suppressed. Similarly, since the heat sinks 42 and 52 are shared by the semiconductor elements 32, voltage fluctuations between the switching elements Q2 can be suppressed. Furthermore, the number of parts can be reduced.
  • FIG. 12 corresponds to FIG. 2, and the elements in the sealing resin bodies 21 and 22 are shown by broken lines.
  • the semiconductor module 10 includes semiconductor devices 11 and 12 having three or more main terminals 71 and 72. All of the main terminals 71 and 72 are configured in the lead frames 101 and 102 for the purpose of position accuracy during molding of the sealing resin body. The order of the main terminals 71 and 72 is reversed, and the semiconductor devices 11 and 12 have a difference in the connection structure between the emitter terminals E1 and E2 and the heat sinks 51 and 52. This may complicate the manufacturing process, that is, reduce the productivity.
  • the heat sink 51 side is not clamped by the mold, but only the heat sink 41 (lead frame 101) side is clamped. Since only one member is clamped, the position accuracy when molding the sealing resin body 21 is improved. For example, resin leakage can be suppressed. The same applies to the lead frame 102.
  • the sealing resin bodies 21 and 22 and the protruding portions of the main terminals 71 and 72 At least the root portions 71r and 72r have the same structure as each other.
  • the sealing resin bodies 21 and 22 have the same shape and the same size as each other.
  • the appearances of the sealing resin bodies 21 and 22 are the same.
  • the root portions 71r and 72r have the same shape and the same size as each other.
  • the base portions 71r and 72r of the collector terminal C1 and the emitter terminal E2 have the same structure.
  • the base portions 71r and 72r of the emitter terminal E1 and the collector terminal C2 have the same structure.
  • the arrangement (position) of the root portions 71r and 72r with respect to the sealing resin bodies 21 and 22 is also the same as each other. From the above, the sealing resin bodies 21 and 22 can be molded using the same mold. Productivity can be improved by standardizing the mold. For example, mold exchange can be eliminated.
  • the root portions 71r and 72r are the portions of the main terminals 71 and 72 that are clamped by the mold when the sealing resin bodies 21 and 22 are molded. It is a portion within a predetermined range (for example, about 1 mm) from the side surfaces 21c and 22c of the sealing resin bodies 21 and 22.
  • the same arrangement means that the root portions 71r and 72r almost completely overlap each other when projected from the Z direction in a state where the semiconductor devices 11 and 12 are laminated so that the sealing resin bodies 21 and 22 coincide with each other. It is a positional relationship.
  • solder joint portion 121 is formed between the heat sink 51 and the emitter terminal E1 via a solder 91d.
  • a solder joint portion 122 is formed between the heat sink 52 and the emitter terminal E2 via a solder 92d.
  • at least one of the sealing resin bodies 21 and 22 and the root portions 71r and 72r is used as a position reference for the semiconductor devices 11 and 12, and at least a part of the solder joint portions 121 and 122 is provided at the same position in the Y direction. There is. As shown in FIG. 12, solder joints 121 and 122 are provided on the virtual line L1 parallel to the X direction, respectively.
  • the semiconductor module 10 it is possible to improve productivity while providing two types (two product numbers) of semiconductor devices 11 and 12.
  • the centers of the solder joints 121 and 122 in the Y direction coincide with each other. As a result, productivity can be further improved.
  • the other clamp portions in the lead frames 101 and 102 have the same structure as each other, and the arrangements with respect to the sealing resin bodies 21 and 22 are also the same as each other.
  • the root portions 81r and 82r have the same structure, and the arrangements (positions) with respect to the sealing resin bodies 21 and 22 are also the same.
  • the root portions 101br and 102br have the same structure, and the arrangements (positions) with respect to the sealing resin bodies 21 and 22 are also the same.
  • the same structure and arrangement are the same for the entire protruding portions of the main terminals 71 and 72.
  • the potentials (collectors / emitters) of the main terminals 71 and 72 are opposite to each other, the semiconductor devices 11 and 12 have the same appearance. According to this, productivity can be further improved. For example, it is easy to manufacture under the same process and conditions. For example, the connection with the smoothing capacitor Cs can be performed in the same process and conditions.
  • the solder joints 121 are arranged line-symmetrically with the axis AX1 as the axis of symmetry.
  • the semiconductor element 31 and the solder joint portion 121 are arranged line-symmetrically with the axis AX1 as the axis of symmetry.
  • the solder joints 122 are arranged line-symmetrically with the axis AX2 as the axis of symmetry.
  • the semiconductor element 32 and the solder joint portion 122 are arranged line-symmetrically with the axis AX2 as the axis of symmetry.
  • the positioning reference holes 101d and 102d provided in the lead frames 101 and 102 are also positioned at the same position with the sealing resin bodies 21 and 22 as the position reference.
  • a positioning pin (not shown) is positioned according to the reference holes 101d and 102d. Therefore, the positions of the corresponding elements in the semiconductor devices 11 and 12 can be accurately aligned.
  • the width W1 of the plurality of main terminals 71 and the width W2 of the plurality of main terminals 72 are equal to each other.
  • the widths of the lead frames 101 and 102 in the X direction are equal to each other.
  • the heat sinks 41 and 42 which are thick portions, have the same structure. Since the heat capacities 41 and 42 have the same heat capacity, solder bonding can be performed under the same reflow process and conditions when forming the semiconductor devices 11 and 12. For example, the 1st reflow can be performed under the same process and conditions.
  • heat sinks 51 and 52 having the same structure may be adopted.
  • the heat sinks 51 and 52 have the same shape and size.
  • the heat sinks 51 and 52 have the same heat capacity. Thereby, the 2nd reflow can be stabilized. Further, by sharing the heat sinks 51 and 52, the number of parts can be reduced.
  • At least one of the semiconductor devices 11 and 12 may be provided with a mark for distinguishing from the others.
  • the mark may be provided on the protruding tip side of the portion to which the bus bar or the like is connected. That is, it is preferable to provide the upper and lower arms 7 in a portion that does not affect the current operation.
  • a notch 71 m which is a mark, is provided in one of the emitter terminals E1 of the semiconductor device 11.
  • the position of the notch 71 m is not limited to the emitter terminal E1.
  • another notch may be provided at different positions of the semiconductor device 12.
  • a notch may be provided at the protruding tip of the emitter terminal E2.
  • a mark different from the notch may be used.
  • a mark formed by printing, laser processing, or the like can be adopted.
  • the above-mentioned notch is preferable.
  • the notch can be formed, for example, when the lead frames 101 and 102 are formed, or when the tie bars 101c and 102c are removed (lead cut).
  • the semiconductor devices 11 and 12 are provided with three main terminals 71 and 72, respectively, but the present invention is not limited to this.
  • a configuration may be configured in which four or more main terminals 71 and 72 are provided.
  • the semiconductor devices 11 and 12 are provided with seven corresponding main terminals 71 and 72.
  • the semiconductor device 11 includes three collector terminals C1 and four emitter terminals E1.
  • the collector terminal C1 and the emitter terminal E1 are arranged alternately in the X direction.
  • the semiconductor device 12 includes four collector terminals C2 and three emitter terminals E2.
  • the collector terminal C2 and the emitter terminal E2 are arranged alternately in the X direction.
  • the arrangement order of the main terminals 71 and 72 is symmetrical with respect to the center of the arrangement.
  • the order of arrangement of the main terminals 71 and 72 as viewed from the center is opposite to each other.
  • the heat sinks 51 and 52 have the same structure as in FIG.
  • the semiconductor devices 11 and 12 include two corresponding semiconductor elements 31 and 32, but the present invention is not limited to this. Three or more semiconductor elements 31 and 32 may be provided.
  • the configuration may not include terminals 61 and 62.
  • the heat sinks 41, 42, 51 and 52 are exposed from the corresponding sealing resin bodies 21 and 22, the heat sinks 41, 42, 51 and 52 may not be exposed from the sealing resin bodies 21 and 22.
  • the heat sinks 41, 42, 51, 52 may be divided into a plurality of heat sinks 41, 42, 51, 52 according to the number of semiconductor elements 31, 32, for example. However, productivity can be improved by integrating them. Moreover, the fluctuation of the voltage can be suppressed in the parallel circuit.
  • the semiconductor module 10 further includes a load line 9.
  • the load line 9 is formed by using a metal material such as copper.
  • the load line 9 is formed in a plate shape, for example.
  • the load line 9 is also referred to as a bus bar.
  • the semiconductor module 10 includes, as the connecting member 13, a connecting member 13a in which the load lines 9 are connected and a connecting member 13b in which the load lines 9 are not connected.
  • the load line 9 may be provided integrally with the connecting member 13a or may be connected to the connecting member 13a.
  • the load line 9 is connected to a predetermined position of the connecting member 13a. In FIGS. 16 and 17, the cooler 14 is omitted for convenience.
  • the connection structure with the motor generator 3 can be simplified. Further, the connection between the collector terminal C1 and the emitter terminal E2 and the smoothing capacitor Cs can be simplified.
  • the basic configuration of the semiconductor devices 11 and 12 is the same as that of the prior embodiment.
  • the semiconductor device 11 includes one collector terminal C1 and two emitter terminals E1.
  • the semiconductor device 12 includes two collector terminals C2 and one emitter terminal E2.
  • the emitter terminals E1 and E2 of the semiconductor devices 11 and 12 are solder-bonded to the corresponding heat sinks 51 and 52.
  • one of the emitter terminals E1 may be referred to as an emitter terminal E11, and the other one may be referred to as an emitter terminal E12.
  • One of the collector terminals C2 may be referred to as a collector terminal C21, and the other one may be referred to as a collector terminal C22.
  • the emitter terminal E11 is arranged on the semiconductor element 31a side
  • the emitter terminal E12 is arranged on the semiconductor element 31b side
  • the collector terminal C21 is arranged on the semiconductor element 32a side
  • the collector terminal C22 is arranged on the semiconductor element 32b side.
  • FIG. 18 is a circuit model of the upper and lower arms 7 in consideration of wiring resistance in order to verify the continuous position of the load lines 9.
  • the load shown in FIG. 18 corresponds to the stator winding of the motor generator 3.
  • the load is an inductive load (L load).
  • the collector terminal C1 which is a P terminal may be simply referred to as P
  • the emitter terminal E2 which is an N terminal may be simply indicated as N
  • the load line 9 which is an output line may be simply referred to as O.
  • the upper and lower arms 7 have a first path F1 and a second path F2 as paths for connecting the upper arm 7U and the lower arm 7L. In the following, it may be simply referred to as routes F1 and F2.
  • the first path F1 has a connecting member 13a, an emitter terminal E11, and a collector terminal C21.
  • the connecting member 13a is welded to the emitter terminal E11 and the collector terminal C21 which are output terminals.
  • the resistance R1 of the welded portion between the emitter terminal E11 and the connecting member 13a, the resistors R2 and R3 which are the wiring resistances of the connecting member 13a itself, the collector terminal C21 and the connecting member 13a Has a resistance R4 of the welded portion of.
  • the second path F2 has a connecting member 13b, an emitter terminal E12, and a collector terminal C22.
  • the connecting member 13b is welded to the emitter terminal E12 and the collector terminal C22, which are output terminals.
  • the resistance R5 of the welded portion between the emitter terminal E12 and the connecting member 13b, the resistors R6 and R7 which are the wiring resistances of the connecting member 13b itself, and the collector terminal C22 and the connecting member 13b Has a resistance R8 of the welded portion of.
  • the load lines 9 are connected closer to the upper arm 7U and the resistors R2 and R3 are on the lower arm 7L side from the position where the load lines 9 are connected in the first path F1.
  • the DC current is a current that flows not at the time of switching but at the steady state when the switching element is turned on.
  • CP1 and CP2 indicated by solid arrows in FIG. 18 are main current paths when driving the switching elements Q1 (Q1a, Q1b) on the upper arm 7U side.
  • CP3 and CP4 indicated by the broken line arrows are the main current paths when the switching elements Q2 (Q2a, Q2b) on the lower arm 7L side are driven.
  • the current path CP1 is collector terminal C1 (P) ⁇ heat sink 41 ⁇ switching element Q1a, Q1b ⁇ heat sink 51 ⁇ emitter terminal E11 ⁇ connecting member 13a ⁇ load line 9 (O).
  • the current path CP2 is the collector terminal C1 (P) ⁇ heat sink 41 ⁇ switching elements Q1a, Q1b ⁇ heat sink 51 ⁇ emitter terminal E12 ⁇ connecting member 13b ⁇ collector terminal C22 ⁇ heat sink 42 ⁇ collector terminal C21 ⁇ connecting member 13a ⁇ load line 9 (O).
  • the current path CP3 is a load line 9 (O) ⁇ a connecting member 13a ⁇ a collector terminal C21 ⁇ a heat sink 42 ⁇ switching elements Q2a and Q2b ⁇ a heat sink 52 ⁇ an emitter terminal E2 (N).
  • the current path CP4 is a load line 9 (O) ⁇ connecting member 13a ⁇ emitter terminal E11 ⁇ heat sink 51 ⁇ emitter terminal E12 ⁇ connecting member 13b ⁇ collector terminal C22 ⁇ heat sink 42 ⁇ switching elements Q2a and Q2b ⁇ heat sink 52 ⁇ emitter terminal E2. (N).
  • the resistance components of the main circuit wiring are different between the current paths CP3 and CP4, there is a risk of DC current imbalance.
  • FIG. 19 shows the simulation result of the current flowing through the output terminal when the motor lock occurs in the model shown in FIG.
  • FIG. 19A shows the current flowing through each output terminal when the upper arm 7U side is being driven.
  • FIG. 19B shows the current flowing through each output terminal when the lower arm 7L side is being driven.
  • the current flowing through the emitter terminal E11 is shown by a solid line
  • the current flowing through the collector terminal C21 is shown by a broken line
  • the current flowing through the emitter terminal E12 and the collector terminal C22 is shown by a dashed line.
  • the load current was 1000 [A]
  • the duty ratio of the output waveform of the upper and lower arms 7 was 55%.
  • the values of the resistors R1 to R8 were set to r, which are equal values to each other.
  • the resistance value of the current path CP1 is r
  • the resistance value of the current path CP2 is 7r
  • the resistance value of the current path CP3 is 3r
  • the resistance value of the current path CP4 is 5r with respect to the total resistance values of the paths F1 and F2 of 8r.
  • the current path CP1 is easier for the current to flow than the current path CP2.
  • the switching element Q1 is driven, a larger current flows in the emitter terminal E11 than in the emitter terminal E12.
  • the current path CP3 is easier for the current to flow than the current path CP4.
  • the switching element Q2 is driven, a larger current flows in the collector terminal C21 than in the collector terminal C22. In this way, the current is concentrated on the output terminals constituting the path F1, specifically, the emitter terminal E11 and the collector terminal C21.
  • a current flows from the upper and lower arms 7 to the load.
  • a current flows from the collector terminal C1 (P) to the load line 9 (O) via the switching element Q1 during the ON period of the PWM cycle.
  • a current flows from the emitter terminal E2 (N) to the load line 9 (O) via the diode D2.
  • the current flowing through the emitter terminal E11 is a rectangular wave of 875 [A] (duty ratio 55%) and 375 [A] (duty ratio 45%).
  • a current of 696 [A] flows through the emitter terminal E11 in terms of effective value.
  • a current flows from the load to the upper and lower arms 7.
  • a current flows from the load line 9 (O) to the emitter terminal E2 (N) via the switching element Q2.
  • a current flows from the load line 9 (O) to the collector terminal C1 (P) via the diode D1.
  • the current flowing through the collector terminal C21 is a rectangular wave of 625 [A] (duty ratio 45%) and 125 [A] (duty ratio 55%).
  • a current of 429 [A] flows through the collector terminal C21 in terms of effective value.
  • the DC current balance of the upper arm 7U is worse than that of the lower arm 7L. Therefore, among the emitter terminal E11 and the collector terminal C21 in which the current is concentrated due to the imbalance of the DC current, a large current flows particularly in the emitter terminal E11.
  • the emitter terminal E11 has a larger energizing stress.
  • the semiconductor module 10 of this embodiment has a solder joint portion 121 and a solder joint portion 122 as joint portions between the heat sinks 51 and 52 and the main terminals 71 and 72, as in the previous embodiment.
  • the solder joint portion 121 is formed between the heat sink 51 and the emitter terminals E11 and E12, respectively.
  • the solder joint portion 122 is formed between the heat sink 52 and the emitter terminal E2.
  • the emitter terminal E11 and the collector terminal C21 where the current is concentrated the emitter terminal E11 is formed with a solder joint portion 121, and the collector terminal C21 is not formed with a solder joint portion.
  • the collector terminal C21 is continuously provided with the heat sink 42 as one member. For example, the electromigration effect increases as the flowing current increases.
  • the emitter terminal E11 has lower resistance to energization stress than the collector terminal C21.
  • the value of the wiring resistance from the continuous position of the load lines 9 (hereinafter referred to as the reference position) to the heat sink 51 via the emitter terminal E11 is determined from the reference position via the collector terminal C21.
  • the reference position is set so as to be larger than the value of the wiring resistance up to the heat sink 42.
  • the load line 9 is formed on the welded portion of the connecting member 13a having a substantially U-shape with the collector terminal C21. It is in a row.
  • the reference position is also called the output branch point.
  • FIG. 20 is an equivalent circuit diagram of the semiconductor module 10 shown in FIGS. 16 and 17.
  • the reference position BP to which the load lines 9 are connected is provided closer to the lower arm 7L.
  • the wiring resistance between the reference position BP and the resistor R4 of the welded portion between the collector terminal C21 is set to zero, and the reference position BP is set between the wiring resistors R2, R3 and the resistor R4 of the connecting member 13a. It is provided in.
  • the resistance value (first resistance value) of the wiring portion from the reference position BP to the heat sink 51 via the emitter terminal E11 and the solder joint portion 121 is the total value of the resistors R1, R2, and R3.
  • the resistance value (second resistance value) of the wiring portion from the reference position BP to the heat sink 42 via the collector terminal C21 is the value of the resistor R4.
  • the first resistance value is 3r and the second resistance value is r.
  • the semiconductor device 11 on the emitter terminal E11 side having low resistance to current stress it is possible to suppress the imbalance of the DC currents of the emitter terminals E11 and E12.
  • the degree of DC current imbalance between the emitter terminals E11 and E12 can be reduced.
  • current concentration on the solder joint portion 121 formed at the emitter terminal E11 can be suppressed.
  • the current flowing through the solder joint 121 can be reduced. Therefore, the reliability of the semiconductor module 10 including the two types (two product numbers) of the semiconductor devices 11 and 12 can be improved.
  • the degree of DC current imbalance on the collector terminal C2 side increases, and the current flowing through the collector terminal C21 increases.
  • the collector terminal C21 has a higher resistance to energization stress than the emitter terminal E11. Therefore, the reliability of the semiconductor module 10 as a whole can be improved.
  • the emitter terminal E11 has lower resistance to energization stress than the collector terminal C21 depending on the presence or absence of solder bonding, but the present invention is not limited to this.
  • the collector terminal C21 may be solder-bonded to the heat sink 42, and the area of the solder-bonded portion of the collector terminal C21 may be larger than the area of the solder-bonded portion 121 of the emitter terminal E11.
  • the magnitude of resistance to energization stress is determined by the presence or absence of solder joints, the area of solder joints, and the like.
  • the collector terminal C21 on the lower arm 7L side may have a lower resistance to energization stress than the emitter terminal E11 on the upper arm 7U side.
  • the load line 9 may be provided in the path F1 so that the wiring resistance value from the reference position BP to the heat sink 42 is larger than the wiring resistance value from the reference position BP to the heat sink 51.
  • the reference position BP may be provided near the upper arm 7U in the connecting member 13a.
  • the connecting members 13a and 13b have the same structure. According to this, it is easy to adjust the imbalance of the DC current by the reference position BP of the load line 9. By using the connecting members 13a and 13b having the same structure and performing welding in the same manner, the resistance value of the entire path F1 and the resistance value of the entire path F2 can be made substantially equal.
  • the resistance ratio x at the cross point between the current flowing through the emitter terminal E11 and the current flowing through the collector terminal C21 is substantially the same as the duty ratio of the output waveform set when the motor is locked. Became clear.
  • FIG. 21 shows the relationship between the resistance ratio x and the ratio of the effective value currents of the emitter terminal E11 and the collector terminal C21 at various duty ratios set when the motor is locked. In the following, for the sake of distinction, the resistance ratio of the cross points is shown as x0.
  • the resistance ratio x is the ratio of the first resistance value to the resistance value of the entire path F1.
  • the duty ratio at the time of motor lock is generally set to about 50% (for example, in the range of 40 to 60%).
  • the duty ratio is 50% in FIG. 21 (a), 55% in FIG. 21 (b), and 60% in FIG. 21 (c).
  • the above simulation result is the result when the resistance ratio x is 0.25 in FIG. 21 (b).
  • the resistance ratio x 0.25, the ratio of the effective value current between the emitter terminal E11 and the collector terminal C21 is 0.62: 0.38.
  • the resistance ratio x0 of the cross point and the duty ratio Rd match at any duty ratio.
  • the resistance ratio x0 is 0.55.
  • the resistance ratio x0 is 0.5.
  • the resistance ratio x0 is 0.6.
  • the effective value current of the emitter terminal E11 can be made equal to or less than the effective value current of the collector terminal C21. Thereby, the reliability of the semiconductor module 10 can be improved.
  • the effective value current of the emitter terminal E11 can be made smaller than the effective value current of the collector terminal C21. Thereby, the reliability of the semiconductor module 10 can be further improved.
  • the collector terminal C21 has a lower resistance to energization stress, it is advisable to set the resistance ratio x, that is, the reference position BP so as to satisfy x ⁇ Rd.
  • the effective value current of the collector terminal C21 can be made equal to or less than the effective value current of the emitter terminal E11. Thereby, the reliability of the semiconductor module 10 can be improved.
  • x ⁇ Rd the effective value current of the collector terminal C21 can be made smaller than the effective value current of the emitter terminal E11. Thereby, the reliability of the semiconductor module 10 can be further improved.
  • the connecting members 13a and 13b have shown an example of the same structure, but the present invention is not limited to this.
  • An example is shown in which the resistance values of the paths F1 and F2 are almost the same, but the present invention is not limited to this. It can also be applied to configurations in which the structures of the connecting members 13a and 13b are different. It can also be applied to configurations in which the resistance values of the paths F1 and F2 are different.
  • at least one of width, thickness, and length may be different in at least a part of the connecting members 13a and 13b.
  • the resistance values of the paths F1 and F2 may be different by using different welding resistances (resistors R1, R4, R5, R8) while using the connecting members 13a and 13b having the same structure.
  • the connection between the connecting members 13a and 13b and the output terminal is not limited to welding. Fixing means other than welding, for example, fixing with a joining member, fastening, or the like may be used.
  • the duty ratio is 50% in FIG. 22 (a), 55% in FIG. 22 (b), and 60% in FIG. 22 (c).
  • the cross point resistance ratio x0 coincides with the duty ratio Rd.
  • the duty ratios are 55% and 60%, there is a discrepancy between the resistance ratio x0 and the duty ratio Rd.
  • the resistance ratio x0 is larger than the duty ratio Rd.
  • the duty ratio is 55%, the resistance ratio x0 is 0.6.
  • the resistance ratio x0 is 0.7.
  • the effective value current of the emitter terminal E11 can be made equal to or less than the effective value current of the collector terminal C21.
  • the effective value current of the emitter terminal E11 can be made smaller than the effective value current of the collector terminal C21.
  • the resistance ratio x that is, the reference position BP may be set so as to satisfy the following equation 4. (Equation 4) x ⁇ ⁇ (Rd-0.5) ⁇ k + 0.5 ⁇
  • the effective value current of the collector terminal C21 can be made equal to or less than the effective value current of the emitter terminal E11.
  • the effective value current of the collector terminal C21 can be made smaller than the effective value current of the emitter terminal E11. (Equation 5) x ⁇ ⁇ (Rd-0.5) xk + 0.5 ⁇
  • the duty ratio is 50% in FIG. 23 (a), 55% in FIG. 23 (b), and 60% in FIG. 23 (c).
  • the duty ratio is 50%
  • the cross point resistance ratio x0 coincides with the duty ratio Rd.
  • the duty ratio is 55%
  • the resistance ratio x0 is 0.575.
  • the resistance ratio x0 is 0.65.
  • the cross point resistance ratio x0 agrees with the value calculated by the above equation 1.
  • the duty ratio is 50% in FIG. 24 (a), 55% in FIG. 24 (b), and 60% in FIG. 24 (c).
  • the duty ratio is 50%
  • the cross point resistance ratio x0 coincides with the duty ratio Rd.
  • the duty ratio is 55%
  • the resistance ratio x0 is 0.525.
  • the duty ratio is 60%
  • the resistance ratio x0 is 0.55.
  • the cross point resistance ratio x0 agrees with the value calculated by the above equation 1.
  • the position of the load line 9 is not limited to the above example.
  • the connecting member 13a is extended from the connecting portion with the collector terminal C21, and the load line 9 is extended to this extending portion. It may be a continuous configuration.
  • the load line 9 may be connected to the connecting portion connecting the connecting portion between the emitter terminal E11 and the collector terminal C21 in the connecting member 13a having a substantially U shape.
  • the welding resistance may be different and / or the width of the connecting portion in the connecting member 13a may be different.
  • the connecting member 13a may be inverted in the Y direction.
  • the present invention is not limited to this.
  • the connecting member 13a is connected to the collector terminal C21 on the front and back sides in the plate thickness direction.
  • the structures of the connecting members 13a and 13b are different from each other.
  • the collector terminal C21 has two connecting portions, and the emitter terminal E11 has one connecting portion. Due to the two connection portions, the connection area of the collector terminal C21 is large. As a result, the value of the resistor R4 is smaller than the value of the resistor R1.
  • the connecting members 13a and 13b may be electrically connected by a thin wire 15 such as a wire.
  • the resistance value of the thin wire 15 is sufficiently larger than the resistance value of the other elements constituting the current paths CP1, CP2, CP3, and CP4.
  • the thin wire 15 does not significantly affect the balance of DC current.
  • Reference numeral B1 shown in FIG. 30 is a bus bar on the positive electrode side
  • reference numeral B2 is a bus bar on the negative electrode side
  • the collector terminal C1 is connected to the terminal on the positive electrode side of the smoothing capacitor Cs via the bus bar B1.
  • the emitter terminal E2 is connected to the terminal on the negative electrode side of the smoothing capacitor Cs via the bus bar B2.
  • some of the elements of the semiconductor devices 11 and 12, such as the sealing resin bodies 21 and 22, are omitted.
  • the structures of the semiconductor devices 11 and 12 are not limited to the double-sided heat dissipation structure. It can also be applied to a single-sided heat dissipation structure. Further, the present invention is not limited to the switching element having a vertical structure, and can be applied to a switching element having a horizontal structure (for example, LDMOS). In the case of a single-sided heat dissipation structure, for example, a connection structure in a flat state can be adopted.
  • the semiconductor devices 11 and 12 include a plurality of semiconductor elements 31 and 32, but the present invention is not limited to this.
  • a configuration including one semiconductor element 31 and 32 having a plurality of paths, for example, two paths F1 and F2, may cause an imbalance of DC current. Therefore, it can be applied to a configuration in which the semiconductor devices 11 and 12 include only one semiconductor element 31 and 32.
  • the semiconductor devices 11 and 12 include the sealing resin bodies 21 and 22, but the present invention is not limited to this.
  • the configuration may not include the sealing resin bodies 21 and 22.
  • FIG. 31 shows semiconductor devices 11 and 12 according to this embodiment.
  • the two semiconductor devices 11 and 12 are shown side by side.
  • the elements in the sealing resin bodies 21 and 22 are shown by broken lines.
  • the basic configuration of the semiconductor devices 11 and 12 is the same as that of the prior embodiment.
  • the semiconductor devices 11 and 12 have a double-sided heat dissipation structure.
  • the areas of the heat sinks 51 and 52 are smaller than the areas of the corresponding heat sinks 41 and 42.
  • Two semiconductor elements 31 are arranged side by side in the longitudinal direction of the heat sink 51 (main body 51a).
  • two semiconductor elements 32 are arranged side by side in the longitudinal direction of the heat sink 52 (main body 52a).
  • the semiconductor device 11 has a solder joint portion 121.
  • the solder joint portion 121 is formed between each of the emitter terminals E1 and the heat sink 51.
  • the semiconductor device 12 has a solder joint portion 122.
  • the solder joint portion 122 is formed between the emitter terminal E2 and the heat sink 52.
  • the semiconductor devices 11 and 12 further have solder joints 131 and 132.
  • the solder joint 131 is formed between each of the terminals 61 and the heat sink 51.
  • Solder joints 132 are formed between each of the terminals 62 and the heat sink 52. In FIG. 31, the solder joints 121, 122, 131, and 132 are hatched to distinguish them from the others.
  • the solder joint on the heat sinks 51 and 52 side is formed by the 2nd reflow as described above.
  • the connector including the heat sink 42 is arranged on the pedestal 200 so that the solders 92c and 92d are on the top.
  • the heat sink 52 is arranged. In this arrangement state, 2nd reflow is performed. At that time, the position of the heat sink 42 is determined by the weight of the member, the jig, etc., with the pedestal 200 as the position reference in the Z direction.
  • the heat sink 52 is positioned and arranged on the pedestal 200 by the jig 201, it is free in the Z direction when the solder is melted.
  • the relationship between the center of gravity Cg2 of the heat sink 52 and the surface tension of the solder connected to the heat sink 52 may cause the heat sink 52 to tilt.
  • the solders 92c and 92d do not harden at the same timing.
  • the volume change from the liquid phase to the solid phase of the solder may affect the inclination.
  • the semiconductor device 11 heat sink 51.
  • FIG. 32 attention is paid to the heat sinks 42 and 52 and the solders 92c and 92d, and for convenience, other elements are shown integrally with the heat sink 42.
  • the main solder joints of the heat sink 51 are arranged line-symmetrically with the axis AX11 passing through the center of gravity Cg1 of the heat sink 51 as the axis of symmetry.
  • the axis AX11 is orthogonal to the longitudinal direction of the heat sink 51, that is, the X direction and the Z direction, which is the plate thickness direction of the semiconductor element 31.
  • the main solder joints are arranged line-symmetrically with the axis AX12 passing through the center of gravity Cg2 of the heat sink 52 as the axis of symmetry.
  • the axis AX12 is orthogonal to the longitudinal direction of the heat sink 52, that is, the X direction and the Z direction, which is the plate thickness direction of the semiconductor element 32.
  • the amount of displacement is larger in the longitudinal direction than in the lateral direction. According to this embodiment, the amount of displacement can be suppressed. By suppressing the inclination, for example, heat dissipation can be ensured. In the semiconductor elements 31 and 32 connected in parallel, the deviation of the wiring inductance can be suppressed.
  • the semiconductor device 11 electrically connects the solder joint portion 131 that electrically connects the heat sink 51 and the semiconductor element 31 and the heat sink 51 and the emitter terminal E1 as the solder joint portion formed on the heat sink 51. It has a solder joint 121 connected to.
  • the solder joint 131 is formed to include the solder 91c
  • the solder joint 121 is formed to include the solder 91d.
  • the semiconductor device 11 has two solder joints 131 and two solder joints 121.
  • the two solder joints 131 are arranged line-symmetrically with the axis AX11 as the axis of symmetry. As a result, the surface tension of the solder 91c can be balanced in the longitudinal direction of the heat sink 51.
  • the two solder joints 121 are arranged line-symmetrically with the axis AX11 as the axis of symmetry. As a result, the surface tension of the solder 91d can be balanced in the longitudinal direction of the heat sink 51. As described above, it is possible to prevent the heat sink 51 from being tilted in the longitudinal direction.
  • the semiconductor device 12 electrically connects the solder joint portion 132 that electrically connects the heat sink 52 and the semiconductor element 32, and the heat sink 52 and the emitter terminal E2 as the solder joint portion formed on the heat sink 52. It has a solder joint 122.
  • the solder joint portion 132 is formed to include the solder 92c, and the solder joint portion 122 is formed to include the solder 92d.
  • the semiconductor device 12 has two solder joints 132 and one solder joint 122.
  • the two solder joints 132 are arranged line-symmetrically with the axis AX12 as the axis of symmetry. As a result, the surface tension of the solder 92c can be balanced in the longitudinal direction of the heat sink 52.
  • the solder joints 122 are arranged line-symmetrically with the axis AX12 as the axis of symmetry. As a result, the surface tension of the solder 92d can be balanced in the longitudinal direction of the heat sink 52. As described above, it is possible to prevent the heat sink 52 from being tilted in the longitudinal direction.
  • At least the upper two solder joints are provided so as to overlap the shaft AX21 in the lateral direction of the heat sink 51 in descending order of the connection area with the heat sink 51.
  • the axis AX21 is orthogonal to the lateral direction of the heat sink 51, that is, the Y direction and the Z direction, and passes through the center of gravity Cg1. Since the surface tension works at a position close to the axis AX21, the torque that causes tilt can be reduced in the lateral direction. As a result, it is possible to prevent the heat sink 51 from being tilted in the lateral direction.
  • all the solder joints 131 are provided on the shaft AX21.
  • the upper two solder joints are provided so as to overlap the shaft AX22 in the lateral direction of the heat sink 52 in descending order of the connection area with the heat sink 52.
  • the axis AX22 is orthogonal to the lateral direction of the heat sink 52, that is, the Y direction and the Z direction, and passes through the center of gravity Cg2. Since the surface tension works at a position close to the axis AX22, the torque that causes tilt can be reduced in the lateral direction. As a result, it is possible to prevent the heat sink 52 from being tilted in the lateral direction.
  • all the solder joints 132 are provided on the shaft AX22.
  • the solder joints 121 and 122 are provided at positions separated from the shafts AX21 and AX22 in the lateral direction so as not to overlap the shafts AX21 and AX22. This makes it possible to simplify the connection structure between the heat sinks 51 and 52, the semiconductor elements 31 and 32, and the emitter terminals E1 and E2. In particular, in the semiconductor device 11, since the two solder joints 121 are arranged on the same side with respect to the shaft AX21, the structure can be simplified.
  • the center 131c of the solder joint portion 131 is provided at a position farther from the solder joint portion 121 than the shaft AX21 in the lateral direction.
  • the center 131c substantially coincides with the center of the emitter electrode 31e.
  • the center 132c of the solder joint portion 132 is provided at a position farther from the solder joint portion 122 than the shaft AX22 in the lateral direction.
  • the surface tension of the solder 92c can be applied to the side that cancels the torque due to the surface tension of the solder 92d. Therefore, the inclination of the heat sink 52 in the lateral direction can be effectively suppressed.
  • the center 132c substantially coincides with the center of the emitter electrode 32e.
  • the heat sinks 41, 42, 51, and 52 correspond to the heat radiating members.
  • the heat sinks 41 and 42 correspond to the first member, and the heat sinks 51 and 52 correspond to the second member.
  • Solder joints 121, 122, 131, 132 correspond to a plurality of solder joints.
  • the solder joints 131 and 132 correspond to the first joint, and the solder joints 121 and 122 correspond to the second joint.
  • the shafts AX11 and AX12 correspond to the shaft and the first shaft.
  • the axes AX21 and AX22 correspond to the second axis.
  • heat sinks 41, 42, 51, and 52 are shown as heat radiating members, but the heat radiating member is not limited to this.
  • a DBC (Direct Bonded Copper) substrate can be used as at least one of the heat sinks 41 and 42 and the heat sinks 51 and 52.
  • the number and arrangement of the semiconductor elements 31 included in the semiconductor device 11 are not limited to the above examples.
  • the number and arrangement of the semiconductor elements 32 included in the semiconductor device 12 are not limited to the above examples. Three or more semiconductor elements 31 and 32 may be provided.
  • the semiconductor device 11 has four solder joints 131.
  • the plurality of solder joints 131 and 132 may be arranged line-symmetrically with respect to the axes AX11 and AX12.
  • the semiconductor device 11 has three solder joints 131. The two solder joints 131 are arranged side by side in the X direction so as to be line-symmetrical with respect to the axis AX11.
  • solder joints 131 are arranged so as to be offset in the Y direction with respect to the other two, and are arranged line-symmetrically with respect to the axis AX11.
  • the signal terminal 81, the suspension lead 101b, and the like are omitted for convenience.
  • the semiconductor device 11 is shown in FIGS. 33 and 34, it can also be applied to the semiconductor device 12.
  • the semiconductor devices 11 and 12 include the sealing resin bodies 21 and 22, but the present invention is not limited to this.
  • the configuration may be such that the sealing resin bodies 21 and 22 are not provided.
  • the semiconductor device 11 shown in the preceding embodiment has a solder joint portion 121 between the heat sink 51 and the main terminal 71.
  • the semiconductor device 12 has a solder joint portion 122 between the heat sink 52 and the main terminal 72.
  • FIG. 35 as an example, the periphery of the solder joint portion 122 of the semiconductor device 12 is schematically shown. In FIG. 35, the current flow is indicated by a solid arrow.
  • the solder 92d is interposed between the joint portion 52b of the heat sink 52 and the facing portion E2a of the emitter terminal E2, and the solder joint portion 122 is formed. If the current does not flow more easily in the facing portion E2a than in the joint portion 52b, the movement of the solder joint portion 122 to flow farther in the joint portion 52b having a low resistance is strengthened. As a result, in the solder 92d, the current density on the back side of the solder 92d is higher than that on the front side in the flow direction. As described above, in the solder 92d, the current tends to be locally concentrated.
  • Both the heat sink 52 and the emitter terminal E2 are formed of a metal material such as copper.
  • the heat sink 52 and the emitter terminal E2 have at least the same main component metal. For example, if the facing portion E2a is thinner than the joint portion 52b, the facing portion E2a is less likely to flow, so that the movement flow of the solder joint portion 122 that tries to flow farther in the joint portion 52b is strengthened.
  • the plate surfaces of the joint portion 52b and the facing portion E2a face each other.
  • the solder 92d is interposed between the plate surfaces of the joint portion 52b and the facing portion E2a.
  • the terminal arrangement surface (opposing surface) of the joint portion 52b is larger than the facing portion E2a in the projection view from the opposite direction, the flow of the solder joint portion 122 trying to flow farther in the joint portion 52b is strengthened. ..
  • the same problem occurs in the semiconductor device 11.
  • the current is locally concentrated in the solders 91d and 92d, for example, electromigration is a concern.
  • FIG. 36 is a cross-sectional view taken along the line XXXVII-XXXVII of FIG. In FIG. 37, the sealing resin bodies 21 and 22 are also shown. FIG. 37 corresponds to FIG. 5 of the prior embodiment.
  • the heat sink 51 of the semiconductor device 11 has a main body portion 51a and a joint portion 51b.
  • the two emitter terminals E1 have an opposing portion E1a and an extending portion E1b, respectively.
  • the facing portion E1a is arranged on the joint portion 51b so that the plate surfaces face each other.
  • the facing portion E1a is connected to the joint portion 51b via the solder 91d.
  • the extension portion E1b is connected to the facing portion E1a.
  • the extension portion E1b extends in the Y direction and away from the joint portion 51b. As shown in FIG.
  • the thickness tb1 is at least the thickness ta1 (tb1 ⁇ ta1) at least in the solder joint portion 121.
  • the thickness of the joint portion 51b is made substantially uniform over the entire area. Further, the thickness of the facing portion E1a is made substantially uniform over the entire area. The thickness tb1 of the facing portion E1a is thicker than the thickness ta1 of the joint portion 51b (tb1> ta1). The arrangement surface of the emitter terminal E1 in the joint portion 51b is made larger than that of the facing portion E1a.
  • the joint portion 51b has two convex portions 51c corresponding to the two facing portions E1a. The convex portion 51c projects in the Y direction and away from the main body portion 51a.
  • Arrangement regions 51d of the facing portion E1a are provided at both ends of the joint portion 51b in the X direction.
  • the region facing the collector terminal C1 is a non-arranged region 51e in which the facing portion E1a is not arranged.
  • the arrangement area 51d, the non-arrangement area 51e, and the arrangement area 51d are provided in this order.
  • the width Wa1 of the arrangement region 51d and the width of the convex portion 51c are the same.
  • the width Wa1 is the length in the X direction.
  • the width Wa1 is the length in the plate thickness direction of the joint portion 51b and in the direction orthogonal to the main flow direction of the current in the joint portion 51b.
  • the width Wa1 is a length in a direction orthogonal to the plate thickness direction and the extending direction of the joint portion 51b from the main body portion 51a.
  • a part of the arrangement region 51d in the Y direction, specifically, a portion away from the main body 51a forms a convex portion 51c.
  • Each of the arrangement regions 51d has a substantially rectangular shape in a plane. In the XY plane, the solder 91d is connected to the central portion of the arrangement region 51d, and the solder 91d is not connected to the peripheral portion surrounding the central portion.
  • Solder 91d is connected to a part of the facing portion E1a.
  • the junction portion is provided at one end of the emitter terminal E1 in the longitudinal direction.
  • the width Wb1 of the facing portion E1a is narrower than the width Wa1 of the arrangement region 51d of the joint portion 51b. That is, the width Wa1 is wider than the width Wb1 (Wa1> Wb1).
  • the width Wb1 is the length in the X direction including the joint portion.
  • the width Wb1 is a length in a direction orthogonal to the plate thickness direction and the longitudinal direction of the emitter terminal E1.
  • the heat sink 52 of the semiconductor device 12 has a main body portion 52a and a joint portion 52b.
  • One emitter terminal E2 has a facing portion E2a and an extending portion E2b, respectively.
  • the facing portion E2a is arranged on the joint portion 52b so that the plate surfaces face each other.
  • the facing portion E2a is connected to the joint portion 52b via the solder 92d.
  • the extension portion E2b is connected to the facing portion E2a.
  • the extension portion E2b extends in the Y direction and away from the joint portion 52b. As shown in FIG.
  • the thickness tb2 is at least the thickness ta2 (tb2 ⁇ ta2) at least in the solder joint portion 122.
  • the thickness of the joint portion 52b is made substantially uniform over the entire area. Further, the thickness of the facing portion E2a is made substantially uniform over the entire area. The thickness tb2 of the facing portion E2a is thicker than the thickness ta2 of the joint portion 52b (tb2> ta2). The arrangement surface of the emitter terminal E2 in the joint portion 52b is made larger than that of the facing portion E2a.
  • the joint portion 52b has one convex portion 52c corresponding to the facing portion E2a. The convex portion 52c projects in the Y direction and away from the main body portion 52a.
  • An arrangement area 52d of the facing portion E2a is provided at the center of the joint portion 52b in the X direction.
  • the region facing the collector terminal C2 is a non-arranged region 52e in which the facing portion E2a is not arranged.
  • the non-arranged area 52e, the arranged area 52d, and the non-arranged area 52e are provided in this order.
  • the width Wa2 of the arrangement region 52d and the width of the convex portion 52c are the same.
  • the width Wa2 is the length in the X direction.
  • the width Wa2 is the length in the plate thickness direction of the joint portion 52b and in the direction orthogonal to the main flow direction of the current in the joint portion 52b.
  • the width Wa2 is a length in a direction orthogonal to the plate thickness direction and the extending direction of the joint portion 52b with respect to the main body portion 52a.
  • a part of the arrangement region 52d in the Y direction, specifically, a portion away from the main body 52a forms a convex portion 52c.
  • the arrangement area 52d has a substantially rectangular shape in a plane. In the XY plane, the solder 92d is connected to the central portion of the arrangement region 52d, and the solder 92d is not connected to the peripheral portion surrounding the central portion.
  • Solder 92d is connected to a part of the facing portion E2a.
  • the junction portion is provided at one end of the emitter terminal E2 in the longitudinal direction.
  • the width Wb2 of the facing portion E2a is narrower than the width Wa2 of the arrangement region 52d of the joint portion 52b. That is, the width Wa2 is wider than the width Wb2 (Wa2> Wb2).
  • the width Wb2 is the length in the X direction including the joint portion.
  • the width Wb2 is a length in a direction orthogonal to the plate thickness direction and the longitudinal direction of the emitter terminal E2.
  • the thickness tb1 of the facing portion E1a is set to be equal to or larger than the thickness ta1 of the joint portion 51b. Since the current easily flows through the facing portion E1a as compared with the configuration in which the facing portion E1a is thinner than the joint portion 51b, it is possible to suppress the local concentration of the current in the solder 91d. Therefore, the reliability of the semiconductor device 11 can be improved. Similarly, the thickness tb2 of the facing portion E2a is set to be equal to or greater than the thickness ta2 of the joint portion 52b. Therefore, the reliability of the semiconductor device 12 can be improved.
  • the arrangement surface of the emitter terminal E1 in the joint portion 51b is made larger than that of the facing portion E1a.
  • the width Wa1 of the arrangement region 51d is wider than the width Wb1 of the facing portion E1a.
  • the reliability of the semiconductor device 11 can be improved by satisfying the above-mentioned relationship of tb1 ⁇ ta1.
  • the arrangement surface of the emitter terminal E2 in the joint portion 52b is made larger than that of the facing portion E2a.
  • the width Wa2 of the arrangement area 52d is wider than the width Wb2 of the facing portion E2a.
  • the semiconductor devices 11 and 12 are provided with a plurality of corresponding semiconductor elements 31 and 32.
  • a plurality of semiconductor elements 31 are connected to the same main body 51a via solders 91b and 91c.
  • the reliability of the semiconductor device 11 can be improved by satisfying the above-mentioned relationship of tb1 ⁇ ta1.
  • a plurality of semiconductor elements 32 are connected to the same main body 52a via solders 92b and 92c.
  • the reliability of the semiconductor device 12 can be improved by satisfying the above-mentioned relationship of tb2 ⁇ ta2.
  • the number of emitter terminals E2 is smaller than the number of semiconductor elements 32.
  • the number of emitter terminals E2 is smaller than the number of collector terminals C2.
  • the semiconductor device 12 includes two semiconductor elements 32 and one emitter terminal E2. As described above, the reliability of the semiconductor device 11 is improved by satisfying the above-mentioned relationship of tb1 ⁇ ta1 while having a configuration in which the current tends to be locally concentrated on the emitter terminal E2, that is, the solder 92d of the solder joint portion 122. can do.
  • the thickness of the facing portion E1a of the emitter terminal E1 is made thicker than the thickness of the collector terminal C1.
  • the thickness of the facing portion E2a of the emitter terminal E2 is made thicker than the thickness of the collector terminal C2.
  • FIG. 38 shows the model used in the simulation.
  • FIG. 39 shows the simulation results.
  • the periphery of the solder joint 122 of the semiconductor device 12 was simplified and used as a model.
  • the main flow of current is indicated by a solid arrow.
  • FIG. 38 (a) the main flow direction of the current flowing through the joint portion 52b and the main flow direction of the current flowing through the emitter terminal E2 are the same. That is, the angle ⁇ formed by the current is 0 °.
  • ⁇ is 90 °
  • FIG. 38 (c) ⁇ is 180 °.
  • the width of the solder joint portion 122 substantially coincides with the width Wb2 of the emitter terminal E2.
  • the width Wa2 was set to 13 mm and the width Wb2 was set to 10 mm. Further, the thickness ta2 of the joint portion 52b was set to 0.5 mm. Then, the thickness tb2 of the emitter terminal E2 was variously changed to obtain the maximum value of the current density at the solder joint portion 122.
  • the thickness tb2 is thicker than the thickness ta2 within a range of twice ⁇ having the lowest point as the apex. This range is represented by the following equation 7. (Equation 7) ta2 ⁇ tb2 ⁇ ta2 ⁇ ⁇ (2 ⁇ Wa2-Wb2) / Wb2 ⁇
  • the maximum value of the current density can be made smaller. That is, it is possible to effectively suppress the local concentration of the current in the solder joint portion 122.
  • the maximum value of the current density was shown at tb2 ⁇ ta2.
  • the thicker the thickness tb2 the smaller the maximum value of the current density.
  • the maximum value of the current density was shown at tb2 ⁇ ta2.
  • the thicker the thickness tb2 the smaller the maximum value of the current density.
  • the maximum value of the current density decreases as the thickness tb2 increases in the range of tb2 ⁇ ta2.
  • tb2> ta2 it is possible to effectively suppress the local concentration of the current. The same effect can be obtained with the semiconductor device 11.
  • the thicknesses of the opposing portions E1a and E2a of the emitter terminals E1 and E2 may be substantially equal to the thicknesses of the extending portions E1b and E2b.
  • the emitter terminals E1 and E2 may be configured to have the same total length and thickness.
  • the thickness of the facing portion E1a may be thicker than the thickness of the extending portion E1b.
  • the thickness of the extension portion E1b is thinner than the thickness ta1 of the joint portion 51b.
  • the facing portion E1a is thickened and the extending portion E1b is thinned.
  • the local concentration of the current can be suppressed without changing the connection condition with the bus bar or the like.
  • the cost can be reduced as compared with the configuration in which the total length has the same thickness. The same applies to the emitter terminal E2.
  • the semiconductor devices 11 and 12 according to the present embodiment are provided with at least a semiconductor element, a metal member having a main body portion and a joint portion electrically connected to the semiconductor element, and terminals solder-bonded to the joint portion. Good.
  • the semiconductor devices 11 and 12 are provided with two corresponding semiconductor elements 31 and 32, but the present invention is not limited to this. Only one semiconductor element 31 or 32 may be provided, or three or more semiconductor elements 31 or 32 may be provided. For example, as shown in FIG. 33, the four semiconductor elements 31 may be electrically connected to the same heat sinks 41 and 51.
  • the arrangement of the plurality of semiconductor elements 31 and 32 is not limited to the above example.
  • the configuration is not limited to the configuration in which all the semiconductor elements 31 and 32 are arranged side by side in the X direction. It can also be applied to a configuration in which a part of the semiconductor element 31 is arranged so as to be displaced in the Y direction with respect to the other semiconductor element 31. It can also be applied to a configuration in which a part of the semiconductor element 32 is arranged so as to be displaced in the Y direction with respect to the other semiconductor element 32.
  • the configuration shown in FIG. 34 may be used.
  • the semiconductor devices 11 and 12 include the sealing resin bodies 21 and 22, but the present invention is not limited to this.
  • the configuration may not include the sealing resin bodies 21 and 22.
  • the structures of the semiconductor devices 11 and 12 are not limited to the double-sided heat dissipation structure. It can also be applied to a single-sided heat dissipation structure. Further, the present invention is not limited to the switching element having a vertical structure, and can be applied to a switching element having a horizontal structure (for example, LDMOS).
  • the basic configurations of the semiconductor devices 11 and 12 of the present embodiment are the same as the configurations described in the preceding embodiments.
  • the semiconductor devices 11 and 12 include wiring members.
  • the wiring member is electrically connected to the semiconductor elements 31 and 32 to provide a wiring function.
  • the wiring member has a plurality of conductor portions and a joint portion formed between the two conductor portions.
  • the conductor portion includes at least one set of heat radiating portions arranged so as to sandwich the semiconductor elements 31 and 32, and a plurality of terminal portions connected to the heat radiating portion.
  • the heat sinks 41, 42, 51, 52 correspond to the heat radiating portion
  • the main terminals 71, 72 correspond to the terminal portions.
  • the solder joints 121 and 122 correspond to the joints
  • the solders 91d and 92d correspond to the joints.
  • the heat sinks 41, 42, 51, 52 and the main terminals 71, 72 correspond to the wiring members.
  • FIG. 41 shows the heat sinks 51 and 52 on the emitter side in the semiconductor devices 11 and 12 of the present embodiment.
  • FIG. 42 is an enlarged view of the heat sink 51.
  • FIG. 43 is a cross-sectional view of the semiconductor device 11 corresponding to the line XLIII-XLIII of FIG. 42.
  • the sealing resin body 21 is omitted for convenience.
  • the heat sinks 51 and 52 on the emitter side are provided with a structure for accommodating excess solder.
  • the heat sinks 51 and 52 correspond to the first conductor portion, and the emitter terminals E1 and E2 correspond to the second conductor portion.
  • the heat sink 51 has a low wet area 151a and a high wet area 151b on the surface facing the emitter terminal E1, that is, the mounting surface. In the plan views of FIGS. 41 and 42, hatching is applied to the low wet area for clarification.
  • the low wetting region 151a is a region having a lower wettability to solder than the high wetting region 151b.
  • the low-wetting region 151a is provided adjacent to the high-wetting region 151b, and the adjacency defines at least a part of the outer periphery of the high-wetting region 151b.
  • the low-wetting region 151a is a portion where the solder does not easily wet and spread at the time of joining, and the high-wetting region 151b is a portion where the solder easily wets and spreads.
  • the highly wet region 151b is a region connected to the overlapping region 151c, which is a region overlapping the junction forming region of the emitter terminal E1, and a region connected to the overlapping region 151c in a plan view in the Z direction, which is the plate thickness direction of the semiconductor element 31, and is an emitter. It has a non-overlapping region 151d, which is a region that does not overlap with the joint portion forming region of the terminal E1.
  • the junction forming region of the emitter terminal E1 is the facing portion E1a.
  • the solder 91d (not shown) is at least interposed between the facing regions E1a and the overlapping region 151c, and the joint 131 is mainly formed in the overlapping region 151c.
  • the highly wet region 151b including the overlapping region 151c and the non-overlapping region 151c is formed in the joint portion 51b of the heat sink 51.
  • the overlapping region 151c and the non-overlapping region 151c are surrounded by a low wetting region 151a.
  • the heat sink 52 forms a joint portion 121 with each of the two emitter terminals E1.
  • the heat sink 52 has two overlapping regions 151c.
  • Each of the overlapping regions 151c has a substantially rectangular shape with the X direction as the longitudinal direction.
  • the two overlapping regions 151c are aligned in the X direction.
  • the non-overlapping region 151d includes at least the accommodation region 151e.
  • the accommodating region 151e is connected to the overlapping region 151c and is a highly wet region 151b accommodating the excess solder 91d with respect to the joint portion 121.
  • the accommodation area 151e of the present embodiment is connected to two overlapping areas 151c. In the alignment direction of the two overlapping regions 151c, one end of the accommodating region 151e is connected to one of the overlapping regions 151c, and the other end of the accommodating region 151e is connected to the other one of the overlapping regions 151c.
  • one accommodation region 151e is provided as a common region with respect to the two overlapping regions 151c.
  • the non-overlapping region 151d further includes a fillet forming region 151f.
  • the fillet forming region 151f is also a highly wet region 151b connected to the overlapping region 151c.
  • the fillet forming region 151f is a region narrower than the accommodating region 151e provided so that the fillet of the solder 91d can be formed.
  • the fillet forming region 151f corresponds to a narrow region.
  • the accommodating area 151e is connected to one side of the overlapping area 151c, and the fillet forming area 151f is connected to the remaining three sides of the overlapping area 151c.
  • the fillet forming region 151f is connected to both sides in the Y direction and the outer side in the X direction, and the accommodating region 151e is connected to the inner side in the X direction.
  • the inside in the X direction is the opposite side of the two overlapping regions 151c, and the outside is the non-opposite side. In this way, the non-overlapping region 151d surrounds the overlapping region 151c.
  • the low-wetting region 151a is adjacent to the non-overlapping region 151d on the entire circumference so as to define the outer circumference of the non-overlapping region 151d.
  • the low-wetting region 151a is adjacent to the outer peripheral portion of the high-wetting region 151b in the accommodation region 151e over the entire area.
  • the highly wet region 151b including the two overlapping regions 151c and the accommodating region 151e is provided in a straight line along the X direction.
  • the width of the non-overlapping region 151d is the length in the direction in which the non-overlapping region 151d is connected to the overlapping region 151c, that is, in the alignment direction with the overlapping region 151c.
  • the width of the accommodation area 151e is the length in the X direction.
  • the width of the portions arranged in the X direction with respect to the overlapping region 151f is the length in the X direction.
  • the fillet forming region 151f has a width sufficient to form a fillet.
  • the accommodating region 151e has a sufficiently wide width as compared with the width of the fillet forming region 151f.
  • the accommodating region 151e has a width capable of accommodating a surplus portion of the solder 91d when the facing distance between the overlapping region 151c and the facing portion E1a is the narrowest in order to absorb the height variation of the semiconductor device 11.
  • the accommodating region 151e has a width capable of accommodating a surplus with respect to the joint portion 121 of the two overlapping regions 151c.
  • the heat sink 51 has a high wet area 151 g in addition to the high wet area 151 b described above.
  • the highly wet region 151b has an overlapping region 151h, which is a region where the terminals 61 overlap in a plan view, and a non-overlapping region 151i, which is a region continuous with the overlapping region 151h and is a region where the terminals 61 do not overlap.
  • the heat sink 51 has two highly wet areas 151 g corresponding to each of the two terminals 61 (semiconductor element 31).
  • the non-overlapping region 151i includes the accommodating region 151j and the fillet forming region 151k, similarly to the non-overlapping region 151d.
  • the accommodating area 151j is connected to the overlapping area 151h and accommodates the solder 91c overflowing from the area facing the overlapping area 151h and the terminal 61.
  • the accommodating region 151j is connected to one side of the overlapping region 151h forming a substantially rectangular plane, and the fillet forming region 151k is connected to the remaining three sides of the overlapping region 151h.
  • the fillet forming region 151k is connected to both sides in the X direction and one side in the Y direction, and the accommodating region 151j is connected to the remaining side in the Y direction.
  • the non-overlapping region 151i surrounds the overlapping region 151h.
  • the low wetting region 151a is adjacent to the non-overlapping region 151i on the entire circumference so as to define the outer circumference of the non-overlapping region 151i.
  • the low-wetting region 151a is adjacent to the outer peripheral portion of the high-wetting region 151b in the accommodation region 151j over the entire area.
  • the two highly wet areas 151 g each have a substantially rectangular shape in a plane.
  • the fillet forming region 151k is a region narrower than the accommodating region 151j.
  • the fillet forming region 151k has a width sufficient to form a fillet.
  • the accommodating region 151j has a sufficiently wide width as compared with the width of the fillet forming region 151k.
  • the accommodating region 151j has a width capable of accommodating a surplus portion of the solder 91c when the facing distance between the overlapping region 151h and the terminal 61 is the narrowest in order to absorb the height variation of the semiconductor device 11.
  • the low-wetting region 151a is provided on the entire surface of the mounting surface of the heat sink 51 except for the high-wetting region 151b and the two high-wetting regions 151g. Since the heat sink 52 has the same configuration as the heat sink 51, detailed description thereof will be omitted.
  • the heat sink 52 also has a low wet area 152a and high wet areas 152b and 152 g.
  • the low-wetting region 152a is provided on the entire surface of the portion excluding the high-wetting regions 152b and 152g.
  • the highly wetted region 152b includes an overlapping region 152c and a non-overlapping region 152d.
  • the highly wetted region 152g includes an overlapping region 152h and a non-overlapping region 152i.
  • the non-overlapping regions 152d and 152i include accommodating regions 152e and 152j (not shown) and fillet forming regions 152f and 152k.
  • the heat sink 52 has the same shape (common component) as the heat sink 51, and the patterning of the low wettability regions 151a and 152a is also the same. Unlike the heat sink 51, the heat sink 52 has only one overlapping region 152c with the facing portion E2a of the emitter terminal E2. The overlapping region 152c is provided near the center of the highly wet region 152b extending along the X direction.
  • FIG. 44 is an enlarged view of the region XLIV of FIG. 43.
  • the solder 91d is omitted for convenience.
  • the heat sink 51 will be described as an example.
  • the heat sink 51 has a base material 160 containing a metal, a metal film 161 provided on the surface of the base material 160, and an uneven oxide film 162.
  • the base material 160 forms a main part of the heat sink 51.
  • the base material 160 is formed by using a Cu-based material.
  • the metal film 161 is formed by including a material having a higher wettability to solder than the base material 160.
  • the metal film 161 is formed over the entire mounting surface of the heat sink 51.
  • the uneven oxide film 162 is locally formed on the mounting surface.
  • the uneven oxide film 162 is locally formed on the metal film 161 by irradiating the metal film 161 with a laser beam.
  • the metal film 161 is provided on the entire surface of the base material 160 except for the exposed surface, for example.
  • the metal film 161 has a base film containing Ni (nickel) as a main component and an upper ground film containing Au (gold) as a main component.
  • an electroless Ni plating film containing P (phosphorus) is used as the base film.
  • the upper ground film (Au) of the portion in contact with the solder diffuses into the solder during reflow.
  • the upper ground film (Au) of the portion of the metal film 161 on which the concave-convex oxide film 162 is formed is removed by irradiation with a laser beam when the concave-convex oxide film 162 is formed.
  • the concave-convex oxide film 162 is an oxide film containing Ni as a main component.
  • 80% is NI 2 O 3
  • 10% is NiO
  • 10% is Ni.
  • the uneven oxide film 162 is formed in the low wetting region 151a on the mounting surface of the heat sink 51.
  • the uneven oxide film 162 is not formed in the highly wet areas 151b and 151g.
  • the concave-convex oxide film 162 provides a low wetting region 151a.
  • the metal film 161 exposed from the concavo-convex oxide film 162 provides highly wet areas 151b and 151g.
  • Reference numeral 161a shown in FIG. 44 is a recess formed on the surface of the metal film 161.
  • the recess 161a is formed by irradiating a pulsed laser beam. One recess 161a is formed for each pulse.
  • the uneven oxide film 162 is formed by melting, vaporizing, and depositing the surface layer portion of the metal film 161 by irradiation with a laser beam.
  • the uneven oxide film 162 is an oxide film derived from the metal film 161.
  • the concave-convex oxide film 162 is a film of an oxide of a metal (Ni) as a main component of the metal film 161.
  • the uneven oxide film 162 is formed following the unevenness of the surface of the metal film 161 having the concave portions 161a. On the surface of the uneven oxide film 162, unevenness is formed at a pitch finer than the width of the concave portion 161a. That is, very fine unevenness (roughened portion) is formed.
  • the uneven oxide film 162 can be formed by, for example, the following manufacturing method. First, electroless Ni plating containing P (phosphorus) is applied to the base material 160, and then Au plating is applied to obtain a metal film 161. After the metal film 161 is formed, the mounting surface is irradiated with a pulsed laser beam to melt and evaporate the surface of the metal film 161.
  • Pulsed laser light energy density is large 100 J / cm 2 or less than 0 J / cm 2, the pulse width is adjusted to be equal to or less than 1 ⁇ seconds.
  • a YAG laser, YVO 4 laser such as a fiber laser with.
  • the energy density may be 1 J / cm 2 or more.
  • the metal film 161 can be processed even at about 5 J / cm 2, for example.
  • the laser light is irradiated to a plurality of positions in order.
  • a recess 161a is formed on the surface of the metal film 161.
  • the average thickness of the portion of the metal film 161 irradiated with the laser beam is thinner than the average thickness of the portion not irradiated with the laser beam.
  • the plurality of recesses 161a formed corresponding to the spots of the laser beam are continuous and form, for example, a scale.
  • the portion of the molten metal film 161 is solidified. Specifically, the molten and vaporized metal film 161 is vapor-deposited on the portion irradiated with the laser beam and the peripheral portion thereof. By depositing the molten and vaporized metal film 161 in this way, the uneven oxide film 162 is formed on the surface of the metal film 161. This makes it possible to prepare a heat sink 51 having a low wetting region 151a formed by the concave-convex oxide film 162 and a high-wetting region 151b and 151 g formed by the metal film 161 exposed from the concave-convex oxide film 162.
  • the heat sink 52 also has the same configuration as the heat sink 51.
  • the same manufacturing method as the heat sink 51 it is possible to prepare a heat sink 52 having a low wet area 152a formed by the uneven oxide film 162 and high wet areas 152b and 152 g formed by the metal film 161 exposed from the uneven oxide film 162.
  • the semiconductor devices 11 and 12 having the double-sided heat dissipation structure are sandwiched by the cooler from both sides in the Z direction. Therefore, high parallelism of the surfaces and high dimensional accuracy between the surfaces are required in the Z direction. Therefore, for the solders 91d and 92d, an amount capable of absorbing the height variation of the semiconductor devices 11 and 12 is arranged. That is, a large amount of solder 91d and 92d are arranged. Then, at the time of 2nd reflow, a load is applied in the Z direction so that the heights of the semiconductor devices 11 and 12 become predetermined heights. The solders 91d and 92d absorb height variations due to dimensional tolerances and assembly tolerances of the elements constituting the semiconductor devices 11 and 12.
  • the total amount of the solder 91d is required to make the height of the semiconductor device 11 a predetermined height
  • the total amount of the solder 91d is in the facing region of the facing portion E1a and the overlapping region 151c, and the capillary phenomenon and the surface surface. It stays due to tension.
  • an external force exceeding the force held between the facing regions such as capillary action and surface tension is applied, so that a part of the solder 91d is removed from the facing region. Overflow.
  • the accommodating area 151e which is the highly wet area 151b, is connected to the overlapping area 151c. Therefore, the excess solder 91d tends to wet and spread from the overlapping region 151c to the accommodating region 151e as shown by the white arrows in FIG. 45.
  • the white arrows in FIG. 45 indicate the flow direction (overflow direction) of the excess solder.
  • the excess solder 91d is restricted from spreading by the low wetting region 151a.
  • the low wet area 151a adjacent to the high wet area 151b promotes the wet spread to the accommodation area 151e and / or suppresses the wet spread to the outside of the accommodation area 151e. From the above, as shown in FIG.
  • FIG. 46 is a cross-sectional view of the semiconductor device 11 corresponding to the XLVI-XLVI line of FIG. 42.
  • FIG. 46 shows a state in which the solder 91d has overflowed.
  • the excess solder 92d can be accommodated in the accommodating area 152e without providing the groove.
  • FIG. 47 is a cross-sectional view of the semiconductor device 11 corresponding to the XLVII-XLVII line of FIG. 42.
  • the sealing resin body 21 is omitted for convenience.
  • FIG. 47 shows this example (an example of this embodiment) and a reference example. Since the potentials of the heat sink 51 and the collector terminal C1 are different, it is necessary to secure a predetermined insulation distance DI in the sealing resin body 21 between them. When the bent portion of the collector terminal C1 is moved away from the heat sink 51 in the Y direction, the insulation distance DI can be secured, but on the other hand, the physique of the sealing resin body 21 and the physique of the semiconductor device 11 become large. Therefore, it is preferable to arrange the collector terminal C1 so that the distance between the bent portion and the end portion of the heat sink 51 (joint portion 51b) is the insulation distance DI.
  • the clearance from the end portion of the heat sink 51 to the overlapping region 151c becomes CL1.
  • the clearance up to the overlapping region 151cr is CL2.
  • Clearance CL2 is longer than clearance CL1.
  • the clearance CL1 is, for example, about half the length of the clearance CL2. Therefore, according to the present embodiment, it is possible to reduce the size of the semiconductor device 11 in the extending direction of the emitter terminal E1 while ensuring the insulation distance DI.
  • the semiconductor device 12 (heat sink 52) has the same configuration as the semiconductor device 11 (heat sink 51).
  • the elements that are the same as or related to the elements of the present embodiment are shown by adding r to the end of the reference numerals of the present embodiment. The same applies to the following reference examples.
  • the accommodating area 151e overlaps and is connected to only a part of the overlapping area 151c.
  • the low-wetting region 151a is adjacent to the outer periphery of the high-wetting region 151b on both sides in the Y direction orthogonal to the arrangement direction (X direction) of the overlapping region 151c and the accommodating region 151e, and sandwiches the overlapping region 151c and the accommodating region 151e. I'm out.
  • the low wetting regions 151a located on both sides function as a guide for the flow of excess solder 91d.
  • the excess solder 91d easily wets and spreads from the overlapping region 151c to the accommodating region 151e. Further, the low wetting regions 151a on both sides make it easy to hold the excess solder 91d in the accommodating region 151e. The same applies to the heat sink 52.
  • the low wet area 151a is adjacent to the outer peripheral portion of the high wet area 151b in the accommodation area 151e over the entire area.
  • the solder 91d it is possible to prevent the solder 91d from getting wet and spreading outside the accommodation area 151e. That is, the surplus solder 91d can be more reliably held in the accommodating area 151e.
  • the heat sink 52 the same applies to the heat sink 52.
  • the low wet area 151a is adjacent to the outer periphery of the high wet area 151b over the entire area.
  • the excess solder 91d is surely wetted and spread in the accommodating area 151e and is held in the accommodating area 151e.
  • FIG. 48 shows a reference example.
  • grooves 151r and 152r for accommodating excess solder are provided in the joint portions 51br and 52br of the heat sinks 51r and 52r.
  • the heat sink 51r has grooves 151r near both ends of the joint portion 51br in the X direction.
  • the heat sink 52r has a groove 151 near the center of the joint portion 52br in the X direction. Therefore, the heat sinks 51r and 52r cannot be shared.
  • the heat sinks 51 and 52 have the same shape, and the wet patterns of the low wet areas 151a and 152a and the high wet areas 151b and 152b are also the same. That is, the irradiation pattern of the laser beam forming the concave-convex oxide film 162 is also the same.
  • the semiconductor device 11 in the highly wet region 151b, the vicinity of both ends is the overlapping region 151c, and the space between the two overlapping regions 151c is the accommodating region 151e.
  • the semiconductor device 12 in the highly wet region 152b, the vicinity of the center is the overlapping region 152c, and both sides are the accommodation regions 152e.
  • the metal film 161 having high wettability to solder is locally irradiated with a laser beam to provide an uneven oxide film 162 to form low wettability regions 151a and 152a.
  • the oxide film (concave and convex oxide film 162) has lower wettability to solder than the metal film 161. Further, since the surface has fine irregularities, the contact area with the solder becomes small, and a part of the solder becomes spherical due to surface tension. That is, the contact angle becomes large. Therefore, the wettability to the solder is low. From the above, the uneven oxide film 162 is suitable for the low wetting regions 151a and 152a. Since the laser beam is used, patterning of the low-wetting regions 151a and 152a and the high-wetting regions 151b and 152b is easy.
  • a groove for accommodating the excess solder 91c and 92c may be provided in the portion forming the solder joint portions 131 and 132. If the arrangements of the semiconductor elements 31 and 32 are the same in the semiconductor devices 11 and 12, the shape and arrangement of the grooves can be the same. In the present embodiment, the same excess solder accommodating structure as the solder joints 121 and 122 is applied to the portions forming the solder joints 131 and 132. Therefore, the surplus solders 91c and 92c can be accommodated in the accommodating areas 151j and 152j without providing the grooves. In the heat sinks 51 and 52, the press working to form the groove can be completely eliminated.
  • the non-overlapping region 151d may include at least the accommodation region 151e.
  • the heat sink 51 may have a configuration in which the fillet forming region 151f is excluded from the non-overlapping region 151d.
  • the highly wetted region 151b has only an overlapping region 151c and an accommodating region 151e. Even with such a configuration, the same effect as that of the above embodiment can be obtained.
  • the highly wet region 151g on the terminal 61 side also has a configuration in which the fillet forming region 151k is similarly excluded. The same applies to the heat sink 52.
  • the low wet area 151a may be adjacent to at least a part of the high wet area 151b. As shown in FIG. 50, the low wetting region 151a may be provided only on both sides in the Y direction orthogonal to the alignment direction (X direction) of the overlapping region 151c and the accommodating region 151e. The low wetting region 151a extends over the overlapping region 151c and the accommodating region 151e on both sides in the Y direction, sandwiching the overlapping region 151c and the accommodating region 151e. In FIG. 50, as in FIG. 49, the low wetting region 151a is continuously adjacent to the overlapping region 151c and the accommodating region 151e. The same applies to the heat sink 52.
  • FIG. 52 is a cross-sectional view of the semiconductor device 11 corresponding to the LII-LII line of FIG. 51, and shows a state in which the solder 91d overflows as in FIG. 46. According to this modification, the patterns of the low-wetting region and the high-wetting region are different between the heat sinks 51 and 52.
  • the same effect as the above-described configuration can be obtained.
  • the heat sinks 51 and 52 having the same shape can be used because the irradiation pattern of the laser beam may be switched.
  • the accommodation area 151e may be connected to at least a part of the overlapping area 151c.
  • An example is shown in which the accommodation region 151e is connected to only one of the four sides of the overlapping region 151c, but the present invention is not limited to this.
  • the accommodation region 151e may be provided so as to be continuous with the two sides of the overlapping region 151c forming a substantially rectangular plane. According to this, the excess solder 91d can be released to the inside in the X direction and one side in the Y direction. The volume for accommodating the excess solder 91d can be increased.
  • the accommodating area 151e may be connected to the three sides of the overlapping area 151c.
  • the accommodating area 151e may be connected to the four sides of the overlapping area 151c.
  • the accommodating area 151e may be provided in an annular shape so as to surround the overlapping area 151c.
  • the accommodating area 151e forms the entire outer circumference of the highly wet area 151b.
  • the accommodation regions 151e connected to different sides with respect to the common overlapping region 151c may be separated from each other. The same applies to the heat sink 52.
  • a concave-convex oxide film 162 may be provided on the side surface of the facing portion E1a of the emitter terminal E1.
  • the uneven oxide film 162 forms a low wetting region. Therefore, it is possible to prevent the solder 91d from spreading on the side surface side of the emitter terminal E1.
  • the high wetting region 151b may be defined by the low wetting region 151a provided on the mounting surface and the side surface of the heat sink 51.
  • the mounting surface can be widely utilized as the high-wetting region 151b. Therefore, it is possible to reduce the size of the heat sink 51.
  • FIG. 54 shows an example in which the concave-convex oxide film 162 is provided on each of the side surface of the emitter terminal E1 and the side surface of the heat sink 51, only one of them may be provided. The same applies to the heat sink 52.
  • the number of semiconductor elements sandwiched by a set of heat radiating parts is not particularly limited.
  • the above-mentioned excess solder accommodating structure can be applied to a configuration in which only one semiconductor element 31 is arranged between the heat sinks 41 and 51 and only one semiconductor element 32 is arranged between the heat sinks 42 and 52. .. It can also be applied to a configuration in which three or more semiconductor elements 31 and 32 are arranged.
  • the above-mentioned structure for accommodating excess solder is not limited to the semiconductor device 11 constituting the upper arm 7U and the semiconductor device 12 constituting the lower arm 7L. That is, the application is not limited to the semiconductor device constituting one arm.
  • FIGS. 55, 56, and 57 it may be applied to a semiconductor device 10A provided with semiconductor elements 31 and 32 constituting the upper and lower arms 7.
  • One semiconductor device 10A constitutes an upper and lower arm 7 for one phase.
  • the sealing resin body 20 is omitted from the semiconductor device 10A shown in FIG. 55.
  • FIG. 57 is a cross-sectional view taken along the line LVII-LVII of FIG. 55.
  • the semiconductor device 10A includes a semiconductor element 31 on the upper arm 7U side and a semiconductor element 32 on the lower arm 7L side.
  • a heat sink 41 is solder-bonded to the collector electrode 31c of the semiconductor element 31.
  • a heat sink 51 is solder-bonded to the emitter electrode 31e of the semiconductor element 31 via the terminal 61.
  • a heat sink 42 is solder-bonded to the collector electrode 32c of the semiconductor element 32.
  • a heat sink 52 is solder-bonded to the emitter electrode 32e of the semiconductor element 31 via the terminal 62.
  • the heat sink 42 has a main body portion to which the semiconductor element 32 is connected and a joint portion 42e connected to the main body portion.
  • the heat sink 51 has a main body portion to which the semiconductor element 31 is connected and a joint portion 51f connected to the main body portion.
  • the joint portions 42e and 51f are arranged so as to face each other in the Z direction, and are connected via the solder 93.
  • the heat sink 52 has a joint portion 52b.
  • the sealing resin body 20 has one surface 20a and a back surface 20b which is the opposite surface to the one surface 20a in the Z direction.
  • the heat sinks 41 and 42 are exposed from the sealing resin body 20 with the heat radiating surface opposite to the mounting surface substantially flush with the surface 20a.
  • the heat sinks 51 and 52 are exposed from the sealing resin body 20 with the heat radiating surface opposite to the mounting surface substantially flush with the back surface 20b.
  • the semiconductor device 10A has one collector terminal C1, one emitter terminal E2, and one output terminal OP1 as main terminals 70.
  • the collector terminal C1 is connected to the heat sink 41, and the output terminal OP1 is connected to the heat sink 42.
  • the emitter terminal E2 is solder-bonded to the joint portion 52b of the heat sink 52.
  • low wettability regions 151a and 152a are locally provided on the mounting surface.
  • the low wetting region 151a is also provided in the joint portion 51f.
  • the joint portion 51f has a low wetting region 151a and a high wetting region 151b on the surface on the mounting surface side.
  • the highly wet region 151b has an overlapping region 151c with the joint portion 42e and an accommodating region 151e.
  • the low-wetting region 151a surrounds the high-wetting region 151b and defines the outer circumference of the high-wetting region 151b.
  • the excess solder 93 overflowing from the facing regions of the joints 42e and 51f wets and spreads from the overlapping region 151c to the accommodation region 151e in order to absorb the height variation. Then, the excess solder 93 is held in the accommodating area 151e.
  • the joint portions 42e and 51f are terminal portions provided in the semiconductor device 10A. In this way, it can also be applied to a joint portion between terminal portions that electrically connects the upper arm 7U and the lower arm 7L.
  • the above-mentioned structure for accommodating excess solder can also be applied to the solder joint portion between the emitter terminal E2 and the heat sink 52 (joint portion 52b).
  • 55 to 57 show an example in which joint portions 42e and 51f are provided on the heat sinks 42 and 51, respectively, and the joint portions 42e and 51f are solder-bonded to each other, but the present invention is not limited to this.
  • the above-mentioned structure for accommodating excess solder may be applied in a configuration in which a joint portion (terminal portion) is provided only on one of the heat sinks 42 and 51.
  • a plurality of semiconductor elements 31 may be arranged in parallel with each other between the heat sinks 41 and 51.
  • the above-mentioned structure for accommodating excess solder may be applied to the solder joints of the heat sinks 51 and 52 with the terminals 61 and 62. The same applies to the semiconductor element 32.
  • heat sinks 41, 42, 51, and 52 are shown as wiring members that are electrically connected to the semiconductor elements 31, 32, but the present invention is not limited to these.
  • a wiring board in which a conductor made of Cu or the like is arranged as an insulator such as ceramics may be adopted.
  • the semiconductor device 10A shown in FIGS. 58 and 59 includes wiring boards 40 and 50 arranged so as to sandwich the semiconductor elements 31 and 32. DBC (Direct Bonded Copper) boards are used as the wiring boards 40 and 50.
  • the wiring boards 40 and 50 have insulators 40a and 50a and conductors 40b and 50b.
  • the conductors 40b and 50b are arranged on at least the surface (mounting surface) on the semiconductor elements 31 and 32 side in the Z direction, in other words, in the plate thickness direction of the insulator. Here, it is also arranged on the back surface of the mounting surface.
  • FIG. 59 is a plan view of FIG. 58 as viewed from the X4 direction, and the periphery of the solder joint portion between the main terminal and the wiring board is enlarged.
  • the wiring board 40 has a plurality of electrically separated conductors 40b on the mounting surface.
  • the collector electrode 31c of the semiconductor element 31 is connected to one of the conductors 40b, and the collector electrode 32c of the semiconductor element 32 is connected to the other one of the conductors 40b.
  • the wiring board 50 also has a plurality of electrically separated conductors 50b on the mounting surface.
  • the emitter electrode 31e of the semiconductor element 31 is electrically connected to one of the conductors 50b, and the emitter electrode 32e of the semiconductor element 32 is electrically connected to the other conductor 50b.
  • a solder joint portion 123 is formed between the collector terminal C1 and the conductor 40b to which the semiconductor element 31 is connected.
  • a solder joint portion 124 is formed between the output terminal OP1 and the conductor 40b to which the semiconductor element 32 is connected.
  • a solder joint portion 122 is formed between the emitter terminal E2 and the conductor 50b to which the semiconductor element 32 is connected.
  • a solder joint 125 is formed between the conductor 50b to which the semiconductor element 31 is connected and the conductor 40b to which the semiconductor element 32 is connected.
  • the semiconductor device 10A has four solder joints 122 to 125 as joints formed between the two conductors.
  • FIG. 60 is a plan view showing the periphery of the solder joint portion 124.
  • the conductor 40b of the wiring board 40 has a low wetting region 142a and a high wetting region 142b on the mounting surface.
  • the low-wetting region 142a corresponds to the low-wetting regions 151a and 152a shown above, and the high-wetting region 142b corresponds to the high-wetting regions 151b and 152b.
  • the highly wetted region 142b has an overlapping region 142c that overlaps with the joint forming region of the output terminal OP1 and a non-overlapping region 142d that is continuous with the overlapping region 142c.
  • the non-overlapping region 142d includes only the containment region 142e.
  • the accommodating region 142a is continuous with only one side of the overlapping region 142c forming a substantially rectangular plane.
  • the low-wetting region 142a surrounds the overlapping region 142c and the accommodating region 142e, and is adjacent to the outer periphery of the high-wetting region 142b over the entire area.
  • the excess solder wets and spreads from the overlapping region 142c to the accommodating region 142e and is held in the accommodating region 142e.
  • solder joint portion 124 Although an example of applying the above-mentioned excess solder accommodating structure to the solder joint portion 124 has been shown, it can also be applied to other solder joint portions 122, 123, 125.
  • the above-mentioned excess solder accommodating structure may be applied to all four solder joints 122 to 125, or may be applied to at least one of the four solder joints 122 to 125.
  • wiring boards 40 and 50 such as a DBC board may be used in the semiconductor device (for example, semiconductor devices 11 and 12) constituting one arm.
  • wiring boards 40, 50 such as a DBC board may be used instead of the heat sinks 41, 42, 51, 52.
  • As a wiring member a combination of a heat sink and a wiring board is also possible.
  • the present invention is not limited to this.
  • the high-wetting regions 142b, 151b, 152b may be masked and then subjected to thermal oxidation treatment to provide an oxide film on the low-wetting regions 142a, 151a, 152a.
  • the portion provided with the oxide film has lower wettability with respect to the bonding material (solder) than the portion not provided with the oxide film.
  • the resin-deposited portions may be designated as low-wetting regions 142a, 151a, 152a, and the non-deposited portions may be designated as high-wetting regions 142b, 151b, 152b.
  • the adhesion to the sealing resin bodies 20, 21 and 22 can be improved by the primer effect.
  • an inorganic material having low wettability to solder a material that repels solder
  • the rough-plated portion may be the low-wetting region 142a, 151a, 152a
  • the non-rough-plated portion may be the high-wetting region 142b, 151b, 152b.
  • the low-wetting regions 142a, 151a, 152a are selectively treated to provide a film having low wettability, but the high-wetting regions 142b, 151b, 152b may be selectively treated. ..
  • a film having high wettability to the bonding material (for example, a plating film) may be formed in the high wetting areas 142b, 151b, 152b of the mounting surface, and a film having high wettability may not be formed in the low wetting areas 142a, 151a, 152a. ..
  • the bonding material is not limited to solder. Sintered bonding materials such as Ag and Cu, and conductive adhesives such as Ag paste may be used.
  • FIG. 61 shows the semiconductor device 11 of this embodiment.
  • FIG. 61 corresponds to FIG.
  • the basic configuration of the semiconductor device 11 is the same as the configuration described in the prior embodiment.
  • the semiconductor device 11 includes two semiconductor elements 31 (31a, 31b) arranged side by side in the X direction.
  • the semiconductor element 31 has five pads 31p on the forming surface of the emitter electrode 31e (not shown).
  • the five pads 31p are arranged along the X direction.
  • the semiconductor element 31 includes, as pads 31p, a cathode pad P1 for the cathode potential of the temperature-sensitive diode, an anode pad P2 for the anode potential, a gate pad P3 for the gate electrode, a current sense pad P4 for the current sense, and an emitter electrode 31e.
  • Each has a Kelvin emitter pad P5 for detecting the potential of the above.
  • the pads 31p of the semiconductor element 31a on which the switching element Q1a is formed are arranged in the order of the cathode pad P1, the anode pad P2, the gate pad P3, the current sense pad P4, and the Kelvin emitter pad P5 when viewed from the X5 direction.
  • the pads 31p of the semiconductor element 31b on which the switching element Q1b is formed are arranged in the order of the Kelvin emitter pad P5, the current sense pad P4, the gate pad P3, the anode pad P2, and the cathode pad P1 when viewed from the X5 direction.
  • the arrow of the alternate long and short dash line shown in FIG. 61 indicates the path of the current (main current) flowing through the main terminal 71.
  • the main current path is formed between the collector terminal C1 and the emitter terminal E1 via the semiconductor element 31.
  • the solid arrow indicates the path of the current (signal current) flowing through the signal terminal 81.
  • the signal current path is formed between the signal terminal 81 connected to the gate pad P3 and the signal terminal 81 connected to the Kelvin emitter pad P5 via the semiconductor element 31.
  • the circuit through which the main current flows and the circuit through which the signal current flows are magnetically coupled.
  • the two semiconductor elements 31a and 31b are arranged line-symmetrically with respect to the axis AX1. Further, the collector terminal C1 and the emitter terminal E1 are arranged line-symmetrically with the axis AX1 as the axis of symmetry. Therefore, the path of the main current on the semiconductor element 31a side and the path of the main current on the semiconductor element 31b side are substantially axisymmetric with the axis AX1 as the axis of symmetry.
  • the arrangement order of the pads 31p in the two semiconductor elements 31 is line-symmetrical with respect to the axis AX1.
  • the signal terminal 81 is also line-symmetrically arranged with respect to the axis AX1. Therefore, the signal current path on the semiconductor element 31a side and the signal current path on the semiconductor element 31b side are substantially axisymmetric with the axis AX1 as the axis of symmetry. Therefore, the magnetic coupling is also substantially line-symmetrical between the semiconductor element 31a side and the semiconductor element 31b side.
  • the pads 31p are arranged in the same order in the two semiconductor elements 31a and 31b, the magnetic coupling becomes asymmetric.
  • the symmetry of the magnetic coupling of the signal current circuit that is, the symmetry of the mutual inductance is also taken into consideration, so that the imbalance of the AC current can be suppressed more effectively.
  • the wiring member is characterized by the shape of the heat radiating portion arranged so as to sandwich the semiconductor element.
  • the shape of the heat dissipation part is devised to increase the wiring inductance on the emitter side.
  • FIG. 62 is an equivalent circuit diagram of the semiconductor device 12 constituting the lower arm 7L.
  • the semiconductor device 12 includes two semiconductor elements 32 (32a, 32b) as in the previous embodiment.
  • the wiring inductance Le21 exists between the semiconductor element 32a and the emitter terminal E2
  • the wiring inductance Le22 exists between the semiconductor element 32b and the emitter terminal E2. Therefore, the emitter potential fluctuates (rises) during switching, that is, when AC current flows.
  • the switching speed of the switching element Q2a is dI1 / dt
  • the switching speed of the switching element Q2b is dI2 / dt.
  • the amount of fluctuation ⁇ Ve of the emitter potential at the time of switching is equal to the multiplication value of the switching speed and the wiring inductance.
  • the wiring inductances Le21 and Le22 are equal to each other. Due to the deviation of the switching speeds dI1 / dt and dI2 / dt, there is a difference in the fluctuation amount ⁇ Ve. When the values of the wiring inductances Le21 and Le22 are large, the difference in the fluctuation amount ⁇ Ve becomes large, which affects the gate voltage Vge. For example, when dI1 / dt> dI2 / dt, the fluctuation amount ⁇ Ve1 becomes larger than the fluctuation amount ⁇ Ve2, and the gate voltage Vge1 becomes lower than the gate voltage Vge2. In this way, the gate voltage Vge shifts to the side that suppresses the imbalance (bias) of the AC current. Therefore, the imbalance of AC current can be suppressed.
  • the value of the fluctuation amount ⁇ Ve becomes small. Therefore, even if the switching speeds dI1 / dt and dI2 / dt deviate from each other, the difference between the fluctuation amounts ⁇ Ve1 and ⁇ Ve2 is small. Therefore, the effect of suppressing imbalance due to the wiring inductance is weakened. In other words, if the values of the wiring inductances Le21 and Le22 are small, the AC current is likely to be unbalanced due to the deviation of the switching speeds dI1 / dt and dI2 / dt, that is, the difference in element characteristics.
  • FIG. 63 shows the heat sink 52 and the emitter terminal E2 on the emitter side in the semiconductor device 12 according to the present embodiment.
  • FIG. 64 shows the heat sink 42 and the collector terminal C2 on the collector side.
  • the configuration of the collector terminal C2 and the emitter terminal E2 is the same as the configuration described in the prior embodiment (see, for example, FIG. 12).
  • the arrangement of the two semiconductor elements 32 is the same.
  • the basic configuration of the heat sinks 42 and 52 is the same.
  • the heat sink 52 of this embodiment has slits 52s.
  • the slit 52s penetrates the heat sink 52 in the Z direction and divides the main body 52a into two islands 52i.
  • One of the islands 52i is a mounting area for the semiconductor element 32a.
  • the other one of the islands 52i is a mounting area for the semiconductor element 32b.
  • the main body 52a has a substantially rectangular shape in a plane, and has a first long side on the side where the emitter terminals E2 are connected and a second long side located opposite to the first long side.
  • the slit 52s opens in the second long side of the main body 52a and extends in the Y direction toward the first long side.
  • the slit 52s straddles the facing regions 32t of the two semiconductor elements 32 in the Y direction. That is, the slit 52s extends in the Y direction to a position closer to the emitter terminal E2 (opposing portion E2a) than the semiconductor element 32.
  • the slit 52s is provided substantially in the center of the main body 52a (heat sink 52) in the X direction.
  • the two islands 52i have a line-symmetrical arrangement with the axis AX2 as the axis of symmetry.
  • the slits 52s are sometimes referred to as notches and separation regions.
  • the heat sink 42 of this embodiment has slits 42s.
  • the slit 42s penetrates the heat sink 42 in the Z direction and is divided into two islands 42i.
  • One of the islands 42i is a mounting area for the semiconductor element 32a.
  • the other one of the islands 42i is a mounting area for the semiconductor element 32b.
  • the heat sink 42 has a substantially rectangular shape in a plane, and has a first long side on the side where the collector terminals C2 are connected and a second long side located opposite to the first long side.
  • the slit 42s opens on the first long side and extends in the Y direction toward the second long side.
  • the slit 42s is open on the side opposite to the opening end of the slit 52s.
  • the slit 42s straddles the facing regions 32t of the two semiconductor elements 32 in the Y direction. That is, the slit 42s extends to a position closer to the second long side than the semiconductor element 32 in the Y direction.
  • the slit 42s is provided substantially in the center of the heat sink 42 in the X direction.
  • the two islands 42i have a line-symmetrical arrangement with the axis AX2 as the axis of symmetry.
  • the slits 42s are sometimes referred to as notches and separation regions.
  • the broken line shown in FIG. 63 indicates the current path. Due to the presence of the slit 52s, the current path on the semiconductor element 32a side and the current path on the semiconductor element 32b side merge at the extension destination of the slit 52s. As described above, since the heat sink 52 has the slits 52s, the distance (wiring length) from the semiconductor elements 32a and 32b to the confluence of the two current paths can be made longer than in the configuration without the slits 52s. .. In other words, the confluence can be moved away from the configuration without the slit 52s. Thereby, the values of the wiring inductances Le21 and Le22 can be increased. As a result, the imbalance of AC current due to the difference in element characteristics can be suppressed.
  • the slit 52s straddles the facing region 32t of the semiconductor element 32. Therefore, the merging portion is not formed in the facing region 32t. As a result, the wiring length to the confluence can be further increased. Therefore, the values of the wiring inductances Le21 and Le22 can be further increased, and the effect of suppressing the current imbalance described above can be enhanced.
  • the heat sink 52 including the slit 52s is line-symmetric with respect to the axis AX2.
  • the current path on the semiconductor element 32a side and the current path on the semiconductor element 32b side become line-symmetrical while providing the slit 52s.
  • the wiring inductance Le21 and the wiring inductance Le22 become substantially equal. Therefore, the imbalance of AC current can be suppressed.
  • the heat sink 52 is divided into two islands 52i by the slits 52s.
  • a plurality of islands 52i are formed in one metal plate or conductor. Therefore, the configuration can be simplified.
  • FIG. 65 shows a reference example having no slits 42s and 52s.
  • the solid arrow indicates the current path between the collector terminal C2r and the semiconductor element 32r.
  • the dashed arrow indicates the current path between the emitter terminal E2r and the semiconductor element 32r.
  • the current flowing between the collector terminal C21r and the semiconductor element 32br and the current flowing between the semiconductor element 32br and the emitter terminal E2r have components in opposite directions to each other.
  • the current flowing between the collector terminal C22r and the semiconductor element 32ar and the current flowing between the semiconductor element 32ar and the emitter terminal E2r have components in opposite directions to each other.
  • the current flowing between the collector terminal C2r and the semiconductor element 32r, which are in a distant positional relationship in the X direction, and the current flowing between the semiconductor element 32r and the emitter terminal E2r have components in opposite directions. .. Therefore, the wiring inductance becomes small due to the cancellation of the magnetic flux.
  • the current path between the semiconductor element 32 and the emitter terminal E2 becomes a path different from the current path shown in FIG. 65.
  • the magnetic flux cancellation can be reduced.
  • mutual inductance acts on the positive side.
  • the values of the wiring inductances Le21 and Le22 can be increased, and the imbalance of the AC current due to the difference in element characteristics can be suppressed.
  • the heat sink 42 has slits 42s. Therefore, a current path shown by a solid arrow in FIG. 64 is formed between the collector terminal C2 and the semiconductor element 32. A current path that bypasses the slit 42s is formed between the collector terminal C22 and the semiconductor element 32a. Similarly, a current path that bypasses the slit 42s is formed between the collector terminal C21 and the semiconductor element 32b.
  • the components of the current flowing between the semiconductor element 32 and the collector terminal C2 and the current flowing between the semiconductor element 32 and the emitter terminal E2, which are opposite to each other, are compared with the configuration in which the slit 42s is not provided. Can be reduced. As a result, the values of the wiring inductances Le21 and Le22 can be increased, and the imbalance of the AC current due to the difference in element characteristics can be suppressed.
  • the slit 42s straddles the facing region 32t of the semiconductor element 32.
  • the current path formed between the collector terminal C22 and the semiconductor element 32a has a substantially J-shape.
  • the current path formed between the collector terminal C21 and the semiconductor element 32b also has a substantially J shape. Therefore, the reverse current component can be further reduced.
  • the values of the wiring inductances Le21 and Le22 can be further increased, and the effect of suppressing the current imbalance described above can be enhanced.
  • the heat sink 42 including the slit 42s is axisymmetric with respect to the axis AX2.
  • the current path on the semiconductor element 32a side and the current path on the semiconductor element 32b side become line-symmetrical while providing the slit 42s.
  • the wiring inductance Lc21 and the wiring inductance Lc22 become substantially equal. Therefore, the imbalance of AC current can be suppressed.
  • the heat sink 42 is divided into two islands 42i by the slits 42s.
  • a plurality of islands 42i are formed in one metal plate or conductor. Therefore, the configuration can be simplified.
  • slits 42s and 52s are provided in the heat sinks 42 and 52, respectively, is shown, but the present invention is not limited to this.
  • the slit 42s may be provided only in the heat sink 42, and the slit 52s may not be provided in the heat sink 52.
  • the slit 52s may be provided only in the heat sink 52, and the slit 42s may not be provided in the heat sink 42.
  • slits 42s and 52s in the semiconductor device 12 has been shown, but the present invention is not limited to this.
  • the current path when the slit is not provided is the same as that of the reference example shown in FIG. 65. Therefore, in the semiconductor device 11, slits may be provided in at least one of the heat sinks 41 and 51.
  • the values of the wiring inductances Le11 and Le12 can be increased by the above-mentioned effect of moving the merging portion away and / or the effect of reducing the magnetic flux cancellation. As a result, the imbalance of AC current due to the difference in element characteristics can be suppressed.
  • a slit may be provided in the heat sink 41.
  • This slit opens on the long side opposite to the side where the collector terminals C1 are connected.
  • the heat sink 51 may be provided with a slit. The slit opens on the long side where the two emitter terminals E1 are connected.
  • the configuration may include two heat sinks 52. That is, the heat sink 52 may be completely divided into two regions. It is possible to obtain the same effect as the configuration in which the slits 52s are provided.
  • the heat sink 52 has islands 52i, respectively. A predetermined gap is provided between the two heat sinks 52 in the X direction.
  • the two heat sinks 52 are electrically connected via a connecting member.
  • the emitter terminal E2 also serves as a connecting member.
  • the opposing portion E2a of the emitter terminal E2 bridges the two heat sinks 52. As a result, the number of parts can be reduced.
  • the configuration may include two heat sinks 42. That is, the heat sink 42 may be completely divided into two regions. It is possible to obtain the same effect as the configuration in which the slits 42s are provided.
  • Each of the heat sinks 42 has an island 42i. A predetermined gap is provided between the two heat sinks 42 in the X direction.
  • the connecting member 43 electrically connected via the connecting member 43 bridges the two heat sinks 42.
  • the two heat sinks 52 may be electrically connected by using a connecting member different from the emitter terminal E2, and the emitter terminal E2 may be connected to this connecting member.
  • the divided structure of the heat sinks 41 and 51 may be adopted.
  • wiring boards 40, 50 such as a DBC board may be used instead of the heat sinks 41, 42, 51, 52. 68, 69, and 70 are examples thereof.
  • FIG. 68 is a cross-sectional view of the semiconductor device corresponding to the LXVIII-LXVIII line of FIGS. 69 and 70. In FIG. 68, the sealing resin body 22 and the signal terminal 82 are omitted for convenience.
  • FIG. 69 shows the wiring board 40 and the collector terminal C2 on the collector side
  • FIG. 70 shows the wiring board 50 and the emitter terminal E2 on the emitter side.
  • the semiconductor device 12 shown in FIG. 68 includes wiring boards 40, 50 arranged so as to sandwich the two semiconductor elements 32 (32a, 32b) as wiring members. ..
  • the wiring boards 40 and 50 are DBC boards.
  • the wiring boards 40 and 50 have insulators 40a and 50a and conductors 40b and 50b.
  • the conductors 40b and 50b are arranged at least on the mounting surface in the Z direction. Here, it is also arranged on the back surface of the mounting surface.
  • the conductor 40b on the mounting surface side has two islands 40i and a slit 40s.
  • the conductor 40b having the islands 40i and the slits 40s corresponds to the heat sink 42.
  • the island 40i corresponds to the island 42i, and the slit 40s corresponds to the slit 42s.
  • the slit 40s penetrates the conductor 40b, and divides the conductor 40b into an island 40i, which is a mounting region of the semiconductor element 32a, and an island 40i, which is a mounting region of the semiconductor element 32b.
  • a collector terminal C21 is connected to one of the islands 40i, and a collector terminal C22 is connected to the other island 40i.
  • the conductor 40b has, for example, a substantially rectangular shape in a plane.
  • the slit 40s is opened on the long side where the collector terminals C2 are connected and extends in the Y direction.
  • the slit 40s straddles the facing regions of the semiconductor elements 32a and 32b.
  • the semiconductor element 32, the conductor 40b including the slit 40s, and the collector terminal C2 have the same symmetry as the above-described embodiment.
  • the conductor 50b on the mounting surface side has two islands 50i and a slit 50s.
  • the conductor 50b having the islands 50i and the slits 50s corresponds to the heat sink 52.
  • the island 50i corresponds to the island 52i, and the slit 50s corresponds to the slit 52s.
  • the slit 50s penetrates the conductor 50b, and divides the conductor 50b into an island 50i, which is a mounting area of the semiconductor element 32a, and an island 50i, which is a mounting area of the semiconductor element 32b.
  • the emitter terminal E2 is connected to a portion of the conductor 50b that connects the two islands 50i.
  • the conductor 50b has, for example, a substantially rectangular shape in a plane.
  • the slit 50s is opened on a long side opposite to the side where the emitter terminals E2 are connected, and extends in the Y direction.
  • the slit 50s straddles the facing regions of the semiconductor elements 32a and 32b.
  • the semiconductor element 32, the conductor 50b including the slit 50s, and the emitter terminal E2 have the same symmetry as the above-described embodiment.
  • the semiconductor device 12 using the wiring boards 40 and 50 can also have the same effect as the semiconductor device 12 using the heat sinks 42 and 52.
  • a heat sink and a wiring board may be combined as the wiring member.
  • a configuration may include a heat sink 42 and a wiring board 50 (DBC substrate), or a configuration may include a wiring board 40 and a heat sink 52. It can also be applied to the semiconductor device 11.
  • Disclosure in this specification, drawings and the like is not limited to the illustrated embodiments.
  • the disclosure includes exemplary embodiments and modifications by those skilled in the art based on them.
  • disclosure is not limited to the parts and / or element combinations shown in the embodiments. Disclosure can be carried out in various combinations.
  • the disclosure can have additional parts that can be added to the embodiments. Disclosures include those in which the parts and / or elements of the embodiment are omitted. Disclosures include the replacement or combination of parts and / or elements between one embodiment and another.
  • the technical scope disclosed is not limited to the description of the embodiments. Some technical scopes disclosed are indicated by the claims description and should be understood to include all modifications within the meaning and scope equivalent to the claims statement.

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PCT/JP2020/038747 2019-12-12 2020-10-14 半導体装置 Ceased WO2021117334A1 (ja)

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WO2025009316A1 (ja) * 2023-07-05 2025-01-09 株式会社デンソー 半導体装置

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JP7647630B2 (ja) * 2022-03-02 2025-03-18 株式会社デンソー 半導体装置
CN120826781A (zh) * 2023-03-15 2025-10-21 三菱电机株式会社 半导体装置
JP2024171657A (ja) * 2023-05-30 2024-12-12 株式会社デンソー 電力変換装置
JP2024171658A (ja) * 2023-05-30 2024-12-12 株式会社デンソー 電力変換装置

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JP7740055B2 (ja) * 2022-02-22 2025-09-17 株式会社デンソー 半導体装置
JP7694512B2 (ja) * 2022-09-02 2025-06-18 株式会社デンソー 半導体装置
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WO2025009316A1 (ja) * 2023-07-05 2025-01-09 株式会社デンソー 半導体装置

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US20220278030A1 (en) 2022-09-01
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US12476172B2 (en) 2025-11-18
JP2021093503A (ja) 2021-06-17

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