JP7167907B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7167907B2 JP7167907B2 JP2019224847A JP2019224847A JP7167907B2 JP 7167907 B2 JP7167907 B2 JP 7167907B2 JP 2019224847 A JP2019224847 A JP 2019224847A JP 2019224847 A JP2019224847 A JP 2019224847A JP 7167907 B2 JP7167907 B2 JP 7167907B2
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Description
一面と、一面とは板厚方向において反対の裏面とに、主電極(31c、31e、32c、32e)をそれぞれ有する少なくともひとつの半導体素子(31、32)と、
板厚方向において半導体素子を挟むように一面側および裏面側のそれぞれに配置され、対応する主電極と電気的に接続された少なくとも一組の放熱部(41、42、51、52)と、放熱部に連なる複数の端子部(C1、C2、E1、E2)と、を含む複数の導体部と、板厚方向において2つの導体部の間に接合材(91d、92d)が配置されて形成された少なくともひとつの接合部(121、122)と、を有する配線部材と、を備える。
本実施形態に係る半導体装置および半導体モジュールは、電力変換装置に適用される。電力変換装置は、たとえば車両の駆動システムに適用される。電力変換装置は、電気自動車(EV)やハイブリッド自動車(HV)などの車両に適用可能である。以下では、ハイブリッド自動車に適用される例について説明する。
先ず、車両の駆動システムの概略構成について説明する。図1に示すように、車両の駆動システム1は、直流電源2と、モータジェネレータ3と、電力変換装置4を備えている。
次に、電力変換装置4の回路構成について説明する。図1に示すように、電力変換装置4は、インバータ5と、制御回路部6と、平滑コンデンサCsを備えている。インバータ5は、電力変換部である。インバータ5は、DC-AC変換部である。電力変換部は、上下アーム7を備えて構成されている。
次に、インバータ5を構成する半導体装置について説明する。上下アーム7は、後述するひとつの半導体モジュール10により構成される。半導体モジュール10は、図2~図8に示す2種類(2品番)の半導体装置11、12を備えて構成される。半導体装置11は上アーム7Uを構成し、半導体装置12は下アーム7Lを構成する。
次に、半導体装置11、12の製造方法について説明する。製造する工程(ステップ)は半導体装置11、12で同じであるため、半導体装置11を例に説明する。
次に、半導体モジュールの概略構造について説明する。ひとつの半導体モジュールにより、一相分の上下アーム7が構成される。3つの半導体モジュールにより、インバータ5が構成される。図9および図10に示すように、半導体モジュール10は、上記した半導体装置11、12と、連結部材13と、冷却器14を備えている。図9では、便宜上、冷却器14を省略している。
次に、上記した半導体モジュールの構造について詳細に説明する。図12は、図2に対応しており、封止樹脂体21、22内の要素を破線で示している。
本実施形態において、先行実施形態と機能的におよび/または構造的に対応する部分および/または関連付けられる部分には、同一の参照符号を付与する。対応する部分および/または関連付けられる部分については、先行実施形態の説明を参照することができる。
(式1)x0={(Rd-0.5)×k+0.5}
(式2)x≧{(Rd-0.5)×k+0.5}
(式3)x>{(Rd-0.5)×k+0.5}
(式4)x≦{(Rd-0.5)×k+0.5}
(式5)x<{(Rd-0.5)×k+0.5}
本実施形態において、先行実施形態と機能的におよび/または構造的に対応する部分および/または関連付けられる部分には、同一の参照符号を付与する。対応する部分および/または関連付けられる部分については、先行実施形態の説明を参照することができる。
本実施形態において、先行実施形態と機能的におよび/または構造的に対応する部分および/または関連付けられる部分には、同一の参照符号を付与する。対応する部分および/または関連付けられる部分については、先行実施形態の説明を参照することができる。
(式6)Δ=tb2m-tb2s=ta2×{(Wa2/Wb2)-1}
(式7)ta2<tb2≦ta2×{(2×Wa2-Wb2)/Wb2}
本実施形態において、先行実施形態と機能的におよび/または構造的に対応する部分および/または関連付けられる部分には、同一の参照符号を付与する。対応する部分および/または関連付けられる部分については、先行実施形態の説明を参照することができる。
図41~図43に基づき、余剰はんだの収容構造について説明する。図41は、本実施形態の半導体装置11、12において、エミッタ側のヒートシンク51、52を示している。図42は、ヒートシンク51を拡大した図である。図43は、図42のXLIII-XLIII線に対応する半導体装置11の断面図である。図43では、便宜上、封止樹脂体21を省略している。本実施形態では、エミッタ側のヒートシンク51、52に、余剰はんだの収容構造を設けている。ヒートシンク51、52が第1導体部に相当し、エミッタ端子E1、E2が第2導体部に相当する。
図44に基づき、低濡れ領域について説明する。図44は、図43の領域XLIVを拡大した図である。図44では、便宜上、はんだ91dを省略して図示している。以下では、ヒートシンク51を例に説明する。
先行実施形態に記載のように、両面放熱構造の半導体装置11、12は、冷却器によってZ方向の両面側から挟まれる。よって、Z方向において表面の高い平行度と表面間の高い寸法精度が求められる。このため、はんだ91d、92dについては、半導体装置11、12の高さばらつきを吸収可能な量を配置する。すなわち、多めのはんだ91d、92dを配置する。そして、2ndリフロー時に、Z方向に荷重を加えることで、半導体装置11、12の高さが所定高さとなるようにする。はんだ91d、92dは、半導体装置11、12を構成する要素の寸法公差や組み付け公差による高さばらつきを吸収する。
非重なり領域151dは、少なくとも収容領域151eを含めばよい。図49に示すように、ヒートシンク51において、非重なり領域151dからフィレット形成領域151fを排除した構成としてもよい。高濡れ領域151bは、重なり領域151cと、収容領域151eのみを有している。このような構成としても、上記実施形態と同等の効果を奏することができる。なお、ターミナル61側の高濡れ領域151gも、同様にフィレット形成領域151kを排除した構成となっている。ヒートシンク52についても同様である。
本実施形態において、先行実施形態と機能的におよび/または構造的に対応する部分および/または関連付けられる部分には、同一の参照符号を付与する。対応する部分および/または関連付けられる部分については、先行実施形態の説明を参照することができる。
図61に示す一点鎖線の矢印は主端子71を流れる電流(主電流)の経路を示している。主電流の経路は、半導体素子31を介して、コレクタ端子C1とエミッタ端子E1との間に形成される。実線矢印は信号端子81を流れる電流(信号電流)の経路を示している。信号電流の経路は、半導体素子31を介して、ゲートパッドP3に接続された信号端子81とケルビンエミッタパッドP5に接続された信号端子81との間に形成される。主電流が流れる回路と信号電流が流れる回路とは、磁気的に結合する。
本実施形態において、先行実施形態と機能的におよび/または構造的に対応する部分および/または関連付けられる部分には、同一の参照符号を付与する。対応する部分および/または関連付けられる部分については、先行実施形態の説明を参照することができる。
エミッタ側の配線インダクタンスは、並列回路におけるAC電流のアンバランスを緩和する機能を果たす。図62は、下アーム7Lを構成する半導体装置12の等価回路図である。半導体装置12は、先行実施形態同様、2つの半導体素子32(32a、32b)を備えている。半導体素子32aとエミッタ端子E2との間には配線インダクタンスLe21が存在し、半導体素子32bとエミッタ端子E2との間には配線インダクタンスLe22が存在する。このため、スイッチング時、すなわちAC電流が流れる際、エミッタ電位が変動(上昇)する。
図63は、本実施形態に係る半導体装置12において、エミッタ側のヒートシンク52およびエミッタ端子E2を示している。図64は、コレクタ側のヒートシンク42およびコレクタ端子C2を示している。コレクタ端子C2およびエミッタ端子E2の構成は、先行実施形態に記載の構成(たとえば図12参照)と同じである。2つの半導体素子32の配置も、同様である。ヒートシンク42、52の基本構成も、同様である。
図63に示す破線は、電流経路を示している。半導体素子32a側の電流経路と、半導体素子32b側の電流経路とは、スリット52sの存在により、スリット52sの延設先で合流する。このように、ヒートシンク52がスリット52sを有することで、スリット52sを有さない構成よりも、半導体素子32a、32bから2つの電流経路の合流部までの距離(配線長)を長くすることができる。換言すれば、スリット52sを有さない構成よりも、合流部を遠ざけることができる。これにより、配線インダクタンスLe21、Le22の値を大きくすることができる。この結果、素子特性差によるAC電流のアンバランスを抑制することができる。
ヒートシンク42、52にそれぞれスリット42s、52sを設ける例を示したが、これに限定されない。ヒートシンク42のみにスリット42sを設け、ヒートシンク52にスリット52sを設けない構成としてもよい。ヒートシンク52のみにスリット52sを設け、ヒートシンク42にスリット42sを設けない構成としてもよい。
この明細書および図面等における開示は、例示された実施形態に制限されない。開示は、例示された実施形態と、それらに基づく当業者による変形態様を包含する。例えば、開示は、実施形態において示された部品および/または要素の組み合わせに限定されない。開示は、多様な組み合わせによって実施可能である。開示は、実施形態に追加可能な追加的な部分をもつことができる。開示は、実施形態の部品および/または要素が省略されたものを包含する。開示は、ひとつの実施形態と他の実施形態との間における部品および/または要素の置き換え、または組み合わせを包含する。開示される技術的範囲は、実施形態の記載に限定されない。開示されるいくつかの技術的範囲は、請求の範囲の記載によって示され、さらに請求の範囲の記載と均等の意味および範囲内での全ての変更を含むものと解されるべきである。
Claims (10)
- 一面と、前記一面とは板厚方向において反対の裏面とに、主電極(31c、31e、32c、32e)をそれぞれ有する少なくともひとつの半導体素子(31、32)と、
前記板厚方向において前記半導体素子を挟むように前記一面側および前記裏面側のそれぞれに配置され、対応する前記主電極と電気的に接続された少なくとも一組の放熱部(41、42、51、52)と、前記放熱部に連なる複数の端子部(C1、C2、E1、E2)と、を含む複数の導体部と、前記板厚方向において2つの前記導体部の間に接合材(91d、92d)が配置されて形成された少なくともひとつの接合部(121、122)と、を有する配線部材と、を備え、
前記接合部の少なくともひとつにおいて、前記導体部のひとつである第1導体部(51、52)は、前記導体部の他のひとつである第2導体部(E1、E2)と対向する側の面に、高濡れ領域(151b、152b)と、前記板厚方向の平面視において前記高濡れ領域の外周を規定するように前記高濡れ領域に隣接して設けられ、前記高濡れ領域よりも前記接合材に対する濡れ性が低い低濡れ領域(151a、152a)と、を有し、
前記高濡れ領域は、前記平面視において、前記第2導体部における前記接合部の形成領域と重なる領域であり、少なくとも一部に前記接合材が配置された重なり領域(151c、152c)と、前記重なり領域に面一で連なり、前記第2導体部の接合部形成領域と重なっていない領域である非重なり領域(151d、152d)と、を有し、
前記非重なり領域は、前記重なり領域に面一で連なり、前記接合部に対して余剰の前記接合材を収容する収容領域(151e、152e)を少なくとも含む半導体装置。 - 前記収容領域は、前記平面視において前記重なり領域の外周の一部のみに連なっており、
前記低濡れ領域は、前記重なり領域と前記収容領域との並び方向および前記板厚方向に直交する方向において前記重なり領域と前記低濡れ領域との両方を挟むように、前記直交する方向の両側で前記高濡れ領域の外周に隣接している請求項1に記載の半導体装置。 - 前記低濡れ領域は、前記収容領域において前記高濡れ領域の外周をなす部分に全域で隣接している請求項1または請求項2に記載の半導体装置。
- 前記低濡れ領域は、互いに連なる前記重なり領域および前記非重なり領域を一体的に取り囲み、前記高濡れ領域の外周に全域で隣接している請求項1~3いずれか1項に記載の半導体装置。
- 前記第1導体部は、前記高濡れ領域として、2つの前記重なり領域と、2つの前記重なり領域の並び方向において前記重なり領域の間に設けられ、前記重なり領域のそれぞれに連なる前記収容領域と、を有する請求項1~4いずれか1項に記載の半導体装置。
- 前記第1導体部は、前記高濡れ領域として、2つの前記収容領域と、2つの前記収容領域の並び方向において前記収容領域の間に設けられ、前記収容領域のそれぞれに連なる前記重なり領域と、を有する請求項1~4いずれか1項に記載の半導体装置。
- 前記第1導体部において、前記高濡れ領域および前記低濡れ領域のうち、前記低濡れ領域のみに、前記接合材に対する濡れ性の低い膜が形成されている請求項1~6いずれか1項に記載の半導体装置。
- 前記第1導体部は、母材(160)と、前記母材の表面に形成された金属膜(161)と、前記金属膜の主成分の金属と同じ金属の酸化物であり、表面が連続して凹凸をなす凹凸酸化膜(162)と、を有し、
前記低濡れ領域のみに、前記接合材に対する濡れ性が低い膜として、前記凹凸酸化膜が形成されている請求項7に記載の半導体装置。 - 前記非重なり領域は、前記収容領域のみを含む請求項1~8いずれか1項に記載の半導体装置。
- 前記非重なり領域は、前記収容領域と、前記収容領域とは異なる位置で前記重なり領域に連なり、前記重なり領域との並び方向の長さが前記収容領域よりも短い狭幅領域(151f、152f)と、を含む請求項1~8いずれか1項に記載の半導体装置。
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