WO2021103530A1 - Structure à bits quantiques supraconducteurs extensibles bidimensionnels et son procédé de commande de mode de cavité - Google Patents

Structure à bits quantiques supraconducteurs extensibles bidimensionnels et son procédé de commande de mode de cavité Download PDF

Info

Publication number
WO2021103530A1
WO2021103530A1 PCT/CN2020/099765 CN2020099765W WO2021103530A1 WO 2021103530 A1 WO2021103530 A1 WO 2021103530A1 CN 2020099765 W CN2020099765 W CN 2020099765W WO 2021103530 A1 WO2021103530 A1 WO 2021103530A1
Authority
WO
WIPO (PCT)
Prior art keywords
qubit
arms
qubits
dimensional
superconducting qubit
Prior art date
Application number
PCT/CN2020/099765
Other languages
English (en)
Chinese (zh)
Inventor
梁福田
邓辉
龚明
吴玉林
彭承志
朱晓波
潘建伟
Original Assignee
中国科学技术大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学技术大学 filed Critical 中国科学技术大学
Priority to GB2208472.7A priority Critical patent/GB2606880A/en
Priority to JP2022531594A priority patent/JP7395215B2/ja
Priority to US17/780,731 priority patent/US20220416145A1/en
Publication of WO2021103530A1 publication Critical patent/WO2021103530A1/fr

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/80—Constructional details
    • H10N60/81—Containers; Mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Definitions

  • the present disclosure belongs to the technical field of quantum computing, and relates to a two-dimensional expandable superconducting qubit structure and a cavity mode control method thereof.
  • Superconducting quantum computing makes use of superconducting qubit quantum state superposition, entanglement and other properties to realize quantum computing.
  • Superconducting qubit can be fabricated on a chip using micro-nano processing technology, and has superior performance such as integration and scalability.
  • superconducting quantum computing has developed rapidly, but for a one-dimensional chain qubit structure, each bit is only coupled with two adjacent qubits on the left and right, which has certain limitations.
  • the present disclosure provides a two-dimensional scalable superconducting qubit structure and a cavity mode control method thereof to at least partially solve the above-mentioned technical problems.
  • a two-dimensional expandable superconducting qubit structure including: a superconducting qubit chip, the superconducting qubit chip containing a plurality of qubits that are two-dimensionally distributed and expandable; Wherein the capacitance part of each qubit has at least five arms distributed in two dimensions, and two of the at least five arms in each qubit are respectively used to connect to the read coupling line and to the control line Connected, the remaining at least three arms are coupled with adjacent qubits through the coupling cavity.
  • the qubit has separate XY control lines and Z control lines, or the qubit has only XY control lines.
  • At least two qubits share a read coupling line.
  • the two-dimensionally distributed multiple qubits form a qubit array.
  • some of the qubits have the same number of arms, and some of the qubits have different numbers of arms; for the number of qubits
  • the distribution of arms between each qubit is one of the following situations: partly the same, completely the same, or completely different.
  • the qubit array includes one or more of the following distribution forms: honeycomb arrangement, grid distribution, snowflake distribution or tree distribution.
  • a cavity mode control method for a two-dimensional expandable superconducting qubit structure using flip-chip soldering and through silicon via technology, in the superconducting qubit chip, a non-qubit circuit The position forms a three-dimensional lead structure for signal extraction.
  • a cavity mode control method for a two-dimensional expandable superconducting qubit structure A plurality of holes are made in the superconducting qubit chip at the position of the non-qubit circuit, and the quantum The bit control circuit and the read coupling circuit are wire-bonded to the packaging box or the circuit board through a plurality of holes in the plurality of holes.
  • control lines between two adjacent qubits are drawn from different holes for bonding.
  • the plurality of holes are distributed in an array.
  • At least five arms are provided by the qubit-based capacitor part, of which two arms are used to connect to the read coupling line, the other is used to connect to the control line, and the remaining at least three arms are used to connect respectively Coupling with adjacent qubits in various directions through a coupling cavity, that is, one of the remaining arms connects to an adjacent qubit, and the connection between each qubit and adjacent qubits and each qubit are realized through the above expansion method
  • the above-mentioned signal reading and control of the at least five arms and the connection of the qubits make it possible to expand in two dimensions with each qubit as the center; in addition, at least three arms are used to communicate with adjacent quantum bits. Bits are connected. Since at least five arms are distributed in a two-dimensional plane, the structure is convenient for two-dimensional expansion and is suitable for the existing flip-chip soldering process or through silicon via technology (TSV) and signal fan-out The boards are connected.
  • TSV silicon via technology
  • the above-mentioned two-dimensional expandable superconducting qubit structure can input and extract signals from the middle of the quantum chip by cutting hole array, flip-chip bonding, TSV, etc., effectively reducing the crosstalk between adjacent qubit signals.
  • Fig. 1 is a schematic diagram of a two-dimensional scalable superconducting qubit structure according to an embodiment of the present disclosure.
  • Fig. 2 is a schematic diagram of a distribution form of six arms with a two-dimensional distribution in a qubit capacitor part according to an embodiment of the present disclosure.
  • FIGS. 3 to 5 are schematic diagrams of the array distribution formed by different numbers of connecting arms between each qubit in the two-dimensional expandable superconducting qubit structure according to an embodiment of the present disclosure.
  • Figure 3 is an example of the array distribution form when the capacitive coupling arm connecting each qubit in the multiple qubits is 4 arms;
  • Figure 4 is the capacitive coupling connecting each qubit in the multiple qubits An example array distribution form when the arms are 3 arms;
  • Fig. 5 is an example array distribution form when the capacitive coupling arms connecting each qubit among multiple qubits are 6 arms.
  • Fig. 6 is a schematic diagram of a reading coupling line shared by every four qubits in the qubit array according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a cavity mode control method of a two-dimensional scalable superconducting qubit structure according to an embodiment of the present disclosure.
  • a two-dimensional scalable superconducting qubit structure is provided.
  • Fig. 1 is a schematic diagram of a two-dimensional scalable superconducting qubit structure according to an embodiment of the present disclosure.
  • the two-dimensional expandable superconducting qubit structure of the present disclosure includes: a superconducting qubit chip, the superconducting qubit chip contains two-dimensionally distributed and expandable multiple qubits; wherein each The capacitance part of each of the qubits has at least five arms that are two-dimensionally distributed, and two of the at least five arms in each qubit are respectively used to connect with the read coupling line and the control line, The remaining at least three arms are coupled with adjacent qubits through the coupling cavity.
  • the capacitance part of the qubit 1 has six arms as an example, and the corresponding six arms are the first arm 11, the second arm 12, the third arm 13, and the fourth arm.
  • the arms, the fifth arm 15 and the sixth arm 16, wherein two arms of the six arms are respectively used to connect to the reading coupling line and the control line.
  • the fifth arm 15 is connected to the reading coupling line 2 here.
  • the sixth arm 16 is connected to the control line 3 as an example.
  • the remaining four arms are used for coupling with adjacent qubits through the coupling cavity.
  • the dimensional direction forms an extended form of the six lines 1-6. Among them, four lines, such as the four lines 1-4 in this embodiment, are coupled with qubits adjacent in four directions.
  • the number of arms of each qubit is at least 5, that is, at least 3 arms are coupled with other adjacent qubits, except for the 6-arm example described above. In addition, it can also be 7, 8, or even more.
  • the specific connection form can be designed according to actual needs.
  • the length of each arm and the angle distribution between each arm can be simulated or calculated. Arrangement.
  • the qubit has separate XY control lines and Z control lines, or the qubit has only XY control lines. That is, for the capacitance extension arm of the qubit for connecting the control line, the XY control line and the Z control line can be connected separately, or only the XY control line can be connected.
  • Fig. 2 is a schematic diagram of a distribution form of six arms with a two-dimensional distribution in a qubit capacitor part according to an embodiment of the present disclosure.
  • the distribution form of at least five arms of the capacitance part of the qubit of the present disclosure may be various two-dimensional distributions.
  • the included angle between two adjacent arms of the six arms in the qubit is greater than 0° and less than or equal to 180°.
  • the capacitance part of the qubit includes 6 arms, four of the six arms are perpendicular to each other in a "cross" shape, and one of the remaining two arms Distributed between any two adjacent arms of the above four arms, and the remaining one arm is distributed between the remaining three groups of adjacent two arms, specifically which two arms are used to connect to the reading coupling line, Connected to the control circuit, which four arms are used for coupling with adjacent qubits, can be selected according to the actual connection expansion; or in another embodiment, refer to Figure 2 (c) as shown, six The two opposite arms of the two arms are located on the same straight line, and there is an included angle between the two adjacent arms.
  • the angle on the upper left it forms 30°, 120°, 30°, 30°, clockwise in turn. 120° and 30° distribution.
  • some of the qubits have the same number of arms, and some of the qubits have different numbers of arms; for the number of qubits
  • the distribution of arms between each qubit is one of the following situations: partly the same, completely the same, or completely different.
  • each qubit continuously expands to the outside by coupling with adjacent qubits.
  • the "at least five arms" described in this disclosure means that each qubit can continuously expand.
  • the basic unit form, the qubit array form to be introduced below is described with the edge of the array, but in fact, the qubit in the central area can be expanded indefinitely, and then the edges are matched according to the connection needs, and the expansion formed is
  • the qubits located in the middle area are all complete standard structures, that is, as described in the present disclosure, the “capacitance part of each qubit has at least five arms distributed in two dimensions”, which has scalability.
  • Qubits have all arms, and the edge part is the same as the part that "loses" half of the capacitive coupling arms. There is no limit to the qubits at the edge.
  • the qubits at the edge can be adapted according to the needs of the expansion of the middle area.
  • the "capacitive coupling arm” is the arm used for coupling with adjacent qubits in the capacitive extension arm, excluding the capacitive extension arm used for connecting the read coupling line and the control line.
  • FIGS. 3 to 5 are schematic diagrams of the array distribution formed by different numbers of connecting arms between each qubit in the two-dimensional expandable superconducting qubit structure according to an embodiment of the present disclosure.
  • Figure 3 is an example of the array distribution form when the capacitive coupling arm connecting each qubit in the multiple qubits is 4 arms;
  • Figure 4 is the capacitive coupling connecting each qubit in the multiple qubits An example array distribution form when the arms are 3 arms;
  • Fig. 5 is an example array distribution form when the capacitive coupling arms connecting each qubit among multiple qubits are 6 arms.
  • the two-dimensionally distributed multiple qubits form a qubit array
  • the qubit array includes one or more of the following distribution forms: honeycomb arrangement, grid distribution, snowflake distribution or tree distribution.
  • the distribution of the arms between each qubit is one of the following situations: partly the same, completely the same or completely different, among which, the completely identical situation refers to the figure 3.
  • the middle area shown in 3, refer to the middle area shown in Fig. 4 if the part is the same.
  • the expansion method corresponding to the above two cases is relatively simple. It can be copied and expanded by a certain basic unit, corresponding to each qubit in the same array. In completely different situations, you can refer to Figure 3, Figure 4, and Figure 5 to connect and expand them in three different qubit forms.
  • the expansion method can be mesh expansion or dendritic expansion, etc., and each example of the qubit The angle between the arms can be changed to obtain a completely different form, which is not illustrated here.
  • the distribution of qubits in the middle area is taken as an example.
  • the qubits in the edge/edge part are used as an example to make the array have a visual boundary. In fact, The edge part in the figure can be removed to expand infinitely, or the edge part can be added under the required size or expansion specification.
  • a qubit has 6 capacitive expansion arms, 4 of which are used as capacitive coupling arms to couple with adjacent qubits through a resonant cavity. After multiple qubits are expanded in two dimensions Form a grid distribution.
  • a qubit has 5 capacitive expansion arms, of which 3 are used as capacitive coupling arms to couple with adjacent qubits through a resonant cavity. After multiple qubits are expanded in two dimensions Form a honeycomb arrangement.
  • each qubit is connected to other qubits through 3 (as shown in Figure 4) or 4 (as shown in Figure 3) capacitance extension arms.
  • a qubit has 8 capacitive expansion arms, of which 6 are used as capacitive coupling arms to couple with adjacent qubits through a resonant cavity.
  • After multiple qubits are expanded in two dimensions Form a snowflake distribution.
  • a tree-like distribution or other expandable array distribution form can be formed, as long as it follows each mentioned in the present disclosure.
  • the arrays obtained by the expansion of the qubits by connecting the remaining at least three arms with adjacent qubits are all within the protection scope of the present disclosure.
  • each qubit is connected with a read coupling line.
  • adjacent qubits can share the read coupling line, which can reduce the total number of read lines and simplify wiring.
  • at least two qubits share one read coupling line.
  • at least two qubits adjacent to the left and right or up and down share one reading coupling line.
  • FIG. 5 an example case in which at least two qubits share one read coupling line is introduced.
  • Fig. 6 is a schematic diagram of a reading coupling line shared by every four qubits in the qubit array according to an embodiment of the present disclosure.
  • the two-dimensionally distributed multiple qubits form a qubit array.
  • the multiple qubits are distributed in a grid pattern.
  • Two qubits share one read coupling line.
  • the form of the two-dimensionally distributed qubit array can be, but is not limited to, a tree topology or a mesh topology.
  • the two-dimensional expandable superconducting qubit structure of this embodiment is provided with at least five arms based on the capacitance part of the qubit.
  • One of the two arms is used to connect to the reading coupling line, and the other Connected to the control circuit, the remaining at least three arms are used to couple with adjacent qubits in four directions respectively through the coupling cavity, that is, one of the remaining arms is connected to an adjacent qubit, and each is realized by the above-mentioned expansion method.
  • the connection between two qubits and adjacent qubits and the signal reading and control of each qubit realizes the connection of two adjacent qubits.
  • the above-mentioned six-arm distribution form and the connection method of qubits make each The qubit is centered and can be expanded in two dimensions; in addition, at least three arms are used to connect to adjacent qubits, and the distribution of the three arms can cover the two-dimensional plane, so that at least five arms are in two dimensions.
  • the expansion distribution in the three-dimensional plane makes the structure convenient for two-dimensional expansion, and is suitable for the existing flip-chip soldering process or through-silicon via technology (TSV) to connect with the signal fan-out board.
  • TSV through-silicon via technology
  • a cavity mode control method of a two-dimensional scalable superconducting qubit structure is provided.
  • a cavity mode control method for a two-dimensional expandable superconducting qubit structure is provided.
  • a three-dimensional structure is formed at the position of a non-qubit circuit in a superconducting qubit chip.
  • Each through silicon via corresponds to a lead, and the read coupling line and control line can be laid out by setting the distribution and distance of each through silicon hole, thereby reducing the number of read lines, between control lines, and between read and control lines Signal crosstalk effects.
  • FIG. 7 is a schematic diagram of a cavity mode control method of a two-dimensional scalable superconducting qubit structure according to an embodiment of the present disclosure.
  • a cavity mode control method for a two-dimensional expandable superconducting qubit structure includes: making a plurality of holes in the superconducting qubit chip at positions other than the qubit circuit, and the qubit The control circuit and the read coupling circuit are wire-bonded to the packaging box or the circuit board through a plurality of holes in the plurality of holes.
  • control lines between two adjacent qubits are drawn from different holes for bonding.
  • the hole is made by laser cutting; of course, the hole can be made in other forms.
  • a plurality of qubits distributed in two dimensions form a qubit array, and every four qubits share one read coupling line, here Take 4 qubits to form a network unit, and expand on the basis of the network unit to form a grid-like distribution as an illustration.
  • the four qubits are defined In the area, there are multiple holes in the non-line area, and the 4 qubits sharing one read coupling line are interconnected. It is only necessary to wire-bond the shared read coupling line through one of the multiple holes To the macro packaging box or circuit board.
  • the control lines between two adjacent qubits are led out from different holes for bonding. Then, corresponding to a number of network units in a grid-like distribution, the corresponding holes are also in an array distribution.
  • the above-mentioned multiple qubits forming a qubit array is a grid-like distribution as an example, and other types of array distribution forms are also possible, and the corresponding holes are also in the form of array distribution.
  • multiple holes such as laser-cut circular hole arrays
  • the circuit and the reading coupling circuit are wire-bonded to the macro package box or circuit board through several holes in the plurality of holes, which can shorten the wiring length of the two-dimensional qubit, better realize the grounding of the chip, and reduce the phase
  • the crosstalk between adjacent bits suppresses the resonant mode of the sample box and is scalable. It can be used to implement many quantum computing schemes such as error correction codes and two-dimensional quantum simulations, and has good application prospects.
  • the present disclosure provides a two-dimensional scalable superconducting qubit structure and its cavity mode control method. At least five capacitive expansion arms are provided based on the capacitance part of the qubit, and one of the two arms is Used to connect to the reading coupling line, the other arm is used to connect to the control line, and the remaining at least three arms are used to couple with adjacent qubits through the coupling cavity, thereby realizing the connection of two adjacent qubits ,
  • the above-mentioned capacitive extension arm distribution form and qubit connection mode make it possible to expand in two dimensions with each qubit as the center, with good scalability and diversity of distribution forms; two-dimensional expandable superconducting quantum
  • the bit structure can input and extract signals from the quantum chip by cutting hole array, flip-chip soldering and TSV, etc., which can shorten the wiring length of the two-dimensional qubit, better realize the grounding of the chip, and effectively reduce adjacent qubits.
  • the crosstalk between the signals suppresses the resonance mode of the sample box

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Nanotechnology (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Artificial Intelligence (AREA)
  • Computational Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

Structure à bits quantiques supraconducteurs extensibles bidimensionnels et son procédé de commande de mode de cavité. La structure à bits quantiques supraconducteurs extensibles bidimensionnels comprend : une puce à bits quantiques supraconducteurs, la puce à bits quantiques supraconducteurs comprenant une pluralité de bits quantiques extensibles répartis en deux dimensions ; une partie de capacité de chacun des bits quantiques comporte au moins cinq bras répartis de manière bidimensionnelle, deux bras des cinq bras ou plus dans chacun des bits quantiques étant respectivement utilisés pour être connectés à une ligne de couplage de lecture et être connectés à une ligne de commande, et les trois bras ou plus restants étant couplés à des bits quantiques adjacents au moyen de cavités de couplage. La structure facilite l'expansion bidimensionnelle, et est appropriée pour connecter une plaque de sortance de signal dans le processus de liaison par puce retournée existant ou par l'intermédiaire d'une technologie à trou d'interconnexion à travers le silicium ; et lorsque le processus de liaison par puce retournée et le processus à trou d'interconnexion à travers le silicium ne sont pas fournis ou sont rejetés, en faisant une pluralité de trous à des positions où il n'y a pas de ligne de bits quantiques dans la puce à bits quantiques supraconducteurs, la liaison filaire à une boîte de conditionnement ou à une carte de circuit imprimé est effectuée sur la base des trous, ce qui permet de réduire efficacement la diaphonie de signal.
PCT/CN2020/099765 2019-11-29 2020-07-01 Structure à bits quantiques supraconducteurs extensibles bidimensionnels et son procédé de commande de mode de cavité WO2021103530A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB2208472.7A GB2606880A (en) 2019-11-29 2020-07-01 Two-dimensional scalable superconducting qubit structure and cavity mode control method therefor
JP2022531594A JP7395215B2 (ja) 2019-11-29 2020-07-01 二次元拡張可能な超伝導量子ビット構造及びそのキャビティモードの制御方法
US17/780,731 US20220416145A1 (en) 2019-11-29 2020-07-01 Two-dimensional scalable superconducting qubit structure and method for controlling cavity mode thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911210369.4 2019-11-29
CN201911210369.4A CN111081768B (zh) 2019-11-29 2019-11-29 二维可扩展超导量子比特结构及其腔模控制方法

Publications (1)

Publication Number Publication Date
WO2021103530A1 true WO2021103530A1 (fr) 2021-06-03

Family

ID=70312363

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/099765 WO2021103530A1 (fr) 2019-11-29 2020-07-01 Structure à bits quantiques supraconducteurs extensibles bidimensionnels et son procédé de commande de mode de cavité

Country Status (5)

Country Link
US (1) US20220416145A1 (fr)
JP (1) JP7395215B2 (fr)
CN (1) CN111081768B (fr)
GB (1) GB2606880A (fr)
WO (1) WO2021103530A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114580338A (zh) * 2022-02-21 2022-06-03 北京百度网讯科技有限公司 模拟布线方法、制造方法、芯片及装置、设备、存储介质

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111081768B (zh) * 2019-11-29 2021-12-10 中国科学技术大学 二维可扩展超导量子比特结构及其腔模控制方法
CN114077778A (zh) * 2020-08-11 2022-02-22 北京量子信息科学研究院 用于超导量子电路的真空间隙平行板电容及其制备方法和应用
CN112036573B (zh) * 2020-08-26 2023-09-19 南通大学 一种基于中等规模有噪声量子计算机的量子位交互拓扑结构及其映射方法
CN113887732B (zh) * 2021-09-24 2022-07-26 材料科学姑苏实验室 一种量子芯片及抑制量子芯片中信号串扰的方法
CN114373635B (zh) * 2022-01-12 2024-07-26 北京百度网讯科技有限公司 量子比特的电容、量子比特及其构建方法
CN114819164B (zh) * 2022-04-12 2023-09-01 北京百度网讯科技有限公司 量子芯片结构及确定方法、装置、设备、存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019117930A1 (fr) * 2017-12-15 2019-06-20 Intel Corporation Conceptions de bits quantiques améliorées pour circuits quantiques
US10374612B1 (en) * 2017-10-06 2019-08-06 Rigetti & Co, Inc. Ancilla qubit devices in a superconducting quantum processor
CN110402446A (zh) * 2017-03-13 2019-11-01 谷歌有限责任公司 在堆叠量子计算设备中的集成电路元件
CN110444526A (zh) * 2019-07-23 2019-11-12 中国科学技术大学 一种量子处理器芯片结构及其封装结构和制作方法
CN111081768A (zh) * 2019-11-29 2020-04-28 中国科学技术大学 二维可扩展超导量子比特结构及其腔模控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110402446A (zh) * 2017-03-13 2019-11-01 谷歌有限责任公司 在堆叠量子计算设备中的集成电路元件
US10374612B1 (en) * 2017-10-06 2019-08-06 Rigetti & Co, Inc. Ancilla qubit devices in a superconducting quantum processor
WO2019117930A1 (fr) * 2017-12-15 2019-06-20 Intel Corporation Conceptions de bits quantiques améliorées pour circuits quantiques
CN110444526A (zh) * 2019-07-23 2019-11-12 中国科学技术大学 一种量子处理器芯片结构及其封装结构和制作方法
CN111081768A (zh) * 2019-11-29 2020-04-28 中国科学技术大学 二维可扩展超导量子比特结构及其腔模控制方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114580338A (zh) * 2022-02-21 2022-06-03 北京百度网讯科技有限公司 模拟布线方法、制造方法、芯片及装置、设备、存储介质
CN114580338B (zh) * 2022-02-21 2023-02-28 北京百度网讯科技有限公司 模拟布线方法、制造方法、芯片及装置、设备、存储介质

Also Published As

Publication number Publication date
CN111081768A (zh) 2020-04-28
GB202208472D0 (en) 2022-07-27
JP2023503675A (ja) 2023-01-31
GB2606880A (en) 2022-11-23
US20220416145A1 (en) 2022-12-29
JP7395215B2 (ja) 2023-12-11
CN111081768B (zh) 2021-12-10

Similar Documents

Publication Publication Date Title
WO2021103530A1 (fr) Structure à bits quantiques supraconducteurs extensibles bidimensionnels et son procédé de commande de mode de cavité
US9825843B2 (en) Die-stacked device with partitioned multi-hop network
JP2023029561A (ja) 量子チップ及びその構築方法、構築装置
JP5618603B2 (ja) 多層回路配列を設計する方法
JP4576538B2 (ja) 多次元のスイッチトポロジーを有する集積回路
WO1996012391A1 (fr) Interconnexion tridimensionnelle comportant des modules a connecteurs superieurs et inferieurs verticaux
DE19639247A1 (de) Schaltungsanordnung
CN113764399A (zh) 集成电路系统、制造集成电路的方法及存储介质
US11656662B2 (en) Layered super-reticle computing : architectures and methods
CN216083732U (zh) 一种量子芯片及一种量子计算机
Ahmed et al. Increasing interposer utilization: A scalable, energy efficient and high bandwidth multicore-multichip integration solution
JP5024530B2 (ja) 三次元集積電気回路の配線構造及びそのレイアウト方法
CN111786894B (zh) 实现片上网络传输带宽扩充功能的fpga装置
JP6951568B2 (ja) プレーナ量子デバイスにおいて垂直接続を制限する超電導共振器
KR101292773B1 (ko) 집적 장치
CN217690117U (zh) 一种量子芯片和量子计算机
TW201810581A (zh) 用於高頻寬記憶體介面之橋接晶粒設計
CN217181559U (zh) 量子芯片以及量子计算机
Li et al. Equinox: Equivalent noc injection routers for silicon interposer-based throughput processors
CN217982406U (zh) 一种量子芯片及量子计算机
EP1520298A1 (fr) Circuit integre pourvu de blocs constitutifs
CN219799831U (zh) 用于芯片互连的光学中介层
Ilyushin et al. Cluster self-organization of crystal-forming systems: Suprapolyhedral cluster precursors and self-assembly of the icosahedral structure of ZrZn22 (c F184)
CN118193445A (zh) 一种片上网络、逻辑芯片以及三维芯片
CN117494820A (zh) 一种量子芯片及量子计算机

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20892343

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022531594

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 202208472

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20200701

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20892343

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20892343

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09.01.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20892343

Country of ref document: EP

Kind code of ref document: A1