WO2021102696A1 - 一种红外发光二极管 - Google Patents

一种红外发光二极管 Download PDF

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Publication number
WO2021102696A1
WO2021102696A1 PCT/CN2019/121018 CN2019121018W WO2021102696A1 WO 2021102696 A1 WO2021102696 A1 WO 2021102696A1 CN 2019121018 W CN2019121018 W CN 2019121018W WO 2021102696 A1 WO2021102696 A1 WO 2021102696A1
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layer
emitting diode
light emitting
diode according
light
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PCT/CN2019/121018
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English (en)
French (fr)
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蔡均富
萧至宏
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天津三安光电有限公司
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Priority to JP2021513333A priority Critical patent/JP7227357B2/ja
Priority to PCT/CN2019/121018 priority patent/WO2021102696A1/zh
Priority to CN201980005977.3A priority patent/CN111819702B/zh
Priority to KR1020217009686A priority patent/KR102560008B1/ko
Publication of WO2021102696A1 publication Critical patent/WO2021102696A1/zh
Priority to US17/354,022 priority patent/US12009453B2/en
Priority to JP2023018074A priority patent/JP7432024B2/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the invention relates to the technical field of semiconductor optoelectronics, and more specifically, to an infrared light-emitting diode.
  • Infrared light-emitting diodes are a kind of diodes that emit infrared rays, which are used in security monitoring, wearable devices, infrared communications, infrared remote control devices, light sources for sensors, and night lighting, especially in the field of gas detection. Since flip-chip technology has the advantages of improving luminous efficiency, improving heat dissipation performance, and improving package reliability and yield, flip-chip technology has become an important chip technology.
  • the P-type semiconductor layer is usually made of P-type AlGaAs material, which is made with the current flip-chip bonding technology.
  • the transparent bonding layer SiO 2 material has poor adhesion to the epitaxial AlGaAs material. After the substrate is removed, the epitaxial layer is easily detached from the transparent bonding layer, resulting in extremely low bonding yield, and even bonding cannot be achieved.
  • the mesa etching of the infrared ternary epitaxy system needs to use a wet etching method, and the current red light flip chip process uses a dry etching method, which is also not applicable. Without changing the composition of the infrared light epitaxial layer, the current infrared light flip-chip manufacturing process cannot be realized.
  • the present invention changes the active layer in the red light epitaxial structure to the active layer of the infrared light epitaxial structure, and the rest of the epitaxial structure adopts the red light epitaxial structure. Without changing the current flip-chip process flow, the infrared light can be realized.
  • the flip-chip technology has a certain practicability.
  • the present invention provides an infrared light emitting diode characterized by comprising: a semiconductor light emitting series having an active layer of a quantum well structure in which well layers and barrier layers are alternately laminated, and sandwiching the active layer Layer of the first waveguide layer and the second waveguide layer, and the first cladding layer and the second cladding layer sandwiching the active layer via the first and second waveguide layers; the first waveguide layer and The second waveguide layer is composed of a compound semiconductor whose composition formula is (Al X3 Ga 1-X3 ) Y1 In 1-Y1 P (where 0 ⁇ X3 ⁇ 1, 0 ⁇ Y1 ⁇ 1).
  • the well layer is composed of a compound semiconductor with the composition formula (In X1 Ga 1-X1 )As
  • the barrier layer is composed of a compound semiconductor with the composition formula (Al X2 Ga 1-X2 )As, wherein 0 ⁇ X1 ⁇ 1. 0 ⁇ X2 ⁇ 1.
  • the first and second covering layers are composed of compound semiconductors with the composition formula (Al X4 Ga 1-X4 ) Y2 In 1-Y2 P, where 0 ⁇ X4 ⁇ 1, 0 ⁇ Y2 ⁇ 1.
  • it further includes a current spreading layer on the semiconductor light emitting series, and the current spreading layer is GaP.
  • it further includes a transparent substrate bonded to the current spreading layer.
  • the number of pairs of the well layer and the barrier layer is 10 pairs or less, and 1 pair or more.
  • the composition X1 of In of the well layer is set to 0.1 ⁇ X1 ⁇ 0.3.
  • the thickness of the well layer is 4-15 nm.
  • the transparent substrate is composed of GaP, sapphire or SiC.
  • the wavelength of light emitted by the semiconductor light emitting series is 680-1100 nm.
  • the thickness of the current spreading layer is 3-10 ⁇ m.
  • the surface of the current spreading layer is roughened to form a roughened surface, and the roughness of the roughened surface is 100-300 nm.
  • a transparent bonding layer is vapor-deposited on the roughened surface, and the transparent substrate is bonded to the current spreading layer through the transparent bonding layer.
  • the material of the transparent bonding layer is SiO 2 material with a thickness of 1 to 5 ⁇ m.
  • the Al composition X3 of the first and or second waveguide layers is set to 0.2 ⁇ X3 ⁇ 0.8, 0.3 ⁇ Y1 ⁇ 0.7.
  • the Al composition X4 of the first and or second coating layers is set to 0.2 ⁇ X4 ⁇ 0.8, 0.3 ⁇ Y1 ⁇ 0.7.
  • the main light emitting surface is a surface on the opposite side of the surface where the transparent substrate and the current spreading layer are joined.
  • a first electrode and a second electrode are further provided, and the first electrode and the second electrode are provided on a surface opposite to the main light-emitting surface of the light-emitting diode.
  • the first electrode and the second electrode are ohmic electrodes.
  • the present invention also provides a light-emitting diode package, including a mounting substrate and at least one light-emitting diode mounted on the mounting substrate, and at least one or more or all of the light-emitting diodes are the aforementioned light-emitting diodes.
  • the present invention also provides a light-emitting device, which is provided with any one of the aforementioned light-emitting diodes.
  • the present invention also provides a remote control device, which is provided with any one of the aforementioned light emitting diodes.
  • the light-emitting diode designed by the present invention includes the following beneficial effects:
  • the flip-chip fabrication of infrared light emitting diodes can be realized.
  • FIG. 1 is a schematic cross-sectional view of a light emitting diode according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of the active layer of the light-emitting diode according to Embodiment 1 of the present invention.
  • Example 3 is a schematic cross-sectional view of the epitaxial wafer used in the light-emitting diode of Example 1 of the present invention.
  • Example 4 is a schematic cross-sectional view of the bonding wafer used in the light-emitting diode of Example 1 of the present invention.
  • FIG. 5 is a schematic diagram of the structure of a package formed by using the light-emitting diode of Embodiment 1 of the present invention.
  • the present invention provides the following light-emitting diode 10, as shown in the schematic cross-sectional view of FIG. 1, which includes the following stacked layers: 001: a transparent substrate; 002: a transparent bonding layer; 003: a current spreading layer; 004: a lower cover layer; 005 : Lower waveguide layer; 006: active layer; 007: upper waveguide layer; 008: upper cladding layer; 009: first electrode; 010: second electrode.
  • the compound semiconductor layer 1 also called an epitaxial growth layer, has a structure in which a PN junction type semiconductor light emitting series 2 and a current spreading layer 003 are sequentially stacked as shown in FIG. 3.
  • the structure of the compound semiconductor layer 1 also includes other well-known functional layers, such as a contact layer for reducing the contact resistance of the ohmic electrode, and an n-type current spreading layer for spreading the driving current of the light-emitting diode in the entire plane.
  • the compound semiconductor layer 1 is preferably a layer formed by epitaxial growth on a GaAs substrate.
  • the main light-emitting surface in this embodiment is the surface on the opposite side of the surface where the transparent substrate 001 and the current spreading layer 003 are joined.
  • the transparent substrate 001 is bonded to the surface of the compound semiconductor layer 1 on the opposite side to the main light extraction surface via the transparent bonding layer 002.
  • the transparent bonding layer in this embodiment is made of SiO 2 material, and the transparent bonding layer 002 is formed on the current spreading layer 003 by evaporation.
  • the transparent substrate 001 has sufficient strength to mechanically support the semiconductor light emitting series 2 and can transmit light emitted from the semiconductor light emitting series 2, and is made of a material that is optically transparent with respect to the emission wavelength from the active layer 006.
  • a chemically stable material with excellent moisture resistance is preferable, and for example, it is preferable to use a material that does not contain Al which is easily corroded.
  • the transparent substrate 001 is a substrate with a thermal expansion coefficient close to that of the semiconductor light emitting series 2 and excellent moisture resistance performance, preferably a GaP, SiC or sapphire substrate with good thermal conductivity.
  • the thickness of the transparent substrate is preferably 50 ⁇ m or more.
  • the thickness is preferably not more than 300 ⁇ m.
  • the transparent substrate 001 is preferably a sapphire substrate.
  • Semiconductor light emitting series 2 as shown in FIG. 1, consists of stacking at least p-type lower cladding layer (first cladding layer) 004, lower waveguide layer 005, active layer 006, upper waveguide layer 007, n A type upper covering layer (second covering layer) 008 is formed.
  • the semiconductor light emitting series 2 is formed to include a lower cladding layer 004 and a lower waveguide arranged opposite to each other on the lower and upper sides of the active layer 006 in order to confine the carriers to emit light in the active layer 006 Double heterojunction structure of layer 005, upper waveguide layer 007, and upper cladding layer 008.
  • the active layer 006 forms a quantum well structure in order to adjust the emission wavelength of the light-emitting diode. That is, the active layer 006 has a multilayer structure having a barrier layer 012, a well layer 011, and a barrier layer 012 at both ends. When one well layer 011 and one barrier layer 012 are used as a pair of counter layers, the quantum well structure of five pairs of layers is composed of five well layers 011 and six barrier layers 012.
  • the thickness of the active layer 006 is preferably in the range of 0.02 to 2 ⁇ m.
  • the conductivity type of the active layer 006 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to improve the luminous efficiency, it is preferably undoped with good crystallinity or a carrier concentration lower than 3*10 17 cm -3.
  • the improvement of the crystallinity of the active layer 006 can reduce the defects of epitaxial growth, and can suppress the absorption of light in the epitaxial defects, thereby improving the luminous efficiency.
  • the well layer 011 is composed of a compound semiconductor having a composition formula of In X1 Ga 1-X1 As (0 ⁇ X1 ⁇ 1).
  • the composition of In is preferably 0.1 ⁇ X1 ⁇ 0.3.
  • the thickness of the well layer 011 is preferably in the range of 3 to 30 nm, and preferably in the range of 4 to 15 nm.
  • the barrier layer 012 is composed of a compound semiconductor having a composition formula (Al X2 Ga 1-X2 )As (0 ⁇ X2 ⁇ 1). In order to prevent the absorption of light in the barrier layer 012, it is preferable that the band gap of the barrier layer 012 be larger than that of the well layer. In addition, the barrier layer 012 preferably has a low Al concentration from the viewpoint of crystallinity. Therefore, the Al composition of the barrier layer 012 is preferably a composition of 0.05 to 0.5.
  • the thickness of the barrier layer 012 is preferably equal to or thicker than the thickness of the well layer 011.
  • the number of pairs of the well layer 011 and the barrier layer 012 alternately stacked is 10 pairs or less, and it may be one pair of layers. That is, it is preferable to include 0-10 well layers 011 in the active layer 006.
  • the smaller the number of quantum well layers the narrower the area where electrons and holes are enclosed, and the higher the probability of recombination of electrons and holes.
  • the number of pairs of the well layer 011 and the barrier layer 012 is preferably 10 pairs or less.
  • the bonding area of the active layer 006 and the lower cover layer 004 or the upper cover layer 008 is preferably 20,000 to 90,000 ⁇ m 2 .
  • the lower waveguide layer 005 and the upper waveguide layer 007 are provided under and above the active layer 006, respectively. Specifically, a lower guide layer 005 is provided under the active layer 006, and an upper guide layer 007 is provided on the upper surface of the active layer 006.
  • the lower guide layer 005 and the upper guide layer 007 are composed of (Al X3 Ga 1-X3 ) Y1 In 1-Y1 P (0 ⁇ X3 ⁇ 1, 0 ⁇ Y1 ⁇ 1) compound semiconductor, wherein the composition of Al X3 is preferably a band gap
  • the composition equal to or larger than the barrier layer is preferably in the range of 0.2 to 0.8, and Y1 is preferably in the range of 0.3 to 0.7.
  • the lower guide layer 005 and the upper guide layer 007 are provided to reduce the propagation of defects between the lower cover layer 004 and the upper cover layer 008 and the active layer 006, respectively.
  • the thickness of the lower waveguide layer 005 and the upper waveguide layer 007 is preferably 10 nm or more, and more preferably 20 nm to 100 nm.
  • the conduction types of the lower waveguide layer 005 and the upper waveguide layer 007 are not particularly limited, and any of undoped, p-type and n-type can be selected. In order to improve the luminous efficiency, undoped with good crystallinity or a carrier concentration lower than 3*10 17 cm -3 is preferred.
  • the lower cladding layer 004 and the upper cladding layer 008 are respectively arranged under the lower waveguide layer 005 and above the upper waveguide layer 007 as shown in FIG. 1.
  • the lower cladding layer 004 and the upper cladding layer 008 are composed of (Al X4 Ga 1-X4 ) Y2 In 1-Y2 P (0 ⁇ X4 ⁇ 1, 0 ⁇ Y2 ⁇ 1) compound semiconductors, preferably with a band gap larger than that of the barrier layer
  • the material is more preferably a material with a larger band gap than the lower waveguide layer 004 and the upper waveguide layer 006.
  • the Al composition X4 of (Al X4 Ga 1-X4 ) Y2 In 1-Y2 P is 0.2 to 0.8.
  • Y2 is preferably 0.3 to 0.7.
  • X4 is selected in a range that functions as a cover layer and is transparent to the emission wavelength. Since the cover layer is a thick film, from the viewpoint of lattice matching with the substrate, Y2 is preferably a range where high-quality crystal growth can be performed.
  • the lower cladding layer 004 and the upper cladding layer 008 are composed of different polarities.
  • the carrier concentration and thickness of the lower cladding layer 004 and the upper cladding layer 008 can be in a well-known suitable range, and the conditions are preferably optimized so that the luminous efficiency of the active layer 006 can be improved.
  • the warpage of the compound semiconductor layer 1 can be reduced.
  • the lower cladding layer 004 it is preferable to use, for example, a Mg-doped p-type (Al X4a Ga 1-X4a ) Y2a In 1-Y2a P (0.2 ⁇ X4a ⁇ 0.8, 0.3 ⁇ Y2a ⁇ 0.7).
  • Semiconductor material the carrier concentration is preferably in the range of 7*10 17 to 3*10 18 cm -3 , and the layer thickness is preferably in the range of 0.1 to 1 ⁇ m.
  • the upper cladding layer 008 it is preferable to use, for example, a Si-doped n-type (Al X4b Ga 1-X4b ) Y2b In 1-Y2b P (0.2 ⁇ X4b ⁇ 0.8, 0.3 ⁇ Y2b ⁇ 0.7).
  • Semiconductor material the carrier concentration is preferably in the range of 7*10 17 to 3*10 18 cm -3 , and the layer thickness is preferably in the range of 0.1 to 1 ⁇ m.
  • the polarity of the lower cladding layer 004 and the upper cladding layer 008 can be selected in combination with the element structure of the compound semiconductor.
  • a contact layer for reducing the contact resistance of the ohmic electrode a current diffusion layer for spreading the element drive current flatly throughout the semiconductor light emitting series, and vice versa can be provided.
  • a known layer structure such as a current blocking layer that limits the current flow area of the element drive.
  • the current spreading layer 003 is disposed under the semiconductor light emitting series 2.
  • the current spreading layer 003 can reduce the strain generated by the active layer 006 when the compound semiconductor layer 1 is epitaxially grown on the GaAs substrate.
  • the current spreading layer 003 may use a material that is transparent to the emission wavelength from the active layer 006, such as GaP.
  • the thickness of the current spreading layer 003 is preferably in the range of 3 to 10 ⁇ m. This is because when the thickness of the current spreading layer 003 is 3 ⁇ m or less, the current spreading is insufficient. If the thickness of the current spreading layer 003 is 10 ⁇ m or more, the manufacturing cost of the light emitting diode will increase.
  • the current spreading layer 003 is roughened by solution etching, and an irregular cone-shaped surface is formed after roughening.
  • the transparent bonding layer 002 is formed on the roughened surface by vapor deposition. By roughening the current spreading layer 003, the bonding effect of the current spreading layer 003 and the transparent bonding layer 002 after the roughening treatment is better.
  • the transparent bonding layer in this embodiment is SiO 2 with a thickness of 1 to 5 ⁇ m.
  • the compound semiconductor layer 1 is bonded to the transparent substrate 001 through the transparent bonding layer 002.
  • the first electrode 009 and the second electrode 010 are provided on a surface opposite to the main light-emitting surface of the light-emitting diode.
  • the first electrode and the second electrode are ohmic electrodes.
  • the first electrode n-type ohmic electrode
  • the second electrode P-type ohmic electrode
  • the P-type ohmic electrode 010 as the second electrode on the current spreading layer 003, that is, on the current spreading layer composed of p-type GaP, and a good ohmic contact can be obtained. Reduce the operating voltage.
  • a compound semiconductor layer 1 is formed on the growth substrate GaAs substrate 013.
  • the compound semiconductor layer 1 includes a buffer layer 014 composed of GaAs, an etching stop layer 015 provided for use in selective etching, and an n-type Si-doped (Al X5 Ga 1-X5 ) Y3 In 1- Y3 P (0 ⁇ X5 ⁇ 1, 0 ⁇ Y3 ⁇ 1) composed of contact layer 016, n-type upper cladding layer 008, upper waveguide layer 007, active layer 006, lower waveguide layer 005, p-type lower cladding layer 004 , A current spreading layer 003 composed of Mg-doped P-type GaP.
  • the GaAs substrate 013 a commercially available single crystal substrate produced by a known manufacturing method can be used.
  • the surface of the GaAs substrate 013 on which the epitaxial growth is performed is preferably smooth. From the viewpoint of quality stability, it is preferable that the plane orientation of the surface of the GaAs substrate 013 is a (100) plane that is easy to epitaxially grow and mass-produce, and a substrate shifted within ⁇ 20° from (100). In addition, the more preferable range of the plane orientation of the GaAs substrate 013 is a deviation of 15° ⁇ 5° from the (100) direction to the (0-1-1) direction.
  • the GaAs substrate 013 has a low dislocation density. Specifically, for example, it is desired to be 10,000 cm -2 or less, and preferably 1,000 cm -2 or less.
  • the GaAs substrate is n-type, generally doped with Si, and preferably has a carrier concentration in the range of 1*10 17 to 5*10 18 cm -3 .
  • the thickness of the GaAs substrate 013 has an appropriate range according to the size of the substrate. If the thickness of the GaAs substrate 013 is relatively thin, cracks are likely to occur during the manufacturing process of the compound semiconductor. On the other hand, if the thickness of the GaAs substrate 013 is too thick, the material cost will increase. Therefore, when the size of the GaAs substrate 013 is large, for example, when the diameter is 75 mm, in order to prevent cracks during the manufacturing process, the thickness of the GaAs substrate 013 is preferably 250 to 500 ⁇ m. Similarly, when the diameter is 50 mm, the thickness is preferably 200 to 400 ⁇ m, and when the diameter is 100 mm, the thickness is preferably 350 to 600 ⁇ m.
  • the warpage of the compound semiconductor layer 1 caused by the active layer 006 can be reduced.
  • the temperature distribution in the epitaxial growth becomes uniform, so the uniformity of the wavelength distribution in the plane of the active layer can be improved.
  • the buffer layer 014 is provided to reduce the propagation of defects in the constituent layers of the GaAs substrate 013 and the semiconductor light emitting series 2.
  • the material of the buffer layer 014 is preferably the same material as the substrate for epitaxial growth. Therefore, in this embodiment, the buffer layer 014 is preferably GaAs, which is the same material as the GaAs substrate 013.
  • the buffer layer 014 may also use a multilayer film made of a material different from the GaAs substrate.
  • the thickness of the buffer layer 014 is preferably 0.1 ⁇ m or more, and more preferably 0.2 ⁇ m or more.
  • the contact layer 016 is provided to reduce the contact resistance with the electrode.
  • the material of the contact layer 016 is a material with a larger band gap than the active layer 006, and AlGaInP can be used well.
  • the lower limit of the carrier concentration of the contact layer 016 is preferably 5*10 17 cm -3 or more, and more preferably 1*10 18 cm -3 or more in order to reduce the contact resistance with the electrode.
  • the upper limit of the carrier concentration is preferably 2*10 19 cm -3 or less, which easily causes a decrease in crystallinity.
  • the thickness of the contact layer 016 is preferably 0.5 ⁇ m or more, most preferably 1 ⁇ m or more.
  • the upper limit of the thickness of the contact layer 016 is not particularly limited, but in order to set the cost of epitaxial growth in an appropriate range, it is preferably 5 ⁇ m or less.
  • the surface of the current spreading layer 003 of the compound semiconductor layer 1 is roughened by solution etching to form a roughened surface; the transparent bonding layer 002 is vapor-deposited on the surface of the roughened surface.
  • the transparent bonding layer material is SiO 2 with a thickness of 2 ⁇ m.
  • the transparent bonding layer 002 is polished to form a flat surface; the above structure is bonded to the transparent substrate 001, this embodiment
  • the transparent substrate 001 is a sapphire substrate.
  • the epitaxial growth substrate GaAs substrate 013, the buffer layer 014 and the etching stop layer 015 are thinned and removed by chemical etching to expose the contact layer 016, and a first electrode 009 is fabricated on the contact layer 016; for the contact layer 016, the upper cover layer 008 ,
  • the upper guide layer 007, the active layer 006, the lower guide layer 005, and the P-type lower cladding layer 004 are selectively etched away in a predetermined range, so that the current spreading layer 003 leaks, and a second is formed on the exposed current spreading layer 003 Eletrode 010.
  • the transparent substrate is thinned by grinding and laser cutting to form independent light-emitting diodes.
  • the present invention also provides a package as shown in FIG. 5.
  • At least one light-emitting diode in Embodiment 1 of the present invention is mounted on the mounting substrate 30.
  • the mounting substrate 30 is an insulating substrate, and one surface of the mounting substrate 30 is electrically isolated.
  • the light emitting diode 10 is located on a surface of the mounting substrate 30.
  • the first electrode 009 and the second electrode 010 of the light emitting diode 10 pass through the first coupling portion 303 and the second coupling portion 304, respectively, and the first electrode terminal 301 and the second electrode terminal 302. connection.
  • the first bonding portion 303 and the second bonding portion 304 include but are not limited to solder, such as eutectic solder or reflow solder.
  • the light emitting diode manufactured in this embodiment is an infrared light emitting diode having an active layer composed of a quantum well structure composed of a well layer composed of InGaAs and a barrier layer composed of AlGaAs.
  • the compound semiconductor layer grown on the GaAs substrate and the transparent substrate are combined to form a light emitting diode.
  • the combined area of the active layer and the cover layer is 60,000 ⁇ m 2 (300 ⁇ m*200 ⁇ m).
  • Example 1 In the light emitting diode of Example 1, first, compound semiconductor layers were sequentially laminated on a GaAs substrate composed of Si-doped n-type GaAs single crystals to form an epitaxial wafer with a light emitting wavelength of 830 nm.
  • a GaAs substrate composed of Si-doped n-type GaAs single crystals
  • the carrier concentration is set to 2*10 18 cm -3 .
  • the thickness of the GaAs substrate is approximately 0.5 ⁇ m.
  • the compound semiconductor layer comprising: a buffer layer made of undoped Si-GaAs, the etching stop layer composed of Ga 0.5 In 0.5 P, n is type Si-doped (Al 0.6 Ga 0.4) 0.5 In 0.5 P configuration
  • a metal organic chemical vapor deposition apparatus (MOCVD apparatus) is used to epitaxially grow a compound semiconductor layer on a GaAs substrate with a diameter of 100 mm and a thickness of 350 ⁇ m to form an epitaxial wafer.
  • MOCVD apparatus metal organic chemical vapor deposition apparatus
  • Mg bis-cyclopentadienyl magnesium (bis-(C 5 H 5 ) 2 Mg) is used.
  • Si disilane (Si 2 H 6 ) is used.
  • the current spreading layer composed of P-type GaP is grown at 750°C or higher, and the other layers are grown at 680-750°C.
  • the buffer layer made of GaAs has a thickness of about 0.3 ⁇ m.
  • the carrier concentration is set to 1*10 18 cm -3 and the layer thickness is set to about 3 ⁇ m.
  • the upper cover layer has a carrier concentration of about 1*10 18 cm -3 and a layer thickness of about 0.5 ⁇ m.
  • the upper guide layer is undoped and its layer thickness is about 80 nm.
  • the well layer is undoped In 0.2 Ga 0.8 As with a thickness of about 5.5 nm, and the barrier layer is undoped Al 0.2 Ga 0.8 As with a thickness of about 15 nm.
  • the lower guide layer is undoped and has a layer thickness of 0.2 ⁇ m.
  • the carrier concentration of the lower covering layer is 1.5*10 18 cm -3 , and the layer thickness is about 0.4 ⁇ m.
  • the carrier concentration in the middle layer is 1*10 18 cm -3 , and the current spreading layer composed of GaP has a carrier concentration of 4*10 18 cm -3 and the thickness is about 8 ⁇ m.
  • the surface of the current spreading layer GaP of the compound semiconductor layer is roughened to form a roughened surface; the surface of the roughened surface is vapor-deposited with a transparent bonding layer SiO 2 with a thickness of 2 ⁇ m.
  • the transparent bonding layer is polished after deposition to form a flat surface; the above structure is bonded to the transparent sapphire substrate.
  • the epitaxial growth substrate GaAs substrate and the buffer layer and the etching stop layer are removed to expose the contact layer, and the first electrode is fabricated above the contact layer; the part is selectively etched and removed by means of a photolithography mask
  • the upper covering layer, the upper guiding layer, the active layer, the lower guiding layer, and the P-type lower covering layer of the P-type lower covering layer expose the current spreading layer, and a second electrode is formed on the exposed current spreading layer.
  • Embodiment 1 The difference from Embodiment 1 is that in this embodiment, the material of the upper waveguide layer and the lower waveguide layer is AlGaAs, except that the same conditions as in Embodiment 1 are used to manufacture the light-emitting diode.
  • Example 1 a current was passed between the n-type and p-type ohmic electrodes, and infrared light with a peak emission wavelength of 830 nm was emitted.
  • the forward voltage (Vf) when a current of 5 milliamperes (mA) flows in the forward direction reflects the bonding interface between the current spreading layer constituting the compound semiconductor layer and the transparent substrate. Low resistance characteristics and good ohmic contact characteristics of each ohmic electrode, the Vf1 is 1.95V.
  • the luminous output power (P 0 ) is 2mW.
  • the light-emitting diode in Example 2 was tested, and when the forward current was 5 mA, its light-emitting output power (P 0 ) and forward voltage (Vf1) were 1 mW and 3.0V, respectively.
  • the experimental results show that when the waveguide layer is AlInP, compared to using AlGaAs as the waveguide layer, the optical output power (P 0 ) is higher and the forward voltage (Vf1) is lower. This is due to the epitaxial growth of the waveguide layer on the cover layer AlGaInP In the case of AlGaAS, defects will occur on the interface, which will affect the luminous efficiency and forward voltage of the light-emitting diode.

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Abstract

一种红外发光二极管（10），其特征在于，具备：半导体发光系列（2），该半导体发光系列（2）具有交替地层叠有阱层（011）和垒层（012）的量子阱结构的活性层（006）、夹持所述活性层（006）的第1波导层（005）和第2波导层（007）、以及隔着所述第1波导层（005）和第2波导层（007）夹持所述活性层（006）的第1覆盖层（004）和第2覆盖层（008）；所述第1波导层（005）和第2波导层（007）由组成式为(Al X3Ga 1-X3) Y1In 1-Y1P(0≤X3≤1，0＜Y1≤1)的化合物半导体组成；原红外光外延结构因倒装工艺会有键合良率低和台面蚀刻问题，无法实现倒装发光二极管的制作。通过使用上述外延系统材料，可实现红外光发光二极管（10）倒装工艺的制作。

Description

一种红外发光二极管 技术领域
本发明涉及半导体光电技术领域，更具体地说，涉及的是一种红外发光二极管。
背景技术
红外发光二极管是一种能发出红外线的二极管，应用于安全监控、穿戴式装置、红外线通信、红外线遥控装置、传感器用光源及夜间照明等领域，特别是气体检测领域。由于倒装技术具有提升发光效率、提升散热性能、提升封装可靠性及良率的优势，倒装技术成为一种重要的芯片技术。
在常见的红外光的三元外延系统中，P型半导体层通常为P型AlGaAs材料，用现行的倒装键合技术去做，透明键合层SiO 2材料与外延AlGaAs材料附着度很差，去除衬底后，外延层容易从透明键合层上脱落，导致键合良率极低，甚至无法实现键合。另外红外光的三元外延系统的台面蚀刻需要使用湿蚀刻方式，而目前红光倒装工艺使用的是干蚀刻方式，这也是不适用的。在不改变红外光的外延层的组成的情况下，无法实现目前红外光倒装工艺的制作。
发明概述
技术问题
问题的解决方案
技术解决方案
鉴于以上问题，本发明通过改变红光外延结构中的活性层为红外光外延结构的活性层，其余外延结构套用红光的外延结构，无需变更目前的倒装工艺流程，就可以实现红外光的倒装工艺，具有一定的实用性。
为了实现上述目的，本发明提供一种红外发光二极管，其特征在于，具备：半导体发光系列，该半导体发光系列具有交替地层叠阱层和垒层的量子阱结构的活性层、夹持所述活性层的第1波导层和第2波导层、以及隔着所述第1波导层和第2波导层夹持所述活性层的第1覆盖层和第2覆盖层；所述第1波导层和第2波导 层由组成式为(Al X3Ga 1-X3) Y1In 1-Y1P(其中0≤X3≤1、0＜Y1≤1)的化合物半导体组成。
优选地，所述阱层由组成式为(In X1Ga 1-X1)As的化合物半导体构成，垒层由组成式为(Al X2Ga 1-X2)As的化合物半导体构成，其中0≤X1≤1、0≤X2≤1。
优选地，所述第1和第2覆盖层由组成式为(Al X4Ga 1-X4) Y2In 1-Y2P的化合物半导体组成，其中0≤X4≤1、0＜Y2≤1。
优选地，还具备在所述半导体发光系列上的电流扩展层，所述电流扩展层为GaP。
优选地，还具备与所述电流扩展层接合的透明基板。
优选地，所述阱层和垒层的对数为10对以下，1对以上。
优选地，所述阱层的In的组成X1设定为0.1≤X1≤0.3。
优选地，所述阱层的厚度为4～15nm。
优选地，所述透明基板由GaP、蓝宝石或SiC构成。
优选地，所述半导体发光系列发射出的光的波长为680～1100nm。
优选地，所述电流扩展层的厚度为3～10μm。
优选地，对所述电流扩展层的表面进行粗化，形成粗化面，该粗化面的粗糙度为100～300nm。
优选地，在所述粗化面上蒸镀透明键合层，所述透明基板通过该透明键合层键合在所述电流扩展层上。
优选地，所述透明键合层的材料为SiO 2材料，其厚度为1～5μm。
优选地，所述第1和或第2波导层的Al的组成X3设定为0.2≤X3≤0.8，0.3≤Y1≤0.7。
优选地，所述第1和或第2覆盖层的Al的组成X4设定为0.2≤X4≤0.8，0.3≤Y1≤0.7。
优选地，主要出光面为所述透明基板与电流扩展层接合的面的相反侧的面。
优选地，还具备第1电极和第2电极，所述第1电极和第2电极设置在发光二极管的所述主要出光面的相反侧的面。
优选地，所述第1电极和第2电极为欧姆电极。
本发明同时提供一种发光二极管封装体，包括安装基板和安装在所述安装基板上的至少一个发光二极管，所述发光二极管至少一个或多个或全部为前述的一种发光二极管。
本发明还提供一种发光装置，该发光装置具备任一项前述的发光二极管。
本发明还提供一种遥控装置，该遥控装置具备任一项前述的发光二极管。
发明的有益效果
有益效果
如上所述，本发明设计的发光二极管，包括以下有益效果：
通过变更红光外延系统中的活性层部分为红外光外延系统InGaAs/AlGaAs材料，在不变更现有的倒装工艺流程的情况下，可实现红外光发光二极管的倒装工艺的制作。
对附图的简要说明
附图说明
图1为本发明实施例1的发光二极管的截面示意图。
图2为本发明实施例1的发光二极管的活性层的示意图。
图3为本发明实施例1的发光二极管中使用的外延晶片的截面示意图。
图4为本发明实施例1的发光二极管中使用的接合晶片的截面示意图。
图5为使用本发明实施例1的发光二极管形成的封装体的结构示意图。
图中元件标号说明：
001                  透明基板
002                  透明键合层
003                  电流扩展层
004                  下部覆盖层
005                  下部波导层
006                  活性层
007                  上部波导层
008                  上部覆盖层
009                  第一电极
010                  第二电极
011                  阱层
012                  垒层
013                  GaAs基板
014                  缓冲层
015                  腐蚀截止层
016                  接触层
10                   发光二极管
1                    化合物半导体层
2                    半导体发光系列
30                   安装基板
301                  第一电极端子
302                  第二电极端子
303                  第一结合部
304                  第二结合部
发明实施例
本发明的实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施例加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例1
本发明提供如下一种发光二极管10，如图1所示的剖面示意图，其包括如下堆叠层：001：透明基板；002：透明键合层；003：电流扩展层；004：下部覆盖层；005：下部波导层；006：活性层；007：上部波导层；008：上部覆盖层；009：第一电极；010：第二电极。
下面针对各结构堆叠层进行详细描述。
化合物半导体层1，也称为外延生长层，如图3所示，具有依次层叠有PN结型的半导体发光系列2和电流扩展层003的结构。在该化合物半导体层1的结构中，还包括其他公知的功能层，例如用于降低欧姆电极的接触电阻的接触层，用于使发光二极管的驱动电流在整个平面内扩散的n型电流扩展层。再者，化合物半导体层1优选为在GaAs基板上外延生长形成的层。
本实施例中的主要出光面为所述透明基板001与电流扩展层003接合的面的相反侧的面。
透明基板001通过透明键合层002键合在化合物半导体层1的与主要的光取出面相反侧的面上。本实施例中的透明键合层为SiO 2材料，通过蒸镀在电流扩展层003上形成透明键合层002。该透明基板001具有足以机械性地支撑半导体发光系列2的强度，并且能透过从半导体发光系列2射出的光，由相对于来自活性层006的发光波长在光学上透明的材料构成。另外，优选耐湿性优异的化学上稳定的 材质，例如优选采用不含有容易腐蚀的Al等的材质。
透明基板001为热膨胀系数与半导体发光系列2接近、耐湿性性能优异的基板，优选导热性能良好的GaP、SiC或蓝宝石衬底。为了能够以充分的机械强度支撑半导体发光系列2，透明基板的厚度优选为50μm以上。另外，为了便于在向化合物半导体层1键合后对透明基板001的机械加工，优选为厚度不超过300μm的厚度。本实施例中，优选透明基板001为蓝宝石基板。
半导体发光系列2，如图1所示，由在电流扩展层003上至少依次层叠p型的下部覆盖层(第1覆盖层)004、下部波导层005、活性层006、上部波导层007、n型的上部覆盖层(第2覆盖层)008而构成。为了得到高强度的发光，优选半导体发光系列2形成为：为了将载流子限制在活性层006里发光而含有在活性层006的下侧和上侧对峙地配置的下部覆盖层004、下部波导层005和上部波导层007、上部覆盖层008的双异质结结构。
活性层006，如图所示2，为了可调节发光二极管的发光波长，形成量子阱结构。即活性层006为在两端具有垒层012、阱层011与垒层012的多层结构。在将一个阱层011和一个垒层012作为一对的对层的情况下，5对的对层数的量子阱结构由5层阱层011和6层垒层012构成的。
活性层006的层厚优选为0.02～2μm的范围。活性层006的传导类型没有特别的限定，无掺杂、p型和n型的任一种都可以选择。为了提高发光效率，优选为结晶性良好的无掺杂或低于3*10 17cm -3的载流子浓度。通过活性层006的结晶性提高可减少外延生长的缺陷，可抑制外延缺陷中光的吸收，从而提高发光效率。
阱层011由组成式为In X1Ga 1-X1As(0≤X1≤1)的化合物半导体构成。In的组成优选为0.1≤X1≤0.3。通过将阱层011的In组成X1设为该范围，可以实现发光二极管的发光波长在680～1100nm的范围内。固定阱层011的厚度，阱层011In的组成(X1)越高，发光波长就越长。
阱层011的层厚为3～30nm的范围较合适，优选为4～15nm的范围。
垒层012由组成式为(Al X2Ga 1-X2)As(0≤X2≤1)的化合物半导体构成。为了防止光在垒层012的吸收，优选垒层012的带隙比阱层的大。另外，垒层012从结晶性的角度出发考虑，优选Al的浓度低。因此，垒层012的Al的组成优选为0.05～0.5的 组成。
垒层012的层厚优选与阱层011的层厚相等或比阱层011的层厚厚。通过使垒层012的层厚在产生隧道效应的范围内充分地增厚，兼顾隧道效应所引起的阱层011的结合和扩展的限制，载流子的封入效果增大，电子和空穴的发光再结合概率变大，能够提高发光效率。
在本发明的发光二极管中，阱层011和垒层012的多层结构中，交替层叠阱层011和垒层012的对数为10对层以下，为1对层也可以。即优选在活性层006中包含0～10层的阱层011。多量子阱结构的活性层的情况下，量子阱层的数量越少，电子和空穴被封入的区域变得越窄，电子和空穴的发光再结合的概率变高；另外，由于阱层011和垒层012之间存在晶格失配，如果对层数过多，则由于晶体缺陷的产生，发光效率会降低。因此，优选阱层011和垒层012的对层数在10对以下。
活性层006与下部覆盖层004或上部覆盖层008的结合面积优选为20000～90000μm 2。
下部波导层005和上部波导层007分别被设置在活性层006的下面和上面。具体地讲，在活性层006的下面设置有下部引导层005，并在活性层006的上面设置有上部引导层007。
下部引导层005和上部引导层007由(Al X3Ga 1-X3) Y1In 1-Y1P(0≤X3≤1、0＜Y1≤1)化合物半导体组成，其中Al的组成X3优选为带隙与垒层相等或比其大的组成，优选为0.2～0.8的范围，Y1优选为0.3～0.7的范围。
下部引导层005和上部引导层007分别是为了降低下部覆盖层004和上部覆盖层008与活性层006之间的缺陷的传播而设置的。下部波导层005和上部波导层007的层厚优选为10nm以上，更优选为20nm～100nm。
下部波导层005和上部波导层007的传导类型没有特别的限定，无掺杂、p型和n型的任一种都可以选择。为了提高发光效率，优选结晶性良好的无掺杂或低于3*10 17cm -3的载流子浓度。
下部覆盖层004和上部覆盖层008，如附图1所示，分别被被配置在下部波导层005的下面和上部波导层007的上面。下部覆盖层004和上部覆盖层008由(Al X4Ga 1-X4) Y2In 1-Y2P(0≤X4≤1、0＜Y2≤1)的化合物半导体组成，优选带隙比垒层大的材质，更优选带隙比下部波导层004和上部波导层006大的材质。为了满足上述条件，优选具有(Al X4Ga 1-X4) Y2In 1-Y2P的Al组成X4为0.2～0.8的组成。另外，Y2优选为0.3～0.7。X4在作为覆盖层发挥功能，并且相对于发光波长透明的范围选择，由于覆盖层为厚膜，因此从与基板的晶格匹配的观点出发，Y2优选为能够进行优质的晶体生长的范围。
下部覆盖层004和上部覆盖层008以极性不同的方式组成。下部覆盖层004和上部覆盖层008的载流子浓度以及厚度，可以采用公知的合适的范围，优选将条件最佳化，使得活性层006的发光效率可以提高。另外，通过控制下部覆盖层004和上部覆盖层008的组成，可以使化合物半导体层1的翘曲降低。
具体地讲，作为下部覆盖层004，优选使用例如由掺杂Mg的p型的(Al X4aGa 1-X4a) Y2aIn 1-Y2aP(0.2≤X4a≤0.8、0.3＜Y2a≤0.7)构成的半导体材料。另外，载流子浓度优选为7*10 17～3*10 18cm -3的范围，层厚优选为0.1～1μm的范围。
另一方面，作为上部覆盖层008，优选使用例如由掺杂Si的n型的(Al X4bGa 1-X4b) Y2bIn 1-Y2bP(0.2≤X4b≤0.8、0.3＜Y2b≤0.7)构成的半导体材料。另外，载流子浓度优选为7*10 17～3*10 18cm -3的范围，层厚优选为0.1～1μm的范围。
下部覆盖层004和上部覆盖层008的极性可以结合化合物半导体的元件结构进行选择。
另外，在半导体发光系列2的构成层的上方，可以设置用于降低欧姆电极的接触电阻的接触层、用于使元件驱动电流在整个半导体发光系列平面性地扩散的电流扩散层、相反地用于限制元件驱动电流流通区域的电流阻止层等公知的层结构。
电流扩展层003，设置在半导体发光系列2的下方、该电流扩展层003可使化合物半导体层1在GaAs基板上外延生长时因活性层006而产生的应变减小。
电流扩展层003可以应用相对于来自活性层006的发光波长透明的材料，例如GaP。电流扩展层003的厚度优选为3～10μm的范围。因为电流扩展层003的厚度为3μm以下时，电流扩展不充分，如果电流扩展层003的厚度为10μm以上时，发光二极管的制作成本会增大。
电流扩展层003利用溶液蚀刻的方式进行粗化，粗化后形成不规则的锥状表面。通过蒸镀的方式在粗化面上形成透明键合层002。通过对电流扩展层003进行粗化，粗化处理后电流扩展层003与透明键合层002的键合效果较好。本实施例中的透明键合层为SiO 2，厚度为1～5μm。化合物半导体层1通过透明键合层002键合在透明基板001上。
第1电极009和第2电极010设置在发光二极管的所述主要出光面的相反侧的面。所述第1电极和第2电极为欧姆电极。其中第1电极(n型欧姆电极)被设置在上部覆盖层008的上方，可以使用由例如AuGe、Ni合金/Au形成的合金。另一方面，第2电极(P型欧姆电极)可以在露出的电流扩展层003的表面使用由AuBe/Au、或AuZn/Au形成的合金。
在本实施例的发光二极管中，优选将作为第2电极的P型欧姆电极010形成于电流扩展层003上，即由p型GaP构成的电流扩展层上，可得到良好的欧姆接触，因此可以降低工作电压。
下面对实施例1中所述发光二极管的制作方法进行说明。
首先，如图3所示，在生长衬底GaAs基板上013上形成化合物半导体层1。该化合物半导体层1包括依次层叠的由GaAs构成的缓冲层014、为了在选择蚀刻中利用而设置的腐蚀截止层015、掺杂Si的n型的(Al X5Ga 1-X5) Y3In 1-Y3P(0≤X5≤1、0＜Y3≤1)构成的接触层016、n型的上部覆盖层008、上部波导层007、活性层006、下部波导层005、P型的下部覆盖层004、由掺杂Mg的P型GaP构成的电流扩展层003。
GaAs基板013可以使用由公知的制法制作的市场上销售的单晶基板。GaAs基板013进行外延生长的表面优选是平滑的。从品质的稳定性方面出发，优选：GaAs基板013的表面的面取向为容易外延生长并量产的(100)面以及从(100)在±20°以内偏移的基板。而且，更优选的GaAs基板013的面取向的范围为从(100)方向向(0-1-1)方向偏移15°±5°。
为了使长在GaAs基板013上的化合物半导体的晶体质量好，优选GaAs基板013的位错密度低。具体地讲，例如，希望为10000个cm -2以下，优选的为1000个cm -2以下。GaAs基板为n型的，一般掺杂Si，优选其载流子浓度为1*10 17～5*10 18cm -3的范围。
GaAs基板013的厚度根据基板的尺寸有适当的范围。如果GaAs基板013的厚度比较薄，则在化合物半导体的制作过程中容易发生龟裂。另一方面，GaAs基板013的厚度过厚，则材料的成本会增加。因此，在GaAs基板013的尺寸大的情况下，例如，直径为75mm的情况下，为了防止制作过程中的开裂，优选GaAs基板013的厚度为250～500μm的厚度。同样地，在直径为50mm的情况下，优选为200～400μm的厚度，在直径为100mm的情况下，优选为350～600μm的厚度。
通过根据GaAs基板013的基板尺寸来增厚基板的厚度，可以降低起因于活性层006的化合物半导体层1的翘曲。外延生长中的温度分布变得均匀，因此可以提升活性层的面内的波长分布的均匀性。
缓冲层014是为了降低GaAs基板013和半导体发光系列2的构成层的缺陷的传播而设置的。缓冲层014的材质优选为与进行外延生长的基板相同的材质。因此，在本实施例中，缓冲层014优选为与GaAs基板013的同样的材质GaAs。另外，为了降低缺陷的传播，缓冲层014也可以使用由不同于GaAs基板的材质构成的多层膜。缓冲层014的厚度优选为0.1μm以上，更优选为0.2μm以上。
接触层016是为了降低与电极的接触电阻而设置的。优选接触层016的材质为带隙比活性层006大的材质，可以很好地使用AlGaInP。另外，接触层016的载流子浓度的下限值，为了降低与电极的接触电阻而优选为5*10 17cm -3以上，更优选为1*10 18cm -3以上。载流子浓度的上限值优选为容易引起结晶性降低的2*10 19cm -3以下。接触层016的厚度优选为0.5μm以上，最佳为1μm以上。接触层016的厚度的上限值没有特别限定，但为了将外延生长的成本设在适当范围而优选为5μm以下。
然后，如图4所示，通过溶液蚀刻的方式，在化合物半导体层1的电流扩展层003的表面进行粗化，形成粗化面；在粗化面的表面蒸镀透明键合层002，本实施例中，所述透明键合层材料为SiO 2，厚度为2μm，所述透明键合层002在沉积后经抛光处理，形成平坦面；将上述结构键合至透明基板001上，本实施例中，所述透明基板001为蓝宝石基板。
接着外延生长衬底GaAs基板013和缓冲层014以及腐蚀截止层015经过减薄、化 学腐蚀去除，露出接触层016，在接触层016上方制作第一电极009；对于接触层016，上部覆盖层008、上部引导层007、活性层006、下部引导层005、P型的下部覆盖层004的规定范围选择性地蚀刻去除，使电流扩展层003漏出，在该露出的电流扩展层003上形成第二电极010。
最后，通过研磨减薄透明基板，激光切割形成独立的发光二极管。
另外，本发明同时提供如图5所示的封装体，至少本发明实施例1中的一个发光二极管安装到安装基板30上，安装基板30为绝缘性基板，安装基板30的一表面具有电隔离的第一电极端子301和第二电极端子302。发光二极管10位于安装基板30的一表面上，发光二极管10的第一电极009和第二电极010分别通过第一结合部303和第二结合部304与第一电极端子301和第二电极端子302连接。第一结合部303和第二结合部304包括但不限于是焊料，如共晶焊或回流焊料。
使用具体的实施例来说明本发明的效果。本发明并不限定于这些实施例。
在本实施例中，具体地说明本发明设计的发光二极管的例子。在本实施例中制成的发光二极管，是具有由InGaAs构成的阱层和由AlGaAs构成的垒层的量子阱结构构成的活性层的红外发光二极管。在本实施例中，使在GaAs基板上生长的化合物半导体层和透明基板结合制成发光二极管。
实施例1的发光二极管，活性层和覆盖层的结合面积为60000μm 2(300μm*200μm)。
实施例1中的发光二极管，首先，在由掺杂Si的n型的GaAs单晶构成的GaAs基板上，依次层叠化合物半导体层制成发光波长为830nm的外延晶片。GaAs基板，以从(100)面向(0-1-1)方向倾斜了15°的面为生长面，载流子浓度设为2*10 18cm -3。另外，GaAs的基板的厚度约为0.5μm。作为化合物半导体层，包含：由未掺杂Si的GaAs构成的缓冲层、由Ga 0.5In 0.5P构成的腐蚀阻止层、由掺杂Si的(Al 0.6Ga 0.4) 0.5In 0.5P构成的n型的接触层、由掺杂Si的Al 0.5In 0.5P构成的n型的上部覆盖层、由(Al 0.7Ga 0.3) 0.5In 0.5P构成的上部波导层、由In 0.2Ga 0.8As/Al 0.2Ga 0.8P的对构成的阱层/垒层、由(Al 0.7Ga 0.3) 0.5In 0.5P构成的下部波导层、由掺杂Mg的Al 0.5In 0.5P构成的p型的下部覆盖层、由(Al 0.4Ga 0.6) 0.5In 0.5P构成的薄膜的中间过渡层和由掺杂Mg的P型GaP构成的电流扩展层。
在本实施例中，采用有机金属化学气相沉积装置(MOCVD装置)，在直径为100mm、厚度为350μm的GaAs基板上外延生长化合物半导体层，形成了外延晶片。在生长外延生长层时，作为III族构成元素的原料，使用三甲基铝((CH 3) 3Al)、三甲基镓((CH 3) 3Ga)和三甲基铟((CH 3) 3In)。作为Mg的掺杂原料，使用双环戊二烯基镁(bis-(C 5H 5) 2Mg)。作为Si的掺杂原料，使用乙硅烷(Si 2H 6)。另外，作为V族构成元素的原料，使用了磷烷(PH 3)和砷烷(AsH 3)。作为各层的生长温度，由P型GaP构成的电流扩展层在750℃以上生长，其他各层在680～750℃生长。
由GaAs构成的缓冲层，其厚度约为0.3μm。接触层，载流子浓度设为1*10 18cm -3、层厚设为约3μm。上部覆盖层，载流子浓度设为约1*10 18cm -3、层厚约为0.5μm。上部引导层为未掺杂且其层厚约为80nm。阱层是未掺杂且层厚约为5.5nm的In 0.2Ga 0.8As，垒层为未掺杂的且层厚约为15nm的Al 0.2Ga 0.8As。下部引导层为未掺杂且层厚为0.2μm。下部覆盖层载流子浓度为1.5*10 18cm -3、层厚约为0.4μm。中间层载流子浓度为1*10 18cm -3，由GaP构成的电流扩展层，载流子浓度为4*10 18cm -3，厚度约为8μm。
接着，通过溶液蚀刻的方式，在化合物半导体层的电流扩展层GaP的表面进行粗化，形成粗化面；在粗化面的表面蒸镀透明键合层SiO 2，其厚度为2μm，所述透明键合层在沉积后经抛光处理，形成平坦面；将上述结构键合至透明蓝宝石基板上。
接着，经过减薄、化学腐蚀去除外延生长衬底GaAs基板和缓冲层以及腐蚀截止层，露出接触层，在接触层上方制作第1电极；通过光刻掩膜的方式，选择性地蚀刻去除部分的上部覆盖层、上部引导层、活性层、下部引导层和P型的下部覆盖层，使电流扩展层露出，在该露出的电流扩展层上形成第2电极。
最后，通过研磨减薄蓝宝石基板和激光切割，形成独立的发光二极管芯片。
实验结果发现，去除衬底后，外延层与键合层之间附着性好，通过键合层稳定的连接到透明基板上。
实施例2
与实施例1的区别在于，本实施例中将上部波导层和下部波导层的材料设为AlGaAs，除此之外以实施例1相同的条件进行发光二极管的制作。
对该实施例1和2的发光二极管进行光电性能测试，其特性结果示于下表1。
表1
  基板 接合面积 覆盖层 波导层 对层数 P0(5mA) VF(5mA)
实施例1 蓝宝石 60000μm 2 AlGaInP AlInP 5 2 1.95
实施例2 蓝宝石 60000μm 2 AlGaInP AlGaAs 5 1 3
在实施例1中，在n型和p型欧姆电极间流通了电流，发射出峰发光波长为830nm的红外光。另外，如表1所示，在实施例1中，正向流通5毫安(mA)的电流时的正向电压(Vf)，反映构成化合物半导体层的电流扩展层和透明基板的接合界面的低电阻特性和各欧姆电极的良好的欧姆接触特性，其Vf1为1.95V。正向电流设为5mA时发光的输出功率(P 0)为2mW。对实施例2中发光二极管进行测试，正向电流为5mA时，其发光输出功率(P 0)和正向电压(Vf1)分别为1mW，3.0V。实验结果显示，波导层为AlInP时，相对于使用AlGaAs作为波导层，其光输出功率(P 0)较高，正向电压(Vf1)较低，这是由于在覆盖层AlGaInP上外延生长波导层AlGaAS时，其界面上会产生缺陷，从而影响发光二极管的发光效率和正向电压。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，这样的修改和变型均落入由所附权利要求所限定的范围之内。

Claims (22)

  1. 一种红外发光二极管，其特征在于，具备：
    半导体发光系列，该半导体发光系列具有交替地层叠阱层和垒层的量子阱结构的活性层、夹持所述活性层的第1波导层和第2波导层、以及隔着所述第1波导层和第2波导层夹持所述活性层的第1覆盖层和第2覆盖层；
    所述第1波导层和第2波导层由组成式为(Al X3Ga 1-X3) Y1In 1-Y1P的化合物半导体组成，其中0≤X3≤1、0＜Y1≤1。
  2. 根据权利要求1所述的一种红外发光二极管，其特征在于，所述阱层由组成式为(In X1Ga 1-X1)As的化合物半导体构成，垒层由组成式为(Al X2Ga 1-X2)As的化合物半导体构成，其中0≤X1≤1、0≤X2≤1。
  3. 根据权利要求1所述的一种红外发光二极管，其特征在于，所述第1和第2覆盖层由组成式为(Al X4Ga 1-X4) Y2In 1-Y2P的化合物半导体组成，其中0≤X4≤1、0＜Y2≤1。
  4. 根据权利要求1所述的一种红外发光二极管，其特征在于，还具备在所述半导体发光系列上的电流扩展层，所述的电流扩展层为GaP。
  5. 根据权利要求5所述的一种红外发光二极管，其特征在于，还具备与所述电流扩展层接合的透明基板。
  6. 根据权利要求1所述的一种红外发光二极管，其特征在于，所述阱层和垒层的对数为10对以下，1对以上。
  7. 根据权利要求2所述的一种红外发光二极管，其特征在于，所述阱层的In的组成X1设定为0.1≤X1≤0.3。
  8. 根据权利要求1所述的一种发光二极管，其特征在于，所述阱层的厚度为4～15nm。
  9. 根据权利要求5所述的一种发光二极管，其特征在于，所述透明基板由GaP、蓝宝石或SiC构成。
  10. 根据权利要求1所述的一种发光二极管，其特征在于，所述半导体 发光系列发射出的光的波长为680～1100nm。
  11. 根据权利要求4所述的一种发光二极管，其特征在于，所述电流扩展层的厚度为3～10μm。
  12. 根据权利要求4所述的一种发光二极管，其特征在于，对所述电流扩展层的表面进行粗化，形成粗化面，该粗化面的粗糙度为100～300nm。
  13. 根据权利要求5或12所述的一种发光二极管，其特征在于，在所述粗化面上蒸镀透明键合层，所述透明基板通过该透明键合层键合在所述电流扩展层上。
  14. 根据权利要求13所述的一种发光二极管，其特征在于，所述透明键合层的材料为SiO 2材料，其厚度为1～5μm。
  15. 根据权利要求1所述的一种发光二极管，其特征在于，所述第1和或第2波导层的Al的组成X3设定为0.2≤X3≤0.8，0.3≤Y1≤0.7。
  16. 根据权利要求3所述的一种发光二极管，其特征在于，所述第1和或第2覆盖层的Al的组成X4设定为0.2≤X4≤0.8，0.3≤Y1≤0.7。
  17. 根据权利要求5所述的一种发光二极管，其特征在于，主要出光面为所述透明基板与电流扩展层接合的面的相反侧的面。
  18. 根据权利要求17所述的一种发光二极管，其特征在于，还具备第1电极和第2电极，所述第1电极和第2电极设置在发光二极管的主要出光面的相反侧的面。
  19. 根据权利要求18所述的发光二极管，其特征在于，所述第1电极和第2电极为欧姆电极。
  20. 一种发光二极管封装体，包括安装基板和安装在所述安装基板上的至少一个发光二极管，其特征在于，所述发光二极管至少一个或多个或全部为权利要求1-19中任一项所述的发光二极管。
  21. 一种发光装置，其特征在于，具备权利要求1～19的任一项所述的发光二极管。
  22. 一种遥控装置，其特征在于，具备权利要求1～19的任一项所述的 发光二极管。
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