WO2021079913A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2021079913A1
WO2021079913A1 PCT/JP2020/039584 JP2020039584W WO2021079913A1 WO 2021079913 A1 WO2021079913 A1 WO 2021079913A1 JP 2020039584 W JP2020039584 W JP 2020039584W WO 2021079913 A1 WO2021079913 A1 WO 2021079913A1
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WIPO (PCT)
Prior art keywords
metal layer
surface metal
main surface
back surface
conductive layer
Prior art date
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PCT/JP2020/039584
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English (en)
Japanese (ja)
Inventor
舞子 畑野
Original Assignee
ローム株式会社
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Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to DE112020005132.3T priority Critical patent/DE112020005132T5/de
Priority to JP2021553500A priority patent/JPWO2021079913A1/ja
Priority to US17/765,756 priority patent/US20220344253A1/en
Publication of WO2021079913A1 publication Critical patent/WO2021079913A1/fr

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Definitions

  • This disclosure relates to semiconductor devices.
  • Patent Document 1 An example of a conventional semiconductor device (power module) is disclosed in Patent Document 1.
  • This semiconductor device includes a semiconductor element, a support substrate (ceramic substrate), and a heat radiating member.
  • the support substrate supports the semiconductor element.
  • the support substrate includes an insulating base material and a copper conductor layer laminated on both sides of the base material.
  • a semiconductor element is bonded to one conductor layer, and a heat radiating member is bonded to the other conductor layer.
  • a member called a heat spreader may be provided between the semiconductor element and the support substrate in the thickness direction of the semiconductor device.
  • the heat spreader is a heat diffusion plate that diffuses the heat generated by the semiconductor element.
  • Copper and aluminum are generally used as the heat spreader, but graphite, which has a higher thermal conductivity than copper and aluminum, is attracting attention. Copper has a thermal conductivity of about 398 W / mK and aluminum has a thermal conductivity of about 236 W / mK, whereas graphite has a thermal conductivity of about 1500 W / mK.
  • Graphite has a hexagonal crystal structure and is layered, and has a relatively high thermal conductivity in the direction parallel to the layer and a relatively low thermal conductivity in the direction perpendicular to the layer.
  • the thermal conductivity in the direction parallel to the layer is about 1500 W / mk
  • the thermal conductivity in the direction orthogonal to the layer is about 5 W / mK. That is, graphite has anisotropy in thermal conductivity. Therefore, the direction parallel to the layer is arranged so as to face the direction in which heat is transferred.
  • the direction of heat transfer is, for example, the direction from the semiconductor element to the support substrate (thickness direction) in the conventional semiconductor device.
  • Graphite also has anisotropy in the coefficient of linear expansion, and the coefficient of linear expansion in the direction orthogonal to the layer is larger than the coefficient of linear expansion in the direction parallel to the layer.
  • the coefficient of linear expansion in the direction orthogonal to the layer is about 25 ppm / K
  • the coefficient of linear expansion in the direction parallel to the layer is about 0 ppm / K. Therefore, there is a difference in the coefficient of linear expansion in the plane orthogonal to the thickness direction, and this difference may cause warpage of the support substrate.
  • This warpage of the support substrate can occur, for example, due to a thermal cycle during the manufacture of the semiconductor device or the operation of the semiconductor device.
  • the warp of the support substrate causes, for example, poor bonding and poor continuity between the members of the semiconductor device, and may reduce the reliability of the semiconductor device.
  • the present disclosure has been conceived in view of the above problems, and an object of the present disclosure is to provide a semiconductor device capable of reducing warpage of a support substrate even when the coefficient of linear expansion has anisotropy. To do.
  • the semiconductor device provided by the first aspect of the present disclosure includes an insulating substrate having a first main surface and a first back surface that are separated from each other in the first direction, each of which is arranged on the first main surface and separated from each other.
  • the first main surface metal layer and the first back surface metal layer overlap each other when viewed in the first direction, and the second main surface metal layer and the second back surface metal layer are viewed in the first direction. Overlap each other.
  • the first main surface metal layer and the second main surface metal layer are arranged in a second direction orthogonal to the first direction.
  • the first conductive layer and the second conductive layer have anisotropy in the linear expansion coefficient, respectively, and the direction in which the linear expansion coefficient is relatively large is the third direction orthogonal to the first direction and the second direction.
  • the dimensions of the first back surface metal layer and the second back surface metal layer in the third direction are smaller than the dimensions of the first main surface metal layer and the second main surface metal layer in the third direction.
  • the semiconductor device provided by the second aspect of the present disclosure includes an insulating substrate having a first main surface and a first back surface that are separated from each other in the first direction, each of which is arranged on the first main surface and separated from each other.
  • the first main surface metal layer and the second main surface metal layer are arranged in a second direction orthogonal to the first direction, and each overlaps the back surface metal layer when viewed in the first direction.
  • the first conductive layer and the second conductive layer have anisotropy in the linear expansion coefficient, respectively, and the direction in which the linear expansion coefficient is relatively large is the third direction orthogonal to the first direction and the second direction.
  • the insulating substrate is made of a resin material having an anisotropic coefficient of linear expansion, and the direction in which the coefficient of linear expansion is relatively large is along the third direction.
  • the semiconductor device provided by the third aspect of the present disclosure comprises a first insulating substrate having a first main surface and a first back surface that are separated in a first direction, and a second main surface and a first surface that are separated in the first direction.
  • a second insulating substrate having two back surfaces, a first main surface metal layer arranged on the first main surface, a second main surface metal layer arranged on the second main surface, and an arrangement on the first back surface.
  • the second conductive layer arranged in the first conductive layer, the first semiconductor element arranged on the first conductive layer and conducting the first conductive layer, and the second conductive layer arranged on the second conductive layer and on the second conductive layer. It includes a second semiconductor element that conducts electricity.
  • the first insulating substrate and the second insulating substrate are arranged so as to be separated from each other in a second direction orthogonal to the first direction.
  • the first main surface metal layer and the first back surface metal layer overlap each other when viewed in the first direction.
  • the second main surface metal layer and the second back surface metal layer overlap each other when viewed in the first direction.
  • the first conductive layer and the second conductive layer have anisotropy in the linear expansion coefficient, respectively, and the direction in which the linear expansion coefficient is relatively large is the third direction orthogonal to the first direction and the second direction.
  • the first insulating substrate and the second insulating substrate are each made of a resin material having a Young's modulus of 50 GPa or less.
  • the warp of the support substrate can be reduced, so that the reliability of the semiconductor device can be improved.
  • FIG. 1 It is a perspective view which shows the semiconductor device which concerns on 1st Embodiment.
  • the sealing member is omitted.
  • FIG. 2 the sealing member is omitted.
  • FIG. 2 It is a partially enlarged view which enlarged a part of FIG.
  • FIG. 2 It is the figure which excerpted a part of FIG.
  • It is a front view which shows the semiconductor device which concerns on 1st Embodiment.
  • FIG. 5 is a cross-sectional view taken along the line XX-XX of FIG. It is a top view which shows the semiconductor device which concerns on 3rd Embodiment. It is the figure which excerpted a part in the plan view shown in FIG.
  • FIG. 2 is a cross-sectional view taken along the line XXIII-XXIII of FIG. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment. It is a bottom view which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 5th Embodiment. It is a bottom view which shows the semiconductor device which concerns on 5th Embodiment.
  • something A is formed on a certain thing B
  • something A is formed on a certain thing B
  • something B means “there is a certain thing A” unless otherwise specified. It includes “being formed directly on the object B” and “being formed on the object B with the object A while interposing another object between the object A and the object B”.
  • something A is placed on something B” and “something A is placed on something B” means “something A is placed on something B” unless otherwise specified. It includes "being placed directly on B” and “being placed on a certain thing B while having another thing intervening between a certain thing A and a certain thing B".
  • something A is located on something B
  • something A is in contact with something B and some thing A is on something B
  • something B unless otherwise specified.
  • What you are doing and "The thing A is located on the thing B while another thing is intervening between the thing A and the thing B”.
  • something A overlaps with some thing B when viewed in a certain direction means “something A overlaps with all of some thing B” and “something A overlaps” unless otherwise specified. "Overlapping a part of a certain object B" is included.
  • the illustrated semiconductor device A1 includes a plurality of semiconductor elements 10, a support substrate 20, two input terminals 31, 32, an output terminal 33, a pair of gate terminals 34A and 34B, a pair of detection terminals 35A and 35B, and a plurality of dummy terminals. It includes 36 and a pair of side terminals 37A and 37B, a plurality of base portions 41, a plurality of linear connecting members 51, a plurality of plate-shaped connecting members 52, and a sealing member 60.
  • FIG. 1 is a perspective view showing the semiconductor device A1.
  • FIG. 2 is a perspective view of FIG. 1 in which the sealing member 60 is omitted.
  • FIG. 3 is a plan view showing the semiconductor device A1.
  • FIG. 4 shows the sealing member 60 as an imaginary line (dashed-dotted line) in the plan view of FIG.
  • FIG. 5 is a partially enlarged view of a part of FIG. 4.
  • FIG. 6 is an excerpt of some components in the plan view of FIG.
  • FIG. 7 is a front view showing the semiconductor device A1.
  • FIG. 8 is a bottom view showing the semiconductor device A1.
  • FIG. 9 is a side view (left side view) showing the semiconductor device A1.
  • FIG. 10 is a side view (right side view) showing the semiconductor device A1.
  • FIG. 1 is a perspective view showing the semiconductor device A1.
  • FIG. 2 is a perspective view of FIG. 1 in which the sealing member 60 is omitted.
  • FIG. 3 is a plan view showing the semiconductor device A1.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG.
  • FIG. 12 is a cross-sectional view taken along the line XII-XII of FIG.
  • FIG. 13 is a partially enlarged view of a part of FIG. 12.
  • FIG. 14 is a cross-sectional view taken along the line XIV-XIV of FIG.
  • FIG. 15 is a cross-sectional view taken along the line XV-XV of FIG.
  • FIGS. 1 to 14 will be described with reference to three directions (x direction, y direction, and z direction) that are orthogonal to each other.
  • the x direction is the left-right direction in the plan view (see FIGS. 2 and 3) of the semiconductor device A1.
  • the y direction is the vertical direction in the plan view (see FIGS. 2 and 3) of the semiconductor device A1. If necessary, one in the x direction is set to the x1 direction, and the other in the x direction is set to the x2 direction.
  • one in the y direction is the y1 direction, the other in the y direction is the y2 direction, one in the z direction is the z1 direction, and the other in the z direction is the z2 direction.
  • the z1 direction is referred to as the lower side and the z2 direction is referred to as the upper side.
  • the dimension in the z direction may be referred to as "thickness" or "thickness”.
  • Each of the plurality of semiconductor elements 10 is configured by using a semiconductor material mainly composed of SiC (silicon carbide).
  • the semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like.
  • Each of the plurality of semiconductor elements 10 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • Each semiconductor element 10 is not limited to MOSFET, but is not limited to MOSFET, field effect transistor including MISFET (Metal-Insulator-Semiconductor FET), bipolar transistor such as IGBT (Insulated Gate Bipolar Transistor), IC chip such as LSI, diode, capacitor. And so on.
  • the plurality of semiconductor elements 10 are all the same element, and are, for example, n-channel MOSFETs.
  • Each semiconductor element 10 has, for example, a rectangular shape when viewed in the z direction (hereinafter, also referred to as “planar view”), but the present disclosure is not limited thereto.
  • the thickness of each semiconductor element 10 is, for example, about 50 to 370 ⁇ m.
  • the plurality of semiconductor elements 10 include a plurality of semiconductor elements 10A and a plurality of semiconductor elements 10B. As shown in FIGS. 2 and 4, the semiconductor device A1 includes four semiconductor elements 10A and four semiconductor elements 10B. The number of semiconductor elements 10 is not limited to this configuration, and can be appropriately changed according to the performance required for the semiconductor device A1. When the semiconductor device A1 is, for example, a half-bridge type switching circuit, the plurality of semiconductor elements 10A form an upper arm circuit in the switching circuit, and the plurality of semiconductor elements 10B form a lower arm circuit in the switching circuit. To do.
  • Each of the plurality of semiconductor elements 10A is mounted on the support substrate 20 (conductive member 24A described later) as shown in FIGS. 2, 4, 5, and 12.
  • the plurality of semiconductor elements 10A are arranged along the y direction and are separated from each other.
  • each semiconductor element 10A is conductively bonded to the support substrate 20 (conductive member 24A) via the conductive bonding material 19A.
  • the conductive bonding material 19A is, for example, solder, a metal paste, a sintered metal, or the like.
  • Each of the plurality of semiconductor elements 10B is mounted on the support substrate 20 (conductive member 24B described later) as shown in FIGS. 2, 4, 5, and 11.
  • the plurality of semiconductor elements 10B are arranged along the y direction and are separated from each other.
  • each semiconductor element 10B is conductively bonded to the support substrate 20 (conductive member 24B) via the conductive bonding material 19B.
  • the conductive bonding material 19B is, for example, solder, a metal paste, a sintered metal, or the like, similarly to the conductive bonding material 19A. In the example shown in FIG.
  • the plurality of semiconductor elements 10A and the plurality of semiconductor elements 10B are arranged side by side alternately when viewed in the x direction, but the plurality of semiconductor elements 10A and the plurality of semiconductor elements 10B are arranged. They may be arranged so as to overlap when viewed in the x direction.
  • each of the plurality of semiconductor elements 10 has an element main surface 101 and an element back surface 102.
  • the semiconductor element 10A is shown in FIG. 13, the semiconductor element 10B is also configured in the same manner.
  • the element main surface 101 and the element back surface 102 are separated from each other in the z direction.
  • the element main surface 101 faces the z2 direction, and the element back surface 102 faces the z1 direction.
  • the element back surface 102 of each semiconductor element 10A faces the conductive member 24A.
  • the element back surface 102 of each semiconductor element 10B faces the conductive member 24B.
  • Each of the plurality of semiconductor elements 10 has a main surface electrode 11, a back surface electrode 12, and an insulating film 13 as shown in FIGS. 5 and 13.
  • the main surface electrode 11 is provided on the element main surface 101.
  • the main surface electrode 11 includes a first electrode 111 and a second electrode 112, as shown in FIGS. 4 and 11.
  • the first electrode 111 is, for example, a source electrode through which a source current flows.
  • the second electrode 112 is, for example, a gate electrode, and a gate voltage for driving each semiconductor element 10 is applied.
  • the first electrode 111 is larger than the second electrode 112. In the example shown in FIG. 5, the first electrode 111 is composed of one region, but may be divided into a plurality of regions.
  • the back surface electrode 12 is provided on the back surface 102 of the element.
  • the back surface electrode 12 is formed over the entire back surface 102 of the element.
  • the back surface electrode 12 is, for example, a drain electrode through which a drain current flows.
  • the insulating film 13 is provided on the element main surface 101.
  • the insulating film 13 has an electrical insulating property.
  • the insulating film 13 surrounds the main surface electrode 11 in a plan view.
  • the insulating film 13 insulates the first electrode 111 and the second electrode 112.
  • a SiO 2 (silicon dioxide) layer, a SiN 4 (silicon nitride) layer, and a polybenzoxazole layer are laminated in this order from the element main surface 101.
  • the configuration of the insulating film 13 is not limited to that described above, and for example, a polyimide layer may be used instead of the polybenzoxazole layer.
  • the support substrate 20 supports a plurality of semiconductor elements 10.
  • the support substrate 20 includes an insulating substrate 21, a pair of main surface metal layers 22A and 22B, a pair of back surface metal layers 23A and 23B, a pair of conductive members 24A and 24B, a pair of insulating layers 25A and 25B, and a pair of gate layers 26A. It contains 26B and a pair of detection layers 27A, 27B.
  • the insulating substrate 21, the pair of main surface metal layers 22A and 22B, and the pair of back surface metal layers 23A and 23B are composed of a so-called DBC (Direct Bonded Copper) substrate. In the present embodiment, the case of a DBC substrate is shown, but the present invention is not limited to this, and for example, a DBA (Direct Bonded Aluminum) substrate may be used.
  • DBC Direct Bonded Copper
  • the insulating substrate 21 insulates the main surface metal layers 22A and 22B and the back surface metal layers 23A and 23B.
  • the constituent material of the insulating substrate 21 is, for example, ceramic having excellent thermal conductivity.
  • a ceramic for example, AlN (aluminum nitride), SiN (silicon nitride), Al 2 O 3 (aluminum oxide) and the like are used.
  • the thickness of the insulating substrate 21 is, for example, about 0.32 mm.
  • the insulating substrate 21 has a rectangular shape in a plan view.
  • the insulating substrate 21 has a flat plate shape.
  • the insulating substrate 21 has a main surface 211 and a back surface 212 as shown in FIGS. 11, 12, 14 and 15.
  • the main surface 211 and the back surface 212 are separated from each other in the z direction.
  • the main surface 211 faces the z2 direction, and the back surface 212 faces the z1 direction.
  • a pair of main surface metal layers 22A and 22B are arranged on the main surface 211.
  • a pair of back surface metal layers 23A and 23B are arranged on the back surface 212.
  • the pair of main surface metal layers 22A and 22B are arranged on the main surface 211 of the insulating substrate 21, respectively.
  • the pair of main surface metal layers 22A and 22B are separated from each other and are arranged in the x direction.
  • the constituent materials of the main surface metal layers 22A and 22B are, for example, Cu (copper), Cu alloy, and Al (aluminum).
  • the thickness of each of the main surface metal layers 22A and 22B is, for example, about 0.2 mm.
  • Each of the main surface metal layers 22A and 22B has a substantially rectangular shape in a plan view.
  • Each of the main surface metal layers 22A and 22B has, for example, a dimension in the x direction of about 20 mm and a dimension in the y direction of about 30 mm.
  • each main surface metal layer 22A and 22B has a pair of edge edges 221,222 and a pair of edge edges 223 and 224.
  • Each of the pair of edge edges 221,222 extends in the y direction in a plan view.
  • the pair of edge edges 221,222 are separated from each other in the x direction.
  • the edge 222 is located in the x2 direction with respect to the edge 221.
  • the pair of edge edges 221,222 are substantially parallel.
  • Each of the pair of edge edges 223 and 224 extends in the x direction in a plan view.
  • the pair of edge edges 223 and 224 are separated from each other in the y direction.
  • the edge 224 is located in the y2 direction with respect to the edge 223.
  • the pair of edge edges 221,222 and the pair of edge edges 223 and 224 are substantially parallel to each other.
  • the pair of back surface metal layers 23A and 23B are arranged on the back surface 212 of the insulating substrate 21 as shown in FIGS. 11, 12, 14, and 15, respectively.
  • the pair of back surface metal layers 23A and 23B are separated from each other and are arranged along the x direction.
  • the lower surfaces (surfaces facing the z1 direction) of the back surface metal layers 23A and 23B are exposed from the sealing member 60.
  • a heat sink (not shown) may be connected to the lower surfaces of the back metal layers 23A and 23B.
  • the constituent materials of the back surface metal layers 23A and 23B are the same as those of the main surface metal layers 22A and 22B. That is, the constituent materials of the back metal layers 23A and 23B are, for example, Cu, a Cu alloy, or Al.
  • each of the back metal layers 23A and 23B is, for example, about 0.2 mm.
  • the back metal layers 23A and 23B have a substantially rectangular shape in a plan view.
  • Each of the back surface metal layers 23A and 23B has, for example, a dimension in the x direction of about 20 mm and a dimension in the y direction of about 23 mm.
  • the dimensions of the back surface metal layers 23A and 23B in the y direction are not limited to the above values (23 mm), and are preferably about 75 to 90% of the dimensions of the main surface metal layers 22A and 22B in the y direction.
  • each back metal layer 23A and 23B has a pair of edge edges 231 and 232 and a pair of edge edges 233 and 234.
  • Each of the pair of edge edges 231,232 extends in the y direction in a plan view.
  • the pair of edge edges 231,232 are separated from each other in the x direction.
  • the edge 232 is located in the x2 direction with respect to the edge 231.
  • Each of the pair of edge edges 233 and 234 extends in the x direction in a plan view.
  • the pair of edge edges 233 and 234 are separated from each other in the y direction.
  • the edge 234 is located in the y2 direction with respect to the edge 233.
  • the pair of edge edges 231 and 232 and the pair of edge edges 233 and 234 are substantially parallel to each other.
  • the edge 233 of the back surface metal layer 23A overlaps the semiconductor element 10A located most in the y1 direction among the plurality of semiconductor elements 10A in a plan view.
  • the edge 234 of the back surface metal layer 23B overlaps the semiconductor element 10B located most in the y2 direction among the plurality of semiconductor elements 10B in a plan view.
  • the main surface metal layer 22A and the back surface metal layer 23A overlap in a plan view
  • the main surface metal layer 22B and the back surface metal layer 23B overlap in a plan view.
  • the center of the main surface metal layers 22A and 22B in the y direction and the center of the back surface metal layers 23A and 23B in the y direction overlap.
  • the edge 231 of each of the back surface metal layers 23A and 23B overlaps the edge 221 of each of the main surface metal layers 22A and 22B in a plan view
  • the edge 232 of each back surface metal layer 23A and 23B is each in a plan view.
  • each of the back surface metal layers 23A and 23B overlaps with each of the main surface metal layers 22A and 22B in a plan view, and is located in the y2 direction with respect to the edge 223 of each of the main surface metal layers 22A and 22B.
  • the edge 234 of each of the back surface metal layers 23A and 23B overlaps with each of the main surface metal layers 22A and 22B in a plan view, and is located in the y1 direction with respect to the edge 224 of each of the main surface metal layers 22A and 22B.
  • the pair of conductive members 24A and 24B are separated from each other and are arranged in the x direction.
  • the conductive member 24A is arranged on the main surface metal layer 22A, and the conductive member 24B is arranged on the main surface metal layer 22B.
  • a plurality of semiconductor elements 10A are arranged on the conductive member 24A, and a plurality of semiconductor elements 10B are arranged on the conductive member 24B.
  • the conductive member 24A includes a conductive layer 241A and two metal layers 242A and 243A
  • the conductive member 24B includes a conductive layer 241B and two metal layers 242B and 243B.
  • Each conductive layer 241A and 241B is composed of, for example, graphite.
  • graphite has a hexagonal crystal structure and is layered, and the thermal conductivity is anisotropic between the direction parallel to the layer and the direction orthogonal to the layer.
  • the thermal conductivity in the direction parallel to the layer is about 1500 W / mK, and the thermal conductivity in the direction orthogonal to the layer is about 5 W / mK.
  • Each of the conductive layers 241A and 241B is arranged in a direction parallel to the layer along the z direction. Further, as described above, graphite has anisotropy in the coefficient of linear expansion.
  • the coefficient of linear expansion in the direction parallel to the layer is about 0 ppm / K
  • the coefficient of linear expansion in the direction orthogonal to the layer is about 25 ppm / K.
  • the conductive layers 241A and 241B are arranged so that the direction orthogonal to the layers is along the y direction. Therefore, the conductive layers 241A and 241B are arranged so that the coefficient of linear expansion in the y direction is about 25 ppm / K and the coefficient of linear expansion in the x direction is about 0 ppm / K. That is, in each of the conductive layers 241A and 241B, the direction having a relatively large coefficient of linear expansion is arranged along the y direction.
  • the thickness of each of the conductive layers 241A and 241B is, for example, about 2.0 mm.
  • the metal layers 242A and 242B are arranged on the upper surface (the surface facing the z2 direction) of the conductive layers 241A and 241B.
  • the constituent materials of the metal layers 242A and 242B are, for example, Cu or a Cu alloy.
  • the metal layers 242A and 242B are provided to improve the bonding between the conductive members 24A and 24B and the semiconductor elements 10A and 10B.
  • the thickness of each metal layer 242A and 242B is, for example, about 0.1 to 0.5 mm.
  • the metal layers 243A and 243B are arranged on the lower surface (the surface facing the z1 direction) of the conductive layers 241A and 241B.
  • the constituent materials of the metal layers 243A and 243B are, for example, Cu or a Cu alloy.
  • the metal layers 243A and 243B are provided to improve the bonding between the conductive members 24A and 24B and the main surface metal layers 22A and 22B.
  • the thickness of each metal layer 243A and 243B is, for example, about 0.1 to 0.5 mm.
  • a conductive bonding layer 29A is interposed between the conductive member 24A (metal layer 243A) and the main surface metal layer 22A.
  • the conductive member 24A is bonded to the main surface metal layer 22A by the conductive bonding layer 29A.
  • a conductive bonding layer 29B is interposed between the conductive member 24B (metal layer 243B) and the main surface metal layer 22B.
  • the conductive member 24B is bonded to the main surface metal layer 22B by the conductive bonding layer 29B.
  • Each of the conductive bonding layers 29A and 29B is, for example, solder, a metal paste, a sintered metal, or the like.
  • the pair of insulating layers 25A and 25B have electrical insulating properties, and the constituent material thereof is, for example, glass epoxy resin. As shown in FIG. 4, each of the pair of insulating layers 25A and 25B has a strip shape extending in the y direction.
  • the insulating layer 25A is joined to the conductive member 24A as shown in FIGS. 4, 5 and 12.
  • the insulating layer 25A is located in the x2 direction with respect to the plurality of semiconductor elements 10A.
  • the insulating layer 25B is joined to the conductive member 24B as shown in FIGS. 4, 5 and 11.
  • the insulating layer 25B is located in the x1 direction with respect to the plurality of semiconductor elements 10B.
  • the pair of gate layers 26A and 26B have conductivity, and the constituent material thereof is, for example, Cu or a Cu alloy. As shown in FIG. 4, each of the pair of gate layers 26A and 26B has a strip shape extending in the y direction.
  • the gate layer 26A is arranged on the insulating layer 25A as shown in FIGS. 4, 5 and 12.
  • the gate layer 26A conducts to the second electrode 112 (gate electrode) of each semiconductor element 10A via the linear connecting member 51 (gate wire 511 described later).
  • the gate layer 26B is arranged on the insulating layer 25B as shown in FIGS. 4, 5 and 11.
  • the gate layer 26B conducts to the second electrode 112 (gate electrode) of each semiconductor element 10B via the linear connecting member 51 (gate wire 511 described later).
  • the pair of detection layers 27A and 27B have conductivity, and the constituent material thereof is, for example, Cu or a Cu alloy. As shown in FIG. 4, each of the pair of detection layers 27A and 27B has a band shape extending in the y direction. As shown in FIGS. 4, 5 and 12, the detection layer 27A is arranged on the insulating layer 25A together with the gate layer 26A. The detection layer 27A is located next to the gate layer 26A on the insulating layer 25A in a plan view, and is separated from the gate layer 26A. In the examples shown in FIGS. 4, 5 and 12, the detection layer 27A is located in the x1 direction with respect to the gate layer 26A, and is arranged closer to the plurality of semiconductor elements 10A than with the gate layer 26A.
  • the arrangement of the gate layer 26A and the detection layer 27A in the x direction may be reversed.
  • the detection layer 27A conducts to the first electrode 111 (source electrode) of each semiconductor element 10A via the linear connecting member 51 (detection wire 512 described later).
  • the detection layer 27B is arranged on the insulating layer 25B together with the gate layer 26B.
  • the detection layer 27B is located next to the gate layer 26B on the insulating layer 25B in a plan view, and is separated from the gate layer 26B.
  • the detection layer 27B is located in the x2 direction with respect to the gate layer 26B, and is arranged closer to the plurality of semiconductor elements 10B than with the gate layer 26B.
  • the arrangement of the gate layer 26B and the detection layer 27B in the x direction may be reversed.
  • the detection layer 27B conducts to the first electrode 111 (source electrode) of each semiconductor element 10B via the linear connecting member 51 (detection wire 512 described later).
  • the two input terminals 31 and 32 are metal plates, respectively.
  • the constituent material of the metal plate is Cu or a Cu alloy.
  • Both of the two input terminals 31 and 32 have a dimension in the z direction of, for example, about 0.8 mm, but are not limited thereto.
  • Both the two input terminals 31 and 32 are located closer to the x2 direction in the semiconductor device A1 as shown in FIGS. 1, 4, 11 and 12.
  • a power supply voltage is applied between the two input terminals 31 and 32.
  • a power supply voltage may be directly applied to the input terminals 31 and 32 from a power source (not shown), or a bus bar (not shown) is connected so as to sandwich the input terminals 31 and 32, via the bus bar. , May be applied.
  • the input terminal 31 is a positive electrode (P terminal), and the input terminal 32 is a negative electrode (N terminal).
  • the input terminal 32 is arranged apart from both the input terminal 31 and the support substrate 20 (conductive member 24A) in the z direction.
  • the input terminal 31 has a pad portion 311 and a terminal portion 312 as shown in FIGS. 4 and 11.
  • the pad portion 311 is a portion of the input terminal 31 covered with the sealing member 60.
  • the end portion of the pad portion 311 on the x1 direction side has a comb-tooth shape in a plan view, but may have a rectangular shape in a plan view instead of a comb-tooth shape.
  • the comb-shaped portion of the pad portion 311 is conductively bonded to the conductive member 24A (metal layer 242A).
  • the bonding between the pad portion 311 and the conductive member 24A may be laser bonding, ultrasonic bonding, or bonding using a conductive bonding material.
  • the terminal portion 312 is a portion of the input terminal 31 exposed from the sealing member 60. As shown in FIGS. 4, 7, 8, 10 and 11, the terminal portion 312 extends from the sealing member 60 in the x2 direction in a plan view.
  • the input terminal 32 has a pad portion 321 and a terminal portion 322 as shown in FIGS. 4 and 11.
  • the pad portion 321 is a portion of the input terminal 32 covered with the sealing member 60. As shown in FIG. 4, the pad portion 321 includes a connecting portion 321a and a plurality of extending portions 321b.
  • the connecting portion 321a has a strip shape extending in the y direction.
  • the connecting portion 321a is connected to the terminal portion 322.
  • the plurality of extending portions 321b are strip-shaped extending from the connecting portion 321a in the x1 direction.
  • the plurality of extending portions 321b are separated from each other and are arranged in the y direction in a plan view.
  • the tip portion of each extension portion 321b overlaps each base portion 41 in a plan view and is joined to each base portion 41.
  • the bonding may be laser welding using a laser beam, ultrasonic bonding, or bonding using a bonding material.
  • the tip portion is an end edge portion of the extending portion 321b that is opposite to the side connected to the connecting portion 321a in the x direction and is on the x1 direction side.
  • the terminal portion 322 is a portion of the input terminal 32 exposed from the sealing member 60. As shown in FIGS. 3, 4, and 8, the terminal portion 322 extends from the sealing member 60 in the x2 direction in a plan view.
  • the terminal portion 322 has a rectangular shape in a plan view. As shown in FIGS. 3, 4, and 8, the terminal portion 322 overlaps the terminal portion 312 of the input terminal 31 in a plan view.
  • the terminal portion 322 is separated from the terminal portion 312 in the z2 direction.
  • the shape of the terminal portion 322 is the same as the shape of the terminal portion 312, for example.
  • the output terminal 33 is a metal plate.
  • the constituent material of the metal plate is, for example, Cu or a Cu alloy.
  • the output terminal 33 is located closer to the x1 direction in the semiconductor device A1 as shown in FIGS. 1, 3, 4, 7, 7, 8 and 11.
  • the AC power (voltage) converted into power by the plurality of semiconductor elements 10 is output from the output terminal 33.
  • the output terminal 33 includes a pad portion 331 and a terminal portion 332.
  • the pad portion 331 is a portion of the output terminal 33 covered with the sealing member 60.
  • the portion of the pad portion 331 on the x2 direction side has a comb-tooth shape in a plan view, but may have a rectangular shape in a plan view instead of a comb-tooth shape.
  • the comb-shaped portion of the pad portion 331 is conductively bonded to the conductive member 24B (metal layer 242B).
  • the bonding between the pad portion 331 and the conductive member 24B may be laser bonding, ultrasonic bonding, or bonding using a conductive bonding material.
  • the terminal portion 332 is a portion of the output terminal 33 exposed from the sealing member 60. As shown in FIGS. 3, 4, 7, 8, 11, and 12, the terminal portion 332 extends from the sealing member 60 in the x1 direction.
  • the pair of gate terminals 34A and 34B are located next to the conductive members 24A and 24B in the y direction.
  • a gate voltage for driving a plurality of semiconductor elements 10A is applied to the gate terminal 34A.
  • a gate voltage for driving a plurality of semiconductor elements 10B is applied to the gate terminal 34B.
  • Both the pair of gate terminals 34A and 34B have a pad portion 341 and a terminal portion 342 as shown in FIG.
  • the pad portion 341 is covered with a sealing member 60.
  • the gate terminals 34A and 34B are supported by the sealing member 60.
  • the surface of the pad portion 341 may be, for example, silver-plated.
  • the terminal portion 342 is connected to the pad portion 341 and is exposed from the sealing member 60.
  • the terminal portion 342 has an L shape when viewed in the x direction.
  • the pair of detection terminals 35A and 35B are located next to the pair of gate terminals 34A and 34B in the x direction. From the detection terminal 35A, the voltage (voltage corresponding to the source current) applied to each main surface electrode 11 (first electrode 111) of the plurality of semiconductor elements 10A is detected. From the detection terminal 35B, a voltage (voltage corresponding to the source current) applied to each of the main surface electrodes 11 (first electrode 111) of the plurality of semiconductor elements 10B is detected.
  • Both the pair of detection terminals 35A and 35B have a pad portion 351 and a terminal portion 352 as shown in FIG.
  • the pad portion 351 is covered with a sealing member 60.
  • the detection terminals 35A and 35B are supported by the sealing member 60.
  • the surface of the pad portion 351 may be, for example, silver-plated.
  • the terminal portion 352 is connected to the pad portion 351 and is exposed from the sealing member 60.
  • the terminal portion 352 has an L shape when viewed in the x direction.
  • the plurality of dummy terminals 36 are located on the opposite side of the pair of detection terminals 35A and 35B from the pair of gate terminals 34A and 34B in the x direction.
  • the number of dummy terminals 36 is six. Of these, the three dummy terminals 36 are located on one side (x2 direction) in the x direction. The remaining three dummy terminals 36 are located on the other side (x1 direction) in the x direction.
  • the number and arrangement of the plurality of dummy terminals 36 are not limited to the above configuration. Further, the configuration may not include a plurality of dummy terminals 36.
  • Each of the plurality of dummy terminals 36 has a pad portion 361 and a terminal portion 362 as shown in FIG.
  • the pad portion 361 is covered with a sealing member 60.
  • the surface of the pad portion 361 may be, for example, silver-plated.
  • the terminal portion 362 is connected to the pad portion 361 and is exposed from the sealing member 60.
  • the terminal portion 362 has an L shape when viewed in the x direction.
  • the shape of the terminal portion 362 is the same as the shape of each terminal portion 342 of the pair of gate terminals 34A and 34B and the shape of each terminal portion 352 of the pair of detection terminals 35A and 35B.
  • the pair of side terminals 37A and 37B are end edges of the sealing member 60 on the y1 direction side in a plan view, and each of the sealing members 60 in the x direction. It overlaps the edge part.
  • the side terminal 37A is joined to the conductive member 24A and is covered with the sealing member 60 except for the end face facing the x2 direction.
  • the side terminal 37B is joined to the conductive member 24B and is covered with the sealing member 60 except for the end face facing the x1 direction. All of the side terminals 37A and 37B overlap the sealing member 60 in a plan view.
  • the method of bonding the side terminals 37A and 37B may be any of bonding using a bonding material, laser bonding, or ultrasonic bonding.
  • each of the side terminals 37A and 37B is bent in a plan view, and the other part is bent in the z direction.
  • the configuration of the side terminals 37A and 37B is not limited to this, and may extend from the sealing member 60 in a plan view. Further, the semiconductor device A1 does not have to include the side terminals 37A and 37B.
  • the pair of gate terminals 34A and 34B, the pair of detection terminals 35A and 35B, and the plurality of dummy terminals 36 are arranged along the x direction in a plan view as shown in FIGS. 1 to 5, 7 and 8. There is.
  • the pair of gate terminals 34A and 34B, the pair of detection terminals 35A and 35B, the plurality of dummy terminals 36, and the pair of side terminals 37A and 37B are all formed from the same lead frame.
  • the insulating plate 39 has electrical insulating properties, and its constituent material is, for example, a sheet-shaped insulating member.
  • a part of the insulating plate 39 is a flat plate, and as shown in FIGS. 4, 7, 10, 11 and 12, the terminal portion 312 of the input terminal 31 and the terminal portion of the input terminal 32 in the z direction. It is sandwiched between 322 and 322.
  • all of the input terminals 31 overlap the insulating plate 39.
  • a part of the pad portion 321 and the entire terminal portion 322 overlap the insulating plate 39.
  • the two input terminals 31 and 32 are insulated from each other by the insulating plate 39.
  • a part of the insulating plate 39 (the part on the x1 direction side) is covered with the sealing member 60.
  • the insulating plate 39 has an intervening portion 391 and an extending portion 392.
  • the intervening portion 391 is interposed between the terminal portion 312 of the input terminal 31 and the terminal portion 322 of the input terminal 32 in the z direction.
  • the entire intervening portion 391 is sandwiched between the terminal portion 312 and the terminal portion 322.
  • the extending portion 392 extends from the intervening portion 391 further from the terminal portion 312 and the terminal portion 322 in the x2 direction.
  • Each of the plurality of base portions 41 has electrical insulation, and the constituent material thereof is, for example, ceramic. As shown in FIG. 11, each base portion 41 is joined to the surface of the conductive member 24A. Each base portion 41 has, for example, a rectangular shape in a plan view. The plurality of base portions 41 are arranged in the y direction and are separated from each other. The dimension of each base portion 41 in the z direction is substantially the same as the sum of the dimension of the input terminal 31 in the z direction and the dimension of the insulating plate 39 in the z direction. Each extension portion 321b of the pad portion 321 of the input terminal 32 is joined to each base portion 41. Each base portion 41 supports the input terminal 32 so that the input terminal 32 is substantially parallel to the support substrate 20.
  • the plurality of linear connecting members 51 are so-called bonding wires.
  • Each of the plurality of linear connecting members 51 has conductivity, and the constituent material thereof is, for example, Al, Cu, a clad material, or an alloy having one or more of these.
  • the plurality of linear connecting members 51 include a plurality of gate wires 511, a plurality of detection wires 512, a pair of first connecting wires 513, and a pair of second connecting wires 514. I'm out.
  • the plurality of gate wires 511 are joined to the second electrode 112 (gate electrode) of each semiconductor element 10 and to any of the pair of gate layers 26A and 26B, respectively.
  • the plurality of gate wires 511 include one that conducts the second electrode 112 of each semiconductor element 10A and the gate layer 26A, and one that conducts the second electrode 112 of each semiconductor element 10B and the gate layer 26B.
  • the plurality of detection wires 512 are attached to the first electrode 111 (source electrode) of each semiconductor element 10 and to any one of the pair of detection layers 27A and 27B. It is joined.
  • the plurality of detection wires 512 include one that conducts the first electrode 111 of each semiconductor element 10A and the detection layer 27A, and one that conducts the first electrode 111 of each semiconductor element 10B and the detection layer 27B.
  • one of the pair of first connecting wires 513 conducts the gate layer 26A and the gate terminal 34A, and the other conducts the gate layer 26B and the gate terminal 34B.
  • One of the first connecting wires 513 is joined to the gate layer 26A and the pad portion 341 of the gate terminal 34A.
  • the other first connection wire 513 is connected to the gate layer 26B and the pad portion 341 of the gate terminal 34B.
  • one of the pair of second connecting wires 514 conducts the detection layer 27A and the detection terminal 35A, and the other conducts the detection layer 27B and the insulating layer 25B.
  • One second connection wire 514 is joined to the detection layer 27A and the pad portion 351 of the detection terminal 35A.
  • the other second connection wire 514 is joined to the detection layer 27B and the pad portion 351 of the detection terminal 35B.
  • Each of the plurality of plate-shaped connecting members 52 has conductivity, and the constituent materials thereof include, for example, a composite material of Cu, Cu alloy, CuMo (copper molybdenum), a composite material of CIC (Copper-Inver-Copper), and the like. Is.
  • Each plate-shaped connecting member 52 can be formed by bending a plate-shaped metal plate.
  • the plurality of plate-shaped connecting members 52 include a plurality of first reeds 521 and a plurality of second reeds 522, as shown in FIGS. 4 and 5.
  • the same bonding wire as the linear connecting member 51 may be used.
  • Each of the plurality of first leads 521 conducts the semiconductor element 10A and the conductive member 24B as shown in FIGS. 4, 5 and 12, respectively.
  • Each first lead 521 is joined to the first electrode 111 (source electrode) of each semiconductor element 10A and the metal layer 242B of the conductive member 24B.
  • Each first lead 521 is bonded by a conductive bonding material such as solder and silver paste, but may be ultrasonic bonding or laser bonding.
  • Each first lead 521 is partially bent in the z direction.
  • Each of the plurality of second reeds 522 connects the semiconductor element 10B and the input terminal 32 as shown in FIGS. 4, 5 and 11, respectively.
  • Each second lead 522 is joined to the first electrode 111 (source electrode) of each semiconductor element 10B and each extension portion 321b of the pad portion 321 of the input terminal 32.
  • Each second reed 522 is bonded by a conductive bonding material such as solder and silver paste, but may be ultrasonic bonded or laser bonded.
  • Each second reed 522 is partially bent in the z direction.
  • the sealing member 60 includes a plurality of semiconductor elements 10, a part of the support substrate 20, and a part of each of the two input terminals 31 and 32.
  • the constituent material of the sealing member 60 is an insulating resin material, for example, an epoxy resin.
  • the sealing member 60 can be formed, for example, by transfer molding.
  • the dimension of the sealing member 60 in the z direction is, for example, about 10 mm.
  • the sealing member 60 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634. ing.
  • the resin main surface 61 and the resin back surface 62 are separated from each other in the z direction as shown in FIGS. 7, 9 to 12, 14 and 15.
  • the resin main surface 61 faces the z1 direction
  • the resin back surface 62 faces the z2 direction.
  • the resin back surface 62 has a frame shape surrounding the pair of back surface metal layers 23A and 23B in a plan view.
  • the plurality of resin side surfaces 631 to 634 are connected to both the resin main surface 61 and the resin back surface 62, respectively, and are sandwiched between them in the z direction.
  • FIGS. 3, 4, 7, 8, 11 and 12 the two resin side surfaces 631, 632 are separated from each other in the x direction.
  • the resin side surface 631 faces the x1 direction, and the resin side surface 632 faces the x2 direction. As shown in FIGS. 3, 4, 8, 10, 14 and 15, the two resin side surfaces 633 and 634 are separated from each other in the y direction.
  • the resin side surface 633 faces the y1 direction, and the resin side surface 634 faces the y2 direction.
  • each of the sealing member 60 includes a plurality of recesses 65 recessed in the z direction from the resin back surface 62.
  • Each of the plurality of recesses 65 extends in the y direction, and is connected from the edge of the resin back surface 62 on the y1 direction side to the edge on the y2 direction side in a plan view.
  • the plurality of recesses 65 are formed in the x direction by three each with the pair of back surface metal layers 23A and 23B interposed therebetween. A plurality of recesses 65 may not be formed in the sealing member 60.
  • the effects of the semiconductor device A1 according to the first embodiment are as follows.
  • the two conductive layers 241A and 241B are arranged along the y direction in which the linear expansion coefficient is relatively large, respectively. Further, the dimensions of the back surface metal layers 23A and 23B in the y direction are smaller than the dimensions of the main surface metal layers 22A and 22B in the y direction.
  • the back metal in the y direction The binding force of the insulating substrate 21 by the back surface metal layers 23A and 23B is reduced as compared with the case where the dimensions of the layers 23A and 23B and the dimensions of the main surface metal layers 22A and 22B in the y direction are the same. Thereby, the warp of the support substrate 20 (particularly the insulating substrate 21) can be reduced. Therefore, the reliability of the semiconductor device A1 is improved.
  • the dimensions of the back surface metal layers 23A and 23B in the y direction are the main surface metal layers 22A and 22B. It is preferably about 75 to 90% of the dimension in the y direction.
  • the constituent material of the insulating substrate 21 is ceramic. Since the coefficient of linear expansion of ceramic is small, the thermal expansion and contraction of the insulating substrate 21 due to the thermal cycle are small. Further, each constituent material of the main surface metal layers 22A and 22B and the back surface metal layers 23A and 23B is Cu or a Cu alloy. Since the coefficient of linear expansion of Cu is large, the main surface metal layers 22A and 22B and the back surface metal layers 23A and 23B have large thermal expansion and contraction due to the thermal cycle, respectively. That is, the thermal stress applied to the insulating substrate 21 by the thermal cycle is large.
  • the warp of the support substrate 20 becomes large. Therefore, as described above, making the dimensions of the back surface metal layers 23A and 23B smaller than the dimensions of the main surface metal layers 22A and 22B in the y direction reduces the warpage of the support substrate 20. It is effective in.
  • each conductive layer 241A, 241B (each conductive member 24A, 24B) is arranged on one insulating substrate 21.
  • the thermal stress applied to the insulating substrate 21 in the thermal cycle becomes high.
  • the warp of the support substrate 20 becomes large. Therefore, as described above, making the dimensions of the back surface metal layers 23A and 23B in the y direction smaller than the dimensions of the main surface metal layers 22A and 22B in the y direction reduces the warpage of the support substrate 20. It is effective in.
  • the pair of edge edges 233 and 234 of the back surface metal layers 23A and 23B overlap each of the main surface metal layers 22A and 22B in a plan view. Further, the pair of edge edges 231,232 of the back surface metal layers 23A and 23B overlap each other of the pair of edge edges 221,222 of the main surface metal layers 22A and 22B in a plan view.
  • the warp of the support substrate 20 is reduced. was found to be obtained.
  • the back metal layers 23A and 23B are exposed from the sealing member 60, and for example, a heat sink or the like can be connected. Therefore, the larger the plan view area of the back surface metal layers 23A and 23B is, the larger the heat dissipation is. Therefore, if the plan view areas of the back surface metal layers 23A and 23B are small, the heat dissipation is lowered.
  • the dimensions of the back surface metal layers 23A and 23B in the x direction are made substantially the same as the dimensions of the main surface metal layers 22A and 22B in the x direction, and the dimensions of the back surface metal layers 23A and 23B are in the y direction.
  • the semiconductor device A1 can reduce the warp of the support substrate 20 and suppress the decrease in heat dissipation.
  • an insulating resin material may be used instead of ceramic.
  • an insulating resin material include an epoxy-based resin material and a PDMS (polydimethylsiloxane) -based resin material. Since these resin materials have a Young's modulus smaller than that of ceramics, the warp of the support substrate 20 is further reduced.
  • the Young's modulus of SiN (silicon nitride), which is a ceramic is about 300 GPa
  • the Young's modulus of an epoxy resin material is about 14 GPa.
  • the Young's modulus of the PDMS-based resin material is about 5 MPa. The higher the Young's modulus, the higher the rigidity.
  • the insulating resin material has lower rigidity (softer) than ceramic. Therefore, even if there is a difference in expansion during thermal expansion due to the thermal cycle, the softness of the insulating substrate 21 relaxes the thermal stress applied to the support substrate 20. This makes it possible to further reduce the warpage of the support substrate 20.
  • the Young's modulus of the insulating resin material used for the insulating substrate 21 is about 50 GPa or less (preferably about 10 GPa or less), the effect of further reducing the warp of the supporting substrate 20 can be obtained. ..
  • FIG. 16 is a perspective view showing a semiconductor device having a different shape of the sealing member 60 as described above.
  • each end edge portion in the y direction extends in the x direction in a plan view.
  • a part of each of the two input terminals 31, 32 and the insulating plate 39 is covered by the portion of the sealing member 60 extending in the x2 direction.
  • a part of the output terminal 33 is covered by a portion of the sealing member 60 extending in the x1 direction.
  • FIG. 17 is a plan view (excerpt of some components) showing a semiconductor device in which the back metal layers 23A and 23B are divided in this way.
  • each of the back metal layers 23A and 23B is divided into four, but the number of divisions is not limited to this.
  • the dimensions Da and Db shown in FIG. 17 may be substantially the same as the y-direction dimensions from the edge 233 to the edge 234 of the back metal layers 23A and 23B in the semiconductor device A1, respectively.
  • FIG. 18 to 20 show the semiconductor device A2 according to the second embodiment.
  • FIG. 18 is a plan view showing the semiconductor device A2, and the sealing member 60 is shown by an imaginary line (dashed line).
  • FIG. 19 is a cross-sectional view taken along the line XIX-XIX of FIG.
  • FIG. 20 is a cross-sectional view taken along the line XX-XX of FIG.
  • the shape of the first lead 521 of the semiconductor device A2 (FIG. 18) is different from that of the semiconductor device A1 (FIG. 4). Further, the semiconductor device A2 does not include the second reed 522 (FIG. 4).
  • each first lead 521 of the semiconductor device A2 is not bent, and as shown in FIG. 20, the thickness of the portion joined to the conductive member 24B is large. In this way, it is possible to join each first lead 521 to the conductive member 24B without bending each first lead 521.
  • each first lead 521 of the semiconductor device A1 may be used instead of each first lead 521 of the semiconductor device A2.
  • each first lead 521 of the semiconductor device A2 may be used instead of each first lead 521 of the semiconductor device A1.
  • the input terminal 32 of the semiconductor device A2 extends until each extending portion 321b of the pad portion 321 extends so as to overlap each semiconductor element 10B in a plan view. Then, as shown in FIGS. 18 and 19, a conductive block material 42 is interposed between each semiconductor element 10B and each extension portion 321b, respectively. Each block material 42 is bonded to each extension portion 321b and each semiconductor element 10B (first electrode 111).
  • the bonding between each extending portion 321b and each block material 42, and the bonding between each block material 42 and each semiconductor element 10B (first electrode 111) can be performed by bonding using a conductive bonding material, laser bonding, or ultrasonic bonding. It may be any of joining and the like.
  • each block material 42 is not particularly limited, but for example, a Cu, Cu alloy, a CuMo composite material, a CIC composite material, or the like is used.
  • the input terminal 32 and each semiconductor element 10B are made conductive in this way without using each second reed 522.
  • the semiconductor device A2 can reduce the warp of the support substrate 20 in the same manner as the semiconductor device A1.
  • FIG. 21 to 23 show the semiconductor device A3 according to the third embodiment.
  • FIG. 21 is a plan view showing the semiconductor device A3, and the sealing member 60 is shown by an imaginary line (dashed line).
  • FIG. 22 is a partially excerpted view of the plan view of FIG. 21.
  • FIG. 23 is a cross-sectional view taken along the line XXIII-XXIII of FIG.
  • the semiconductor device A3 is arranged such that a plurality of semiconductor elements 10A and a plurality of semiconductor elements 10B overlap each other when viewed in the x direction, as shown in FIGS. 21 and 22.
  • the edge 233 of the back surface metal layer 23A is located on the most y1 direction side of the plurality of semiconductor elements 10A in a plan view, similarly to the semiconductor device A1.
  • the edge 234 of the back surface metal layer 23A overlaps the semiconductor element 10A located on the most y2 direction side of the plurality of semiconductor elements 10A in a plan view. Further, as shown in FIG.
  • the edge 233 of the back surface metal layer 23B overlaps with the semiconductor element 10B located on the most y1 direction side of the plurality of semiconductor elements 10B in a plan view, and the end of the back surface metal layer 23B.
  • the edge 234 overlaps the semiconductor element 10B located on the y2 direction side of the plurality of semiconductor elements 10B in a plan view.
  • the semiconductor device A3 has a different configuration of the two input terminals 31 and 32 and the output terminal 33 as compared with the semiconductor device A1.
  • the two input terminals 31 and 32 are arranged so as to overlap in the y direction as shown in FIGS. 21 and 23, instead of overlapping in the z direction as in the semiconductor device A1. ing.
  • the pad portion 311 is conductively bonded to the conductive member 24A via the conductive block material 43 as shown in FIGS. 21 and 23.
  • the pad portion 331 is joined to the block material 43, and the block material 43 is joined to the conductive member 24A.
  • the bonding between the pad portion 331 and the block material 43 and the bonding between the block material 43 and the conductive member 24A may be bonding using a conductive bonding material, laser bonding, ultrasonic bonding, or the like. May be good.
  • the constituent material of the block material 43 is not particularly limited, but for example, a Cu, Cu alloy, a CuMo composite material, a CIC composite material, or the like is used.
  • the pad portion 321 is x until each extension portion 321b overlaps with each semiconductor element 10B in a plan view, similarly to the semiconductor device A2. It extends in the direction. Then, similarly to the semiconductor device A2, the tip end portion (end portion in the x1 direction) of each extension portion 321b is conductive to each semiconductor element 10B (first electrode 111) via the block material 42.
  • a part of the pad portion 331 is conductively bonded to the conductive member 24B via the conductive block material 44.
  • the pad portion 331 is joined to the block material 44, and the block material 44 is joined to the conductive member 24B.
  • the bonding between the pad portion 331 and the block material 44 and the bonding between the block material 44 and the conductive member 24B may be bonding using a conductive bonding material, laser bonding, ultrasonic bonding, or the like. May be good.
  • the constituent material of the block material 44 is not particularly limited, but for example, a Cu, Cu alloy, a CuMo composite material, a CIC composite material, or the like is used.
  • the semiconductor device A2 can reduce the warp of the support substrate 20 in the same manner as the semiconductor device A1.
  • FIG. 24 and 25 show the semiconductor device A4 according to the fourth embodiment.
  • FIG. 24 is a cross-sectional view showing the semiconductor device A4, and corresponds to the cross section shown in FIG. 11 of the first embodiment.
  • FIG. 25 is a bottom view showing the semiconductor device A4.
  • the semiconductor device A4 is different from the semiconductor device A1 mainly in the configuration of the support substrate 20.
  • the constituent material of the insulating substrate 21 is not ceramic but, for example, BN (boron nitride) resin.
  • the BN resin is a mixed resin material containing BN as a filler, and has an anisotropy in the coefficient of linear expansion like graphite.
  • the insulating substrate 21 is arranged along the y direction in a direction having a relatively large coefficient of linear expansion.
  • the insulating substrate 21 has a coefficient of linear expansion in the x direction of about 2 ppm / K, a coefficient of linear expansion in the y direction of about 27 ppm / K, and a coefficient of linear expansion in the z direction of about 2 ppm / K.
  • the support substrate 20 of the semiconductor device A4 does not include a pair of back metal layers 23A and 23B, but includes one back metal layer 23.
  • the back surface metal layer 23 has a rectangular shape in a plan view.
  • the main surface metal layers 22A and 22B overlap the back surface metal layer 23 in a plan view.
  • the dimensions of the back surface metal layer 23 in the y direction are substantially the same as the dimensions of the main surface metal layers 22A and 22B in the y direction and the dimensions of the insulating substrate 21 in the y direction.
  • the dimensions of the insulating substrate 21, the main metal layers 22A and 22B, and the back metal layers 23 in the z direction are, for example, about 0.1 mm.
  • the insulating substrate 21 is made of a BN resin having an anisotropic linear expansion coefficient.
  • the direction in which the coefficient of linear expansion is relatively large is along the y direction. That is, the direction in which the linear expansion coefficient of the insulating substrate 21 is relatively large and the direction in which the linear expansion coefficients of the conductive layers 241A and 241B are relatively large are substantially the same.
  • the semiconductor device A4 can reduce the warp of the support substrate 20 without dividing the back surface metal layer 23 into two or reducing the dimension in the y direction.
  • the back surface metal layer 23 in the y direction are substantially the same as the dimensions of the main surface metal layers 22A and 22B in the y direction has been described, but the back surface metal layer 23 in the y direction The dimensions may be smaller than the dimensions of the main surface metal layers 22A and 22B in the y direction.
  • the semiconductor device A4 the case where the support substrate 20 includes one back surface metal layer 23 is shown, but similarly to the semiconductor device A1, two back surface metal layers 23A and 23B may be included.
  • the dimensions of the back surface metal layers 23A and 23B in the y direction may be the same as the dimensions of the main surface metal layers 22A and 22B in the y direction, or the dimensions of the main surface metal layers 22A and 22B in the y direction. It may be smaller than the size of.
  • FIG. 26 and 27 show the semiconductor device A5 according to the fifth embodiment.
  • FIG. 26 is a cross-sectional view showing the semiconductor device A5, and corresponds to the cross section shown in FIG. 11 of the first embodiment.
  • FIG. 27 is a bottom view showing the semiconductor device A5.
  • the semiconductor device A5 includes a pair of insulating boards 21A and 21B separated from each other instead of one insulating board 21 as shown in FIGS. 26 and 27. That is, the semiconductor device A5 has a configuration in which the insulating substrate 21 is divided into two. The pair of insulating substrates 21A and 21B are separated in the x direction and are arranged in the x direction. Each of the insulating substrates 21A and 21B has a rectangular shape in a plan view.
  • the constituent materials of the insulating substrates 21A and 21B may be ceramics or insulating resin materials having a Young's modulus of 50 GPa or less. Further, the constituent materials of the insulating substrates 21A and 21B may be BN resin. In this case, the insulating substrates 21A and 21B are arranged along the y direction in a direction having a relatively large coefficient of linear expansion.
  • the insulating substrate 21A has a main surface 211A and a back surface 212A.
  • the main surface 211A and the back surface 212A are separated from each other in the z direction.
  • the main surface 211A faces the z2 direction, and the back surface 212A faces the z1 direction.
  • the main surface metal layer 22A is arranged on the main surface 211A, and the back surface metal layer 23A is arranged on the back surface 212A.
  • the insulating substrate 21A, the main surface metal layer 22A, and the back surface metal layer 23A overlap in a plan view.
  • the dimensions of the main surface metal layer 22A and the back surface metal layer 23A in the y direction are substantially the same, and the main surface metal layer 22A and the back surface metal layer 23A are substantially the same in a plan view. That is, in a plan view, each end edge 221 to 224 of the main surface metal layer 22A overlaps each end edge 231 to 234 of the back surface metal layer 23A.
  • the insulating substrate 21B has a main surface 211B and a back surface 212B.
  • the main surface 211B and the back surface 212B are separated in the z direction.
  • the main surface 211B faces the z2 direction, and the back surface 212B faces the z1 direction.
  • the main surface metal layer 22B is arranged on the main surface 211B, and the back surface metal layer 23B is arranged on the back surface 212B.
  • the insulating substrate 21B, the main surface metal layer 22B, and the back surface metal layer 23B overlap in a plan view.
  • the dimensions of the main surface metal layer 22B and the back surface metal layer 23B in the y direction are substantially the same, and the main surface metal layer 22B and the back surface metal layer 23B are substantially the same in a plan view. That is, in a plan view, each end edge 221 to 224 of the main surface metal layer 22B overlaps each end edge 231 to 234 of the back surface metal layer 23B, respectively.
  • the semiconductor device A5 two insulating substrates 21A and 21B that are separated from each other are provided, the conductive layer 241A is arranged on the insulating substrate 21A, and the conductive layer 241B is arranged on the insulating substrate 21B. That is, unlike the semiconductor device A1, the semiconductor device A5 does not have the two conductive layers 241A and 241B arranged on one insulating substrate 21. According to this configuration, the thermal stress applied to the insulating substrates 21A and 21B at the time of the thermal cycle is reduced as compared with the case where the insulating substrate 21 is composed of one insulating substrate 21.
  • the warpage of the insulating substrates 21A and 21B is reduced, so that the semiconductor device A5 can reduce the warpage of the support substrate 20.
  • the constituent materials of the insulating substrates 21A and 21B are insulating resin materials having a Young's modulus of 50 GPa or less, the softness of the insulating substrates 21A and 21B alleviates the thermal stress applied to the insulating substrates 21A and 21B. Therefore, it is preferable in reducing the warp of the support substrate 20.
  • the back surface metal layers 23A and 23B in the y direction are substantially the same as the dimensions of the main surface metal layers 22A and 22B in the y direction, but the back surface metal layers 23A have been described.
  • the dimension of 23B in the y direction may be smaller than the dimension of each of the main surface metal layers 22A and 22B in the y direction.
  • the semiconductor device according to the present disclosure is not limited to the above-described embodiment.
  • the specific configuration of each part of the semiconductor device of the present disclosure can be freely redesigned.
  • the present disclosure includes semiconductor devices described in the following appendix. Appendix 1.
  • An insulating substrate having a first main surface and a first back surface that are separated in the first direction,
  • the first back surface metal layer and the second back surface metal layer each of which is arranged on the first back surface and is separated from each other,
  • the first conductive layer arranged on the first main surface metal layer and
  • the second conductive layer arranged on the second main surface metal layer and A first semiconductor element arranged on the first conductive layer and conducting with the first conductive layer, It is provided with a second semiconductor element that is arranged on the second conductive layer and conducts to the second conductive layer.
  • the first main surface metal layer and the first back surface metal layer overlap each other when viewed in the first direction.
  • the second main surface metal layer and the second back surface metal layer overlap each other when viewed in the first direction.
  • the first main surface metal layer and the second main surface metal layer are arranged in a second direction orthogonal to the first direction.
  • the first conductive layer and the second conductive layer have anisotropy in the linear expansion coefficient, respectively, and the direction in which the linear expansion coefficient is relatively large is the third direction orthogonal to the first direction and the second direction.
  • the dimensions of the first back surface metal layer and the second back surface metal layer in the third direction are smaller than the dimensions of the first main surface metal layer and the second main surface metal layer in the third direction.
  • the first main surface metal layer, the second main surface metal layer, the first back surface metal layer, and the second back surface metal layer are each a pair extending in the third direction when viewed in the first direction.
  • the semiconductor device has the first edge and The pair of first edge edges of the first main surface metal layer and the pair of first edge edges of the first back surface metal layer overlap each other when viewed in the first direction.
  • the semiconductor device according to Appendix 1, wherein the pair of first edge edges of the second main surface metal layer and the pair of first edge edges of the second back surface metal layer overlap each other when viewed in the first direction. .. Appendix 3.
  • the first back surface metal layer and the second back surface metal layer each have a pair of second edge edges extending in the second direction when viewed in the first direction.
  • the pair of second edge edges of the first back surface metal layer overlap the first main surface metal layer when viewed in the first direction.
  • the semiconductor device according to Appendix 2 wherein the pair of second edge edges of the second back surface metal layer overlap the second main surface metal layer when viewed in the first direction.
  • Appendix 4. With the additional first semiconductor element arranged side by side with the first semiconductor element in the third direction, An additional second semiconductor element arranged side by side with the second semiconductor element in the third direction is further provided. The additional first semiconductor element is arranged on the first conductive layer and overlaps with any of the pair of second edge of the first back metal layer when viewed in the first direction. The additional second semiconductor element is arranged on the second conductive layer and overlaps with any of the pair of second edge of the second back surface metal layer when viewed in the first direction. 3. The semiconductor device according to 3. Appendix 5.
  • a sealing member that covers the insulating substrate, the first main surface metal layer, the second main surface metal layer, the first conductive layer, the second conductive layer, the first semiconductor element, and the second semiconductor element.
  • the semiconductor device according to any one of Supplementary note 1 to Supplementary note 7, further comprising.
  • Appendix 9. A connecting member covered with the sealing member is further provided.
  • the first semiconductor element includes a first back surface electrode that conducts to the first conductive layer and a first main surface electrode that is separated from the first back surface electrode in the first direction.
  • the semiconductor device according to Appendix 8 wherein the first main surface electrode and the second conductive layer are electrically conductive with each other via the connecting member.
  • the semiconductor device according to Appendix 9, wherein the second semiconductor device includes a second back surface electrode that conducts to the second conductive layer and a second main surface electrode that is separated from the second back surface electrode in the first direction. .. Appendix 11. A first input terminal that conducts to the first back surface electrode via the first conductive layer, and A second input terminal conducting on the second main surface electrode and Further, an output terminal conducting the second conductive layer is provided. The semiconductor device according to Appendix 10, wherein the first input terminal, the second input terminal, and the output terminal are each partially exposed from the sealing member. Appendix 12. The semiconductor device according to any one of Supplementary note 1 to Supplementary note 11, wherein the first conductive layer and the second conductive layer are made of graphite. Appendix 13.
  • the semiconductor device according to any one of Supplementary note 1 to Supplementary note 12, wherein the insulating substrate is made of ceramic.
  • Appendix 14 The insulating substrate is made of a resin material having an anisotropic coefficient of linear expansion. In Appendix 1 to Appendix 12, the direction in which the linear expansion coefficient of the insulating substrate is relatively large and the direction in which the linear expansion coefficient is relatively large in each of the first conductive layer and the second conductive layer substantially coincide with each other.
  • Appendix 15 An insulating substrate having a first main surface and a first back surface that are separated in the first direction, A first main surface metal layer and a second main surface metal layer, each of which is arranged on the first main surface and is separated from each other.
  • the back surface metal layer arranged on the first back surface and The first conductive layer arranged on the first main surface metal layer and The second conductive layer arranged on the second main surface metal layer and A first semiconductor element arranged on the first conductive layer and conducting with the first conductive layer, It is provided with a second semiconductor element that is arranged on the second conductive layer and conducts to the second conductive layer.
  • the first main surface metal layer and the second main surface metal layer are arranged in a second direction orthogonal to the first direction, and each overlaps the back surface metal layer when viewed in the first direction.
  • the first conductive layer and the second conductive layer have anisotropy in the linear expansion coefficient, respectively, and the direction in which the linear expansion coefficient is relatively large is the third direction orthogonal to the first direction and the second direction.
  • the insulating substrate is made of a resin material having an anisotropic coefficient of linear expansion, and the direction in which the coefficient of linear expansion is relatively large is along the third direction.
  • the dimension of the insulating substrate in the first direction is substantially the same as the dimensions of the first main surface metal layer, the second main surface metal layer, and the back surface metal layer in the first direction, as described in Appendix 15. Semiconductor equipment. Appendix 17.
  • the semiconductor device according to any one of Supplementary note 14 to Supplementary note 16, wherein the resin material constituting the insulating substrate has a Young's modulus of 50 GPa or less.
  • Appendix 18 A first insulating substrate having a first main surface and a first back surface that are separated in the first direction, A second insulating substrate having a second main surface and a second back surface that are separated from each other in the first direction, The first main surface metal layer arranged on the first main surface and The second main surface metal layer arranged on the second main surface and The first back surface metal layer arranged on the first back surface and The second back surface metal layer arranged on the second back surface and The first conductive layer arranged on the first main surface metal layer and The second conductive layer arranged on the second main surface metal layer and A first semiconductor element arranged on the first conductive layer and conducting with the first conductive layer, It is provided with a second semiconductor element that is arranged on the second conductive layer and conducts to the second conductive layer.
  • the first insulating substrate and the second insulating substrate are arranged so as to be separated from each other in a second direction orthogonal to the first direction.
  • the first main surface metal layer and the first back surface metal layer overlap each other when viewed in the first direction.
  • the second main surface metal layer and the second back surface metal layer are overlapped with each other when viewed in the first direction.
  • the first conductive layer and the second conductive layer have anisotropy in the linear expansion coefficient, respectively, and the direction in which the linear expansion coefficient is relatively large is the third direction orthogonal to the first direction and the second direction.
  • the first insulating substrate and the second insulating substrate are each made of a resin material having a Young's modulus of 50 GPa or less.
  • A1 to A5 Semiconductor devices 10, 10A, 10B: Semiconductor element 101: Element main surface 102: Element back surface 11: Main surface electrode 111: First electrode 112: Second electrode 12: Back surface electrode 13: Insulating film 19A, 19B: Conductive bonding material 20: Support substrate 21,21A, 21B: Insulation substrate 211,211A, 211B: Main surface 212, 212A, 212B: Back surface 22A, 22B: Main surface metal layer 221-224: Edge edges 23, 23A, 23B : Back surface metal layers 231 to 234: Edge edges 24A, 24B: Conductive members 241A, 241B: Conductive layers 242A, 242B: Metal layers 243A, 243B: Metal layers 25A, 25B: Insulation layers 26A, 26B: Gate layers 27A, 27B: Detection layers 29A, 29B: Conductive bonding layer 31: Input terminal 311: Pad unit 312: Terminal unit 32: Input terminal 321: Pad unit 321a:

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Abstract

La présente invention concerne un dispositif à semi-conducteur comprenant : un substrat isolant ; des première et seconde couches métalliques de surface principale qui sont disposées sur la surface principale du substrat isolant ; des première et seconde couches métalliques de surface arrière qui sont disposées sur la surface arrière du substrat isolant ; une première couche conductrice et un premier élément semi-conducteur, qui sont disposés sur la première couche métallique de surface principale ; et une seconde couche conductrice et un second élément semi-conducteur qui sont disposés sur la seconde couche métallique de surface principale. La première couche conductrice et la seconde couche conductrice présentent une anisotropie de coefficient de dilatation linéaire ; et la direction dans laquelle le coefficient de dilatation linéaire est relativement élevé s'étend le long d'une direction prédéfinie perpendiculaire à la direction d'épaisseur du substrat isolant. En ce qui concerne les tailles dans la direction prédéfinie, les première et seconde couches métalliques de surface arrière sont plus petites que les première et seconde couches métalliques de surface principale.
PCT/JP2020/039584 2019-10-24 2020-10-21 Dispositif à semi-conducteur WO2021079913A1 (fr)

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Citations (4)

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JP2016115810A (ja) * 2014-12-15 2016-06-23 株式会社デンソー 電子装置
JP2018074089A (ja) * 2016-11-03 2018-05-10 株式会社デンソー 半導体装置
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JP6300633B2 (ja) 2014-05-20 2018-03-28 三菱電機株式会社 パワーモジュール
US11367669B2 (en) * 2016-11-21 2022-06-21 Rohm Co., Ltd. Power module and fabrication method of the same, graphite plate, and power supply equipment
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WO2010150297A1 (fr) * 2009-06-22 2010-12-29 三菱電機株式会社 Boîtier de semi-conducteur et structure de montage de boîtier de semi-conducteur
JP2016115810A (ja) * 2014-12-15 2016-06-23 株式会社デンソー 電子装置
JP2018074089A (ja) * 2016-11-03 2018-05-10 株式会社デンソー 半導体装置
JP2019071399A (ja) * 2016-11-21 2019-05-09 ローム株式会社 パワーモジュールおよびその製造方法、グラファイトプレート、および電源装置

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